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Rev | Author | Line No. | Line |
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2997 | Serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Christian König. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Christian König |
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25 | * Rafał Miłecki |
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26 | */ |
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3764 | Serge | 27 | #include |
2997 | Serge | 28 | #include |
29 | #include |
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30 | #include "radeon.h" |
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31 | #include "radeon_asic.h" |
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32 | #include "evergreend.h" |
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33 | #include "atom.h" |
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34 | |||
5078 | serge | 35 | extern void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder); |
36 | extern void dce6_afmt_write_sad_regs(struct drm_encoder *encoder); |
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37 | extern void dce6_afmt_select_pin(struct drm_encoder *encoder); |
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38 | extern void dce6_afmt_write_latency_fields(struct drm_encoder *encoder, |
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39 | struct drm_display_mode *mode); |
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40 | |||
5271 | serge | 41 | /* enable the audio stream */ |
42 | static void dce4_audio_enable(struct radeon_device *rdev, |
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43 | struct r600_audio_pin *pin, |
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44 | u8 enable_mask) |
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45 | { |
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46 | u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL); |
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47 | |||
48 | if (!pin) |
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49 | return; |
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50 | |||
51 | if (enable_mask) { |
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52 | tmp |= AUDIO_ENABLED; |
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53 | if (enable_mask & 1) |
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54 | tmp |= PIN0_AUDIO_ENABLED; |
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55 | if (enable_mask & 2) |
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56 | tmp |= PIN1_AUDIO_ENABLED; |
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57 | if (enable_mask & 4) |
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58 | tmp |= PIN2_AUDIO_ENABLED; |
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59 | if (enable_mask & 8) |
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60 | tmp |= PIN3_AUDIO_ENABLED; |
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61 | } else { |
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62 | tmp &= ~(AUDIO_ENABLED | |
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63 | PIN0_AUDIO_ENABLED | |
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64 | PIN1_AUDIO_ENABLED | |
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65 | PIN2_AUDIO_ENABLED | |
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66 | PIN3_AUDIO_ENABLED); |
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67 | } |
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68 | |||
69 | WREG32(AZ_HOT_PLUG_CONTROL, tmp); |
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70 | } |
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71 | |||
2997 | Serge | 72 | /* |
73 | * update the N and CTS parameters for a given pixel clock rate |
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74 | */ |
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75 | static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) |
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76 | { |
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77 | struct drm_device *dev = encoder->dev; |
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78 | struct radeon_device *rdev = dev->dev_private; |
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79 | struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); |
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80 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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81 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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82 | uint32_t offset = dig->afmt->offset; |
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83 | |||
84 | WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz)); |
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85 | WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz); |
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86 | |||
87 | WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz)); |
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88 | WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz); |
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89 | |||
90 | WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz)); |
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91 | WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz); |
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92 | } |
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93 | |||
5078 | serge | 94 | static void dce4_afmt_write_latency_fields(struct drm_encoder *encoder, |
95 | struct drm_display_mode *mode) |
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96 | { |
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97 | struct radeon_device *rdev = encoder->dev->dev_private; |
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98 | struct drm_connector *connector; |
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99 | struct radeon_connector *radeon_connector = NULL; |
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100 | u32 tmp = 0; |
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101 | |||
102 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
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103 | if (connector->encoder == encoder) { |
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104 | radeon_connector = to_radeon_connector(connector); |
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105 | break; |
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106 | } |
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107 | } |
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108 | |||
109 | if (!radeon_connector) { |
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110 | DRM_ERROR("Couldn't find encoder's connector\n"); |
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111 | return; |
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112 | } |
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113 | |||
114 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
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115 | if (connector->latency_present[1]) |
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116 | tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | |
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117 | AUDIO_LIPSYNC(connector->audio_latency[1]); |
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118 | else |
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119 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); |
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120 | } else { |
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121 | if (connector->latency_present[0]) |
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122 | tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | |
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123 | AUDIO_LIPSYNC(connector->audio_latency[0]); |
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124 | else |
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125 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); |
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126 | } |
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127 | WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp); |
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128 | } |
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129 | |||
130 | static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder) |
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131 | { |
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132 | struct radeon_device *rdev = encoder->dev->dev_private; |
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133 | struct drm_connector *connector; |
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134 | struct radeon_connector *radeon_connector = NULL; |
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135 | u32 tmp; |
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5271 | serge | 136 | u8 *sadb = NULL; |
5078 | serge | 137 | int sad_count; |
138 | |||
139 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
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140 | if (connector->encoder == encoder) { |
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141 | radeon_connector = to_radeon_connector(connector); |
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142 | break; |
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143 | } |
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144 | } |
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145 | |||
146 | if (!radeon_connector) { |
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147 | DRM_ERROR("Couldn't find encoder's connector\n"); |
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148 | return; |
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149 | } |
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150 | |||
151 | sad_count = drm_edid_to_speaker_allocation(radeon_connector_edid(connector), &sadb); |
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5179 | serge | 152 | if (sad_count < 0) { |
153 | DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); |
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154 | sad_count = 0; |
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5078 | serge | 155 | } |
156 | |||
157 | /* program the speaker allocation */ |
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158 | tmp = RREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); |
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159 | tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); |
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160 | /* set HDMI mode */ |
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161 | tmp |= HDMI_CONNECTION; |
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162 | if (sad_count) |
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163 | tmp |= SPEAKER_ALLOCATION(sadb[0]); |
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164 | else |
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165 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ |
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166 | WREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); |
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167 | |||
168 | kfree(sadb); |
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169 | } |
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170 | |||
3764 | Serge | 171 | static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder) |
2997 | Serge | 172 | { |
3764 | Serge | 173 | struct radeon_device *rdev = encoder->dev->dev_private; |
174 | struct drm_connector *connector; |
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175 | struct radeon_connector *radeon_connector = NULL; |
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176 | struct cea_sad *sads; |
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177 | int i, sad_count; |
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178 | |||
179 | static const u16 eld_reg_to_type[][2] = { |
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180 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, |
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181 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, |
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182 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, |
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183 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, |
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184 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, |
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185 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, |
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186 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, |
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187 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, |
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188 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, |
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189 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, |
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190 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, |
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191 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, |
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192 | }; |
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193 | |||
194 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
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5078 | serge | 195 | if (connector->encoder == encoder) { |
3764 | Serge | 196 | radeon_connector = to_radeon_connector(connector); |
5078 | serge | 197 | break; |
198 | } |
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3764 | Serge | 199 | } |
200 | |||
201 | if (!radeon_connector) { |
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202 | DRM_ERROR("Couldn't find encoder's connector\n"); |
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203 | return; |
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204 | } |
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205 | |||
5078 | serge | 206 | sad_count = drm_edid_to_sad(radeon_connector_edid(connector), &sads); |
207 | if (sad_count <= 0) { |
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3764 | Serge | 208 | DRM_ERROR("Couldn't read SADs: %d\n", sad_count); |
209 | return; |
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210 | } |
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211 | BUG_ON(!sads); |
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212 | |||
213 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { |
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214 | u32 value = 0; |
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5078 | serge | 215 | u8 stereo_freqs = 0; |
216 | int max_channels = -1; |
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3764 | Serge | 217 | int j; |
218 | |||
219 | for (j = 0; j < sad_count; j++) { |
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220 | struct cea_sad *sad = &sads[j]; |
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221 | |||
222 | if (sad->format == eld_reg_to_type[i][1]) { |
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5078 | serge | 223 | if (sad->channels > max_channels) { |
3764 | Serge | 224 | value = MAX_CHANNELS(sad->channels) | |
225 | DESCRIPTOR_BYTE_2(sad->byte2) | |
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226 | SUPPORTED_FREQUENCIES(sad->freq); |
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5078 | serge | 227 | max_channels = sad->channels; |
228 | } |
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229 | |||
3764 | Serge | 230 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) |
5078 | serge | 231 | stereo_freqs |= sad->freq; |
232 | else |
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3764 | Serge | 233 | break; |
234 | } |
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235 | } |
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5078 | serge | 236 | |
237 | value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); |
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238 | |||
3764 | Serge | 239 | WREG32(eld_reg_to_type[i][0], value); |
240 | } |
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241 | |||
242 | kfree(sads); |
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2997 | Serge | 243 | } |
244 | |||
245 | /* |
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246 | * build a HDMI Video Info Frame |
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247 | */ |
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3764 | Serge | 248 | static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder, |
249 | void *buffer, size_t size) |
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2997 | Serge | 250 | { |
251 | struct drm_device *dev = encoder->dev; |
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252 | struct radeon_device *rdev = dev->dev_private; |
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253 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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254 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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255 | uint32_t offset = dig->afmt->offset; |
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3764 | Serge | 256 | uint8_t *frame = buffer + 3; |
5078 | serge | 257 | uint8_t *header = buffer; |
2997 | Serge | 258 | |
259 | WREG32(AFMT_AVI_INFO0 + offset, |
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260 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
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261 | WREG32(AFMT_AVI_INFO1 + offset, |
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262 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
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263 | WREG32(AFMT_AVI_INFO2 + offset, |
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264 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
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265 | WREG32(AFMT_AVI_INFO3 + offset, |
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5078 | serge | 266 | frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); |
2997 | Serge | 267 | } |
268 | |||
5078 | serge | 269 | static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock) |
270 | { |
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271 | struct drm_device *dev = encoder->dev; |
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272 | struct radeon_device *rdev = dev->dev_private; |
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273 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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274 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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275 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
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276 | u32 base_rate = 24000; |
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277 | u32 max_ratio = clock / base_rate; |
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278 | u32 dto_phase; |
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279 | u32 dto_modulo = clock; |
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280 | u32 wallclock_ratio; |
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281 | u32 dto_cntl; |
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282 | |||
283 | if (!dig || !dig->afmt) |
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284 | return; |
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285 | |||
286 | if (ASIC_IS_DCE6(rdev)) { |
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287 | dto_phase = 24 * 1000; |
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288 | } else { |
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289 | if (max_ratio >= 8) { |
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290 | dto_phase = 192 * 1000; |
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291 | wallclock_ratio = 3; |
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292 | } else if (max_ratio >= 4) { |
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293 | dto_phase = 96 * 1000; |
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294 | wallclock_ratio = 2; |
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295 | } else if (max_ratio >= 2) { |
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296 | dto_phase = 48 * 1000; |
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297 | wallclock_ratio = 1; |
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298 | } else { |
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299 | dto_phase = 24 * 1000; |
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300 | wallclock_ratio = 0; |
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301 | } |
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302 | dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
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303 | dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); |
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304 | WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl); |
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305 | } |
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306 | |||
307 | /* XXX two dtos; generally use dto0 for hdmi */ |
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308 | /* Express [24MHz / target pixel clock] as an exact rational |
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309 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
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310 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
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311 | */ |
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312 | WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id)); |
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313 | WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); |
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314 | WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo); |
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315 | } |
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316 | |||
317 | |||
2997 | Serge | 318 | /* |
319 | * update the info frames with the data from the current display mode |
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320 | */ |
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321 | void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) |
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322 | { |
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323 | struct drm_device *dev = encoder->dev; |
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324 | struct radeon_device *rdev = dev->dev_private; |
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325 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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326 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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5078 | serge | 327 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
3764 | Serge | 328 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; |
329 | struct hdmi_avi_infoframe frame; |
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2997 | Serge | 330 | uint32_t offset; |
3764 | Serge | 331 | ssize_t err; |
5078 | serge | 332 | uint32_t val; |
333 | int bpc = 8; |
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2997 | Serge | 334 | |
5078 | serge | 335 | if (!dig || !dig->afmt) |
336 | return; |
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337 | |||
2997 | Serge | 338 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
339 | if (!dig->afmt->enabled) |
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340 | return; |
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341 | offset = dig->afmt->offset; |
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342 | |||
5078 | serge | 343 | /* hdmi deep color mode general control packets setup, if bpc > 8 */ |
344 | if (encoder->crtc) { |
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345 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
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346 | bpc = radeon_crtc->bpc; |
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347 | } |
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2997 | Serge | 348 | |
5078 | serge | 349 | /* disable audio prior to setting up hw */ |
350 | if (ASIC_IS_DCE6(rdev)) { |
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351 | dig->afmt->pin = dce6_audio_get_pin(rdev); |
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5271 | serge | 352 | dce6_audio_enable(rdev, dig->afmt->pin, 0); |
5078 | serge | 353 | } else { |
354 | dig->afmt->pin = r600_audio_get_pin(rdev); |
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5271 | serge | 355 | dce4_audio_enable(rdev, dig->afmt->pin, 0); |
5078 | serge | 356 | } |
357 | |||
358 | evergreen_audio_set_dto(encoder, mode->clock); |
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359 | |||
2997 | Serge | 360 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, |
361 | HDMI_NULL_SEND); /* send null packets when required */ |
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362 | |||
363 | WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000); |
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364 | |||
5078 | serge | 365 | val = RREG32(HDMI_CONTROL + offset); |
366 | val &= ~HDMI_DEEP_COLOR_ENABLE; |
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367 | val &= ~HDMI_DEEP_COLOR_DEPTH_MASK; |
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2997 | Serge | 368 | |
5078 | serge | 369 | switch (bpc) { |
370 | case 0: |
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371 | case 6: |
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372 | case 8: |
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373 | case 16: |
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374 | default: |
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375 | DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", |
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376 | connector->name, bpc); |
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377 | break; |
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378 | case 10: |
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379 | val |= HDMI_DEEP_COLOR_ENABLE; |
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380 | val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR); |
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381 | DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", |
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382 | connector->name); |
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383 | break; |
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384 | case 12: |
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385 | val |= HDMI_DEEP_COLOR_ENABLE; |
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386 | val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR); |
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387 | DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", |
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388 | connector->name); |
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389 | break; |
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390 | } |
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2997 | Serge | 391 | |
5078 | serge | 392 | WREG32(HDMI_CONTROL + offset, val); |
2997 | Serge | 393 | |
394 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, |
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395 | HDMI_NULL_SEND | /* send null packets when required */ |
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396 | HDMI_GC_SEND | /* send general control packets */ |
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397 | HDMI_GC_CONT); /* send general control packets every frame */ |
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398 | |||
399 | WREG32(HDMI_INFOFRAME_CONTROL0 + offset, |
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400 | HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ |
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401 | HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ |
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402 | |||
403 | WREG32(AFMT_INFOFRAME_CONTROL0 + offset, |
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404 | AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ |
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405 | |||
406 | WREG32(HDMI_INFOFRAME_CONTROL1 + offset, |
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407 | HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */ |
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408 | |||
409 | WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ |
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410 | |||
5078 | serge | 411 | WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, |
412 | HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ |
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413 | HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ |
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414 | |||
415 | WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, |
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416 | AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ |
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417 | |||
418 | /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */ |
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419 | |||
420 | if (bpc > 8) |
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421 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, |
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422 | HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ |
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423 | else |
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424 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, |
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425 | HDMI_ACR_SOURCE | /* select SW CTS value */ |
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426 | HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ |
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427 | |||
428 | evergreen_hdmi_update_ACR(encoder, mode->clock); |
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429 | |||
430 | WREG32(AFMT_60958_0 + offset, |
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431 | AFMT_60958_CS_CHANNEL_NUMBER_L(1)); |
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432 | |||
433 | WREG32(AFMT_60958_1 + offset, |
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434 | AFMT_60958_CS_CHANNEL_NUMBER_R(2)); |
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435 | |||
436 | WREG32(AFMT_60958_2 + offset, |
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437 | AFMT_60958_CS_CHANNEL_NUMBER_2(3) | |
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438 | AFMT_60958_CS_CHANNEL_NUMBER_3(4) | |
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439 | AFMT_60958_CS_CHANNEL_NUMBER_4(5) | |
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440 | AFMT_60958_CS_CHANNEL_NUMBER_5(6) | |
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441 | AFMT_60958_CS_CHANNEL_NUMBER_6(7) | |
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442 | AFMT_60958_CS_CHANNEL_NUMBER_7(8)); |
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443 | |||
444 | if (ASIC_IS_DCE6(rdev)) { |
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445 | dce6_afmt_write_speaker_allocation(encoder); |
||
446 | } else { |
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447 | dce4_afmt_write_speaker_allocation(encoder); |
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448 | } |
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449 | |||
450 | WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset, |
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451 | AFMT_AUDIO_CHANNEL_ENABLE(0xff)); |
||
452 | |||
453 | /* fglrx sets 0x40 in 0x5f80 here */ |
||
454 | |||
455 | if (ASIC_IS_DCE6(rdev)) { |
||
456 | dce6_afmt_select_pin(encoder); |
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457 | dce6_afmt_write_sad_regs(encoder); |
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458 | dce6_afmt_write_latency_fields(encoder, mode); |
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459 | } else { |
||
460 | evergreen_hdmi_write_sad_regs(encoder); |
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461 | dce4_afmt_write_latency_fields(encoder, mode); |
||
462 | } |
||
463 | |||
3764 | Serge | 464 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); |
465 | if (err < 0) { |
||
466 | DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); |
||
467 | return; |
||
468 | } |
||
2997 | Serge | 469 | |
3764 | Serge | 470 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); |
471 | if (err < 0) { |
||
472 | DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); |
||
473 | return; |
||
474 | } |
||
475 | |||
476 | evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); |
||
2997 | Serge | 477 | |
5078 | serge | 478 | WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset, |
479 | HDMI_AVI_INFO_SEND | /* enable AVI info frames */ |
||
480 | HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */ |
||
481 | |||
482 | WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset, |
||
483 | HDMI_AVI_INFO_LINE(2), /* anything other than 0 */ |
||
484 | ~HDMI_AVI_INFO_LINE_MASK); |
||
485 | |||
486 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset, |
||
487 | AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */ |
||
488 | |||
2997 | Serge | 489 | /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ |
490 | WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); |
||
491 | WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); |
||
492 | WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); |
||
493 | WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); |
||
5078 | serge | 494 | |
495 | /* enable audio after to setting up hw */ |
||
496 | if (ASIC_IS_DCE6(rdev)) |
||
5271 | serge | 497 | dce6_audio_enable(rdev, dig->afmt->pin, 1); |
5078 | serge | 498 | else |
5271 | serge | 499 | dce4_audio_enable(rdev, dig->afmt->pin, 0xf); |
2997 | Serge | 500 | } |
5078 | serge | 501 | |
502 | void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) |
||
503 | { |
||
5271 | serge | 504 | struct drm_device *dev = encoder->dev; |
505 | struct radeon_device *rdev = dev->dev_private; |
||
5078 | serge | 506 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
507 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
||
508 | |||
509 | if (!dig || !dig->afmt) |
||
510 | return; |
||
511 | |||
512 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
||
513 | if (enable && dig->afmt->enabled) |
||
514 | return; |
||
515 | if (!enable && !dig->afmt->enabled) |
||
516 | return; |
||
517 | |||
5271 | serge | 518 | if (!enable && dig->afmt->pin) { |
519 | if (ASIC_IS_DCE6(rdev)) |
||
520 | dce6_audio_enable(rdev, dig->afmt->pin, 0); |
||
521 | else |
||
522 | dce4_audio_enable(rdev, dig->afmt->pin, 0); |
||
523 | dig->afmt->pin = NULL; |
||
524 | } |
||
525 | |||
5078 | serge | 526 | dig->afmt->enabled = enable; |
527 | |||
528 | DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
||
529 | enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); |
||
530 | }>>><>><>><>><>><>><>><>><>><>><>><>>>=>> |