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2997 | Serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Christian König. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Christian König |
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25 | * Rafał Miłecki |
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26 | */ |
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27 | #include |
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28 | #include |
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29 | #include "radeon.h" |
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30 | #include "radeon_asic.h" |
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31 | #include "evergreend.h" |
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32 | #include "atom.h" |
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33 | |||
34 | /* |
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35 | * update the N and CTS parameters for a given pixel clock rate |
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36 | */ |
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37 | static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) |
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38 | { |
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39 | struct drm_device *dev = encoder->dev; |
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40 | struct radeon_device *rdev = dev->dev_private; |
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41 | struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); |
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42 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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43 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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44 | uint32_t offset = dig->afmt->offset; |
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45 | |||
46 | WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz)); |
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47 | WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz); |
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48 | |||
49 | WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz)); |
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50 | WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz); |
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51 | |||
52 | WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz)); |
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53 | WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz); |
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54 | } |
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55 | |||
56 | /* |
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57 | * calculate the crc for a given info frame |
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58 | */ |
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59 | static void evergreen_hdmi_infoframe_checksum(uint8_t packetType, |
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60 | uint8_t versionNumber, |
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61 | uint8_t length, |
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62 | uint8_t *frame) |
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63 | { |
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64 | int i; |
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65 | frame[0] = packetType + versionNumber + length; |
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66 | for (i = 1; i <= length; i++) |
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67 | frame[0] += frame[i]; |
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68 | frame[0] = 0x100 - frame[0]; |
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69 | } |
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70 | |||
71 | /* |
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72 | * build a HDMI Video Info Frame |
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73 | */ |
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74 | static void evergreen_hdmi_videoinfoframe( |
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75 | struct drm_encoder *encoder, |
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76 | uint8_t color_format, |
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77 | int active_information_present, |
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78 | uint8_t active_format_aspect_ratio, |
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79 | uint8_t scan_information, |
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80 | uint8_t colorimetry, |
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81 | uint8_t ex_colorimetry, |
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82 | uint8_t quantization, |
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83 | int ITC, |
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84 | uint8_t picture_aspect_ratio, |
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85 | uint8_t video_format_identification, |
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86 | uint8_t pixel_repetition, |
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87 | uint8_t non_uniform_picture_scaling, |
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88 | uint8_t bar_info_data_valid, |
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89 | uint16_t top_bar, |
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90 | uint16_t bottom_bar, |
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91 | uint16_t left_bar, |
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92 | uint16_t right_bar |
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93 | ) |
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94 | { |
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95 | struct drm_device *dev = encoder->dev; |
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96 | struct radeon_device *rdev = dev->dev_private; |
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97 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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98 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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99 | uint32_t offset = dig->afmt->offset; |
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100 | |||
101 | uint8_t frame[14]; |
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102 | |||
103 | frame[0x0] = 0; |
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104 | frame[0x1] = |
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105 | (scan_information & 0x3) | |
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106 | ((bar_info_data_valid & 0x3) << 2) | |
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107 | ((active_information_present & 0x1) << 4) | |
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108 | ((color_format & 0x3) << 5); |
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109 | frame[0x2] = |
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110 | (active_format_aspect_ratio & 0xF) | |
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111 | ((picture_aspect_ratio & 0x3) << 4) | |
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112 | ((colorimetry & 0x3) << 6); |
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113 | frame[0x3] = |
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114 | (non_uniform_picture_scaling & 0x3) | |
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115 | ((quantization & 0x3) << 2) | |
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116 | ((ex_colorimetry & 0x7) << 4) | |
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117 | ((ITC & 0x1) << 7); |
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118 | frame[0x4] = (video_format_identification & 0x7F); |
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119 | frame[0x5] = (pixel_repetition & 0xF); |
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120 | frame[0x6] = (top_bar & 0xFF); |
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121 | frame[0x7] = (top_bar >> 8); |
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122 | frame[0x8] = (bottom_bar & 0xFF); |
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123 | frame[0x9] = (bottom_bar >> 8); |
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124 | frame[0xA] = (left_bar & 0xFF); |
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125 | frame[0xB] = (left_bar >> 8); |
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126 | frame[0xC] = (right_bar & 0xFF); |
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127 | frame[0xD] = (right_bar >> 8); |
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128 | |||
129 | evergreen_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame); |
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130 | /* Our header values (type, version, length) should be alright, Intel |
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131 | * is using the same. Checksum function also seems to be OK, it works |
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132 | * fine for audio infoframe. However calculated value is always lower |
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133 | * by 2 in comparison to fglrx. It breaks displaying anything in case |
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134 | * of TVs that strictly check the checksum. Hack it manually here to |
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135 | * workaround this issue. */ |
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136 | frame[0x0] += 2; |
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137 | |||
138 | WREG32(AFMT_AVI_INFO0 + offset, |
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139 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
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140 | WREG32(AFMT_AVI_INFO1 + offset, |
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141 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
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142 | WREG32(AFMT_AVI_INFO2 + offset, |
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143 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
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144 | WREG32(AFMT_AVI_INFO3 + offset, |
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145 | frame[0xC] | (frame[0xD] << 8)); |
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146 | } |
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147 | |||
148 | /* |
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149 | * update the info frames with the data from the current display mode |
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150 | */ |
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151 | void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) |
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152 | { |
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153 | struct drm_device *dev = encoder->dev; |
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154 | struct radeon_device *rdev = dev->dev_private; |
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155 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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156 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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157 | uint32_t offset; |
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158 | |||
159 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
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160 | if (!dig->afmt->enabled) |
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161 | return; |
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162 | offset = dig->afmt->offset; |
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163 | |||
164 | // r600_audio_set_clock(encoder, mode->clock); |
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165 | |||
166 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, |
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167 | HDMI_NULL_SEND); /* send null packets when required */ |
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168 | |||
169 | WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000); |
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170 | |||
171 | WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, |
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172 | HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ |
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173 | HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ |
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174 | |||
175 | WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, |
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176 | AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */ |
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177 | AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ |
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178 | |||
179 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, |
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180 | HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ |
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181 | HDMI_ACR_SOURCE); /* select SW CTS value */ |
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182 | |||
183 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, |
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184 | HDMI_NULL_SEND | /* send null packets when required */ |
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185 | HDMI_GC_SEND | /* send general control packets */ |
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186 | HDMI_GC_CONT); /* send general control packets every frame */ |
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187 | |||
188 | WREG32(HDMI_INFOFRAME_CONTROL0 + offset, |
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189 | HDMI_AVI_INFO_SEND | /* enable AVI info frames */ |
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190 | HDMI_AVI_INFO_CONT | /* send AVI info frames every frame/field */ |
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191 | HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ |
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192 | HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ |
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193 | |||
194 | WREG32(AFMT_INFOFRAME_CONTROL0 + offset, |
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195 | AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ |
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196 | |||
197 | WREG32(HDMI_INFOFRAME_CONTROL1 + offset, |
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198 | HDMI_AVI_INFO_LINE(2) | /* anything other than 0 */ |
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199 | HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */ |
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200 | |||
201 | WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ |
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202 | |||
203 | evergreen_hdmi_videoinfoframe(encoder, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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204 | 0, 0, 0, 0, 0, 0); |
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205 | |||
206 | evergreen_hdmi_update_ACR(encoder, mode->clock); |
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207 | |||
208 | /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ |
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209 | WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); |
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210 | WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); |
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211 | WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); |
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212 | WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); |
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213 | }><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>=> |