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Rev | Author | Line No. | Line |
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2005 | serge | 1 | /* |
2 | * Copyright 2010 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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21 | * DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Alex Deucher |
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25 | */ |
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26 | |||
2997 | Serge | 27 | #include |
28 | #include |
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2005 | serge | 29 | #include "radeon.h" |
30 | |||
31 | #include "evergreend.h" |
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32 | #include "evergreen_blit_shaders.h" |
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33 | #include "cayman_blit_shaders.h" |
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2997 | Serge | 34 | #include "radeon_blit_common.h" |
2005 | serge | 35 | |
36 | /* emits 17 */ |
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37 | static void |
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38 | set_render_target(struct radeon_device *rdev, int format, |
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39 | int w, int h, u64 gpu_addr) |
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40 | { |
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2997 | Serge | 41 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
2005 | serge | 42 | u32 cb_color_info; |
43 | int pitch, slice; |
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44 | |||
45 | h = ALIGN(h, 8); |
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46 | if (h < 8) |
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47 | h = 8; |
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48 | |||
2997 | Serge | 49 | cb_color_info = CB_FORMAT(format) | |
50 | CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) | |
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51 | CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1); |
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2005 | serge | 52 | pitch = (w / 8) - 1; |
53 | slice = ((w * h) / 64) - 1; |
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54 | |||
2997 | Serge | 55 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 15)); |
56 | radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2); |
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57 | radeon_ring_write(ring, gpu_addr >> 8); |
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58 | radeon_ring_write(ring, pitch); |
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59 | radeon_ring_write(ring, slice); |
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60 | radeon_ring_write(ring, 0); |
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61 | radeon_ring_write(ring, cb_color_info); |
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62 | radeon_ring_write(ring, 0); |
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63 | radeon_ring_write(ring, (w - 1) | ((h - 1) << 16)); |
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64 | radeon_ring_write(ring, 0); |
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65 | radeon_ring_write(ring, 0); |
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66 | radeon_ring_write(ring, 0); |
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67 | radeon_ring_write(ring, 0); |
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68 | radeon_ring_write(ring, 0); |
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69 | radeon_ring_write(ring, 0); |
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70 | radeon_ring_write(ring, 0); |
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71 | radeon_ring_write(ring, 0); |
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2005 | serge | 72 | } |
73 | |||
74 | /* emits 5dw */ |
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75 | static void |
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76 | cp_set_surface_sync(struct radeon_device *rdev, |
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77 | u32 sync_type, u32 size, |
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78 | u64 mc_addr) |
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79 | { |
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2997 | Serge | 80 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
2005 | serge | 81 | u32 cp_coher_size; |
82 | |||
83 | if (size == 0xffffffff) |
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84 | cp_coher_size = 0xffffffff; |
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85 | else |
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86 | cp_coher_size = ((size + 255) >> 8); |
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87 | |||
2997 | Serge | 88 | if (rdev->family >= CHIP_CAYMAN) { |
89 | /* CP_COHER_CNTL2 has to be set manually when submitting a surface_sync |
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90 | * to the RB directly. For IBs, the CP programs this as part of the |
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91 | * surface_sync packet. |
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92 | */ |
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93 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
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94 | radeon_ring_write(ring, (0x85e8 - PACKET3_SET_CONFIG_REG_START) >> 2); |
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95 | radeon_ring_write(ring, 0); /* CP_COHER_CNTL2 */ |
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96 | } |
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97 | radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
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98 | radeon_ring_write(ring, sync_type); |
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99 | radeon_ring_write(ring, cp_coher_size); |
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100 | radeon_ring_write(ring, mc_addr >> 8); |
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101 | radeon_ring_write(ring, 10); /* poll interval */ |
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2005 | serge | 102 | } |
103 | |||
104 | /* emits 11dw + 1 surface sync = 16dw */ |
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105 | static void |
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106 | set_shaders(struct radeon_device *rdev) |
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107 | { |
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2997 | Serge | 108 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
2005 | serge | 109 | u64 gpu_addr; |
110 | |||
111 | /* VS */ |
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112 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; |
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2997 | Serge | 113 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 3)); |
114 | radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2); |
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115 | radeon_ring_write(ring, gpu_addr >> 8); |
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116 | radeon_ring_write(ring, 2); |
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117 | radeon_ring_write(ring, 0); |
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2005 | serge | 118 | |
119 | /* PS */ |
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120 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset; |
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2997 | Serge | 121 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 4)); |
122 | radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2); |
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123 | radeon_ring_write(ring, gpu_addr >> 8); |
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124 | radeon_ring_write(ring, 1); |
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125 | radeon_ring_write(ring, 0); |
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126 | radeon_ring_write(ring, 2); |
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2005 | serge | 127 | |
128 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; |
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129 | cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); |
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130 | } |
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131 | |||
132 | /* emits 10 + 1 sync (5) = 15 */ |
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133 | static void |
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134 | set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) |
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135 | { |
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2997 | Serge | 136 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
2005 | serge | 137 | u32 sq_vtx_constant_word2, sq_vtx_constant_word3; |
138 | |||
139 | /* high addr, stride */ |
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2997 | Serge | 140 | sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) | |
141 | SQ_VTXC_STRIDE(16); |
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2005 | serge | 142 | #ifdef __BIG_ENDIAN |
2997 | Serge | 143 | sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32); |
2005 | serge | 144 | #endif |
145 | /* xyzw swizzles */ |
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2997 | Serge | 146 | sq_vtx_constant_word3 = SQ_VTCX_SEL_X(SQ_SEL_X) | |
147 | SQ_VTCX_SEL_Y(SQ_SEL_Y) | |
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148 | SQ_VTCX_SEL_Z(SQ_SEL_Z) | |
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149 | SQ_VTCX_SEL_W(SQ_SEL_W); |
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2005 | serge | 150 | |
2997 | Serge | 151 | radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 8)); |
152 | radeon_ring_write(ring, 0x580); |
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153 | radeon_ring_write(ring, gpu_addr & 0xffffffff); |
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154 | radeon_ring_write(ring, 48 - 1); /* size */ |
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155 | radeon_ring_write(ring, sq_vtx_constant_word2); |
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156 | radeon_ring_write(ring, sq_vtx_constant_word3); |
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157 | radeon_ring_write(ring, 0); |
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158 | radeon_ring_write(ring, 0); |
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159 | radeon_ring_write(ring, 0); |
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160 | radeon_ring_write(ring, S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_BUFFER)); |
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2005 | serge | 161 | |
162 | if ((rdev->family == CHIP_CEDAR) || |
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163 | (rdev->family == CHIP_PALM) || |
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164 | (rdev->family == CHIP_SUMO) || |
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165 | (rdev->family == CHIP_SUMO2) || |
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166 | (rdev->family == CHIP_CAICOS)) |
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167 | cp_set_surface_sync(rdev, |
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168 | PACKET3_TC_ACTION_ENA, 48, gpu_addr); |
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169 | else |
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170 | cp_set_surface_sync(rdev, |
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171 | PACKET3_VC_ACTION_ENA, 48, gpu_addr); |
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172 | |||
173 | } |
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174 | |||
175 | /* emits 10 */ |
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176 | static void |
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177 | set_tex_resource(struct radeon_device *rdev, |
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178 | int format, int w, int h, int pitch, |
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2997 | Serge | 179 | u64 gpu_addr, u32 size) |
2005 | serge | 180 | { |
2997 | Serge | 181 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
2005 | serge | 182 | u32 sq_tex_resource_word0, sq_tex_resource_word1; |
183 | u32 sq_tex_resource_word4, sq_tex_resource_word7; |
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184 | |||
185 | if (h < 1) |
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186 | h = 1; |
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187 | |||
2997 | Serge | 188 | sq_tex_resource_word0 = TEX_DIM(SQ_TEX_DIM_2D); |
2005 | serge | 189 | sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 6) | |
190 | ((w - 1) << 18)); |
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2997 | Serge | 191 | sq_tex_resource_word1 = ((h - 1) << 0) | |
192 | TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1); |
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2005 | serge | 193 | /* xyzw swizzles */ |
2997 | Serge | 194 | sq_tex_resource_word4 = TEX_DST_SEL_X(SQ_SEL_X) | |
195 | TEX_DST_SEL_Y(SQ_SEL_Y) | |
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196 | TEX_DST_SEL_Z(SQ_SEL_Z) | |
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197 | TEX_DST_SEL_W(SQ_SEL_W); |
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2005 | serge | 198 | |
2997 | Serge | 199 | sq_tex_resource_word7 = format | |
200 | S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_TEXTURE); |
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2005 | serge | 201 | |
2997 | Serge | 202 | cp_set_surface_sync(rdev, |
203 | PACKET3_TC_ACTION_ENA, size, gpu_addr); |
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204 | |||
205 | radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 8)); |
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206 | radeon_ring_write(ring, 0); |
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207 | radeon_ring_write(ring, sq_tex_resource_word0); |
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208 | radeon_ring_write(ring, sq_tex_resource_word1); |
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209 | radeon_ring_write(ring, gpu_addr >> 8); |
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210 | radeon_ring_write(ring, gpu_addr >> 8); |
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211 | radeon_ring_write(ring, sq_tex_resource_word4); |
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212 | radeon_ring_write(ring, 0); |
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213 | radeon_ring_write(ring, 0); |
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214 | radeon_ring_write(ring, sq_tex_resource_word7); |
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2005 | serge | 215 | } |
216 | |||
217 | /* emits 12 */ |
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218 | static void |
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219 | set_scissors(struct radeon_device *rdev, int x1, int y1, |
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220 | int x2, int y2) |
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221 | { |
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2997 | Serge | 222 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
2005 | serge | 223 | /* workaround some hw bugs */ |
224 | if (x2 == 0) |
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225 | x1 = 1; |
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226 | if (y2 == 0) |
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227 | y1 = 1; |
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2997 | Serge | 228 | if (rdev->family >= CHIP_CAYMAN) { |
2005 | serge | 229 | if ((x2 == 1) && (y2 == 1)) |
230 | x2 = 2; |
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231 | } |
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232 | |||
2997 | Serge | 233 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
234 | radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); |
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235 | radeon_ring_write(ring, (x1 << 0) | (y1 << 16)); |
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236 | radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); |
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2005 | serge | 237 | |
2997 | Serge | 238 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
239 | radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); |
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240 | radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); |
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241 | radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); |
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2005 | serge | 242 | |
2997 | Serge | 243 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
244 | radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); |
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245 | radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); |
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246 | radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); |
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2005 | serge | 247 | } |
248 | |||
249 | /* emits 10 */ |
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250 | static void |
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251 | draw_auto(struct radeon_device *rdev) |
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252 | { |
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2997 | Serge | 253 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
254 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
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255 | radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2); |
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256 | radeon_ring_write(ring, DI_PT_RECTLIST); |
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2005 | serge | 257 | |
2997 | Serge | 258 | radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0)); |
259 | radeon_ring_write(ring, |
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2005 | serge | 260 | #ifdef __BIG_ENDIAN |
261 | (2 << 2) | |
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262 | #endif |
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263 | DI_INDEX_SIZE_16_BIT); |
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264 | |||
2997 | Serge | 265 | radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0)); |
266 | radeon_ring_write(ring, 1); |
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2005 | serge | 267 | |
2997 | Serge | 268 | radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1)); |
269 | radeon_ring_write(ring, 3); |
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270 | radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX); |
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2005 | serge | 271 | |
272 | } |
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273 | |||
274 | /* emits 39 */ |
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275 | static void |
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276 | set_default_state(struct radeon_device *rdev) |
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277 | { |
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2997 | Serge | 278 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
2005 | serge | 279 | u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3; |
280 | u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2; |
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281 | u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3; |
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282 | int num_ps_gprs, num_vs_gprs, num_temp_gprs; |
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283 | int num_gs_gprs, num_es_gprs, num_hs_gprs, num_ls_gprs; |
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284 | int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads; |
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285 | int num_hs_threads, num_ls_threads; |
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286 | int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries; |
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287 | int num_hs_stack_entries, num_ls_stack_entries; |
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288 | u64 gpu_addr; |
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289 | int dwords; |
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290 | |||
291 | /* set clear context state */ |
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2997 | Serge | 292 | radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); |
293 | radeon_ring_write(ring, 0); |
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2005 | serge | 294 | |
295 | if (rdev->family < CHIP_CAYMAN) { |
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296 | switch (rdev->family) { |
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297 | case CHIP_CEDAR: |
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298 | default: |
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299 | num_ps_gprs = 93; |
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300 | num_vs_gprs = 46; |
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301 | num_temp_gprs = 4; |
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302 | num_gs_gprs = 31; |
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303 | num_es_gprs = 31; |
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304 | num_hs_gprs = 23; |
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305 | num_ls_gprs = 23; |
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306 | num_ps_threads = 96; |
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307 | num_vs_threads = 16; |
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308 | num_gs_threads = 16; |
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309 | num_es_threads = 16; |
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310 | num_hs_threads = 16; |
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311 | num_ls_threads = 16; |
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312 | num_ps_stack_entries = 42; |
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313 | num_vs_stack_entries = 42; |
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314 | num_gs_stack_entries = 42; |
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315 | num_es_stack_entries = 42; |
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316 | num_hs_stack_entries = 42; |
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317 | num_ls_stack_entries = 42; |
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318 | break; |
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319 | case CHIP_REDWOOD: |
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320 | num_ps_gprs = 93; |
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321 | num_vs_gprs = 46; |
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322 | num_temp_gprs = 4; |
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323 | num_gs_gprs = 31; |
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324 | num_es_gprs = 31; |
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325 | num_hs_gprs = 23; |
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326 | num_ls_gprs = 23; |
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327 | num_ps_threads = 128; |
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328 | num_vs_threads = 20; |
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329 | num_gs_threads = 20; |
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330 | num_es_threads = 20; |
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331 | num_hs_threads = 20; |
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332 | num_ls_threads = 20; |
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333 | num_ps_stack_entries = 42; |
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334 | num_vs_stack_entries = 42; |
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335 | num_gs_stack_entries = 42; |
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336 | num_es_stack_entries = 42; |
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337 | num_hs_stack_entries = 42; |
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338 | num_ls_stack_entries = 42; |
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339 | break; |
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340 | case CHIP_JUNIPER: |
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341 | num_ps_gprs = 93; |
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342 | num_vs_gprs = 46; |
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343 | num_temp_gprs = 4; |
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344 | num_gs_gprs = 31; |
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345 | num_es_gprs = 31; |
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346 | num_hs_gprs = 23; |
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347 | num_ls_gprs = 23; |
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348 | num_ps_threads = 128; |
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349 | num_vs_threads = 20; |
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350 | num_gs_threads = 20; |
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351 | num_es_threads = 20; |
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352 | num_hs_threads = 20; |
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353 | num_ls_threads = 20; |
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354 | num_ps_stack_entries = 85; |
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355 | num_vs_stack_entries = 85; |
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356 | num_gs_stack_entries = 85; |
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357 | num_es_stack_entries = 85; |
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358 | num_hs_stack_entries = 85; |
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359 | num_ls_stack_entries = 85; |
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360 | break; |
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361 | case CHIP_CYPRESS: |
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362 | case CHIP_HEMLOCK: |
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363 | num_ps_gprs = 93; |
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364 | num_vs_gprs = 46; |
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365 | num_temp_gprs = 4; |
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366 | num_gs_gprs = 31; |
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367 | num_es_gprs = 31; |
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368 | num_hs_gprs = 23; |
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369 | num_ls_gprs = 23; |
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370 | num_ps_threads = 128; |
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371 | num_vs_threads = 20; |
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372 | num_gs_threads = 20; |
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373 | num_es_threads = 20; |
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374 | num_hs_threads = 20; |
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375 | num_ls_threads = 20; |
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376 | num_ps_stack_entries = 85; |
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377 | num_vs_stack_entries = 85; |
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378 | num_gs_stack_entries = 85; |
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379 | num_es_stack_entries = 85; |
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380 | num_hs_stack_entries = 85; |
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381 | num_ls_stack_entries = 85; |
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382 | break; |
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383 | case CHIP_PALM: |
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384 | num_ps_gprs = 93; |
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385 | num_vs_gprs = 46; |
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386 | num_temp_gprs = 4; |
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387 | num_gs_gprs = 31; |
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388 | num_es_gprs = 31; |
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389 | num_hs_gprs = 23; |
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390 | num_ls_gprs = 23; |
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391 | num_ps_threads = 96; |
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392 | num_vs_threads = 16; |
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393 | num_gs_threads = 16; |
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394 | num_es_threads = 16; |
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395 | num_hs_threads = 16; |
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396 | num_ls_threads = 16; |
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397 | num_ps_stack_entries = 42; |
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398 | num_vs_stack_entries = 42; |
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399 | num_gs_stack_entries = 42; |
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400 | num_es_stack_entries = 42; |
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401 | num_hs_stack_entries = 42; |
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402 | num_ls_stack_entries = 42; |
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403 | break; |
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404 | case CHIP_SUMO: |
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405 | num_ps_gprs = 93; |
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406 | num_vs_gprs = 46; |
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407 | num_temp_gprs = 4; |
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408 | num_gs_gprs = 31; |
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409 | num_es_gprs = 31; |
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410 | num_hs_gprs = 23; |
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411 | num_ls_gprs = 23; |
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412 | num_ps_threads = 96; |
||
413 | num_vs_threads = 25; |
||
414 | num_gs_threads = 25; |
||
415 | num_es_threads = 25; |
||
416 | num_hs_threads = 25; |
||
417 | num_ls_threads = 25; |
||
418 | num_ps_stack_entries = 42; |
||
419 | num_vs_stack_entries = 42; |
||
420 | num_gs_stack_entries = 42; |
||
421 | num_es_stack_entries = 42; |
||
422 | num_hs_stack_entries = 42; |
||
423 | num_ls_stack_entries = 42; |
||
424 | break; |
||
425 | case CHIP_SUMO2: |
||
426 | num_ps_gprs = 93; |
||
427 | num_vs_gprs = 46; |
||
428 | num_temp_gprs = 4; |
||
429 | num_gs_gprs = 31; |
||
430 | num_es_gprs = 31; |
||
431 | num_hs_gprs = 23; |
||
432 | num_ls_gprs = 23; |
||
433 | num_ps_threads = 96; |
||
434 | num_vs_threads = 25; |
||
435 | num_gs_threads = 25; |
||
436 | num_es_threads = 25; |
||
437 | num_hs_threads = 25; |
||
438 | num_ls_threads = 25; |
||
439 | num_ps_stack_entries = 85; |
||
440 | num_vs_stack_entries = 85; |
||
441 | num_gs_stack_entries = 85; |
||
442 | num_es_stack_entries = 85; |
||
443 | num_hs_stack_entries = 85; |
||
444 | num_ls_stack_entries = 85; |
||
445 | break; |
||
446 | case CHIP_BARTS: |
||
447 | num_ps_gprs = 93; |
||
448 | num_vs_gprs = 46; |
||
449 | num_temp_gprs = 4; |
||
450 | num_gs_gprs = 31; |
||
451 | num_es_gprs = 31; |
||
452 | num_hs_gprs = 23; |
||
453 | num_ls_gprs = 23; |
||
454 | num_ps_threads = 128; |
||
455 | num_vs_threads = 20; |
||
456 | num_gs_threads = 20; |
||
457 | num_es_threads = 20; |
||
458 | num_hs_threads = 20; |
||
459 | num_ls_threads = 20; |
||
460 | num_ps_stack_entries = 85; |
||
461 | num_vs_stack_entries = 85; |
||
462 | num_gs_stack_entries = 85; |
||
463 | num_es_stack_entries = 85; |
||
464 | num_hs_stack_entries = 85; |
||
465 | num_ls_stack_entries = 85; |
||
466 | break; |
||
467 | case CHIP_TURKS: |
||
468 | num_ps_gprs = 93; |
||
469 | num_vs_gprs = 46; |
||
470 | num_temp_gprs = 4; |
||
471 | num_gs_gprs = 31; |
||
472 | num_es_gprs = 31; |
||
473 | num_hs_gprs = 23; |
||
474 | num_ls_gprs = 23; |
||
475 | num_ps_threads = 128; |
||
476 | num_vs_threads = 20; |
||
477 | num_gs_threads = 20; |
||
478 | num_es_threads = 20; |
||
479 | num_hs_threads = 20; |
||
480 | num_ls_threads = 20; |
||
481 | num_ps_stack_entries = 42; |
||
482 | num_vs_stack_entries = 42; |
||
483 | num_gs_stack_entries = 42; |
||
484 | num_es_stack_entries = 42; |
||
485 | num_hs_stack_entries = 42; |
||
486 | num_ls_stack_entries = 42; |
||
487 | break; |
||
488 | case CHIP_CAICOS: |
||
489 | num_ps_gprs = 93; |
||
490 | num_vs_gprs = 46; |
||
491 | num_temp_gprs = 4; |
||
492 | num_gs_gprs = 31; |
||
493 | num_es_gprs = 31; |
||
494 | num_hs_gprs = 23; |
||
495 | num_ls_gprs = 23; |
||
496 | num_ps_threads = 128; |
||
497 | num_vs_threads = 10; |
||
498 | num_gs_threads = 10; |
||
499 | num_es_threads = 10; |
||
500 | num_hs_threads = 10; |
||
501 | num_ls_threads = 10; |
||
502 | num_ps_stack_entries = 42; |
||
503 | num_vs_stack_entries = 42; |
||
504 | num_gs_stack_entries = 42; |
||
505 | num_es_stack_entries = 42; |
||
506 | num_hs_stack_entries = 42; |
||
507 | num_ls_stack_entries = 42; |
||
508 | break; |
||
509 | } |
||
510 | |||
511 | if ((rdev->family == CHIP_CEDAR) || |
||
512 | (rdev->family == CHIP_PALM) || |
||
513 | (rdev->family == CHIP_SUMO) || |
||
514 | (rdev->family == CHIP_SUMO2) || |
||
515 | (rdev->family == CHIP_CAICOS)) |
||
516 | sq_config = 0; |
||
517 | else |
||
518 | sq_config = VC_ENABLE; |
||
519 | |||
520 | sq_config |= (EXPORT_SRC_C | |
||
521 | CS_PRIO(0) | |
||
522 | LS_PRIO(0) | |
||
523 | HS_PRIO(0) | |
||
524 | PS_PRIO(0) | |
||
525 | VS_PRIO(1) | |
||
526 | GS_PRIO(2) | |
||
527 | ES_PRIO(3)); |
||
528 | |||
529 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) | |
||
530 | NUM_VS_GPRS(num_vs_gprs) | |
||
531 | NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); |
||
532 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) | |
||
533 | NUM_ES_GPRS(num_es_gprs)); |
||
534 | sq_gpr_resource_mgmt_3 = (NUM_HS_GPRS(num_hs_gprs) | |
||
535 | NUM_LS_GPRS(num_ls_gprs)); |
||
536 | sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) | |
||
537 | NUM_VS_THREADS(num_vs_threads) | |
||
538 | NUM_GS_THREADS(num_gs_threads) | |
||
539 | NUM_ES_THREADS(num_es_threads)); |
||
540 | sq_thread_resource_mgmt_2 = (NUM_HS_THREADS(num_hs_threads) | |
||
541 | NUM_LS_THREADS(num_ls_threads)); |
||
542 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) | |
||
543 | NUM_VS_STACK_ENTRIES(num_vs_stack_entries)); |
||
544 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) | |
||
545 | NUM_ES_STACK_ENTRIES(num_es_stack_entries)); |
||
546 | sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) | |
||
547 | NUM_LS_STACK_ENTRIES(num_ls_stack_entries)); |
||
548 | |||
549 | /* disable dyn gprs */ |
||
2997 | Serge | 550 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
551 | radeon_ring_write(ring, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2); |
||
552 | radeon_ring_write(ring, 0); |
||
2005 | serge | 553 | |
554 | /* setup LDS */ |
||
2997 | Serge | 555 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
556 | radeon_ring_write(ring, (SQ_LDS_RESOURCE_MGMT - PACKET3_SET_CONFIG_REG_START) >> 2); |
||
557 | radeon_ring_write(ring, 0x10001000); |
||
2005 | serge | 558 | |
559 | /* SQ config */ |
||
2997 | Serge | 560 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 11)); |
561 | radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2); |
||
562 | radeon_ring_write(ring, sq_config); |
||
563 | radeon_ring_write(ring, sq_gpr_resource_mgmt_1); |
||
564 | radeon_ring_write(ring, sq_gpr_resource_mgmt_2); |
||
565 | radeon_ring_write(ring, sq_gpr_resource_mgmt_3); |
||
566 | radeon_ring_write(ring, 0); |
||
567 | radeon_ring_write(ring, 0); |
||
568 | radeon_ring_write(ring, sq_thread_resource_mgmt); |
||
569 | radeon_ring_write(ring, sq_thread_resource_mgmt_2); |
||
570 | radeon_ring_write(ring, sq_stack_resource_mgmt_1); |
||
571 | radeon_ring_write(ring, sq_stack_resource_mgmt_2); |
||
572 | radeon_ring_write(ring, sq_stack_resource_mgmt_3); |
||
2005 | serge | 573 | } |
574 | |||
575 | /* CONTEXT_CONTROL */ |
||
2997 | Serge | 576 | radeon_ring_write(ring, 0xc0012800); |
577 | radeon_ring_write(ring, 0x80000000); |
||
578 | radeon_ring_write(ring, 0x80000000); |
||
2005 | serge | 579 | |
580 | /* SQ_VTX_BASE_VTX_LOC */ |
||
2997 | Serge | 581 | radeon_ring_write(ring, 0xc0026f00); |
582 | radeon_ring_write(ring, 0x00000000); |
||
583 | radeon_ring_write(ring, 0x00000000); |
||
584 | radeon_ring_write(ring, 0x00000000); |
||
2005 | serge | 585 | |
586 | /* SET_SAMPLER */ |
||
2997 | Serge | 587 | radeon_ring_write(ring, 0xc0036e00); |
588 | radeon_ring_write(ring, 0x00000000); |
||
589 | radeon_ring_write(ring, 0x00000012); |
||
590 | radeon_ring_write(ring, 0x00000000); |
||
591 | radeon_ring_write(ring, 0x00000000); |
||
2005 | serge | 592 | |
593 | /* set to DX10/11 mode */ |
||
2997 | Serge | 594 | radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); |
595 | radeon_ring_write(ring, 1); |
||
2005 | serge | 596 | |
597 | /* emit an IB pointing at default state */ |
||
598 | dwords = ALIGN(rdev->r600_blit.state_len, 0x10); |
||
599 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; |
||
2997 | Serge | 600 | radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
601 | radeon_ring_write(ring, gpu_addr & 0xFFFFFFFC); |
||
602 | radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF); |
||
603 | radeon_ring_write(ring, dwords); |
||
2005 | serge | 604 | |
605 | } |
||
606 | |||
607 | int evergreen_blit_init(struct radeon_device *rdev) |
||
608 | { |
||
609 | u32 obj_size; |
||
610 | int i, r, dwords; |
||
611 | void *ptr; |
||
612 | u32 packet2s[16]; |
||
613 | int num_packet2s = 0; |
||
2997 | Serge | 614 | #if 0 |
615 | rdev->r600_blit.primitives.set_render_target = set_render_target; |
||
616 | rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync; |
||
617 | rdev->r600_blit.primitives.set_shaders = set_shaders; |
||
618 | rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource; |
||
619 | rdev->r600_blit.primitives.set_tex_resource = set_tex_resource; |
||
620 | rdev->r600_blit.primitives.set_scissors = set_scissors; |
||
621 | rdev->r600_blit.primitives.draw_auto = draw_auto; |
||
622 | rdev->r600_blit.primitives.set_default_state = set_default_state; |
||
2005 | serge | 623 | |
2997 | Serge | 624 | rdev->r600_blit.ring_size_common = 8; /* sync semaphore */ |
625 | rdev->r600_blit.ring_size_common += 55; /* shaders + def state */ |
||
626 | rdev->r600_blit.ring_size_common += 16; /* fence emit for VB IB */ |
||
627 | rdev->r600_blit.ring_size_common += 5; /* done copy */ |
||
628 | rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */ |
||
629 | |||
630 | rdev->r600_blit.ring_size_per_loop = 74; |
||
631 | if (rdev->family >= CHIP_CAYMAN) |
||
632 | rdev->r600_blit.ring_size_per_loop += 9; /* additional DWs for surface sync */ |
||
633 | |||
634 | rdev->r600_blit.max_dim = 16384; |
||
635 | |||
2005 | serge | 636 | /* pin copy shader into vram if already initialized */ |
637 | if (rdev->r600_blit.shader_obj) |
||
638 | goto done; |
||
639 | |||
640 | mutex_init(&rdev->r600_blit.mutex); |
||
641 | rdev->r600_blit.state_offset = 0; |
||
642 | |||
643 | if (rdev->family < CHIP_CAYMAN) |
||
644 | rdev->r600_blit.state_len = evergreen_default_size; |
||
645 | else |
||
646 | rdev->r600_blit.state_len = cayman_default_size; |
||
647 | |||
648 | dwords = rdev->r600_blit.state_len; |
||
649 | while (dwords & 0xf) { |
||
650 | packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0)); |
||
651 | dwords++; |
||
652 | } |
||
653 | |||
654 | obj_size = dwords * 4; |
||
655 | obj_size = ALIGN(obj_size, 256); |
||
656 | |||
657 | rdev->r600_blit.vs_offset = obj_size; |
||
658 | if (rdev->family < CHIP_CAYMAN) |
||
659 | obj_size += evergreen_vs_size * 4; |
||
660 | else |
||
661 | obj_size += cayman_vs_size * 4; |
||
662 | obj_size = ALIGN(obj_size, 256); |
||
663 | |||
664 | rdev->r600_blit.ps_offset = obj_size; |
||
665 | if (rdev->family < CHIP_CAYMAN) |
||
666 | obj_size += evergreen_ps_size * 4; |
||
667 | else |
||
668 | obj_size += cayman_ps_size * 4; |
||
669 | obj_size = ALIGN(obj_size, 256); |
||
670 | |||
671 | r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, |
||
672 | &rdev->r600_blit.shader_obj); |
||
673 | if (r) { |
||
674 | DRM_ERROR("evergreen failed to allocate shader\n"); |
||
675 | return r; |
||
676 | } |
||
677 | |||
678 | DRM_DEBUG("evergreen blit allocated bo %08x vs %08x ps %08x\n", |
||
679 | obj_size, |
||
680 | rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset); |
||
681 | |||
682 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
||
683 | if (unlikely(r != 0)) |
||
684 | return r; |
||
685 | r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr); |
||
686 | if (r) { |
||
687 | DRM_ERROR("failed to map blit object %d\n", r); |
||
688 | return r; |
||
689 | } |
||
690 | |||
691 | if (rdev->family < CHIP_CAYMAN) { |
||
692 | memcpy(ptr + rdev->r600_blit.state_offset, |
||
693 | evergreen_default_state, rdev->r600_blit.state_len * 4); |
||
694 | |||
695 | if (num_packet2s) |
||
696 | memcpy(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), |
||
697 | packet2s, num_packet2s * 4); |
||
698 | for (i = 0; i < evergreen_vs_size; i++) |
||
699 | *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(evergreen_vs[i]); |
||
700 | for (i = 0; i < evergreen_ps_size; i++) |
||
701 | *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(evergreen_ps[i]); |
||
702 | } else { |
||
703 | memcpy(ptr + rdev->r600_blit.state_offset, |
||
704 | cayman_default_state, rdev->r600_blit.state_len * 4); |
||
705 | |||
706 | if (num_packet2s) |
||
707 | memcpy(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), |
||
708 | packet2s, num_packet2s * 4); |
||
709 | for (i = 0; i < cayman_vs_size; i++) |
||
710 | *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(cayman_vs[i]); |
||
711 | for (i = 0; i < cayman_ps_size; i++) |
||
712 | *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(cayman_ps[i]); |
||
713 | } |
||
714 | radeon_bo_kunmap(rdev->r600_blit.shader_obj); |
||
715 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
||
716 | |||
717 | done: |
||
718 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
||
719 | if (unlikely(r != 0)) |
||
720 | return r; |
||
721 | r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, |
||
722 | &rdev->r600_blit.shader_gpu_addr); |
||
723 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
||
724 | if (r) { |
||
725 | dev_err(rdev->dev, "(%d) pin blit object failed\n", r); |
||
726 | return r; |
||
727 | } |
||
728 | // radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
||
729 | |||
2997 | Serge | 730 | #endif |
2005 | serge | 731 | |
732 | return 0; |
||
733 | }>>>>>>>>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>> |