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5078 | serge | 1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. |
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3 | * Copyright 2014 Rafał Miłecki |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice shall be included in |
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13 | * all copies or substantial portions of the Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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21 | * OTHER DEALINGS IN THE SOFTWARE. |
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22 | */ |
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23 | #include |
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24 | #include |
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25 | #include "radeon.h" |
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26 | #include "radeon_asic.h" |
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27 | #include "r600d.h" |
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28 | |||
29 | static void dce3_2_afmt_write_speaker_allocation(struct drm_encoder *encoder) |
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30 | { |
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31 | struct radeon_device *rdev = encoder->dev->dev_private; |
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32 | struct drm_connector *connector; |
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33 | struct radeon_connector *radeon_connector = NULL; |
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34 | u32 tmp; |
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35 | u8 *sadb; |
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36 | int sad_count; |
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37 | |||
38 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
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39 | if (connector->encoder == encoder) { |
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40 | radeon_connector = to_radeon_connector(connector); |
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41 | break; |
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42 | } |
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43 | } |
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44 | |||
45 | if (!radeon_connector) { |
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46 | DRM_ERROR("Couldn't find encoder's connector\n"); |
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47 | return; |
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48 | } |
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49 | |||
50 | sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb); |
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51 | if (sad_count < 0) { |
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52 | DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); |
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53 | return; |
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54 | } |
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55 | |||
56 | /* program the speaker allocation */ |
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57 | tmp = RREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); |
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58 | tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); |
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59 | /* set HDMI mode */ |
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60 | tmp |= HDMI_CONNECTION; |
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61 | if (sad_count) |
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62 | tmp |= SPEAKER_ALLOCATION(sadb[0]); |
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63 | else |
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64 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ |
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65 | WREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); |
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66 | |||
67 | kfree(sadb); |
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68 | } |
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69 | |||
70 | static void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder) |
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71 | { |
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72 | struct radeon_device *rdev = encoder->dev->dev_private; |
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73 | struct drm_connector *connector; |
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74 | struct radeon_connector *radeon_connector = NULL; |
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75 | struct cea_sad *sads; |
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76 | int i, sad_count; |
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77 | |||
78 | static const u16 eld_reg_to_type[][2] = { |
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79 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, |
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80 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, |
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81 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, |
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82 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, |
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83 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, |
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84 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, |
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85 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, |
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86 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, |
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87 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, |
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88 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, |
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89 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, |
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90 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, |
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91 | }; |
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92 | |||
93 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
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94 | if (connector->encoder == encoder) { |
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95 | radeon_connector = to_radeon_connector(connector); |
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96 | break; |
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97 | } |
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98 | } |
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99 | |||
100 | if (!radeon_connector) { |
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101 | DRM_ERROR("Couldn't find encoder's connector\n"); |
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102 | return; |
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103 | } |
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104 | |||
105 | sad_count = drm_edid_to_sad(radeon_connector->edid, &sads); |
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106 | if (sad_count < 0) { |
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107 | DRM_ERROR("Couldn't read SADs: %d\n", sad_count); |
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108 | return; |
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109 | } |
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110 | BUG_ON(!sads); |
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111 | |||
112 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { |
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113 | u32 value = 0; |
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114 | u8 stereo_freqs = 0; |
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115 | int max_channels = -1; |
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116 | int j; |
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117 | |||
118 | for (j = 0; j < sad_count; j++) { |
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119 | struct cea_sad *sad = &sads[j]; |
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120 | |||
121 | if (sad->format == eld_reg_to_type[i][1]) { |
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122 | if (sad->channels > max_channels) { |
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123 | value = MAX_CHANNELS(sad->channels) | |
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124 | DESCRIPTOR_BYTE_2(sad->byte2) | |
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125 | SUPPORTED_FREQUENCIES(sad->freq); |
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126 | max_channels = sad->channels; |
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127 | } |
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128 | |||
129 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) |
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130 | stereo_freqs |= sad->freq; |
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131 | else |
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132 | break; |
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133 | } |
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134 | } |
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135 | |||
136 | value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); |
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137 | |||
138 | WREG32(eld_reg_to_type[i][0], value); |
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139 | } |
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140 | |||
141 | kfree(sads); |
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142 | } |
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143 | |||
144 | /* |
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145 | * update the info frames with the data from the current display mode |
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146 | */ |
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147 | void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) |
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148 | { |
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149 | struct drm_device *dev = encoder->dev; |
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150 | struct radeon_device *rdev = dev->dev_private; |
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151 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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152 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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153 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; |
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154 | struct hdmi_avi_infoframe frame; |
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155 | uint32_t offset; |
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156 | ssize_t err; |
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157 | |||
158 | if (!dig || !dig->afmt) |
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159 | return; |
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160 | |||
161 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
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162 | if (!dig->afmt->enabled) |
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163 | return; |
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164 | offset = dig->afmt->offset; |
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165 | |||
166 | /* disable audio prior to setting up hw */ |
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167 | dig->afmt->pin = r600_audio_get_pin(rdev); |
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168 | r600_audio_enable(rdev, dig->afmt->pin, false); |
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169 | |||
170 | r600_audio_set_dto(encoder, mode->clock); |
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171 | |||
172 | WREG32(HDMI0_VBI_PACKET_CONTROL + offset, |
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173 | HDMI0_NULL_SEND); /* send null packets when required */ |
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174 | |||
175 | WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); |
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176 | |||
177 | if (ASIC_IS_DCE32(rdev)) { |
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178 | WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, |
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179 | HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ |
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180 | HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ |
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181 | WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, |
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182 | AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */ |
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183 | AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ |
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184 | } else { |
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185 | WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, |
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186 | HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ |
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187 | HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ |
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188 | HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */ |
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189 | HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ |
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190 | } |
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191 | |||
192 | if (ASIC_IS_DCE32(rdev)) { |
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193 | dce3_2_afmt_write_speaker_allocation(encoder); |
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194 | dce3_2_afmt_write_sad_regs(encoder); |
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195 | } |
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196 | |||
197 | WREG32(HDMI0_ACR_PACKET_CONTROL + offset, |
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198 | HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */ |
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199 | HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ |
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200 | |||
201 | WREG32(HDMI0_VBI_PACKET_CONTROL + offset, |
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202 | HDMI0_NULL_SEND | /* send null packets when required */ |
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203 | HDMI0_GC_SEND | /* send general control packets */ |
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204 | HDMI0_GC_CONT); /* send general control packets every frame */ |
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205 | |||
206 | /* TODO: HDMI0_AUDIO_INFO_UPDATE */ |
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207 | WREG32(HDMI0_INFOFRAME_CONTROL0 + offset, |
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208 | HDMI0_AVI_INFO_SEND | /* enable AVI info frames */ |
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209 | HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */ |
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210 | HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ |
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211 | HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */ |
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212 | |||
213 | WREG32(HDMI0_INFOFRAME_CONTROL1 + offset, |
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214 | HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */ |
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215 | HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */ |
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216 | |||
217 | WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */ |
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218 | |||
219 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); |
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220 | if (err < 0) { |
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221 | DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); |
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222 | return; |
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223 | } |
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224 | |||
225 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); |
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226 | if (err < 0) { |
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227 | DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); |
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228 | return; |
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229 | } |
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230 | |||
231 | r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); |
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232 | r600_hdmi_update_ACR(encoder, mode->clock); |
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233 | |||
234 | /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ |
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235 | WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF); |
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236 | WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF); |
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237 | WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001); |
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238 | WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); |
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239 | |||
240 | r600_hdmi_audio_workaround(encoder); |
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241 | |||
242 | /* enable audio after to setting up hw */ |
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243 | r600_audio_enable(rdev, dig->afmt->pin, true); |
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244 | }>>>>>> |