WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/cypress_dpm.c

Rev	Author	Line No.	Line
5078	serge	1	/*
		2	* Copyright 2011 Advanced Micro Devices, Inc.
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice shall be included in
		12	* all copies or substantial portions of the Software.
		13	*
		14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		20	* OTHER DEALINGS IN THE SOFTWARE.
		21	*
		22	* Authors: Alex Deucher
		23	*/
		24
		25	#include "drmP.h"
		26	#include "radeon.h"
		27	#include "evergreend.h"
		28	#include "r600_dpm.h"
		29	#include "cypress_dpm.h"
		30	#include "atom.h"
		31
		32	#define SMC_RAM_END 0x8000
		33
		34	#define MC_CG_ARB_FREQ_F0 0x0a
		35	#define MC_CG_ARB_FREQ_F1 0x0b
		36	#define MC_CG_ARB_FREQ_F2 0x0c
		37	#define MC_CG_ARB_FREQ_F3 0x0d
		38
		39	#define MC_CG_SEQ_DRAMCONF_S0 0x05
		40	#define MC_CG_SEQ_DRAMCONF_S1 0x06
		41	#define MC_CG_SEQ_YCLK_SUSPEND 0x04
		42	#define MC_CG_SEQ_YCLK_RESUME 0x0a
		43
		44	struct rv7xx_ps rv770_get_ps(struct radeon_ps rps);
		45	struct rv7xx_power_info rv770_get_pi(struct radeon_device rdev);
		46	struct evergreen_power_info evergreen_get_pi(struct radeon_device rdev);
		47
		48	static void cypress_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
		49	bool enable)
		50	{
		51	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
		52	u32 tmp, bif;
		53
		54	tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
		55	if (enable) {
		56	if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
		57	(tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
		58	if (!pi->boot_in_gen2) {
		59	bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
		60	bif \|= CG_CLIENT_REQ(0xd);
		61	WREG32(CG_BIF_REQ_AND_RSP, bif);
		62
		63	tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
		64	tmp \|= LC_HW_VOLTAGE_IF_CONTROL(1);
		65	tmp \|= LC_GEN2_EN_STRAP;
		66
		67	tmp \|= LC_CLR_FAILED_SPD_CHANGE_CNT;
		68	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
		69	udelay(10);
		70	tmp &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
		71	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
		72	}
		73	}
		74	} else {
		75	if (!pi->boot_in_gen2) {
		76	tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
		77	tmp &= ~LC_GEN2_EN_STRAP;
		78	}
		79	if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) \|\|
		80	(tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
		81	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
		82	}
		83	}
		84
		85	static void cypress_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
		86	bool enable)
		87	{
		88	cypress_enable_bif_dynamic_pcie_gen2(rdev, enable);
		89
		90	if (enable)
		91	WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
		92	else
		93	WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
		94	}
		95
		96	#if 0
		97	static int cypress_enter_ulp_state(struct radeon_device *rdev)
		98	{
		99	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
		100
		101	if (pi->gfx_clock_gating) {
		102	WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
		103	WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
		104	WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
		105
		106	RREG32(GB_ADDR_CONFIG);
		107	}
		108
		109	WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),
		110	~HOST_SMC_MSG_MASK);
		111
		112	udelay(7000);
		113
		114	return 0;
		115	}
		116	#endif
		117
		118	static void cypress_gfx_clock_gating_enable(struct radeon_device *rdev,
		119	bool enable)
		120	{
		121	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		122
		123	if (enable) {
		124	if (eg_pi->light_sleep) {
		125	WREG32(GRBM_GFX_INDEX, 0xC0000000);
		126
		127	WREG32_CG(CG_CGLS_TILE_0, 0xFFFFFFFF);
		128	WREG32_CG(CG_CGLS_TILE_1, 0xFFFFFFFF);
		129	WREG32_CG(CG_CGLS_TILE_2, 0xFFFFFFFF);
		130	WREG32_CG(CG_CGLS_TILE_3, 0xFFFFFFFF);
		131	WREG32_CG(CG_CGLS_TILE_4, 0xFFFFFFFF);
		132	WREG32_CG(CG_CGLS_TILE_5, 0xFFFFFFFF);
		133	WREG32_CG(CG_CGLS_TILE_6, 0xFFFFFFFF);
		134	WREG32_CG(CG_CGLS_TILE_7, 0xFFFFFFFF);
		135	WREG32_CG(CG_CGLS_TILE_8, 0xFFFFFFFF);
		136	WREG32_CG(CG_CGLS_TILE_9, 0xFFFFFFFF);
		137	WREG32_CG(CG_CGLS_TILE_10, 0xFFFFFFFF);
		138	WREG32_CG(CG_CGLS_TILE_11, 0xFFFFFFFF);
		139
		140	WREG32_P(SCLK_PWRMGT_CNTL, DYN_LIGHT_SLEEP_EN, ~DYN_LIGHT_SLEEP_EN);
		141	}
		142	WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
		143	} else {
		144	WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
		145	WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
		146	WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
		147	RREG32(GB_ADDR_CONFIG);
		148
		149	if (eg_pi->light_sleep) {
		150	WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_LIGHT_SLEEP_EN);
		151
		152	WREG32(GRBM_GFX_INDEX, 0xC0000000);
		153
		154	WREG32_CG(CG_CGLS_TILE_0, 0);
		155	WREG32_CG(CG_CGLS_TILE_1, 0);
		156	WREG32_CG(CG_CGLS_TILE_2, 0);
		157	WREG32_CG(CG_CGLS_TILE_3, 0);
		158	WREG32_CG(CG_CGLS_TILE_4, 0);
		159	WREG32_CG(CG_CGLS_TILE_5, 0);
		160	WREG32_CG(CG_CGLS_TILE_6, 0);
		161	WREG32_CG(CG_CGLS_TILE_7, 0);
		162	WREG32_CG(CG_CGLS_TILE_8, 0);
		163	WREG32_CG(CG_CGLS_TILE_9, 0);
		164	WREG32_CG(CG_CGLS_TILE_10, 0);
		165	WREG32_CG(CG_CGLS_TILE_11, 0);
		166	}
		167	}
		168	}
		169
		170	static void cypress_mg_clock_gating_enable(struct radeon_device *rdev,
		171	bool enable)
		172	{
		173	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
		174	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		175
		176	if (enable) {
		177	u32 cgts_sm_ctrl_reg;
		178
		179	if (rdev->family == CHIP_CEDAR)
		180	cgts_sm_ctrl_reg = CEDAR_MGCGCGTSSMCTRL_DFLT;
		181	else if (rdev->family == CHIP_REDWOOD)
		182	cgts_sm_ctrl_reg = REDWOOD_MGCGCGTSSMCTRL_DFLT;
		183	else
		184	cgts_sm_ctrl_reg = CYPRESS_MGCGCGTSSMCTRL_DFLT;
		185
		186	WREG32(GRBM_GFX_INDEX, 0xC0000000);
		187
		188	WREG32_CG(CG_CGTT_LOCAL_0, CYPRESS_MGCGTTLOCAL0_DFLT);
		189	WREG32_CG(CG_CGTT_LOCAL_1, CYPRESS_MGCGTTLOCAL1_DFLT & 0xFFFFCFFF);
		190	WREG32_CG(CG_CGTT_LOCAL_2, CYPRESS_MGCGTTLOCAL2_DFLT);
		191	WREG32_CG(CG_CGTT_LOCAL_3, CYPRESS_MGCGTTLOCAL3_DFLT);
		192
		193	if (pi->mgcgtssm)
		194	WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
		195
		196	if (eg_pi->mcls) {
		197	WREG32_P(MC_CITF_MISC_RD_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
		198	WREG32_P(MC_CITF_MISC_WR_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
		199	WREG32_P(MC_CITF_MISC_VM_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
		200	WREG32_P(MC_HUB_MISC_HUB_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
		201	WREG32_P(MC_HUB_MISC_VM_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
		202	WREG32_P(MC_HUB_MISC_SIP_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
		203	WREG32_P(MC_XPB_CLK_GAT, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
		204	WREG32_P(VM_L2_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
		205	}
		206	} else {
		207	WREG32(GRBM_GFX_INDEX, 0xC0000000);
		208
		209	WREG32_CG(CG_CGTT_LOCAL_0, 0xFFFFFFFF);
		210	WREG32_CG(CG_CGTT_LOCAL_1, 0xFFFFFFFF);
		211	WREG32_CG(CG_CGTT_LOCAL_2, 0xFFFFFFFF);
		212	WREG32_CG(CG_CGTT_LOCAL_3, 0xFFFFFFFF);
		213
		214	if (pi->mgcgtssm)
		215	WREG32(CGTS_SM_CTRL_REG, 0x81f44bc0);
		216	}
		217	}
		218
		219	void cypress_enable_spread_spectrum(struct radeon_device *rdev,
		220	bool enable)
		221	{
		222	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
		223
		224	if (enable) {
		225	if (pi->sclk_ss)
		226	WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
		227
		228	if (pi->mclk_ss)
		229	WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN);
		230	} else {
		231	WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
		232	WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
		233	WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN);
		234	WREG32_P(MPLL_CNTL_MODE, 0, ~SS_DSMODE_EN);
		235	}
		236	}
		237
		238	void cypress_start_dpm(struct radeon_device *rdev)
		239	{
		240	WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
		241	}
		242
		243	void cypress_enable_sclk_control(struct radeon_device *rdev,
		244	bool enable)
		245	{
		246	if (enable)
		247	WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
		248	else
		249	WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
		250	}
		251
		252	void cypress_enable_mclk_control(struct radeon_device *rdev,
		253	bool enable)
		254	{
		255	if (enable)
		256	WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);
		257	else
		258	WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);
		259	}
		260
		261	int cypress_notify_smc_display_change(struct radeon_device *rdev,
		262	bool has_display)
		263	{
		264	PPSMC_Msg msg = has_display ?
		265	(PPSMC_Msg)PPSMC_MSG_HasDisplay : (PPSMC_Msg)PPSMC_MSG_NoDisplay;
		266
		267	if (rv770_send_msg_to_smc(rdev, msg) != PPSMC_Result_OK)
		268	return -EINVAL;
		269
		270	return 0;
		271	}
		272
		273	void cypress_program_response_times(struct radeon_device *rdev)
		274	{
		275	u32 reference_clock;
		276	u32 mclk_switch_limit;
		277
		278	reference_clock = radeon_get_xclk(rdev);
		279	mclk_switch_limit = (460 * reference_clock) / 100;
		280
		281	rv770_write_smc_soft_register(rdev,
		282	RV770_SMC_SOFT_REGISTER_mclk_switch_lim,
		283	mclk_switch_limit);
		284
		285	rv770_write_smc_soft_register(rdev,
		286	RV770_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
		287
		288	rv770_write_smc_soft_register(rdev,
		289	RV770_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
		290
		291	rv770_program_response_times(rdev);
		292
		293	if (ASIC_IS_LOMBOK(rdev))
		294	rv770_write_smc_soft_register(rdev,
		295	RV770_SMC_SOFT_REGISTER_is_asic_lombok, 1);
		296
		297	}
		298
		299	static int cypress_pcie_performance_request(struct radeon_device *rdev,
		300	u8 perf_req, bool advertise)
		301	{
		302	#if defined(CONFIG_ACPI)
		303	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		304	#endif
		305	u32 tmp;
		306
		307	udelay(10);
		308	tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
		309	if ((perf_req == PCIE_PERF_REQ_PECI_GEN1) && (tmp & LC_CURRENT_DATA_RATE))
		310	return 0;
		311
		312	#if defined(CONFIG_ACPI)
		313	if ((perf_req == PCIE_PERF_REQ_PECI_GEN1) \|\|
		314	(perf_req == PCIE_PERF_REQ_PECI_GEN2)) {
		315	eg_pi->pcie_performance_request_registered = true;
		316	return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);
		317	} else if ((perf_req == PCIE_PERF_REQ_REMOVE_REGISTRY) &&
		318	eg_pi->pcie_performance_request_registered) {
		319	eg_pi->pcie_performance_request_registered = false;
		320	return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);
		321	}
		322	#endif
		323
		324	return 0;
		325	}
		326
		327	void cypress_advertise_gen2_capability(struct radeon_device *rdev)
		328	{
		329	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
		330	u32 tmp;
		331
		332	#if defined(CONFIG_ACPI)
		333	radeon_acpi_pcie_notify_device_ready(rdev);
		334	#endif
		335
		336	tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
		337
		338	if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
		339	(tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
		340	pi->pcie_gen2 = true;
		341	else
		342	pi->pcie_gen2 = false;
		343
		344	if (!pi->pcie_gen2)
		345	cypress_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, true);
		346
		347	}
		348
		349	static enum radeon_pcie_gen cypress_get_maximum_link_speed(struct radeon_ps *radeon_state)
		350	{
		351	struct rv7xx_ps *state = rv770_get_ps(radeon_state);
		352
		353	if (state->high.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
		354	return 1;
		355	return 0;
		356	}
		357
		358	void cypress_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
		359	struct radeon_ps *radeon_new_state,
		360	struct radeon_ps *radeon_current_state)
		361	{
		362	enum radeon_pcie_gen pcie_link_speed_target =
		363	cypress_get_maximum_link_speed(radeon_new_state);
		364	enum radeon_pcie_gen pcie_link_speed_current =
		365	cypress_get_maximum_link_speed(radeon_current_state);
		366	u8 request;
		367
		368	if (pcie_link_speed_target < pcie_link_speed_current) {
		369	if (pcie_link_speed_target == RADEON_PCIE_GEN1)
		370	request = PCIE_PERF_REQ_PECI_GEN1;
		371	else if (pcie_link_speed_target == RADEON_PCIE_GEN2)
		372	request = PCIE_PERF_REQ_PECI_GEN2;
		373	else
		374	request = PCIE_PERF_REQ_PECI_GEN3;
		375
		376	cypress_pcie_performance_request(rdev, request, false);
		377	}
		378	}
		379
		380	void cypress_notify_link_speed_change_before_state_change(struct radeon_device *rdev,
		381	struct radeon_ps *radeon_new_state,
		382	struct radeon_ps *radeon_current_state)
		383	{
		384	enum radeon_pcie_gen pcie_link_speed_target =
		385	cypress_get_maximum_link_speed(radeon_new_state);
		386	enum radeon_pcie_gen pcie_link_speed_current =
		387	cypress_get_maximum_link_speed(radeon_current_state);
		388	u8 request;
		389
		390	if (pcie_link_speed_target > pcie_link_speed_current) {
		391	if (pcie_link_speed_target == RADEON_PCIE_GEN1)
		392	request = PCIE_PERF_REQ_PECI_GEN1;
		393	else if (pcie_link_speed_target == RADEON_PCIE_GEN2)
		394	request = PCIE_PERF_REQ_PECI_GEN2;
		395	else
		396	request = PCIE_PERF_REQ_PECI_GEN3;
		397
		398	cypress_pcie_performance_request(rdev, request, false);
		399	}
		400	}
		401
		402	static int cypress_populate_voltage_value(struct radeon_device *rdev,
		403	struct atom_voltage_table *table,
		404	u16 value, RV770_SMC_VOLTAGE_VALUE *voltage)
		405	{
		406	unsigned int i;
		407
		408	for (i = 0; i < table->count; i++) {
		409	if (value <= table->entries[i].value) {
		410	voltage->index = (u8)i;
		411	voltage->value = cpu_to_be16(table->entries[i].value);
		412	break;
		413	}
		414	}
		415
		416	if (i == table->count)
		417	return -EINVAL;
		418
		419	return 0;
		420	}
		421
		422	u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
		423	{
		424	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
		425	u8 result = 0;
		426	bool strobe_mode = false;
		427
		428	if (pi->mem_gddr5) {
		429	if (mclk <= pi->mclk_strobe_mode_threshold)
		430	strobe_mode = true;
		431	result = cypress_get_mclk_frequency_ratio(rdev, mclk, strobe_mode);
		432
		433	if (strobe_mode)
		434	result \|= SMC_STROBE_ENABLE;
		435	}
		436
		437	return result;
		438	}
		439
		440	u32 cypress_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf)
		441	{
		442	u32 ref_clk = rdev->clock.mpll.reference_freq;
		443	u32 vco = clkf * ref_clk;
		444
		445	/* 100 Mhz ref clk */
		446	if (ref_clk == 10000) {
		447	if (vco > 500000)
		448	return 0xC6;
		449	if (vco > 400000)
		450	return 0x9D;
		451	if (vco > 330000)
		452	return 0x6C;
		453	if (vco > 250000)
		454	return 0x2B;
		455	if (vco > 160000)
		456	return 0x5B;
		457	if (vco > 120000)
		458	return 0x0A;
		459	return 0x4B;
		460	}
		461
		462	/* 27 Mhz ref clk */
		463	if (vco > 250000)
		464	return 0x8B;
		465	if (vco > 200000)
		466	return 0xCC;
		467	if (vco > 150000)
		468	return 0x9B;
		469	return 0x6B;
		470	}
		471
		472	static int cypress_populate_mclk_value(struct radeon_device *rdev,
		473	u32 engine_clock, u32 memory_clock,
		474	RV7XX_SMC_MCLK_VALUE *mclk,
		475	bool strobe_mode, bool dll_state_on)
		476	{
		477	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
		478
		479	u32 mpll_ad_func_cntl =
		480	pi->clk_regs.rv770.mpll_ad_func_cntl;
		481	u32 mpll_ad_func_cntl_2 =
		482	pi->clk_regs.rv770.mpll_ad_func_cntl_2;
		483	u32 mpll_dq_func_cntl =
		484	pi->clk_regs.rv770.mpll_dq_func_cntl;
		485	u32 mpll_dq_func_cntl_2 =
		486	pi->clk_regs.rv770.mpll_dq_func_cntl_2;
		487	u32 mclk_pwrmgt_cntl =
		488	pi->clk_regs.rv770.mclk_pwrmgt_cntl;
		489	u32 dll_cntl =
		490	pi->clk_regs.rv770.dll_cntl;
		491	u32 mpll_ss1 = pi->clk_regs.rv770.mpll_ss1;
		492	u32 mpll_ss2 = pi->clk_regs.rv770.mpll_ss2;
		493	struct atom_clock_dividers dividers;
		494	u32 ibias;
		495	u32 dll_speed;
		496	int ret;
		497	u32 mc_seq_misc7;
		498
		499	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
		500	memory_clock, strobe_mode, ÷rs);
		501	if (ret)
		502	return ret;
		503
		504	if (!strobe_mode) {
		505	mc_seq_misc7 = RREG32(MC_SEQ_MISC7);
		506
		507	if(mc_seq_misc7 & 0x8000000)
		508	dividers.post_div = 1;
		509	}
		510
		511	ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div);
		512
		513	mpll_ad_func_cntl &= ~(CLKR_MASK \|
		514	YCLK_POST_DIV_MASK \|
		515	CLKF_MASK \|
		516	CLKFRAC_MASK \|
		517	IBIAS_MASK);
		518	mpll_ad_func_cntl \|= CLKR(dividers.ref_div);
		519	mpll_ad_func_cntl \|= YCLK_POST_DIV(dividers.post_div);
		520	mpll_ad_func_cntl \|= CLKF(dividers.whole_fb_div);
		521	mpll_ad_func_cntl \|= CLKFRAC(dividers.frac_fb_div);
		522	mpll_ad_func_cntl \|= IBIAS(ibias);
		523
		524	if (dividers.vco_mode)
		525	mpll_ad_func_cntl_2 \|= VCO_MODE;
		526	else
		527	mpll_ad_func_cntl_2 &= ~VCO_MODE;
		528
		529	if (pi->mem_gddr5) {
		530	mpll_dq_func_cntl &= ~(CLKR_MASK \|
		531	YCLK_POST_DIV_MASK \|
		532	CLKF_MASK \|
		533	CLKFRAC_MASK \|
		534	IBIAS_MASK);
		535	mpll_dq_func_cntl \|= CLKR(dividers.ref_div);
		536	mpll_dq_func_cntl \|= YCLK_POST_DIV(dividers.post_div);
		537	mpll_dq_func_cntl \|= CLKF(dividers.whole_fb_div);
		538	mpll_dq_func_cntl \|= CLKFRAC(dividers.frac_fb_div);
		539	mpll_dq_func_cntl \|= IBIAS(ibias);
		540
		541	if (strobe_mode)
		542	mpll_dq_func_cntl &= ~PDNB;
		543	else
		544	mpll_dq_func_cntl \|= PDNB;
		545
		546	if (dividers.vco_mode)
		547	mpll_dq_func_cntl_2 \|= VCO_MODE;
		548	else
		549	mpll_dq_func_cntl_2 &= ~VCO_MODE;
		550	}
		551
		552	if (pi->mclk_ss) {
		553	struct radeon_atom_ss ss;
		554	u32 vco_freq = memory_clock * dividers.post_div;
		555
		556	if (radeon_atombios_get_asic_ss_info(rdev, &ss,
		557	ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
		558	u32 reference_clock = rdev->clock.mpll.reference_freq;
		559	u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
		560	u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
		561	u32 clk_v = ss.percentage *
		562	(0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625);
		563
		564	mpll_ss1 &= ~CLKV_MASK;
		565	mpll_ss1 \|= CLKV(clk_v);
		566
		567	mpll_ss2 &= ~CLKS_MASK;
		568	mpll_ss2 \|= CLKS(clk_s);
		569	}
		570	}
		571
		572	dll_speed = rv740_get_dll_speed(pi->mem_gddr5,
		573	memory_clock);
		574
		575	mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
		576	mclk_pwrmgt_cntl \|= DLL_SPEED(dll_speed);
		577	if (dll_state_on)
		578	mclk_pwrmgt_cntl \|= (MRDCKA0_PDNB \|
		579	MRDCKA1_PDNB \|
		580	MRDCKB0_PDNB \|
		581	MRDCKB1_PDNB \|
		582	MRDCKC0_PDNB \|
		583	MRDCKC1_PDNB \|
		584	MRDCKD0_PDNB \|
		585	MRDCKD1_PDNB);
		586	else
		587	mclk_pwrmgt_cntl &= ~(MRDCKA0_PDNB \|
		588	MRDCKA1_PDNB \|
		589	MRDCKB0_PDNB \|
		590	MRDCKB1_PDNB \|
		591	MRDCKC0_PDNB \|
		592	MRDCKC1_PDNB \|
		593	MRDCKD0_PDNB \|
		594	MRDCKD1_PDNB);
		595
		596	mclk->mclk770.mclk_value = cpu_to_be32(memory_clock);
		597	mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
		598	mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
		599	mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
		600	mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
		601	mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
		602	mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
		603	mclk->mclk770.vMPLL_SS = cpu_to_be32(mpll_ss1);
		604	mclk->mclk770.vMPLL_SS2 = cpu_to_be32(mpll_ss2);
		605
		606	return 0;
		607	}
		608
		609	u8 cypress_get_mclk_frequency_ratio(struct radeon_device *rdev,
		610	u32 memory_clock, bool strobe_mode)
		611	{
		612	u8 mc_para_index;
		613
		614	if (rdev->family >= CHIP_BARTS) {
		615	if (strobe_mode) {
		616	if (memory_clock < 10000)
		617	mc_para_index = 0x00;
		618	else if (memory_clock > 47500)
		619	mc_para_index = 0x0f;
		620	else
		621	mc_para_index = (u8)((memory_clock - 10000) / 2500);
		622	} else {
		623	if (memory_clock < 65000)
		624	mc_para_index = 0x00;
		625	else if (memory_clock > 135000)
		626	mc_para_index = 0x0f;
		627	else
		628	mc_para_index = (u8)((memory_clock - 60000) / 5000);
		629	}
		630	} else {
		631	if (strobe_mode) {
		632	if (memory_clock < 10000)
		633	mc_para_index = 0x00;
		634	else if (memory_clock > 47500)
		635	mc_para_index = 0x0f;
		636	else
		637	mc_para_index = (u8)((memory_clock - 10000) / 2500);
		638	} else {
		639	if (memory_clock < 40000)
		640	mc_para_index = 0x00;
		641	else if (memory_clock > 115000)
		642	mc_para_index = 0x0f;
		643	else
		644	mc_para_index = (u8)((memory_clock - 40000) / 5000);
		645	}
		646	}
		647	return mc_para_index;
		648	}
		649
		650	static int cypress_populate_mvdd_value(struct radeon_device *rdev,
		651	u32 mclk,
		652	RV770_SMC_VOLTAGE_VALUE *voltage)
		653	{
		654	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
		655	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		656
		657	if (!pi->mvdd_control) {
		658	voltage->index = eg_pi->mvdd_high_index;
		659	voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
		660	return 0;
		661	}
		662
		663	if (mclk <= pi->mvdd_split_frequency) {
		664	voltage->index = eg_pi->mvdd_low_index;
		665	voltage->value = cpu_to_be16(MVDD_LOW_VALUE);
		666	} else {
		667	voltage->index = eg_pi->mvdd_high_index;
		668	voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
		669	}
		670
		671	return 0;
		672	}
		673
		674	int cypress_convert_power_level_to_smc(struct radeon_device *rdev,
		675	struct rv7xx_pl *pl,
		676	RV770_SMC_HW_PERFORMANCE_LEVEL *level,
		677	u8 watermark_level)
		678	{
		679	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
		680	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		681	int ret;
		682	bool dll_state_on;
		683
		684	level->gen2PCIE = pi->pcie_gen2 ?
		685	((pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0) : 0;
		686	level->gen2XSP = (pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0;
		687	level->backbias = (pl->flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? 1 : 0;
		688	level->displayWatermark = watermark_level;
		689
		690	ret = rv740_populate_sclk_value(rdev, pl->sclk, &level->sclk);
		691	if (ret)
		692	return ret;
		693
		694	level->mcFlags = 0;
		695	if (pi->mclk_stutter_mode_threshold &&
		696	(pl->mclk <= pi->mclk_stutter_mode_threshold) &&
		697	!eg_pi->uvd_enabled) {
		698	level->mcFlags \|= SMC_MC_STUTTER_EN;
		699	if (eg_pi->sclk_deep_sleep)
		700	level->stateFlags \|= PPSMC_STATEFLAG_AUTO_PULSE_SKIP;
		701	else
		702	level->stateFlags &= ~PPSMC_STATEFLAG_AUTO_PULSE_SKIP;
		703	}
		704
		705	if (pi->mem_gddr5) {
		706	if (pl->mclk > pi->mclk_edc_enable_threshold)
		707	level->mcFlags \|= SMC_MC_EDC_RD_FLAG;
		708
		709	if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
		710	level->mcFlags \|= SMC_MC_EDC_WR_FLAG;
		711
		712	level->strobeMode = cypress_get_strobe_mode_settings(rdev, pl->mclk);
		713
		714	if (level->strobeMode & SMC_STROBE_ENABLE) {
		715	if (cypress_get_mclk_frequency_ratio(rdev, pl->mclk, true) >=
		716	((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
		717	dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
		718	else
		719	dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
		720	} else
		721	dll_state_on = eg_pi->dll_default_on;
		722
		723	ret = cypress_populate_mclk_value(rdev,
		724	pl->sclk,
		725	pl->mclk,
		726	&level->mclk,
		727	(level->strobeMode & SMC_STROBE_ENABLE) != 0,
		728	dll_state_on);
		729	} else {
		730	ret = cypress_populate_mclk_value(rdev,
		731	pl->sclk,
		732	pl->mclk,
		733	&level->mclk,
		734	true,
		735	true);
		736	}
		737	if (ret)
		738	return ret;
		739
		740	ret = cypress_populate_voltage_value(rdev,
		741	&eg_pi->vddc_voltage_table,
		742	pl->vddc,
		743	&level->vddc);
		744	if (ret)
		745	return ret;
		746
		747	if (eg_pi->vddci_control) {
		748	ret = cypress_populate_voltage_value(rdev,
		749	&eg_pi->vddci_voltage_table,
		750	pl->vddci,
		751	&level->vddci);
		752	if (ret)
		753	return ret;
		754	}
		755
		756	ret = cypress_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
		757
		758	return ret;
		759	}
		760
		761	static int cypress_convert_power_state_to_smc(struct radeon_device *rdev,
		762	struct radeon_ps *radeon_state,
		763	RV770_SMC_SWSTATE *smc_state)
		764	{
		765	struct rv7xx_ps *state = rv770_get_ps(radeon_state);
		766	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		767	int ret;
		768
		769	if (!(radeon_state->caps & ATOM_PPLIB_DISALLOW_ON_DC))
		770	smc_state->flags \|= PPSMC_SWSTATE_FLAG_DC;
		771
		772	ret = cypress_convert_power_level_to_smc(rdev,
		773	&state->low,
		774	&smc_state->levels[0],
		775	PPSMC_DISPLAY_WATERMARK_LOW);
		776	if (ret)
		777	return ret;
		778
		779	ret = cypress_convert_power_level_to_smc(rdev,
		780	&state->medium,
		781	&smc_state->levels[1],
		782	PPSMC_DISPLAY_WATERMARK_LOW);
		783	if (ret)
		784	return ret;
		785
		786	ret = cypress_convert_power_level_to_smc(rdev,
		787	&state->high,
		788	&smc_state->levels[2],
		789	PPSMC_DISPLAY_WATERMARK_HIGH);
		790	if (ret)
		791	return ret;
		792
		793	smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1;
		794	smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2;
		795	smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3;
		796
		797	if (eg_pi->dynamic_ac_timing) {
		798	smc_state->levels[0].ACIndex = 2;
		799	smc_state->levels[1].ACIndex = 3;
		800	smc_state->levels[2].ACIndex = 4;
		801	} else {
		802	smc_state->levels[0].ACIndex = 0;
		803	smc_state->levels[1].ACIndex = 0;
		804	smc_state->levels[2].ACIndex = 0;
		805	}
		806
		807	rv770_populate_smc_sp(rdev, radeon_state, smc_state);
		808
		809	return rv770_populate_smc_t(rdev, radeon_state, smc_state);
		810	}
		811
		812	static void cypress_convert_mc_registers(struct evergreen_mc_reg_entry *entry,
		813	SMC_Evergreen_MCRegisterSet *data,
		814	u32 num_entries, u32 valid_flag)
		815	{
		816	u32 i, j;
		817
		818	for (i = 0, j = 0; j < num_entries; j++) {
		819	if (valid_flag & (1 << j)) {
		820	data->value[i] = cpu_to_be32(entry->mc_data[j]);
		821	i++;
		822	}
		823	}
		824	}
		825
		826	static void cypress_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
		827	struct rv7xx_pl *pl,
		828	SMC_Evergreen_MCRegisterSet *mc_reg_table_data)
		829	{
		830	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		831	u32 i = 0;
		832
		833	for (i = 0; i < eg_pi->mc_reg_table.num_entries; i++) {
		834	if (pl->mclk <=
		835	eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
		836	break;
		837	}
		838
		839	if ((i == eg_pi->mc_reg_table.num_entries) && (i > 0))
		840	--i;
		841
		842	cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[i],
		843	mc_reg_table_data,
		844	eg_pi->mc_reg_table.last,
		845	eg_pi->mc_reg_table.valid_flag);
		846	}
		847
		848	static void cypress_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
		849	struct radeon_ps *radeon_state,
		850	SMC_Evergreen_MCRegisters *mc_reg_table)
		851	{
		852	struct rv7xx_ps *state = rv770_get_ps(radeon_state);
		853
		854	cypress_convert_mc_reg_table_entry_to_smc(rdev,
		855	&state->low,
		856	&mc_reg_table->data[2]);
		857	cypress_convert_mc_reg_table_entry_to_smc(rdev,
		858	&state->medium,
		859	&mc_reg_table->data[3]);
		860	cypress_convert_mc_reg_table_entry_to_smc(rdev,
		861	&state->high,
		862	&mc_reg_table->data[4]);
		863	}
		864
		865	int cypress_upload_sw_state(struct radeon_device *rdev,
		866	struct radeon_ps *radeon_new_state)
		867	{
		868	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
		869	u16 address = pi->state_table_start +
		870	offsetof(RV770_SMC_STATETABLE, driverState);
		871	RV770_SMC_SWSTATE state = { 0 };
		872	int ret;
		873
		874	ret = cypress_convert_power_state_to_smc(rdev, radeon_new_state, &state);
		875	if (ret)
		876	return ret;
		877
		878	return rv770_copy_bytes_to_smc(rdev, address, (u8 *)&state,
		879	sizeof(RV770_SMC_SWSTATE),
		880	pi->sram_end);
		881	}
		882
		883	int cypress_upload_mc_reg_table(struct radeon_device *rdev,
		884	struct radeon_ps *radeon_new_state)
		885	{
		886	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
		887	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		888	SMC_Evergreen_MCRegisters mc_reg_table = { 0 };
		889	u16 address;
		890
		891	cypress_convert_mc_reg_table_to_smc(rdev, radeon_new_state, &mc_reg_table);
		892
		893	address = eg_pi->mc_reg_table_start +
		894	(u16)offsetof(SMC_Evergreen_MCRegisters, data[2]);
		895
		896	return rv770_copy_bytes_to_smc(rdev, address,
		897	(u8 *)&mc_reg_table.data[2],
		898	sizeof(SMC_Evergreen_MCRegisterSet) * 3,
		899	pi->sram_end);
		900	}
		901
		902	u32 cypress_calculate_burst_time(struct radeon_device *rdev,
		903	u32 engine_clock, u32 memory_clock)
		904	{
		905	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
		906	u32 multiplier = pi->mem_gddr5 ? 1 : 2;
		907	u32 result = (4 * multiplier * engine_clock) / (memory_clock / 2);
		908	u32 burst_time;
		909
		910	if (result <= 4)
		911	burst_time = 0;
		912	else if (result < 8)
		913	burst_time = result - 4;
		914	else {
		915	burst_time = result / 2 ;
		916	if (burst_time > 18)
		917	burst_time = 18;
		918	}
		919
		920	return burst_time;
		921	}
		922
		923	void cypress_program_memory_timing_parameters(struct radeon_device *rdev,
		924	struct radeon_ps *radeon_new_state)
		925	{
		926	struct rv7xx_ps *new_state = rv770_get_ps(radeon_new_state);
		927	u32 mc_arb_burst_time = RREG32(MC_ARB_BURST_TIME);
		928
		929	mc_arb_burst_time &= ~(STATE1_MASK \| STATE2_MASK \| STATE3_MASK);
		930
		931	mc_arb_burst_time \|= STATE1(cypress_calculate_burst_time(rdev,
		932	new_state->low.sclk,
		933	new_state->low.mclk));
		934	mc_arb_burst_time \|= STATE2(cypress_calculate_burst_time(rdev,
		935	new_state->medium.sclk,
		936	new_state->medium.mclk));
		937	mc_arb_burst_time \|= STATE3(cypress_calculate_burst_time(rdev,
		938	new_state->high.sclk,
		939	new_state->high.mclk));
		940
		941	rv730_program_memory_timing_parameters(rdev, radeon_new_state);
		942
		943	WREG32(MC_ARB_BURST_TIME, mc_arb_burst_time);
		944	}
		945
		946	static void cypress_populate_mc_reg_addresses(struct radeon_device *rdev,
		947	SMC_Evergreen_MCRegisters *mc_reg_table)
		948	{
		949	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		950	u32 i, j;
		951
		952	for (i = 0, j = 0; j < eg_pi->mc_reg_table.last; j++) {
		953	if (eg_pi->mc_reg_table.valid_flag & (1 << j)) {
		954	mc_reg_table->address[i].s0 =
		955	cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s0);
		956	mc_reg_table->address[i].s1 =
		957	cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s1);
		958	i++;
		959	}
		960	}
		961
		962	mc_reg_table->last = (u8)i;
		963	}
		964
		965	static void cypress_set_mc_reg_address_table(struct radeon_device *rdev)
		966	{
		967	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		968	u32 i = 0;
		969
		970	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RAS_TIMING_LP >> 2;
		971	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RAS_TIMING >> 2;
		972	i++;
		973
		974	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_CAS_TIMING_LP >> 2;
		975	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_CAS_TIMING >> 2;
		976	i++;
		977
		978	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING_LP >> 2;
		979	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING >> 2;
		980	i++;
		981
		982	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING2_LP >> 2;
		983	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING2 >> 2;
		984	i++;
		985
		986	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D0_LP >> 2;
		987	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D0 >> 2;
		988	i++;
		989
		990	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D1_LP >> 2;
		991	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D1 >> 2;
		992	i++;
		993
		994	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D0_LP >> 2;
		995	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D0 >> 2;
		996	i++;
		997
		998	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D1_LP >> 2;
		999	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D1 >> 2;
		1000	i++;
		1001
		1002	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
		1003	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_EMRS >> 2;
		1004	i++;
		1005
		1006	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
		1007	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS >> 2;
		1008	i++;
		1009
		1010	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
		1011	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS1 >> 2;
		1012	i++;
		1013
		1014	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC1 >> 2;
		1015	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC1 >> 2;
		1016	i++;
		1017
		1018	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RESERVE_M >> 2;
		1019	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RESERVE_M >> 2;
		1020	i++;
		1021
		1022	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC3 >> 2;
		1023	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC3 >> 2;
		1024	i++;
		1025
		1026	eg_pi->mc_reg_table.last = (u8)i;
		1027	}
		1028
		1029	static void cypress_retrieve_ac_timing_for_one_entry(struct radeon_device *rdev,
		1030	struct evergreen_mc_reg_entry *entry)
		1031	{
		1032	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		1033	u32 i;
		1034
		1035	for (i = 0; i < eg_pi->mc_reg_table.last; i++)
		1036	entry->mc_data[i] =
		1037	RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2);
		1038
		1039	}
		1040
		1041	static void cypress_retrieve_ac_timing_for_all_ranges(struct radeon_device *rdev,
		1042	struct atom_memory_clock_range_table *range_table)
		1043	{
		1044	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		1045	u32 i, j;
		1046
		1047	for (i = 0; i < range_table->num_entries; i++) {
		1048	eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max =
		1049	range_table->mclk[i];
		1050	radeon_atom_set_ac_timing(rdev, range_table->mclk[i]);
		1051	cypress_retrieve_ac_timing_for_one_entry(rdev,
		1052	&eg_pi->mc_reg_table.mc_reg_table_entry[i]);
		1053	}
		1054
		1055	eg_pi->mc_reg_table.num_entries = range_table->num_entries;
		1056	eg_pi->mc_reg_table.valid_flag = 0;
		1057
		1058	for (i = 0; i < eg_pi->mc_reg_table.last; i++) {
		1059	for (j = 1; j < range_table->num_entries; j++) {
		1060	if (eg_pi->mc_reg_table.mc_reg_table_entry[j-1].mc_data[i] !=
		1061	eg_pi->mc_reg_table.mc_reg_table_entry[j].mc_data[i]) {
		1062	eg_pi->mc_reg_table.valid_flag \|= (1 << i);
		1063	break;
		1064	}
		1065	}
		1066	}
		1067	}
		1068
		1069	static int cypress_initialize_mc_reg_table(struct radeon_device *rdev)
		1070	{
		1071	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
		1072	u8 module_index = rv770_get_memory_module_index(rdev);
		1073	struct atom_memory_clock_range_table range_table = { 0 };
		1074	int ret;
		1075
		1076	ret = radeon_atom_get_mclk_range_table(rdev,
		1077	pi->mem_gddr5,
		1078	module_index, &range_table);
		1079	if (ret)
		1080	return ret;
		1081
		1082	cypress_retrieve_ac_timing_for_all_ranges(rdev, &range_table);
		1083
		1084	return 0;
		1085	}
		1086
		1087	static void cypress_wait_for_mc_sequencer(struct radeon_device *rdev, u8 value)
		1088	{
		1089	u32 i, j;
		1090	u32 channels = 2;
		1091
		1092	if ((rdev->family == CHIP_CYPRESS) \|\|
		1093	(rdev->family == CHIP_HEMLOCK))
		1094	channels = 4;
		1095	else if (rdev->family == CHIP_CEDAR)
		1096	channels = 1;
		1097
		1098	for (i = 0; i < channels; i++) {
		1099	if ((rdev->family == CHIP_CYPRESS) \|\|
		1100	(rdev->family == CHIP_HEMLOCK)) {
		1101	WREG32_P(MC_CONFIG_MCD, MC_RD_ENABLE_MCD(i), ~MC_RD_ENABLE_MCD_MASK);
		1102	WREG32_P(MC_CG_CONFIG_MCD, MC_RD_ENABLE_MCD(i), ~MC_RD_ENABLE_MCD_MASK);
		1103	} else {
		1104	WREG32_P(MC_CONFIG, MC_RD_ENABLE(i), ~MC_RD_ENABLE_MASK);
		1105	WREG32_P(MC_CG_CONFIG, MC_RD_ENABLE(i), ~MC_RD_ENABLE_MASK);
		1106	}
		1107	for (j = 0; j < rdev->usec_timeout; j++) {
		1108	if (((RREG32(MC_SEQ_CG) & CG_SEQ_RESP_MASK) >> CG_SEQ_RESP_SHIFT) == value)
		1109	break;
		1110	udelay(1);
		1111	}
		1112	}
		1113	}
		1114
		1115	static void cypress_force_mc_use_s1(struct radeon_device *rdev,
		1116	struct radeon_ps *radeon_boot_state)
		1117	{
		1118	struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state);
		1119	u32 strobe_mode;
		1120	u32 mc_seq_cg;
		1121	int i;
		1122
		1123	if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE)
		1124	return;
		1125
		1126	radeon_atom_set_ac_timing(rdev, boot_state->low.mclk);
		1127	radeon_mc_wait_for_idle(rdev);
		1128
		1129	if ((rdev->family == CHIP_CYPRESS) \|\|
		1130	(rdev->family == CHIP_HEMLOCK)) {
		1131	WREG32(MC_CONFIG_MCD, 0xf);
		1132	WREG32(MC_CG_CONFIG_MCD, 0xf);
		1133	} else {
		1134	WREG32(MC_CONFIG, 0xf);
		1135	WREG32(MC_CG_CONFIG, 0xf);
		1136	}
		1137
		1138	for (i = 0; i < rdev->num_crtc; i++)
		1139	radeon_wait_for_vblank(rdev, i);
		1140
		1141	WREG32(MC_SEQ_CG, MC_CG_SEQ_YCLK_SUSPEND);
		1142	cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_SUSPEND);
		1143
		1144	strobe_mode = cypress_get_strobe_mode_settings(rdev,
		1145	boot_state->low.mclk);
		1146
		1147	mc_seq_cg = CG_SEQ_REQ(MC_CG_SEQ_DRAMCONF_S1);
		1148	mc_seq_cg \|= SEQ_CG_RESP(strobe_mode);
		1149	WREG32(MC_SEQ_CG, mc_seq_cg);
		1150
		1151	for (i = 0; i < rdev->usec_timeout; i++) {
		1152	if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE)
		1153	break;
		1154	udelay(1);
		1155	}
		1156
		1157	mc_seq_cg &= ~CG_SEQ_REQ_MASK;
		1158	mc_seq_cg \|= CG_SEQ_REQ(MC_CG_SEQ_YCLK_RESUME);
		1159	WREG32(MC_SEQ_CG, mc_seq_cg);
		1160
		1161	cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_RESUME);
		1162	}
		1163
		1164	static void cypress_copy_ac_timing_from_s1_to_s0(struct radeon_device *rdev)
		1165	{
		1166	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		1167	u32 value;
		1168	u32 i;
		1169
		1170	for (i = 0; i < eg_pi->mc_reg_table.last; i++) {
		1171	value = RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2);
		1172	WREG32(eg_pi->mc_reg_table.mc_reg_address[i].s0 << 2, value);
		1173	}
		1174	}
		1175
		1176	static void cypress_force_mc_use_s0(struct radeon_device *rdev,
		1177	struct radeon_ps *radeon_boot_state)
		1178	{
		1179	struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state);
		1180	u32 strobe_mode;
		1181	u32 mc_seq_cg;
		1182	int i;
		1183
		1184	cypress_copy_ac_timing_from_s1_to_s0(rdev);
		1185	radeon_mc_wait_for_idle(rdev);
		1186
		1187	if ((rdev->family == CHIP_CYPRESS) \|\|
		1188	(rdev->family == CHIP_HEMLOCK)) {
		1189	WREG32(MC_CONFIG_MCD, 0xf);
		1190	WREG32(MC_CG_CONFIG_MCD, 0xf);
		1191	} else {
		1192	WREG32(MC_CONFIG, 0xf);
		1193	WREG32(MC_CG_CONFIG, 0xf);
		1194	}
		1195
		1196	for (i = 0; i < rdev->num_crtc; i++)
		1197	radeon_wait_for_vblank(rdev, i);
		1198
		1199	WREG32(MC_SEQ_CG, MC_CG_SEQ_YCLK_SUSPEND);
		1200	cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_SUSPEND);
		1201
		1202	strobe_mode = cypress_get_strobe_mode_settings(rdev,
		1203	boot_state->low.mclk);
		1204
		1205	mc_seq_cg = CG_SEQ_REQ(MC_CG_SEQ_DRAMCONF_S0);
		1206	mc_seq_cg \|= SEQ_CG_RESP(strobe_mode);
		1207	WREG32(MC_SEQ_CG, mc_seq_cg);
		1208
		1209	for (i = 0; i < rdev->usec_timeout; i++) {
		1210	if (!(RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE))
		1211	break;
		1212	udelay(1);
		1213	}
		1214
		1215	mc_seq_cg &= ~CG_SEQ_REQ_MASK;
		1216	mc_seq_cg \|= CG_SEQ_REQ(MC_CG_SEQ_YCLK_RESUME);
		1217	WREG32(MC_SEQ_CG, mc_seq_cg);
		1218
		1219	cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_RESUME);
		1220	}
		1221
		1222	static int cypress_populate_initial_mvdd_value(struct radeon_device *rdev,
		1223	RV770_SMC_VOLTAGE_VALUE *voltage)
		1224	{
		1225	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		1226
		1227	voltage->index = eg_pi->mvdd_high_index;
		1228	voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
		1229
		1230	return 0;
		1231	}
		1232
		1233	int cypress_populate_smc_initial_state(struct radeon_device *rdev,
		1234	struct radeon_ps *radeon_initial_state,
		1235	RV770_SMC_STATETABLE *table)
		1236	{
		1237	struct rv7xx_ps *initial_state = rv770_get_ps(radeon_initial_state);
		1238	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
		1239	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		1240	u32 a_t;
		1241
		1242	table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =
		1243	cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl);
		1244	table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =
		1245	cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl_2);
		1246	table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =
		1247	cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl);
		1248	table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =
		1249	cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl_2);
		1250	table->initialState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =
		1251	cpu_to_be32(pi->clk_regs.rv770.mclk_pwrmgt_cntl);
		1252	table->initialState.levels[0].mclk.mclk770.vDLL_CNTL =
		1253	cpu_to_be32(pi->clk_regs.rv770.dll_cntl);
		1254
		1255	table->initialState.levels[0].mclk.mclk770.vMPLL_SS =
		1256	cpu_to_be32(pi->clk_regs.rv770.mpll_ss1);
		1257	table->initialState.levels[0].mclk.mclk770.vMPLL_SS2 =
		1258	cpu_to_be32(pi->clk_regs.rv770.mpll_ss2);
		1259
		1260	table->initialState.levels[0].mclk.mclk770.mclk_value =
		1261	cpu_to_be32(initial_state->low.mclk);
		1262
		1263	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
		1264	cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl);
		1265	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
		1266	cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_2);
		1267	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
		1268	cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_3);
		1269	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
		1270	cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum);
		1271	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
		1272	cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum_2);
		1273
		1274	table->initialState.levels[0].sclk.sclk_value =
		1275	cpu_to_be32(initial_state->low.sclk);
		1276
		1277	table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;
		1278
		1279	table->initialState.levels[0].ACIndex = 0;
		1280
		1281	cypress_populate_voltage_value(rdev,
		1282	&eg_pi->vddc_voltage_table,
		1283	initial_state->low.vddc,
		1284	&table->initialState.levels[0].vddc);
		1285
		1286	if (eg_pi->vddci_control)
		1287	cypress_populate_voltage_value(rdev,
		1288	&eg_pi->vddci_voltage_table,
		1289	initial_state->low.vddci,
		1290	&table->initialState.levels[0].vddci);
		1291
		1292	cypress_populate_initial_mvdd_value(rdev,
		1293	&table->initialState.levels[0].mvdd);
		1294
		1295	a_t = CG_R(0xffff) \| CG_L(0);
		1296	table->initialState.levels[0].aT = cpu_to_be32(a_t);
		1297
		1298	table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
		1299
		1300
		1301	if (pi->boot_in_gen2)
		1302	table->initialState.levels[0].gen2PCIE = 1;
		1303	else
		1304	table->initialState.levels[0].gen2PCIE = 0;
		1305	if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
		1306	table->initialState.levels[0].gen2XSP = 1;
		1307	else
		1308	table->initialState.levels[0].gen2XSP = 0;
		1309
		1310	if (pi->mem_gddr5) {
		1311	table->initialState.levels[0].strobeMode =
		1312	cypress_get_strobe_mode_settings(rdev,
		1313	initial_state->low.mclk);
		1314
		1315	if (initial_state->low.mclk > pi->mclk_edc_enable_threshold)
		1316	table->initialState.levels[0].mcFlags = SMC_MC_EDC_RD_FLAG \| SMC_MC_EDC_WR_FLAG;
		1317	else
		1318	table->initialState.levels[0].mcFlags = 0;
		1319	}
		1320
		1321	table->initialState.levels[1] = table->initialState.levels[0];
		1322	table->initialState.levels[2] = table->initialState.levels[0];
		1323
		1324	table->initialState.flags \|= PPSMC_SWSTATE_FLAG_DC;
		1325
		1326	return 0;
		1327	}
		1328
		1329	int cypress_populate_smc_acpi_state(struct radeon_device *rdev,
		1330	RV770_SMC_STATETABLE *table)
		1331	{
		1332	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
		1333	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		1334	u32 mpll_ad_func_cntl =
		1335	pi->clk_regs.rv770.mpll_ad_func_cntl;
		1336	u32 mpll_ad_func_cntl_2 =
		1337	pi->clk_regs.rv770.mpll_ad_func_cntl_2;
		1338	u32 mpll_dq_func_cntl =
		1339	pi->clk_regs.rv770.mpll_dq_func_cntl;
		1340	u32 mpll_dq_func_cntl_2 =
		1341	pi->clk_regs.rv770.mpll_dq_func_cntl_2;
		1342	u32 spll_func_cntl =
		1343	pi->clk_regs.rv770.cg_spll_func_cntl;
		1344	u32 spll_func_cntl_2 =
		1345	pi->clk_regs.rv770.cg_spll_func_cntl_2;
		1346	u32 spll_func_cntl_3 =
		1347	pi->clk_regs.rv770.cg_spll_func_cntl_3;
		1348	u32 mclk_pwrmgt_cntl =
		1349	pi->clk_regs.rv770.mclk_pwrmgt_cntl;
		1350	u32 dll_cntl =
		1351	pi->clk_regs.rv770.dll_cntl;
		1352
		1353	table->ACPIState = table->initialState;
		1354
		1355	table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
		1356
		1357	if (pi->acpi_vddc) {
		1358	cypress_populate_voltage_value(rdev,
		1359	&eg_pi->vddc_voltage_table,
		1360	pi->acpi_vddc,
		1361	&table->ACPIState.levels[0].vddc);
		1362	if (pi->pcie_gen2) {
		1363	if (pi->acpi_pcie_gen2)
		1364	table->ACPIState.levels[0].gen2PCIE = 1;
		1365	else
		1366	table->ACPIState.levels[0].gen2PCIE = 0;
		1367	} else
		1368	table->ACPIState.levels[0].gen2PCIE = 0;
		1369	if (pi->acpi_pcie_gen2)
		1370	table->ACPIState.levels[0].gen2XSP = 1;
		1371	else
		1372	table->ACPIState.levels[0].gen2XSP = 0;
		1373	} else {
		1374	cypress_populate_voltage_value(rdev,
		1375	&eg_pi->vddc_voltage_table,
		1376	pi->min_vddc_in_table,
		1377	&table->ACPIState.levels[0].vddc);
		1378	table->ACPIState.levels[0].gen2PCIE = 0;
		1379	}
		1380
		1381	if (eg_pi->acpi_vddci) {
		1382	if (eg_pi->vddci_control) {
		1383	cypress_populate_voltage_value(rdev,
		1384	&eg_pi->vddci_voltage_table,
		1385	eg_pi->acpi_vddci,
		1386	&table->ACPIState.levels[0].vddci);
		1387	}
		1388	}
		1389
		1390	mpll_ad_func_cntl &= ~PDNB;
		1391
		1392	mpll_ad_func_cntl_2 \|= BIAS_GEN_PDNB \| RESET_EN;
		1393
		1394	if (pi->mem_gddr5)
		1395	mpll_dq_func_cntl &= ~PDNB;
		1396	mpll_dq_func_cntl_2 \|= BIAS_GEN_PDNB \| RESET_EN \| BYPASS;
		1397
		1398	mclk_pwrmgt_cntl \|= (MRDCKA0_RESET \|
		1399	MRDCKA1_RESET \|
		1400	MRDCKB0_RESET \|
		1401	MRDCKB1_RESET \|
		1402	MRDCKC0_RESET \|
		1403	MRDCKC1_RESET \|
		1404	MRDCKD0_RESET \|
		1405	MRDCKD1_RESET);
		1406
		1407	mclk_pwrmgt_cntl &= ~(MRDCKA0_PDNB \|
		1408	MRDCKA1_PDNB \|
		1409	MRDCKB0_PDNB \|
		1410	MRDCKB1_PDNB \|
		1411	MRDCKC0_PDNB \|
		1412	MRDCKC1_PDNB \|
		1413	MRDCKD0_PDNB \|
		1414	MRDCKD1_PDNB);
		1415
		1416	dll_cntl \|= (MRDCKA0_BYPASS \|
		1417	MRDCKA1_BYPASS \|
		1418	MRDCKB0_BYPASS \|
		1419	MRDCKB1_BYPASS \|
		1420	MRDCKC0_BYPASS \|
		1421	MRDCKC1_BYPASS \|
		1422	MRDCKD0_BYPASS \|
		1423	MRDCKD1_BYPASS);
		1424
		1425	/* evergreen only */
		1426	if (rdev->family <= CHIP_HEMLOCK)
		1427	spll_func_cntl \|= SPLL_RESET \| SPLL_SLEEP \| SPLL_BYPASS_EN;
		1428
		1429	spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
		1430	spll_func_cntl_2 \|= SCLK_MUX_SEL(4);
		1431
		1432	table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =
		1433	cpu_to_be32(mpll_ad_func_cntl);
		1434	table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =
		1435	cpu_to_be32(mpll_ad_func_cntl_2);
		1436	table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =
		1437	cpu_to_be32(mpll_dq_func_cntl);
		1438	table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =
		1439	cpu_to_be32(mpll_dq_func_cntl_2);
		1440	table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =
		1441	cpu_to_be32(mclk_pwrmgt_cntl);
		1442	table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
		1443
		1444	table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0;
		1445
		1446	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
		1447	cpu_to_be32(spll_func_cntl);
		1448	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
		1449	cpu_to_be32(spll_func_cntl_2);
		1450	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
		1451	cpu_to_be32(spll_func_cntl_3);
		1452
		1453	table->ACPIState.levels[0].sclk.sclk_value = 0;
		1454
		1455	cypress_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
		1456
		1457	if (eg_pi->dynamic_ac_timing)
		1458	table->ACPIState.levels[0].ACIndex = 1;
		1459
		1460	table->ACPIState.levels[1] = table->ACPIState.levels[0];
		1461	table->ACPIState.levels[2] = table->ACPIState.levels[0];
		1462
		1463	return 0;
		1464	}
		1465
		1466	static void cypress_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
		1467	struct atom_voltage_table *voltage_table)
		1468	{
		1469	unsigned int i, diff;
		1470
		1471	if (voltage_table->count <= MAX_NO_VREG_STEPS)
		1472	return;
		1473
		1474	diff = voltage_table->count - MAX_NO_VREG_STEPS;
		1475
		1476	for (i= 0; i < MAX_NO_VREG_STEPS; i++)
		1477	voltage_table->entries[i] = voltage_table->entries[i + diff];
		1478
		1479	voltage_table->count = MAX_NO_VREG_STEPS;
		1480	}
		1481
		1482	int cypress_construct_voltage_tables(struct radeon_device *rdev)
		1483	{
		1484	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		1485	int ret;
		1486
		1487	ret = radeon_atom_get_voltage_table(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0,
		1488	&eg_pi->vddc_voltage_table);
		1489	if (ret)
		1490	return ret;
		1491
		1492	if (eg_pi->vddc_voltage_table.count > MAX_NO_VREG_STEPS)
		1493	cypress_trim_voltage_table_to_fit_state_table(rdev,
		1494	&eg_pi->vddc_voltage_table);
		1495
		1496	if (eg_pi->vddci_control) {
		1497	ret = radeon_atom_get_voltage_table(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0,
		1498	&eg_pi->vddci_voltage_table);
		1499	if (ret)
		1500	return ret;
		1501
		1502	if (eg_pi->vddci_voltage_table.count > MAX_NO_VREG_STEPS)
		1503	cypress_trim_voltage_table_to_fit_state_table(rdev,
		1504	&eg_pi->vddci_voltage_table);
		1505	}
		1506
		1507	return 0;
		1508	}
		1509
		1510	static void cypress_populate_smc_voltage_table(struct radeon_device *rdev,
		1511	struct atom_voltage_table *voltage_table,
		1512	RV770_SMC_STATETABLE *table)
		1513	{
		1514	unsigned int i;
		1515
		1516	for (i = 0; i < voltage_table->count; i++) {
		1517	table->highSMIO[i] = 0;
		1518	table->lowSMIO[i] \|= cpu_to_be32(voltage_table->entries[i].smio_low);
		1519	}
		1520	}
		1521
		1522	int cypress_populate_smc_voltage_tables(struct radeon_device *rdev,
		1523	RV770_SMC_STATETABLE *table)
		1524	{
		1525	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
		1526	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		1527	unsigned char i;
		1528
		1529	if (eg_pi->vddc_voltage_table.count) {
		1530	cypress_populate_smc_voltage_table(rdev,
		1531	&eg_pi->vddc_voltage_table,
		1532	table);
		1533
		1534	table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDC] = 0;
		1535	table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDC] =
		1536	cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
		1537
		1538	for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
		1539	if (pi->max_vddc_in_table <=
		1540	eg_pi->vddc_voltage_table.entries[i].value) {
		1541	table->maxVDDCIndexInPPTable = i;
		1542	break;
		1543	}
		1544	}
		1545	}
		1546
		1547	if (eg_pi->vddci_voltage_table.count) {
		1548	cypress_populate_smc_voltage_table(rdev,
		1549	&eg_pi->vddci_voltage_table,
		1550	table);
		1551
		1552	table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDCI] = 0;
		1553	table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDCI] =
		1554	cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
		1555	}
		1556
		1557	return 0;
		1558	}
		1559
		1560	static u32 cypress_get_mclk_split_point(struct atom_memory_info *memory_info)
		1561	{
		1562	if ((memory_info->mem_type == MEM_TYPE_GDDR3) \|\|
		1563	(memory_info->mem_type == MEM_TYPE_DDR3))
		1564	return 30000;
		1565
		1566	return 0;
		1567	}
		1568
		1569	int cypress_get_mvdd_configuration(struct radeon_device *rdev)
		1570	{
		1571	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
		1572	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		1573	u8 module_index;
		1574	struct atom_memory_info memory_info;
		1575	u32 tmp = RREG32(GENERAL_PWRMGT);
		1576
		1577	if (!(tmp & BACKBIAS_PAD_EN)) {
		1578	eg_pi->mvdd_high_index = 0;
		1579	eg_pi->mvdd_low_index = 1;
		1580	pi->mvdd_control = false;
		1581	return 0;
		1582	}
		1583
		1584	if (tmp & BACKBIAS_VALUE)
		1585	eg_pi->mvdd_high_index = 1;
		1586	else
		1587	eg_pi->mvdd_high_index = 0;
		1588
		1589	eg_pi->mvdd_low_index =
		1590	(eg_pi->mvdd_high_index == 0) ? 1 : 0;
		1591
		1592	module_index = rv770_get_memory_module_index(rdev);
		1593
		1594	if (radeon_atom_get_memory_info(rdev, module_index, &memory_info)) {
		1595	pi->mvdd_control = false;
		1596	return 0;
		1597	}
		1598
		1599	pi->mvdd_split_frequency =
		1600	cypress_get_mclk_split_point(&memory_info);
		1601
		1602	if (pi->mvdd_split_frequency == 0) {
		1603	pi->mvdd_control = false;
		1604	return 0;
		1605	}
		1606
		1607	return 0;
		1608	}
		1609
		1610	static int cypress_init_smc_table(struct radeon_device *rdev,
		1611	struct radeon_ps *radeon_boot_state)
		1612	{
		1613	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
		1614	RV770_SMC_STATETABLE *table = &pi->smc_statetable;
		1615	int ret;
		1616
		1617	memset(table, 0, sizeof(RV770_SMC_STATETABLE));
		1618
		1619	cypress_populate_smc_voltage_tables(rdev, table);
		1620
		1621	switch (rdev->pm.int_thermal_type) {
		1622	case THERMAL_TYPE_EVERGREEN:
		1623	case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
		1624	table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
		1625	break;
		1626	case THERMAL_TYPE_NONE:
		1627	table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
		1628	break;
		1629	default:
		1630	table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
		1631	break;
		1632	}
		1633
		1634	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
		1635	table->systemFlags \|= PPSMC_SYSTEMFLAG_GPIO_DC;
		1636
		1637	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
		1638	table->systemFlags \|= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
		1639
		1640	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
		1641	table->systemFlags \|= PPSMC_SYSTEMFLAG_STEPVDDC;
		1642
		1643	if (pi->mem_gddr5)
		1644	table->systemFlags \|= PPSMC_SYSTEMFLAG_GDDR5;
		1645
		1646	ret = cypress_populate_smc_initial_state(rdev, radeon_boot_state, table);
		1647	if (ret)
		1648	return ret;
		1649
		1650	ret = cypress_populate_smc_acpi_state(rdev, table);
		1651	if (ret)
		1652	return ret;
		1653
		1654	table->driverState = table->initialState;
		1655
		1656	return rv770_copy_bytes_to_smc(rdev,
		1657	pi->state_table_start,
		1658	(u8 *)table, sizeof(RV770_SMC_STATETABLE),
		1659	pi->sram_end);
		1660	}
		1661
		1662	int cypress_populate_mc_reg_table(struct radeon_device *rdev,
		1663	struct radeon_ps *radeon_boot_state)
		1664	{
		1665	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
		1666	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		1667	struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state);
		1668	SMC_Evergreen_MCRegisters mc_reg_table = { 0 };
		1669
		1670	rv770_write_smc_soft_register(rdev,
		1671	RV770_SMC_SOFT_REGISTER_seq_index, 1);
		1672
		1673	cypress_populate_mc_reg_addresses(rdev, &mc_reg_table);
		1674
		1675	cypress_convert_mc_reg_table_entry_to_smc(rdev,
		1676	&boot_state->low,
		1677	&mc_reg_table.data[0]);
		1678
		1679	cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[0],
		1680	&mc_reg_table.data[1], eg_pi->mc_reg_table.last,
		1681	eg_pi->mc_reg_table.valid_flag);
		1682
		1683	cypress_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, &mc_reg_table);
		1684
		1685	return rv770_copy_bytes_to_smc(rdev, eg_pi->mc_reg_table_start,
		1686	(u8 *)&mc_reg_table, sizeof(SMC_Evergreen_MCRegisters),
		1687	pi->sram_end);
		1688	}
		1689
		1690	int cypress_get_table_locations(struct radeon_device *rdev)
		1691	{
		1692	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
		1693	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		1694	u32 tmp;
		1695	int ret;
		1696
		1697	ret = rv770_read_smc_sram_dword(rdev,
		1698	EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION +
		1699	EVERGREEN_SMC_FIRMWARE_HEADER_stateTable,
		1700	&tmp, pi->sram_end);
		1701	if (ret)
		1702	return ret;
		1703
		1704	pi->state_table_start = (u16)tmp;
		1705
		1706	ret = rv770_read_smc_sram_dword(rdev,
		1707	EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION +
		1708	EVERGREEN_SMC_FIRMWARE_HEADER_softRegisters,
		1709	&tmp, pi->sram_end);
		1710	if (ret)
		1711	return ret;
		1712
		1713	pi->soft_regs_start = (u16)tmp;
		1714
		1715	ret = rv770_read_smc_sram_dword(rdev,
		1716	EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION +
		1717	EVERGREEN_SMC_FIRMWARE_HEADER_mcRegisterTable,
		1718	&tmp, pi->sram_end);
		1719	if (ret)
		1720	return ret;
		1721
		1722	eg_pi->mc_reg_table_start = (u16)tmp;
		1723
		1724	return 0;
		1725	}
		1726
		1727	void cypress_enable_display_gap(struct radeon_device *rdev)
		1728	{
		1729	u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
		1730
		1731	tmp &= ~(DISP1_GAP_MASK \| DISP2_GAP_MASK);
		1732	tmp \|= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) \|
		1733	DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
		1734
		1735	tmp &= ~(DISP1_GAP_MCHG_MASK \| DISP2_GAP_MCHG_MASK);
		1736	tmp \|= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) \|
		1737	DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
		1738	WREG32(CG_DISPLAY_GAP_CNTL, tmp);
		1739	}
		1740
		1741	static void cypress_program_display_gap(struct radeon_device *rdev)
		1742	{
		1743	u32 tmp, pipe;
		1744	int i;
		1745
		1746	tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK \| DISP2_GAP_MASK);
		1747	if (rdev->pm.dpm.new_active_crtc_count > 0)
		1748	tmp \|= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
		1749	else
		1750	tmp \|= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
		1751
		1752	if (rdev->pm.dpm.new_active_crtc_count > 1)
		1753	tmp \|= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
		1754	else
		1755	tmp \|= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
		1756
		1757	WREG32(CG_DISPLAY_GAP_CNTL, tmp);
		1758
		1759	tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
		1760	pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
		1761
		1762	if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
		1763	(!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
		1764	/* find the first active crtc */
		1765	for (i = 0; i < rdev->num_crtc; i++) {
		1766	if (rdev->pm.dpm.new_active_crtcs & (1 << i))
		1767	break;
		1768	}
		1769	if (i == rdev->num_crtc)
		1770	pipe = 0;
		1771	else
		1772	pipe = i;
		1773
		1774	tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
		1775	tmp \|= DCCG_DISP1_SLOW_SELECT(pipe);
		1776	WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
		1777	}
		1778
		1779	cypress_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
		1780	}
		1781
		1782	void cypress_dpm_setup_asic(struct radeon_device *rdev)
		1783	{
		1784	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		1785
		1786	rv740_read_clock_registers(rdev);
		1787	rv770_read_voltage_smio_registers(rdev);
		1788	rv770_get_max_vddc(rdev);
		1789	rv770_get_memory_type(rdev);
		1790
		1791	if (eg_pi->pcie_performance_request)
		1792	eg_pi->pcie_performance_request_registered = false;
		1793
		1794	if (eg_pi->pcie_performance_request)
		1795	cypress_advertise_gen2_capability(rdev);
		1796
		1797	rv770_get_pcie_gen2_status(rdev);
		1798
		1799	rv770_enable_acpi_pm(rdev);
		1800	}
		1801
		1802	int cypress_dpm_enable(struct radeon_device *rdev)
		1803	{
		1804	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
		1805	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		1806	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
		1807	int ret;
		1808
		1809	if (pi->gfx_clock_gating)
		1810	rv770_restore_cgcg(rdev);
		1811
		1812	if (rv770_dpm_enabled(rdev))
		1813	return -EINVAL;
		1814
		1815	if (pi->voltage_control) {
		1816	rv770_enable_voltage_control(rdev, true);
		1817	ret = cypress_construct_voltage_tables(rdev);
		1818	if (ret) {
		1819	DRM_ERROR("cypress_construct_voltage_tables failed\n");
		1820	return ret;
		1821	}
		1822	}
		1823
		1824	if (pi->mvdd_control) {
		1825	ret = cypress_get_mvdd_configuration(rdev);
		1826	if (ret) {
		1827	DRM_ERROR("cypress_get_mvdd_configuration failed\n");
		1828	return ret;
		1829	}
		1830	}
		1831
		1832	if (eg_pi->dynamic_ac_timing) {
		1833	cypress_set_mc_reg_address_table(rdev);
		1834	cypress_force_mc_use_s0(rdev, boot_ps);
		1835	ret = cypress_initialize_mc_reg_table(rdev);
		1836	if (ret)
		1837	eg_pi->dynamic_ac_timing = false;
		1838	cypress_force_mc_use_s1(rdev, boot_ps);
		1839	}
		1840
		1841	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
		1842	rv770_enable_backbias(rdev, true);
		1843
		1844	if (pi->dynamic_ss)
		1845	cypress_enable_spread_spectrum(rdev, true);
		1846
		1847	if (pi->thermal_protection)
		1848	rv770_enable_thermal_protection(rdev, true);
		1849
		1850	rv770_setup_bsp(rdev);
		1851	rv770_program_git(rdev);
		1852	rv770_program_tp(rdev);
		1853	rv770_program_tpp(rdev);
		1854	rv770_program_sstp(rdev);
		1855	rv770_program_engine_speed_parameters(rdev);
		1856	cypress_enable_display_gap(rdev);
		1857	rv770_program_vc(rdev);
		1858
		1859	if (pi->dynamic_pcie_gen2)
		1860	cypress_enable_dynamic_pcie_gen2(rdev, true);
		1861
		1862	ret = rv770_upload_firmware(rdev);
		1863	if (ret) {
		1864	DRM_ERROR("rv770_upload_firmware failed\n");
		1865	return ret;
		1866	}
		1867
		1868	ret = cypress_get_table_locations(rdev);
		1869	if (ret) {
		1870	DRM_ERROR("cypress_get_table_locations failed\n");
		1871	return ret;
		1872	}
		1873	ret = cypress_init_smc_table(rdev, boot_ps);
		1874	if (ret) {
		1875	DRM_ERROR("cypress_init_smc_table failed\n");
		1876	return ret;
		1877	}
		1878	if (eg_pi->dynamic_ac_timing) {
		1879	ret = cypress_populate_mc_reg_table(rdev, boot_ps);
		1880	if (ret) {
		1881	DRM_ERROR("cypress_populate_mc_reg_table failed\n");
		1882	return ret;
		1883	}
		1884	}
		1885
		1886	cypress_program_response_times(rdev);
		1887
		1888	r7xx_start_smc(rdev);
		1889
		1890	ret = cypress_notify_smc_display_change(rdev, false);
		1891	if (ret) {
		1892	DRM_ERROR("cypress_notify_smc_display_change failed\n");
		1893	return ret;
		1894	}
		1895	cypress_enable_sclk_control(rdev, true);
		1896
		1897	if (eg_pi->memory_transition)
		1898	cypress_enable_mclk_control(rdev, true);
		1899
		1900	cypress_start_dpm(rdev);
		1901
		1902	if (pi->gfx_clock_gating)
		1903	cypress_gfx_clock_gating_enable(rdev, true);
		1904
		1905	if (pi->mg_clock_gating)
		1906	cypress_mg_clock_gating_enable(rdev, true);
		1907
		1908	rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
		1909
		1910	return 0;
		1911	}
		1912
		1913	void cypress_dpm_disable(struct radeon_device *rdev)
		1914	{
		1915	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
		1916	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		1917	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
		1918
		1919	if (!rv770_dpm_enabled(rdev))
		1920	return;
		1921
		1922	rv770_clear_vc(rdev);
		1923
		1924	if (pi->thermal_protection)
		1925	rv770_enable_thermal_protection(rdev, false);
		1926
		1927	if (pi->dynamic_pcie_gen2)
		1928	cypress_enable_dynamic_pcie_gen2(rdev, false);
		1929
		1930	if (rdev->irq.installed &&
		1931	r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
		1932	rdev->irq.dpm_thermal = false;
		1933	radeon_irq_set(rdev);
		1934	}
		1935
		1936	if (pi->gfx_clock_gating)
		1937	cypress_gfx_clock_gating_enable(rdev, false);
		1938
		1939	if (pi->mg_clock_gating)
		1940	cypress_mg_clock_gating_enable(rdev, false);
		1941
		1942	rv770_stop_dpm(rdev);
		1943	r7xx_stop_smc(rdev);
		1944
		1945	cypress_enable_spread_spectrum(rdev, false);
		1946
		1947	if (eg_pi->dynamic_ac_timing)
		1948	cypress_force_mc_use_s1(rdev, boot_ps);
		1949
		1950	rv770_reset_smio_status(rdev);
		1951	}
		1952
		1953	int cypress_dpm_set_power_state(struct radeon_device *rdev)
		1954	{
		1955	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
		1956	struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
		1957	struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
		1958	int ret;
		1959
		1960	ret = rv770_restrict_performance_levels_before_switch(rdev);
		1961	if (ret) {
		1962	DRM_ERROR("rv770_restrict_performance_levels_before_switch failed\n");
		1963	return ret;
		1964	}
		1965	if (eg_pi->pcie_performance_request)
		1966	cypress_notify_link_speed_change_before_state_change(rdev, new_ps, old_ps);
		1967
		1968	rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
		1969	ret = rv770_halt_smc(rdev);
		1970	if (ret) {
		1971	DRM_ERROR("rv770_halt_smc failed\n");
		1972	return ret;
		1973	}
		1974	ret = cypress_upload_sw_state(rdev, new_ps);
		1975	if (ret) {
		1976	DRM_ERROR("cypress_upload_sw_state failed\n");
		1977	return ret;
		1978	}
		1979	if (eg_pi->dynamic_ac_timing) {
		1980	ret = cypress_upload_mc_reg_table(rdev, new_ps);
		1981	if (ret) {
		1982	DRM_ERROR("cypress_upload_mc_reg_table failed\n");
		1983	return ret;
		1984	}
		1985	}
		1986
		1987	cypress_program_memory_timing_parameters(rdev, new_ps);
		1988
		1989	ret = rv770_resume_smc(rdev);
		1990	if (ret) {
		1991	DRM_ERROR("rv770_resume_smc failed\n");
		1992	return ret;
		1993	}
		1994	ret = rv770_set_sw_state(rdev);
		1995	if (ret) {
		1996	DRM_ERROR("rv770_set_sw_state failed\n");
		1997	return ret;
		1998	}
		1999	rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
		2000
		2001	if (eg_pi->pcie_performance_request)
		2002	cypress_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
		2003
		2004	return 0;
		2005	}
		2006
		2007	void cypress_dpm_reset_asic(struct radeon_device *rdev)
		2008	{
		2009	rv770_restrict_performance_levels_before_switch(rdev);
		2010	rv770_set_boot_state(rdev);
		2011	}
		2012
		2013	void cypress_dpm_display_configuration_changed(struct radeon_device *rdev)
		2014	{
		2015	cypress_program_display_gap(rdev);
		2016	}
		2017
		2018	int cypress_dpm_init(struct radeon_device *rdev)
		2019	{
		2020	struct rv7xx_power_info *pi;
		2021	struct evergreen_power_info *eg_pi;
		2022	struct atom_clock_dividers dividers;
		2023	int ret;
		2024
		2025	eg_pi = kzalloc(sizeof(struct evergreen_power_info), GFP_KERNEL);
		2026	if (eg_pi == NULL)
		2027	return -ENOMEM;
		2028	rdev->pm.dpm.priv = eg_pi;
		2029	pi = &eg_pi->rv7xx;
		2030
		2031	rv770_get_max_vddc(rdev);
		2032
		2033	eg_pi->ulv.supported = false;
		2034	pi->acpi_vddc = 0;
		2035	eg_pi->acpi_vddci = 0;
		2036	pi->min_vddc_in_table = 0;
		2037	pi->max_vddc_in_table = 0;
		2038
		2039	ret = r600_get_platform_caps(rdev);
		2040	if (ret)
		2041	return ret;
		2042
		2043	ret = rv7xx_parse_power_table(rdev);
		2044	if (ret)
		2045	return ret;
		2046
		2047	if (rdev->pm.dpm.voltage_response_time == 0)
		2048	rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
		2049	if (rdev->pm.dpm.backbias_response_time == 0)
		2050	rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
		2051
		2052	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
		2053	0, false, ÷rs);
		2054	if (ret)
		2055	pi->ref_div = dividers.ref_div + 1;
		2056	else
		2057	pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
		2058
		2059	pi->mclk_strobe_mode_threshold = 40000;
		2060	pi->mclk_edc_enable_threshold = 40000;
		2061	eg_pi->mclk_edc_wr_enable_threshold = 40000;
		2062
		2063	pi->rlp = RV770_RLP_DFLT;
		2064	pi->rmp = RV770_RMP_DFLT;
		2065	pi->lhp = RV770_LHP_DFLT;
		2066	pi->lmp = RV770_LMP_DFLT;
		2067
		2068	pi->voltage_control =
		2069	radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0);
		2070
		2071	pi->mvdd_control =
		2072	radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 0);
		2073
		2074	eg_pi->vddci_control =
		2075	radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0);
		2076
		2077	rv770_get_engine_memory_ss(rdev);
		2078
		2079	pi->asi = RV770_ASI_DFLT;
		2080	pi->pasi = CYPRESS_HASI_DFLT;
		2081	pi->vrc = CYPRESS_VRC_DFLT;
		2082
		2083	pi->power_gating = false;
		2084
		2085	if ((rdev->family == CHIP_CYPRESS) \|\|
		2086	(rdev->family == CHIP_HEMLOCK))
		2087	pi->gfx_clock_gating = false;
		2088	else
		2089	pi->gfx_clock_gating = true;
		2090
		2091	pi->mg_clock_gating = true;
		2092	pi->mgcgtssm = true;
		2093	eg_pi->ls_clock_gating = false;
		2094	eg_pi->sclk_deep_sleep = false;
		2095
		2096	pi->dynamic_pcie_gen2 = true;
		2097
		2098	if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
		2099	pi->thermal_protection = true;
		2100	else
		2101	pi->thermal_protection = false;
		2102
		2103	pi->display_gap = true;
		2104
		2105	if (rdev->flags & RADEON_IS_MOBILITY)
		2106	pi->dcodt = true;
		2107	else
		2108	pi->dcodt = false;
		2109
		2110	pi->ulps = true;
		2111
		2112	eg_pi->dynamic_ac_timing = true;
		2113	eg_pi->abm = true;
		2114	eg_pi->mcls = true;
		2115	eg_pi->light_sleep = true;
		2116	eg_pi->memory_transition = true;
		2117	#if defined(CONFIG_ACPI)
		2118	eg_pi->pcie_performance_request =
		2119	radeon_acpi_is_pcie_performance_request_supported(rdev);
		2120	#else
		2121	eg_pi->pcie_performance_request = false;
		2122	#endif
		2123
		2124	if ((rdev->family == CHIP_CYPRESS) \|\|
		2125	(rdev->family == CHIP_HEMLOCK) \|\|
		2126	(rdev->family == CHIP_JUNIPER))
		2127	eg_pi->dll_default_on = true;
		2128	else
		2129	eg_pi->dll_default_on = false;
		2130
		2131	eg_pi->sclk_deep_sleep = false;
		2132	pi->mclk_stutter_mode_threshold = 0;
		2133
		2134	pi->sram_end = SMC_RAM_END;
		2135
		2136	return 0;
		2137	}
		2138
		2139	void cypress_dpm_fini(struct radeon_device *rdev)
		2140	{
		2141	int i;
		2142
		2143	for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
		2144	kfree(rdev->pm.dpm.ps[i].ps_priv);
		2145	}
		2146	kfree(rdev->pm.dpm.ps);
		2147	kfree(rdev->pm.dpm.priv);
		2148	}
		2149
		2150	bool cypress_dpm_vblank_too_short(struct radeon_device *rdev)
		2151	{
		2152	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
		2153	u32 vblank_time = r600_dpm_get_vblank_time(rdev);
		2154	/* we never hit the non-gddr5 limit so disable it */
		2155	u32 switch_limit = pi->mem_gddr5 ? 450 : 0;
		2156
		2157	if (vblank_time < switch_limit)
		2158	return true;
		2159	else
		2160	return false;
		2161
		2162	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/cypress_dpm.c @ 5271 – Rev 5078