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5078 | serge | 1 | /* |
2 | * Copyright 2012 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
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12 | * all copies or substantial portions of the Software. |
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13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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20 | * OTHER DEALINGS IN THE SOFTWARE. |
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21 | * |
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22 | * Authors: Alex Deucher |
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23 | */ |
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24 | #ifndef __CIK_REG_H__ |
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25 | #define __CIK_REG_H__ |
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26 | |||
27 | #define CIK_DIDT_IND_INDEX 0xca00 |
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28 | #define CIK_DIDT_IND_DATA 0xca04 |
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29 | |||
30 | #define CIK_DC_GPIO_HPD_MASK 0x65b0 |
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31 | #define CIK_DC_GPIO_HPD_A 0x65b4 |
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32 | #define CIK_DC_GPIO_HPD_EN 0x65b8 |
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33 | #define CIK_DC_GPIO_HPD_Y 0x65bc |
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34 | |||
35 | #define CIK_GRPH_CONTROL 0x6804 |
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36 | # define CIK_GRPH_DEPTH(x) (((x) & 0x3) << 0) |
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37 | # define CIK_GRPH_DEPTH_8BPP 0 |
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38 | # define CIK_GRPH_DEPTH_16BPP 1 |
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39 | # define CIK_GRPH_DEPTH_32BPP 2 |
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40 | # define CIK_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2) |
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41 | # define CIK_ADDR_SURF_2_BANK 0 |
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42 | # define CIK_ADDR_SURF_4_BANK 1 |
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43 | # define CIK_ADDR_SURF_8_BANK 2 |
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44 | # define CIK_ADDR_SURF_16_BANK 3 |
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45 | # define CIK_GRPH_Z(x) (((x) & 0x3) << 4) |
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46 | # define CIK_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6) |
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47 | # define CIK_ADDR_SURF_BANK_WIDTH_1 0 |
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48 | # define CIK_ADDR_SURF_BANK_WIDTH_2 1 |
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49 | # define CIK_ADDR_SURF_BANK_WIDTH_4 2 |
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50 | # define CIK_ADDR_SURF_BANK_WIDTH_8 3 |
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51 | # define CIK_GRPH_FORMAT(x) (((x) & 0x7) << 8) |
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52 | /* 8 BPP */ |
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53 | # define CIK_GRPH_FORMAT_INDEXED 0 |
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54 | /* 16 BPP */ |
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55 | # define CIK_GRPH_FORMAT_ARGB1555 0 |
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56 | # define CIK_GRPH_FORMAT_ARGB565 1 |
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57 | # define CIK_GRPH_FORMAT_ARGB4444 2 |
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58 | # define CIK_GRPH_FORMAT_AI88 3 |
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59 | # define CIK_GRPH_FORMAT_MONO16 4 |
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60 | # define CIK_GRPH_FORMAT_BGRA5551 5 |
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61 | /* 32 BPP */ |
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62 | # define CIK_GRPH_FORMAT_ARGB8888 0 |
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63 | # define CIK_GRPH_FORMAT_ARGB2101010 1 |
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64 | # define CIK_GRPH_FORMAT_32BPP_DIG 2 |
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65 | # define CIK_GRPH_FORMAT_8B_ARGB2101010 3 |
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66 | # define CIK_GRPH_FORMAT_BGRA1010102 4 |
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67 | # define CIK_GRPH_FORMAT_8B_BGRA1010102 5 |
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68 | # define CIK_GRPH_FORMAT_RGB111110 6 |
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69 | # define CIK_GRPH_FORMAT_BGR101111 7 |
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70 | # define CIK_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11) |
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71 | # define CIK_ADDR_SURF_BANK_HEIGHT_1 0 |
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72 | # define CIK_ADDR_SURF_BANK_HEIGHT_2 1 |
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73 | # define CIK_ADDR_SURF_BANK_HEIGHT_4 2 |
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74 | # define CIK_ADDR_SURF_BANK_HEIGHT_8 3 |
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75 | # define CIK_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13) |
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76 | # define CIK_ADDR_SURF_TILE_SPLIT_64B 0 |
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77 | # define CIK_ADDR_SURF_TILE_SPLIT_128B 1 |
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78 | # define CIK_ADDR_SURF_TILE_SPLIT_256B 2 |
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79 | # define CIK_ADDR_SURF_TILE_SPLIT_512B 3 |
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80 | # define CIK_ADDR_SURF_TILE_SPLIT_1KB 4 |
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81 | # define CIK_ADDR_SURF_TILE_SPLIT_2KB 5 |
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82 | # define CIK_ADDR_SURF_TILE_SPLIT_4KB 6 |
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83 | # define CIK_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18) |
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84 | # define CIK_ADDR_SURF_MACRO_TILE_ASPECT_1 0 |
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85 | # define CIK_ADDR_SURF_MACRO_TILE_ASPECT_2 1 |
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86 | # define CIK_ADDR_SURF_MACRO_TILE_ASPECT_4 2 |
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87 | # define CIK_ADDR_SURF_MACRO_TILE_ASPECT_8 3 |
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88 | # define CIK_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20) |
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89 | # define CIK_GRPH_ARRAY_LINEAR_GENERAL 0 |
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90 | # define CIK_GRPH_ARRAY_LINEAR_ALIGNED 1 |
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91 | # define CIK_GRPH_ARRAY_1D_TILED_THIN1 2 |
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92 | # define CIK_GRPH_ARRAY_2D_TILED_THIN1 4 |
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93 | # define CIK_GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24) |
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94 | # define CIK_ADDR_SURF_P2 0 |
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95 | # define CIK_ADDR_SURF_P4_8x16 4 |
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96 | # define CIK_ADDR_SURF_P4_16x16 5 |
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97 | # define CIK_ADDR_SURF_P4_16x32 6 |
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98 | # define CIK_ADDR_SURF_P4_32x32 7 |
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99 | # define CIK_ADDR_SURF_P8_16x16_8x16 8 |
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100 | # define CIK_ADDR_SURF_P8_16x32_8x16 9 |
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101 | # define CIK_ADDR_SURF_P8_32x32_8x16 10 |
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102 | # define CIK_ADDR_SURF_P8_16x32_16x16 11 |
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103 | # define CIK_ADDR_SURF_P8_32x32_16x16 12 |
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104 | # define CIK_ADDR_SURF_P8_32x32_16x32 13 |
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105 | # define CIK_ADDR_SURF_P8_32x64_32x32 14 |
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106 | # define CIK_GRPH_MICRO_TILE_MODE(x) (((x) & 0x7) << 29) |
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107 | # define CIK_DISPLAY_MICRO_TILING 0 |
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108 | # define CIK_THIN_MICRO_TILING 1 |
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109 | # define CIK_DEPTH_MICRO_TILING 2 |
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110 | # define CIK_ROTATED_MICRO_TILING 4 |
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111 | |||
112 | /* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */ |
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113 | #define CIK_CUR_CONTROL 0x6998 |
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114 | # define CIK_CURSOR_EN (1 << 0) |
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115 | # define CIK_CURSOR_MODE(x) (((x) & 0x3) << 8) |
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116 | # define CIK_CURSOR_MONO 0 |
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117 | # define CIK_CURSOR_24_1 1 |
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118 | # define CIK_CURSOR_24_8_PRE_MULT 2 |
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119 | # define CIK_CURSOR_24_8_UNPRE_MULT 3 |
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120 | # define CIK_CURSOR_2X_MAGNIFY (1 << 16) |
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121 | # define CIK_CURSOR_FORCE_MC_ON (1 << 20) |
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122 | # define CIK_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24) |
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123 | # define CIK_CURSOR_URGENT_ALWAYS 0 |
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124 | # define CIK_CURSOR_URGENT_1_8 1 |
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125 | # define CIK_CURSOR_URGENT_1_4 2 |
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126 | # define CIK_CURSOR_URGENT_3_8 3 |
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127 | # define CIK_CURSOR_URGENT_1_2 4 |
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128 | #define CIK_CUR_SURFACE_ADDRESS 0x699c |
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129 | # define CIK_CUR_SURFACE_ADDRESS_MASK 0xfffff000 |
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130 | #define CIK_CUR_SIZE 0x69a0 |
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131 | #define CIK_CUR_SURFACE_ADDRESS_HIGH 0x69a4 |
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132 | #define CIK_CUR_POSITION 0x69a8 |
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133 | #define CIK_CUR_HOT_SPOT 0x69ac |
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134 | #define CIK_CUR_COLOR1 0x69b0 |
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135 | #define CIK_CUR_COLOR2 0x69b4 |
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136 | #define CIK_CUR_UPDATE 0x69b8 |
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137 | # define CIK_CURSOR_UPDATE_PENDING (1 << 0) |
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138 | # define CIK_CURSOR_UPDATE_TAKEN (1 << 1) |
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139 | # define CIK_CURSOR_UPDATE_LOCK (1 << 16) |
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140 | # define CIK_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24) |
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141 | |||
142 | #define CIK_ALPHA_CONTROL 0x6af0 |
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143 | # define CIK_CURSOR_ALPHA_BLND_ENA (1 << 1) |
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144 | |||
145 | #define CIK_LB_DATA_FORMAT 0x6b00 |
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146 | # define CIK_INTERLEAVE_EN (1 << 3) |
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147 | |||
148 | #define CIK_LB_DESKTOP_HEIGHT 0x6b0c |
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149 | |||
6104 | serge | 150 | #define KFD_CIK_SDMA_QUEUE_OFFSET 0x200 |
151 | |||
152 | #define SQ_IND_INDEX 0x8DE0 |
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153 | #define SQ_CMD 0x8DEC |
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154 | #define SQ_IND_DATA 0x8DE4 |
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155 | |||
156 | /* |
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157 | * The TCP_WATCHx_xxxx addresses that are shown here are in dwords, |
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158 | * and that's why they are multiplied by 4 |
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159 | */ |
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160 | #define TCP_WATCH0_ADDR_H (0x32A0*4) |
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161 | #define TCP_WATCH1_ADDR_H (0x32A3*4) |
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162 | #define TCP_WATCH2_ADDR_H (0x32A6*4) |
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163 | #define TCP_WATCH3_ADDR_H (0x32A9*4) |
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164 | #define TCP_WATCH0_ADDR_L (0x32A1*4) |
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165 | #define TCP_WATCH1_ADDR_L (0x32A4*4) |
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166 | #define TCP_WATCH2_ADDR_L (0x32A7*4) |
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167 | #define TCP_WATCH3_ADDR_L (0x32AA*4) |
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168 | #define TCP_WATCH0_CNTL (0x32A2*4) |
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169 | #define TCP_WATCH1_CNTL (0x32A5*4) |
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170 | #define TCP_WATCH2_CNTL (0x32A8*4) |
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171 | #define TCP_WATCH3_CNTL (0x32AB*4) |
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172 | |||
173 | #define CPC_INT_CNTL 0xC2D0 |
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174 | |||
5271 | serge | 175 | #define CP_HQD_IQ_RPTR 0xC970u |
6104 | serge | 176 | #define SDMA0_RLC0_RB_CNTL 0xD400u |
177 | #define SDMA_RB_VMID(x) (x << 24) |
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178 | #define SDMA0_RLC0_RB_BASE 0xD404u |
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179 | #define SDMA0_RLC0_RB_BASE_HI 0xD408u |
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180 | #define SDMA0_RLC0_RB_RPTR 0xD40Cu |
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181 | #define SDMA0_RLC0_RB_WPTR 0xD410u |
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182 | #define SDMA0_RLC0_RB_WPTR_POLL_CNTL 0xD414u |
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183 | #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0xD418u |
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184 | #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0xD41Cu |
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185 | #define SDMA0_RLC0_RB_RPTR_ADDR_HI 0xD420u |
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186 | #define SDMA0_RLC0_RB_RPTR_ADDR_LO 0xD424u |
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187 | #define SDMA0_RLC0_IB_CNTL 0xD428u |
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188 | #define SDMA0_RLC0_IB_RPTR 0xD42Cu |
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189 | #define SDMA0_RLC0_IB_OFFSET 0xD430u |
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190 | #define SDMA0_RLC0_IB_BASE_LO 0xD434u |
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191 | #define SDMA0_RLC0_IB_BASE_HI 0xD438u |
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192 | #define SDMA0_RLC0_IB_SIZE 0xD43Cu |
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193 | #define SDMA0_RLC0_SKIP_CNTL 0xD440u |
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194 | #define SDMA0_RLC0_CONTEXT_STATUS 0xD444u |
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195 | #define SDMA_RLC_IDLE (1 << 2) |
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196 | #define SDMA0_RLC0_DOORBELL 0xD448u |
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197 | #define SDMA_OFFSET(x) (x << 0) |
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198 | #define SDMA_DB_ENABLE (1 << 28) |
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199 | #define SDMA0_RLC0_VIRTUAL_ADDR 0xD49Cu |
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200 | #define SDMA_ATC (1 << 0) |
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201 | #define SDMA_VA_PTR32 (1 << 4) |
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202 | #define SDMA_VA_SHARED_BASE(x) (x << 8) |
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203 | #define SDMA0_RLC0_APE1_CNTL 0xD4A0u |
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204 | #define SDMA0_RLC0_DOORBELL_LOG 0xD4A4u |
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205 | #define SDMA0_RLC0_WATERMARK 0xD4A8u |
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206 | #define SDMA0_CNTL 0xD010 |
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207 | #define SDMA1_CNTL 0xD810 |
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5271 | serge | 208 | |
6104 | serge | 209 | enum { |
210 | MAX_TRAPID = 8, /* 3 bits in the bitfield. */ |
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211 | MAX_WATCH_ADDRESSES = 4 |
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212 | }; |
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5271 | serge | 213 | |
6104 | serge | 214 | enum { |
215 | ADDRESS_WATCH_REG_ADDR_HI = 0, |
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216 | ADDRESS_WATCH_REG_ADDR_LO, |
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217 | ADDRESS_WATCH_REG_CNTL, |
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218 | ADDRESS_WATCH_REG_MAX |
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5271 | serge | 219 | }; |
220 | |||
6104 | serge | 221 | enum { /* not defined in the CI/KV reg file */ |
222 | ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL, |
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223 | ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF, |
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224 | ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000, |
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225 | /* extend the mask to 26 bits in order to match the low address field */ |
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226 | ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6, |
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227 | ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF |
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228 | }; |
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229 | |||
230 | union TCP_WATCH_CNTL_BITS { |
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231 | struct { |
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232 | uint32_t mask:24; |
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233 | uint32_t vmid:4; |
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234 | uint32_t atc:1; |
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235 | uint32_t mode:2; |
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236 | uint32_t valid:1; |
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237 | } bitfields, bits; |
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238 | uint32_t u32All; |
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239 | signed int i32All; |
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240 | float f32All; |
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241 | }; |
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242 | |||
5078 | serge | 243 | #endif><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |