WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/cayman_blit_shaders.c

Rev	Author	Line No.	Line
2004	serge	1	/*
		2	* Copyright 2010 Advanced Micro Devices, Inc.
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
		21	* DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors:
		24	* Alex Deucher
		25	*/
		26
		27	#include
		28	#include
		29
		30	/*
		31	* evergreen cards need to use the 3D engine to blit data which requires
		32	* quite a bit of hw state setup. Rather than pull the whole 3D driver
		33	* (which normally generates the 3D state) into the DRM, we opt to use
		34	* statically generated state tables. The regsiter state and shaders
		35	* were hand generated to support blitting functionality. See the 3D
		36	* driver or documentation for descriptions of the registers and
		37	* shader instructions.
		38	*/
		39
		40	const u32 cayman_default_state[] =
		41	{
		42	0xc0066900,
		43	0x00000000,
		44	0x00000060, /* DB_RENDER_CONTROL */
		45	0x00000000, /* DB_COUNT_CONTROL */
		46	0x00000000, /* DB_DEPTH_VIEW */
		47	0x0000002a, /* DB_RENDER_OVERRIDE */
		48	0x00000000, /* DB_RENDER_OVERRIDE2 */
		49	0x00000000, /* DB_HTILE_DATA_BASE */
		50
		51	0xc0026900,
		52	0x0000000a,
		53	0x00000000, /* DB_STENCIL_CLEAR */
		54	0x00000000, /* DB_DEPTH_CLEAR */
		55
		56	0xc0036900,
		57	0x0000000f,
		58	0x00000000, /* DB_DEPTH_INFO */
		59	0x00000000, /* DB_Z_INFO */
		60	0x00000000, /* DB_STENCIL_INFO */
		61
		62	0xc0016900,
		63	0x00000080,
		64	0x00000000, /* PA_SC_WINDOW_OFFSET */
		65
		66	0xc00d6900,
		67	0x00000083,
		68	0x0000ffff, /* PA_SC_CLIPRECT_RULE */
		69	0x00000000, /* PA_SC_CLIPRECT_0_TL */
		70	0x20002000, /* PA_SC_CLIPRECT_0_BR */
		71	0x00000000,
		72	0x20002000,
		73	0x00000000,
		74	0x20002000,
		75	0x00000000,
		76	0x20002000,
		77	0xaaaaaaaa, /* PA_SC_EDGERULE */
		78	0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */
		79	0x0000000f, /* CB_TARGET_MASK */
		80	0x0000000f, /* CB_SHADER_MASK */
		81
		82	0xc0226900,
		83	0x00000094,
		84	0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
		85	0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
		86	0x80000000,
		87	0x20002000,
		88	0x80000000,
		89	0x20002000,
		90	0x80000000,
		91	0x20002000,
		92	0x80000000,
		93	0x20002000,
		94	0x80000000,
		95	0x20002000,
		96	0x80000000,
		97	0x20002000,
		98	0x80000000,
		99	0x20002000,
		100	0x80000000,
		101	0x20002000,
		102	0x80000000,
		103	0x20002000,
		104	0x80000000,
		105	0x20002000,
		106	0x80000000,
		107	0x20002000,
		108	0x80000000,
		109	0x20002000,
		110	0x80000000,
		111	0x20002000,
		112	0x80000000,
		113	0x20002000,
		114	0x80000000,
		115	0x20002000,
		116	0x00000000, /* PA_SC_VPORT_ZMIN_0 */
		117	0x3f800000, /* PA_SC_VPORT_ZMAX_0 */
		118
		119	0xc0016900,
		120	0x000000d4,
		121	0x00000000, /* SX_MISC */
		122
		123	0xc0026900,
		124	0x000000d9,
		125	0x00000000, /* CP_RINGID */
		126	0x00000000, /* CP_VMID */
		127
		128	0xc0096900,
		129	0x00000100,
		130	0x00ffffff, /* VGT_MAX_VTX_INDX */
		131	0x00000000, /* VGT_MIN_VTX_INDX */
		132	0x00000000, /* VGT_INDX_OFFSET */
		133	0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
		134	0x00000000, /* SX_ALPHA_TEST_CONTROL */
		135	0x00000000, /* CB_BLEND_RED */
		136	0x00000000, /* CB_BLEND_GREEN */
		137	0x00000000, /* CB_BLEND_BLUE */
		138	0x00000000, /* CB_BLEND_ALPHA */
		139
		140	0xc0016900,
		141	0x00000187,
		142	0x00000100, /* SPI_VS_OUT_ID_0 */
		143
		144	0xc0026900,
		145	0x00000191,
		146	0x00000100, /* SPI_PS_INPUT_CNTL_0 */
		147	0x00000101, /* SPI_PS_INPUT_CNTL_1 */
		148
		149	0xc0016900,
		150	0x000001b1,
		151	0x00000000, /* SPI_VS_OUT_CONFIG */
		152
		153	0xc0106900,
		154	0x000001b3,
		155	0x20000001, /* SPI_PS_IN_CONTROL_0 */
		156	0x00000000, /* SPI_PS_IN_CONTROL_1 */
		157	0x00000000, /* SPI_INTERP_CONTROL_0 */
		158	0x00000000, /* SPI_INPUT_Z */
		159	0x00000000, /* SPI_FOG_CNTL */
		160	0x00100000, /* SPI_BARYC_CNTL */
		161	0x00000000, /* SPI_PS_IN_CONTROL_2 */
		162	0x00000000, /* SPI_COMPUTE_INPUT_CNTL */
		163	0x00000000, /* SPI_COMPUTE_NUM_THREAD_X */
		164	0x00000000, /* SPI_COMPUTE_NUM_THREAD_Y */
		165	0x00000000, /* SPI_COMPUTE_NUM_THREAD_Z */
		166	0x00000000, /* SPI_GPR_MGMT */
		167	0x00000000, /* SPI_LDS_MGMT */
		168	0x00000000, /* SPI_STACK_MGMT */
		169	0x00000000, /* SPI_WAVE_MGMT_1 */
		170	0x00000000, /* SPI_WAVE_MGMT_2 */
		171
		172	0xc0016900,
		173	0x000001e0,
		174	0x00000000, /* CB_BLEND0_CONTROL */
		175
		176	0xc00e6900,
		177	0x00000200,
		178	0x00000000, /* DB_DEPTH_CONTROL */
		179	0x00000000, /* DB_EQAA */
		180	0x00cc0010, /* CB_COLOR_CONTROL */
		181	0x00000210, /* DB_SHADER_CONTROL */
		182	0x00010000, /* PA_CL_CLIP_CNTL */
		183	0x00000004, /* PA_SU_SC_MODE_CNTL */
		184	0x00000100, /* PA_CL_VTE_CNTL */
		185	0x00000000, /* PA_CL_VS_OUT_CNTL */
		186	0x00000000, /* PA_CL_NANINF_CNTL */
		187	0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */
		188	0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */
		189	0x00000000, /* PA_SU_PRIM_FILTER_CNTL */
		190	0x00000000, /* */
		191	0x00000000, /* */
		192
		193	0xc0026900,
		194	0x00000229,
		195	0x00000000, /* SQ_PGM_START_FS */
		196	0x00000000,
		197
		198	0xc0016900,
		199	0x0000023b,
		200	0x00000000, /* SQ_LDS_ALLOC_PS */
		201
		202	0xc0066900,
		203	0x00000240,
		204	0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
		205	0x00000000,
		206	0x00000000,
		207	0x00000000,
		208	0x00000000,
		209	0x00000000,
		210
		211	0xc0046900,
		212	0x00000247,
		213	0x00000000, /* SQ_GS_VERT_ITEMSIZE */
		214	0x00000000,
		215	0x00000000,
		216	0x00000000,
		217
		218	0xc0116900,
		219	0x00000280,
		220	0x00000000, /* PA_SU_POINT_SIZE */
		221	0x00000000, /* PA_SU_POINT_MINMAX */
		222	0x00000008, /* PA_SU_LINE_CNTL */
		223	0x00000000, /* PA_SC_LINE_STIPPLE */
		224	0x00000000, /* VGT_OUTPUT_PATH_CNTL */
		225	0x00000000, /* VGT_HOS_CNTL */
		226	0x00000000,
		227	0x00000000,
		228	0x00000000,
		229	0x00000000,
		230	0x00000000,
		231	0x00000000,
		232	0x00000000,
		233	0x00000000,
		234	0x00000000,
		235	0x00000000,
		236	0x00000000, /* VGT_GS_MODE */
		237
		238	0xc0026900,
		239	0x00000292,
		240	0x00000000, /* PA_SC_MODE_CNTL_0 */
		241	0x00000000, /* PA_SC_MODE_CNTL_1 */
		242
		243	0xc0016900,
		244	0x000002a1,
		245	0x00000000, /* VGT_PRIMITIVEID_EN */
		246
		247	0xc0016900,
		248	0x000002a5,
		249	0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */
		250
		251	0xc0026900,
		252	0x000002a8,
		253	0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
		254	0x00000000,
		255
		256	0xc0026900,
		257	0x000002ad,
		258	0x00000000, /* VGT_REUSE_OFF */
		259	0x00000000,
		260
		261	0xc0016900,
		262	0x000002d5,
		263	0x00000000, /* VGT_SHADER_STAGES_EN */
		264
		265	0xc0016900,
		266	0x000002dc,
		267	0x0000aa00, /* DB_ALPHA_TO_MASK */
		268
		269	0xc0066900,
		270	0x000002de,
		271	0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
		272	0x00000000,
		273	0x00000000,
		274	0x00000000,
		275	0x00000000,
		276	0x00000000,
		277
		278	0xc0026900,
		279	0x000002e5,
		280	0x00000000, /* VGT_STRMOUT_CONFIG */
		281	0x00000000,
		282
		283	0xc01b6900,
		284	0x000002f5,
		285	0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */
		286	0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */
		287	0x00000000, /* PA_SC_LINE_CNTL */
		288	0x00000000, /* PA_SC_AA_CONFIG */
		289	0x00000005, /* PA_SU_VTX_CNTL */
		290	0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
		291	0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */
		292	0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */
		293	0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */
		294	0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
		295	0x00000000,
		296	0x00000000,
		297	0x00000000,
		298	0x00000000,
		299	0x00000000,
		300	0x00000000,
		301	0x00000000,
		302	0x00000000,
		303	0x00000000,
		304	0x00000000,
		305	0x00000000,
		306	0x00000000,
		307	0x00000000,
		308	0x00000000,
		309	0x00000000,
		310	0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */
		311	0xffffffff,
		312
		313	0xc0026900,
		314	0x00000316,
		315	0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
		316	0x00000010, /* */
		317	};
		318
		319	const u32 cayman_vs[] =
		320	{
		321	0x00000004,
		322	0x80400400,
		323	0x0000a03c,
		324	0x95000688,
		325	0x00004000,
		326	0x15000688,
		327	0x00000000,
		328	0x88000000,
		329	0x04000000,
		330	0x67961001,
		331	#ifdef __BIG_ENDIAN
		332	0x00020000,
		333	#else
		334	0x00000000,
		335	#endif
		336	0x00000000,
		337	0x04000000,
		338	0x67961000,
		339	#ifdef __BIG_ENDIAN
		340	0x00020008,
		341	#else
		342	0x00000008,
		343	#endif
		344	0x00000000,
		345	};
		346
		347	const u32 cayman_ps[] =
		348	{
		349	0x00000004,
		350	0xa00c0000,
		351	0x00000008,
		352	0x80400000,
		353	0x00000000,
		354	0x95000688,
		355	0x00000000,
		356	0x88000000,
		357	0x00380400,
		358	0x00146b10,
		359	0x00380000,
		360	0x20146b10,
		361	0x00380400,
		362	0x40146b00,
		363	0x80380000,
		364	0x60146b00,
		365	0x00000010,
		366	0x000d1000,
		367	0xb0800000,
		368	0x00000000,
		369	};
		370
		371	const u32 cayman_ps_size = ARRAY_SIZE(cayman_ps);
		372	const u32 cayman_vs_size = ARRAY_SIZE(cayman_vs);
		373	const u32 cayman_default_size = ARRAY_SIZE(cayman_default_state);

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(root)/drivers/video/drm/radeon/cayman_blit_shaders.c @ 2175 – Rev 2004