WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/atombios_encoders.c

Rev	Author	Line No.	Line
2997	Serge	1	/*
		2	* Copyright 2007-11 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
		26	#include
		27	#include
		28	#include
		29	#include "radeon.h"
		30	#include "atom.h"
		31	#include
		32
		33	extern int atom_debug;
		34
		35	static u8
		36	radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
		37	{
		38	u8 backlight_level;
		39	u32 bios_2_scratch;
		40
		41	if (rdev->family >= CHIP_R600)
		42	bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
		43	else
		44	bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
		45
		46	backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
		47	ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
		48
		49	return backlight_level;
		50	}
		51
		52	static void
		53	radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
		54	u8 backlight_level)
		55	{
		56	u32 bios_2_scratch;
		57
		58	if (rdev->family >= CHIP_R600)
		59	bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
		60	else
		61	bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
		62
		63	bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
		64	bios_2_scratch \|= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
		65	ATOM_S2_CURRENT_BL_LEVEL_MASK);
		66
		67	if (rdev->family >= CHIP_R600)
		68	WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
		69	else
		70	WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
		71	}
		72
		73	u8
		74	atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
		75	{
		76	struct drm_device *dev = radeon_encoder->base.dev;
		77	struct radeon_device *rdev = dev->dev_private;
		78
		79	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
		80	return 0;
		81
		82	return radeon_atom_get_backlight_level_from_reg(rdev);
		83	}
		84
		85	void
		86	atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
		87	{
		88	struct drm_encoder *encoder = &radeon_encoder->base;
		89	struct drm_device *dev = radeon_encoder->base.dev;
		90	struct radeon_device *rdev = dev->dev_private;
		91	struct radeon_encoder_atom_dig *dig;
		92	DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
		93	int index;
		94
		95	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
		96	return;
		97
		98	if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
		99	radeon_encoder->enc_priv) {
		100	dig = radeon_encoder->enc_priv;
		101	dig->backlight_level = level;
		102	radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
		103
		104	switch (radeon_encoder->encoder_id) {
		105	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		106	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		107	index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
		108	if (dig->backlight_level == 0) {
		109	args.ucAction = ATOM_LCD_BLOFF;
		110	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		111	} else {
		112	args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
		113	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		114	args.ucAction = ATOM_LCD_BLON;
		115	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		116	}
		117	break;
		118	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		119	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		120	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		121	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		122	if (dig->backlight_level == 0)
		123	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
		124	else {
		125	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
		126	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
		127	}
		128	break;
		129	default:
		130	break;
		131	}
		132	}
		133	}
		134
		135	#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) \|\| defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
		136
		137	static u8 radeon_atom_bl_level(struct backlight_device *bd)
		138	{
		139	u8 level;
		140
		141	/* Convert brightness to hardware level */
		142	if (bd->props.brightness < 0)
		143	level = 0;
		144	else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
		145	level = RADEON_MAX_BL_LEVEL;
		146	else
		147	level = bd->props.brightness;
		148
		149	return level;
		150	}
		151
		152	static int radeon_atom_backlight_update_status(struct backlight_device *bd)
		153	{
		154	struct radeon_backlight_privdata *pdata = bl_get_data(bd);
		155	struct radeon_encoder *radeon_encoder = pdata->encoder;
		156
		157	atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
		158
		159	return 0;
		160	}
		161
		162	static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
		163	{
		164	struct radeon_backlight_privdata *pdata = bl_get_data(bd);
		165	struct radeon_encoder *radeon_encoder = pdata->encoder;
		166	struct drm_device *dev = radeon_encoder->base.dev;
		167	struct radeon_device *rdev = dev->dev_private;
		168
		169	return radeon_atom_get_backlight_level_from_reg(rdev);
		170	}
		171
		172	static const struct backlight_ops radeon_atom_backlight_ops = {
		173	.get_brightness = radeon_atom_backlight_get_brightness,
		174	.update_status = radeon_atom_backlight_update_status,
		175	};
		176
		177	void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
		178	struct drm_connector *drm_connector)
		179	{
		180	struct drm_device *dev = radeon_encoder->base.dev;
		181	struct radeon_device *rdev = dev->dev_private;
		182	struct backlight_device *bd;
		183	struct backlight_properties props;
		184	struct radeon_backlight_privdata *pdata;
		185	struct radeon_encoder_atom_dig *dig;
		186	char bl_name[16];
		187
5078	serge	188	/* Mac laptops with multiple GPUs use the gmux driver for backlight
		189	* so don't register a backlight device
		190	*/
		191	if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
		192	(rdev->pdev->device == 0x6741))
		193	return;
		194
2997	Serge	195	if (!radeon_encoder->enc_priv)
		196	return;
		197
		198	if (!rdev->is_atom_bios)
		199	return;
		200
		201	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
		202	return;
		203
		204	pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
		205	if (!pdata) {
		206	DRM_ERROR("Memory allocation failed\n");
		207	goto error;
		208	}
		209
		210	memset(&props, 0, sizeof(props));
		211	props.max_brightness = RADEON_MAX_BL_LEVEL;
		212	props.type = BACKLIGHT_RAW;
		213	snprintf(bl_name, sizeof(bl_name),
		214	"radeon_bl%d", dev->primary->index);
5078	serge	215	bd = backlight_device_register(bl_name, drm_connector->kdev,
2997	Serge	216	pdata, &radeon_atom_backlight_ops, &props);
		217	if (IS_ERR(bd)) {
		218	DRM_ERROR("Backlight registration failed\n");
		219	goto error;
		220	}
		221
		222	pdata->encoder = radeon_encoder;
		223
		224	dig = radeon_encoder->enc_priv;
		225	dig->bl_dev = bd;
		226
		227	bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
5078	serge	228	/* Set a reasonable default here if the level is 0 otherwise
		229	* fbdev will attempt to turn the backlight on after console
		230	* unblanking and it will try and restore 0 which turns the backlight
		231	* off again.
		232	*/
		233	if (bd->props.brightness == 0)
		234	bd->props.brightness = RADEON_MAX_BL_LEVEL;
2997	Serge	235	bd->props.power = FB_BLANK_UNBLANK;
		236	backlight_update_status(bd);
		237
		238	DRM_INFO("radeon atom DIG backlight initialized\n");
		239
		240	return;
		241
		242	error:
		243	kfree(pdata);
		244	return;
		245	}
		246
		247	static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
		248	{
		249	struct drm_device *dev = radeon_encoder->base.dev;
		250	struct radeon_device *rdev = dev->dev_private;
		251	struct backlight_device *bd = NULL;
		252	struct radeon_encoder_atom_dig *dig;
		253
		254	if (!radeon_encoder->enc_priv)
		255	return;
		256
		257	if (!rdev->is_atom_bios)
		258	return;
		259
		260	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
		261	return;
		262
		263	dig = radeon_encoder->enc_priv;
		264	bd = dig->bl_dev;
		265	dig->bl_dev = NULL;
		266
		267	if (bd) {
		268	struct radeon_legacy_backlight_privdata *pdata;
		269
		270	pdata = bl_get_data(bd);
		271	backlight_device_unregister(bd);
		272	kfree(pdata);
		273
		274	DRM_INFO("radeon atom LVDS backlight unloaded\n");
		275	}
		276	}
		277
		278	#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
		279
		280	void radeon_atom_backlight_init(struct radeon_encoder *encoder)
		281	{
		282	}
		283
		284	static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
		285	{
		286	}
		287
		288	#endif
		289
		290	/* evil but including atombios.h is much worse */
		291	bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
		292	struct drm_display_mode *mode);
		293
		294	static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
		295	const struct drm_display_mode *mode,
		296	struct drm_display_mode *adjusted_mode)
		297	{
		298	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		299	struct drm_device *dev = encoder->dev;
		300	struct radeon_device *rdev = dev->dev_private;
		301
		302	/* set the active encoder to connector routing */
		303	radeon_encoder_set_active_device(encoder);
		304	drm_mode_set_crtcinfo(adjusted_mode, 0);
		305
		306	/* hw bug */
		307	if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
		308	&& (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
		309	adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
		310
5078	serge	311	/* get the native mode for scaling */
		312	if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT\|ATOM_DEVICE_DFP_SUPPORT)) {
2997	Serge	313	radeon_panel_mode_fixup(encoder, adjusted_mode);
5078	serge	314	} else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
2997	Serge	315	struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
		316	if (tv_dac) {
		317	if (tv_dac->tv_std == TV_STD_NTSC \|\|
		318	tv_dac->tv_std == TV_STD_NTSC_J \|\|
		319	tv_dac->tv_std == TV_STD_PAL_M)
		320	radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
		321	else
		322	radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
		323	}
5078	serge	324	} else if (radeon_encoder->rmx_type != RMX_OFF) {
		325	radeon_panel_mode_fixup(encoder, adjusted_mode);
2997	Serge	326	}
		327
		328	if (ASIC_IS_DCE3(rdev) &&
		329	((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT \| ATOM_DEVICE_LCD_SUPPORT)) \|\|
		330	(radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
		331	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
3192	Serge	332	radeon_dp_set_link_config(connector, adjusted_mode);
5078	serge	333	}
2997	Serge	334
		335	return true;
		336	}
		337
		338	static void
		339	atombios_dac_setup(struct drm_encoder *encoder, int action)
		340	{
		341	struct drm_device *dev = encoder->dev;
		342	struct radeon_device *rdev = dev->dev_private;
		343	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		344	DAC_ENCODER_CONTROL_PS_ALLOCATION args;
		345	int index = 0;
		346	struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
		347
		348	memset(&args, 0, sizeof(args));
		349
		350	switch (radeon_encoder->encoder_id) {
		351	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		352	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
		353	index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
		354	break;
		355	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		356	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
		357	index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
		358	break;
		359	}
		360
		361	args.ucAction = action;
		362
		363	if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
		364	args.ucDacStandard = ATOM_DAC1_PS2;
		365	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
		366	args.ucDacStandard = ATOM_DAC1_CV;
		367	else {
		368	switch (dac_info->tv_std) {
		369	case TV_STD_PAL:
		370	case TV_STD_PAL_M:
		371	case TV_STD_SCART_PAL:
		372	case TV_STD_SECAM:
		373	case TV_STD_PAL_CN:
		374	args.ucDacStandard = ATOM_DAC1_PAL;
		375	break;
		376	case TV_STD_NTSC:
		377	case TV_STD_NTSC_J:
		378	case TV_STD_PAL_60:
		379	default:
		380	args.ucDacStandard = ATOM_DAC1_NTSC;
		381	break;
		382	}
		383	}
		384	args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		385
		386	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		387
		388	}
		389
		390	static void
		391	atombios_tv_setup(struct drm_encoder *encoder, int action)
		392	{
		393	struct drm_device *dev = encoder->dev;
		394	struct radeon_device *rdev = dev->dev_private;
		395	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		396	TV_ENCODER_CONTROL_PS_ALLOCATION args;
		397	int index = 0;
		398	struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
		399
		400	memset(&args, 0, sizeof(args));
		401
		402	index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
		403
		404	args.sTVEncoder.ucAction = action;
		405
		406	if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
		407	args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
		408	else {
		409	switch (dac_info->tv_std) {
		410	case TV_STD_NTSC:
		411	args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
		412	break;
		413	case TV_STD_PAL:
		414	args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
		415	break;
		416	case TV_STD_PAL_M:
		417	args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
		418	break;
		419	case TV_STD_PAL_60:
		420	args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
		421	break;
		422	case TV_STD_NTSC_J:
		423	args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
		424	break;
		425	case TV_STD_SCART_PAL:
		426	args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
		427	break;
		428	case TV_STD_SECAM:
		429	args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
		430	break;
		431	case TV_STD_PAL_CN:
		432	args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
		433	break;
		434	default:
		435	args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
		436	break;
		437	}
		438	}
		439
		440	args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		441
		442	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		443
		444	}
		445
		446	static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
		447	{
		448	int bpc = 8;
		449
5078	serge	450	if (encoder->crtc) {
		451	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		452	bpc = radeon_crtc->bpc;
		453	}
2997	Serge	454
		455	switch (bpc) {
		456	case 0:
		457	return PANEL_BPC_UNDEFINE;
		458	case 6:
		459	return PANEL_6BIT_PER_COLOR;
		460	case 8:
		461	default:
		462	return PANEL_8BIT_PER_COLOR;
		463	case 10:
		464	return PANEL_10BIT_PER_COLOR;
		465	case 12:
		466	return PANEL_12BIT_PER_COLOR;
		467	case 16:
		468	return PANEL_16BIT_PER_COLOR;
		469	}
		470	}
		471
		472	union dvo_encoder_control {
		473	ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
		474	DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
		475	DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
5078	serge	476	DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
2997	Serge	477	};
		478
		479	void
		480	atombios_dvo_setup(struct drm_encoder *encoder, int action)
		481	{
		482	struct drm_device *dev = encoder->dev;
		483	struct radeon_device *rdev = dev->dev_private;
		484	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		485	union dvo_encoder_control args;
		486	int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
		487	uint8_t frev, crev;
		488
		489	memset(&args, 0, sizeof(args));
		490
		491	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
		492	return;
		493
		494	/* some R4xx chips have the wrong frev */
		495	if (rdev->family <= CHIP_RV410)
		496	frev = 1;
		497
		498	switch (frev) {
		499	case 1:
		500	switch (crev) {
		501	case 1:
		502	/* R4xx, R5xx */
		503	args.ext_tmds.sXTmdsEncoder.ucEnable = action;
		504
		505	if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		506	args.ext_tmds.sXTmdsEncoder.ucMisc \|= PANEL_ENCODER_MISC_DUAL;
		507
		508	args.ext_tmds.sXTmdsEncoder.ucMisc \|= ATOM_PANEL_MISC_888RGB;
		509	break;
		510	case 2:
		511	/* RS600/690/740 */
		512	args.dvo.sDVOEncoder.ucAction = action;
		513	args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		514	/* DFP1, CRT1, TV1 depending on the type of port */
		515	args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
		516
		517	if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		518	args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute \|= PANEL_ENCODER_MISC_DUAL;
		519	break;
		520	case 3:
		521	/* R6xx */
		522	args.dvo_v3.ucAction = action;
		523	args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		524	args.dvo_v3.ucDVOConfig = 0; /* XXX */
		525	break;
5078	serge	526	case 4:
		527	/* DCE8 */
		528	args.dvo_v4.ucAction = action;
		529	args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		530	args.dvo_v4.ucDVOConfig = 0; /* XXX */
		531	args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
		532	break;
2997	Serge	533	default:
		534	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		535	break;
		536	}
		537	break;
		538	default:
		539	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		540	break;
		541	}
		542
		543	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		544	}
		545
		546	union lvds_encoder_control {
		547	LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
		548	LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
		549	};
		550
		551	void
		552	atombios_digital_setup(struct drm_encoder *encoder, int action)
		553	{
		554	struct drm_device *dev = encoder->dev;
		555	struct radeon_device *rdev = dev->dev_private;
		556	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		557	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
		558	union lvds_encoder_control args;
		559	int index = 0;
		560	int hdmi_detected = 0;
		561	uint8_t frev, crev;
		562
		563	if (!dig)
		564	return;
		565
		566	if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
		567	hdmi_detected = 1;
		568
		569	memset(&args, 0, sizeof(args));
		570
		571	switch (radeon_encoder->encoder_id) {
		572	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		573	index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
		574	break;
		575	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		576	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		577	index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
		578	break;
		579	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		580	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
		581	index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
		582	else
		583	index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
		584	break;
		585	}
		586
		587	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
		588	return;
		589
		590	switch (frev) {
		591	case 1:
		592	case 2:
		593	switch (crev) {
		594	case 1:
		595	args.v1.ucMisc = 0;
		596	args.v1.ucAction = action;
		597	if (hdmi_detected)
		598	args.v1.ucMisc \|= PANEL_ENCODER_MISC_HDMI_TYPE;
		599	args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		600	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		601	if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
		602	args.v1.ucMisc \|= PANEL_ENCODER_MISC_DUAL;
		603	if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
		604	args.v1.ucMisc \|= ATOM_PANEL_MISC_888RGB;
		605	} else {
		606	if (dig->linkb)
		607	args.v1.ucMisc \|= PANEL_ENCODER_MISC_TMDS_LINKB;
		608	if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		609	args.v1.ucMisc \|= PANEL_ENCODER_MISC_DUAL;
		610	/if (pScrn->rgbBits == 8) /
		611	args.v1.ucMisc \|= ATOM_PANEL_MISC_888RGB;
		612	}
		613	break;
		614	case 2:
		615	case 3:
		616	args.v2.ucMisc = 0;
		617	args.v2.ucAction = action;
		618	if (crev == 3) {
		619	if (dig->coherent_mode)
		620	args.v2.ucMisc \|= PANEL_ENCODER_MISC_COHERENT;
		621	}
		622	if (hdmi_detected)
		623	args.v2.ucMisc \|= PANEL_ENCODER_MISC_HDMI_TYPE;
		624	args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		625	args.v2.ucTruncate = 0;
		626	args.v2.ucSpatial = 0;
		627	args.v2.ucTemporal = 0;
		628	args.v2.ucFRC = 0;
		629	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		630	if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
		631	args.v2.ucMisc \|= PANEL_ENCODER_MISC_DUAL;
		632	if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
		633	args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
		634	if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
		635	args.v2.ucSpatial \|= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
		636	}
		637	if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
		638	args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
		639	if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
		640	args.v2.ucTemporal \|= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
		641	if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
		642	args.v2.ucTemporal \|= PANEL_ENCODER_TEMPORAL_LEVEL_4;
		643	}
		644	} else {
		645	if (dig->linkb)
		646	args.v2.ucMisc \|= PANEL_ENCODER_MISC_TMDS_LINKB;
		647	if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		648	args.v2.ucMisc \|= PANEL_ENCODER_MISC_DUAL;
		649	}
		650	break;
		651	default:
		652	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		653	break;
		654	}
		655	break;
		656	default:
		657	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		658	break;
		659	}
		660
		661	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		662	}
		663
		664	int
		665	atombios_get_encoder_mode(struct drm_encoder *encoder)
		666	{
		667	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		668	struct drm_connector *connector;
		669	struct radeon_connector *radeon_connector;
		670	struct radeon_connector_atom_dig *dig_connector;
		671
		672	/* dp bridges are always DP */
		673	if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
		674	return ATOM_ENCODER_MODE_DP;
		675
		676	/* DVO is always DVO */
		677	if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) \|\|
		678	(radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
		679	return ATOM_ENCODER_MODE_DVO;
		680
		681	connector = radeon_get_connector_for_encoder(encoder);
		682	/* if we don't have an active device yet, just use one of
		683	* the connectors tied to the encoder.
		684	*/
		685	if (!connector)
		686	connector = radeon_get_connector_for_encoder_init(encoder);
		687	radeon_connector = to_radeon_connector(connector);
		688
		689	switch (connector->connector_type) {
		690	case DRM_MODE_CONNECTOR_DVII:
		691	case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
5078	serge	692	if (radeon_audio != 0) {
		693	if (radeon_connector->use_digital &&
		694	(radeon_connector->audio == RADEON_AUDIO_ENABLE))
		695	return ATOM_ENCODER_MODE_HDMI;
		696	else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
		697	(radeon_connector->audio == RADEON_AUDIO_AUTO))
2997	Serge	698	return ATOM_ENCODER_MODE_HDMI;
		699	else if (radeon_connector->use_digital)
		700	return ATOM_ENCODER_MODE_DVI;
		701	else
		702	return ATOM_ENCODER_MODE_CRT;
5078	serge	703	} else if (radeon_connector->use_digital) {
		704	return ATOM_ENCODER_MODE_DVI;
		705	} else {
		706	return ATOM_ENCODER_MODE_CRT;
		707	}
2997	Serge	708	break;
		709	case DRM_MODE_CONNECTOR_DVID:
		710	case DRM_MODE_CONNECTOR_HDMIA:
		711	default:
5078	serge	712	if (radeon_audio != 0) {
		713	if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
		714	return ATOM_ENCODER_MODE_HDMI;
		715	else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
		716	(radeon_connector->audio == RADEON_AUDIO_AUTO))
2997	Serge	717	return ATOM_ENCODER_MODE_HDMI;
		718	else
		719	return ATOM_ENCODER_MODE_DVI;
5078	serge	720	} else {
		721	return ATOM_ENCODER_MODE_DVI;
		722	}
2997	Serge	723	break;
		724	case DRM_MODE_CONNECTOR_LVDS:
		725	return ATOM_ENCODER_MODE_LVDS;
		726	break;
		727	case DRM_MODE_CONNECTOR_DisplayPort:
		728	dig_connector = radeon_connector->con_priv;
		729	if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) \|\|
5078	serge	730	(dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
2997	Serge	731	return ATOM_ENCODER_MODE_DP;
5078	serge	732	} else if (radeon_audio != 0) {
		733	if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
		734	return ATOM_ENCODER_MODE_HDMI;
		735	else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
		736	(radeon_connector->audio == RADEON_AUDIO_AUTO))
2997	Serge	737	return ATOM_ENCODER_MODE_HDMI;
		738	else
		739	return ATOM_ENCODER_MODE_DVI;
5078	serge	740	} else {
		741	return ATOM_ENCODER_MODE_DVI;
		742	}
2997	Serge	743	break;
		744	case DRM_MODE_CONNECTOR_eDP:
		745	return ATOM_ENCODER_MODE_DP;
		746	case DRM_MODE_CONNECTOR_DVIA:
		747	case DRM_MODE_CONNECTOR_VGA:
		748	return ATOM_ENCODER_MODE_CRT;
		749	break;
		750	case DRM_MODE_CONNECTOR_Composite:
		751	case DRM_MODE_CONNECTOR_SVIDEO:
		752	case DRM_MODE_CONNECTOR_9PinDIN:
		753	/* fix me */
		754	return ATOM_ENCODER_MODE_TV;
		755	/return ATOM_ENCODER_MODE_CV;/
		756	break;
		757	}
		758	}
		759
		760	/*
		761	* DIG Encoder/Transmitter Setup
		762	*
		763	* DCE 3.0/3.1
		764	* - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
		765	* Supports up to 3 digital outputs
		766	* - 2 DIG encoder blocks.
		767	* DIG1 can drive UNIPHY link A or link B
		768	* DIG2 can drive UNIPHY link B or LVTMA
		769	*
		770	* DCE 3.2
		771	* - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
		772	* Supports up to 5 digital outputs
		773	* - 2 DIG encoder blocks.
		774	* DIG1/2 can drive UNIPHY0/1/2 link A or link B
		775	*
		776	* DCE 4.0/5.0/6.0
		777	* - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
		778	* Supports up to 6 digital outputs
		779	* - 6 DIG encoder blocks.
		780	* - DIG to PHY mapping is hardcoded
		781	* DIG1 drives UNIPHY0 link A, A+B
		782	* DIG2 drives UNIPHY0 link B
		783	* DIG3 drives UNIPHY1 link A, A+B
		784	* DIG4 drives UNIPHY1 link B
		785	* DIG5 drives UNIPHY2 link A, A+B
		786	* DIG6 drives UNIPHY2 link B
		787	*
		788	* DCE 4.1
		789	* - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
		790	* Supports up to 6 digital outputs
		791	* - 2 DIG encoder blocks.
		792	* llano
		793	* DIG1/2 can drive UNIPHY0/1/2 link A or link B
		794	* ontario
		795	* DIG1 drives UNIPHY0/1/2 link A
		796	* DIG2 drives UNIPHY0/1/2 link B
		797	*
		798	* Routing
		799	* crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
		800	* Examples:
		801	* crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
		802	* crtc1 -> dig1 -> UNIPHY0 link B -> DP
		803	* crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
		804	* crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
		805	*/
		806
		807	union dig_encoder_control {
		808	DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
		809	DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
		810	DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
		811	DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
		812	};
		813
		814	void
		815	atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
		816	{
		817	struct drm_device *dev = encoder->dev;
		818	struct radeon_device *rdev = dev->dev_private;
		819	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		820	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
		821	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
		822	union dig_encoder_control args;
		823	int index = 0;
		824	uint8_t frev, crev;
		825	int dp_clock = 0;
		826	int dp_lane_count = 0;
		827	int hpd_id = RADEON_HPD_NONE;
		828
		829	if (connector) {
		830	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		831	struct radeon_connector_atom_dig *dig_connector =
		832	radeon_connector->con_priv;
		833
		834	dp_clock = dig_connector->dp_clock;
		835	dp_lane_count = dig_connector->dp_lane_count;
		836	hpd_id = radeon_connector->hpd.hpd;
		837	}
		838
		839	/* no dig encoder assigned */
		840	if (dig->dig_encoder == -1)
		841	return;
		842
		843	memset(&args, 0, sizeof(args));
		844
		845	if (ASIC_IS_DCE4(rdev))
		846	index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
		847	else {
		848	if (dig->dig_encoder)
		849	index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
		850	else
		851	index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
		852	}
		853
		854	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
		855	return;
		856
		857	switch (frev) {
		858	case 1:
		859	switch (crev) {
		860	case 1:
		861	args.v1.ucAction = action;
		862	args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		863	if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
		864	args.v3.ucPanelMode = panel_mode;
		865	else
		866	args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
		867
		868	if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
		869	args.v1.ucLaneNum = dp_lane_count;
		870	else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		871	args.v1.ucLaneNum = 8;
		872	else
		873	args.v1.ucLaneNum = 4;
		874
		875	if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
		876	args.v1.ucConfig \|= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
		877	switch (radeon_encoder->encoder_id) {
		878	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		879	args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
		880	break;
		881	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		882	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		883	args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
		884	break;
		885	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		886	args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
		887	break;
		888	}
		889	if (dig->linkb)
		890	args.v1.ucConfig \|= ATOM_ENCODER_CONFIG_LINKB;
		891	else
		892	args.v1.ucConfig \|= ATOM_ENCODER_CONFIG_LINKA;
		893	break;
		894	case 2:
		895	case 3:
		896	args.v3.ucAction = action;
		897	args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		898	if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
		899	args.v3.ucPanelMode = panel_mode;
		900	else
		901	args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
		902
		903	if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
		904	args.v3.ucLaneNum = dp_lane_count;
		905	else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		906	args.v3.ucLaneNum = 8;
		907	else
		908	args.v3.ucLaneNum = 4;
		909
		910	if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
		911	args.v1.ucConfig \|= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
		912	args.v3.acConfig.ucDigSel = dig->dig_encoder;
		913	args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
		914	break;
		915	case 4:
		916	args.v4.ucAction = action;
		917	args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		918	if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
		919	args.v4.ucPanelMode = panel_mode;
		920	else
		921	args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
		922
		923	if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
		924	args.v4.ucLaneNum = dp_lane_count;
		925	else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		926	args.v4.ucLaneNum = 8;
		927	else
		928	args.v4.ucLaneNum = 4;
		929
		930	if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
5078	serge	931	if (dp_clock == 540000)
		932	args.v1.ucConfig \|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
		933	else if (dp_clock == 324000)
		934	args.v1.ucConfig \|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
		935	else if (dp_clock == 270000)
2997	Serge	936	args.v1.ucConfig \|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
5078	serge	937	else
		938	args.v1.ucConfig \|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
2997	Serge	939	}
		940	args.v4.acConfig.ucDigSel = dig->dig_encoder;
		941	args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
		942	if (hpd_id == RADEON_HPD_NONE)
		943	args.v4.ucHPD_ID = 0;
		944	else
		945	args.v4.ucHPD_ID = hpd_id + 1;
		946	break;
		947	default:
		948	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		949	break;
		950	}
		951	break;
		952	default:
		953	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		954	break;
		955	}
		956
		957	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		958
		959	}
		960
		961	union dig_transmitter_control {
		962	DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
		963	DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
		964	DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
		965	DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
		966	DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
		967	};
		968
		969	void
		970	atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
		971	{
		972	struct drm_device *dev = encoder->dev;
		973	struct radeon_device *rdev = dev->dev_private;
		974	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		975	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
		976	struct drm_connector *connector;
		977	union dig_transmitter_control args;
		978	int index = 0;
		979	uint8_t frev, crev;
		980	bool is_dp = false;
		981	int pll_id = 0;
		982	int dp_clock = 0;
		983	int dp_lane_count = 0;
		984	int connector_object_id = 0;
		985	int igp_lane_info = 0;
		986	int dig_encoder = dig->dig_encoder;
		987	int hpd_id = RADEON_HPD_NONE;
		988
		989	if (action == ATOM_TRANSMITTER_ACTION_INIT) {
		990	connector = radeon_get_connector_for_encoder_init(encoder);
		991	/* just needed to avoid bailing in the encoder check. the encoder
		992	* isn't used for init
		993	*/
		994	dig_encoder = 0;
		995	} else
		996	connector = radeon_get_connector_for_encoder(encoder);
		997
		998	if (connector) {
		999	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		1000	struct radeon_connector_atom_dig *dig_connector =
		1001	radeon_connector->con_priv;
		1002
		1003	hpd_id = radeon_connector->hpd.hpd;
		1004	dp_clock = dig_connector->dp_clock;
		1005	dp_lane_count = dig_connector->dp_lane_count;
		1006	connector_object_id =
		1007	(radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
		1008	igp_lane_info = dig_connector->igp_lane_info;
		1009	}
		1010
		1011	if (encoder->crtc) {
		1012	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		1013	pll_id = radeon_crtc->pll_id;
		1014	}
		1015
		1016	/* no dig encoder assigned */
		1017	if (dig_encoder == -1)
		1018	return;
		1019
		1020	if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
		1021	is_dp = true;
		1022
		1023	memset(&args, 0, sizeof(args));
		1024
		1025	switch (radeon_encoder->encoder_id) {
		1026	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		1027	index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
		1028	break;
		1029	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		1030	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		1031	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
5078	serge	1032	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2997	Serge	1033	index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
		1034	break;
		1035	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		1036	index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
		1037	break;
		1038	}
		1039
		1040	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
		1041	return;
		1042
		1043	switch (frev) {
		1044	case 1:
		1045	switch (crev) {
		1046	case 1:
		1047	args.v1.ucAction = action;
		1048	if (action == ATOM_TRANSMITTER_ACTION_INIT) {
		1049	args.v1.usInitInfo = cpu_to_le16(connector_object_id);
		1050	} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
		1051	args.v1.asMode.ucLaneSel = lane_num;
		1052	args.v1.asMode.ucLaneSet = lane_set;
		1053	} else {
		1054	if (is_dp)
		1055	args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
		1056	else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		1057	args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
		1058	else
		1059	args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		1060	}
		1061
		1062	args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
		1063
		1064	if (dig_encoder)
		1065	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
		1066	else
		1067	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
		1068
		1069	if ((rdev->flags & RADEON_IS_IGP) &&
		1070	(radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
		1071	if (is_dp \|\|
		1072	!radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
		1073	if (igp_lane_info & 0x1)
		1074	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
		1075	else if (igp_lane_info & 0x2)
		1076	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
		1077	else if (igp_lane_info & 0x4)
		1078	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
		1079	else if (igp_lane_info & 0x8)
		1080	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
		1081	} else {
		1082	if (igp_lane_info & 0x3)
		1083	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
		1084	else if (igp_lane_info & 0xc)
		1085	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
		1086	}
		1087	}
		1088
		1089	if (dig->linkb)
		1090	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LINKB;
		1091	else
		1092	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LINKA;
		1093
		1094	if (is_dp)
		1095	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_COHERENT;
		1096	else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
		1097	if (dig->coherent_mode)
		1098	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_COHERENT;
		1099	if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		1100	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
		1101	}
		1102	break;
		1103	case 2:
		1104	args.v2.ucAction = action;
		1105	if (action == ATOM_TRANSMITTER_ACTION_INIT) {
		1106	args.v2.usInitInfo = cpu_to_le16(connector_object_id);
		1107	} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
		1108	args.v2.asMode.ucLaneSel = lane_num;
		1109	args.v2.asMode.ucLaneSet = lane_set;
		1110	} else {
		1111	if (is_dp)
		1112	args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
		1113	else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		1114	args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
		1115	else
		1116	args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		1117	}
		1118
		1119	args.v2.acConfig.ucEncoderSel = dig_encoder;
		1120	if (dig->linkb)
		1121	args.v2.acConfig.ucLinkSel = 1;
		1122
		1123	switch (radeon_encoder->encoder_id) {
		1124	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		1125	args.v2.acConfig.ucTransmitterSel = 0;
		1126	break;
		1127	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		1128	args.v2.acConfig.ucTransmitterSel = 1;
		1129	break;
		1130	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		1131	args.v2.acConfig.ucTransmitterSel = 2;
		1132	break;
		1133	}
		1134
		1135	if (is_dp) {
		1136	args.v2.acConfig.fCoherentMode = 1;
		1137	args.v2.acConfig.fDPConnector = 1;
		1138	} else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
		1139	if (dig->coherent_mode)
		1140	args.v2.acConfig.fCoherentMode = 1;
		1141	if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		1142	args.v2.acConfig.fDualLinkConnector = 1;
		1143	}
		1144	break;
		1145	case 3:
		1146	args.v3.ucAction = action;
		1147	if (action == ATOM_TRANSMITTER_ACTION_INIT) {
		1148	args.v3.usInitInfo = cpu_to_le16(connector_object_id);
		1149	} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
		1150	args.v3.asMode.ucLaneSel = lane_num;
		1151	args.v3.asMode.ucLaneSet = lane_set;
		1152	} else {
		1153	if (is_dp)
		1154	args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
		1155	else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		1156	args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
		1157	else
		1158	args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		1159	}
		1160
		1161	if (is_dp)
		1162	args.v3.ucLaneNum = dp_lane_count;
		1163	else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		1164	args.v3.ucLaneNum = 8;
		1165	else
		1166	args.v3.ucLaneNum = 4;
		1167
		1168	if (dig->linkb)
		1169	args.v3.acConfig.ucLinkSel = 1;
		1170	if (dig_encoder & 1)
		1171	args.v3.acConfig.ucEncoderSel = 1;
		1172
		1173	/* Select the PLL for the PHY
		1174	* DP PHY should be clocked from external src if there is
		1175	* one.
		1176	*/
		1177	/* On DCE4, if there is an external clock, it generates the DP ref clock */
		1178	if (is_dp && rdev->clock.dp_extclk)
		1179	args.v3.acConfig.ucRefClkSource = 2; /* external src */
		1180	else
		1181	args.v3.acConfig.ucRefClkSource = pll_id;
		1182
		1183	switch (radeon_encoder->encoder_id) {
		1184	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		1185	args.v3.acConfig.ucTransmitterSel = 0;
		1186	break;
		1187	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		1188	args.v3.acConfig.ucTransmitterSel = 1;
		1189	break;
		1190	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		1191	args.v3.acConfig.ucTransmitterSel = 2;
		1192	break;
		1193	}
		1194
		1195	if (is_dp)
		1196	args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
		1197	else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
		1198	if (dig->coherent_mode)
		1199	args.v3.acConfig.fCoherentMode = 1;
		1200	if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		1201	args.v3.acConfig.fDualLinkConnector = 1;
		1202	}
		1203	break;
		1204	case 4:
		1205	args.v4.ucAction = action;
		1206	if (action == ATOM_TRANSMITTER_ACTION_INIT) {
		1207	args.v4.usInitInfo = cpu_to_le16(connector_object_id);
		1208	} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
		1209	args.v4.asMode.ucLaneSel = lane_num;
		1210	args.v4.asMode.ucLaneSet = lane_set;
		1211	} else {
		1212	if (is_dp)
		1213	args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
		1214	else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		1215	args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
		1216	else
		1217	args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		1218	}
		1219
		1220	if (is_dp)
		1221	args.v4.ucLaneNum = dp_lane_count;
		1222	else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		1223	args.v4.ucLaneNum = 8;
		1224	else
		1225	args.v4.ucLaneNum = 4;
		1226
		1227	if (dig->linkb)
		1228	args.v4.acConfig.ucLinkSel = 1;
		1229	if (dig_encoder & 1)
		1230	args.v4.acConfig.ucEncoderSel = 1;
		1231
		1232	/* Select the PLL for the PHY
		1233	* DP PHY should be clocked from external src if there is
		1234	* one.
		1235	*/
		1236	/* On DCE5 DCPLL usually generates the DP ref clock */
		1237	if (is_dp) {
		1238	if (rdev->clock.dp_extclk)
		1239	args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
		1240	else
		1241	args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
		1242	} else
		1243	args.v4.acConfig.ucRefClkSource = pll_id;
		1244
		1245	switch (radeon_encoder->encoder_id) {
		1246	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		1247	args.v4.acConfig.ucTransmitterSel = 0;
		1248	break;
		1249	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		1250	args.v4.acConfig.ucTransmitterSel = 1;
		1251	break;
		1252	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		1253	args.v4.acConfig.ucTransmitterSel = 2;
		1254	break;
		1255	}
		1256
		1257	if (is_dp)
		1258	args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
		1259	else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
		1260	if (dig->coherent_mode)
		1261	args.v4.acConfig.fCoherentMode = 1;
		1262	if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		1263	args.v4.acConfig.fDualLinkConnector = 1;
		1264	}
		1265	break;
		1266	case 5:
		1267	args.v5.ucAction = action;
		1268	if (is_dp)
		1269	args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
		1270	else
		1271	args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		1272
		1273	switch (radeon_encoder->encoder_id) {
		1274	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		1275	if (dig->linkb)
		1276	args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
		1277	else
		1278	args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
		1279	break;
		1280	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		1281	if (dig->linkb)
		1282	args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
		1283	else
		1284	args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
		1285	break;
		1286	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		1287	if (dig->linkb)
		1288	args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
		1289	else
		1290	args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
		1291	break;
5078	serge	1292	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
		1293	args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
		1294	break;
2997	Serge	1295	}
		1296	if (is_dp)
		1297	args.v5.ucLaneNum = dp_lane_count;
5078	serge	1298	else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
2997	Serge	1299	args.v5.ucLaneNum = 8;
		1300	else
		1301	args.v5.ucLaneNum = 4;
		1302	args.v5.ucConnObjId = connector_object_id;
		1303	args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
		1304
		1305	if (is_dp && rdev->clock.dp_extclk)
		1306	args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
		1307	else
		1308	args.v5.asConfig.ucPhyClkSrcId = pll_id;
		1309
		1310	if (is_dp)
		1311	args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
		1312	else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
		1313	if (dig->coherent_mode)
		1314	args.v5.asConfig.ucCoherentMode = 1;
		1315	}
		1316	if (hpd_id == RADEON_HPD_NONE)
		1317	args.v5.asConfig.ucHPDSel = 0;
		1318	else
		1319	args.v5.asConfig.ucHPDSel = hpd_id + 1;
		1320	args.v5.ucDigEncoderSel = 1 << dig_encoder;
		1321	args.v5.ucDPLaneSet = lane_set;
		1322	break;
		1323	default:
		1324	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		1325	break;
		1326	}
		1327	break;
		1328	default:
		1329	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		1330	break;
		1331	}
		1332
		1333	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1334	}
		1335
		1336	bool
		1337	atombios_set_edp_panel_power(struct drm_connector *connector, int action)
		1338	{
		1339	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		1340	struct drm_device *dev = radeon_connector->base.dev;
		1341	struct radeon_device *rdev = dev->dev_private;
		1342	union dig_transmitter_control args;
		1343	int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
		1344	uint8_t frev, crev;
		1345
		1346	if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
		1347	goto done;
		1348
		1349	if (!ASIC_IS_DCE4(rdev))
		1350	goto done;
		1351
		1352	if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
		1353	(action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
		1354	goto done;
		1355
		1356	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
		1357	goto done;
		1358
		1359	memset(&args, 0, sizeof(args));
		1360
		1361	args.v1.ucAction = action;
		1362
		1363	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1364
		1365	/* wait for the panel to power up */
		1366	if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
		1367	int i;
		1368
		1369	for (i = 0; i < 300; i++) {
		1370	if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
		1371	return true;
		1372	mdelay(1);
		1373	}
		1374	return false;
		1375	}
		1376	done:
		1377	return true;
		1378	}
		1379
		1380	union external_encoder_control {
		1381	EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
		1382	EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
		1383	};
		1384
		1385	static void
		1386	atombios_external_encoder_setup(struct drm_encoder *encoder,
		1387	struct drm_encoder *ext_encoder,
		1388	int action)
		1389	{
		1390	struct drm_device *dev = encoder->dev;
		1391	struct radeon_device *rdev = dev->dev_private;
		1392	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1393	struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
		1394	union external_encoder_control args;
		1395	struct drm_connector *connector;
		1396	int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
		1397	u8 frev, crev;
		1398	int dp_clock = 0;
		1399	int dp_lane_count = 0;
		1400	int connector_object_id = 0;
		1401	u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
		1402
		1403	if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
		1404	connector = radeon_get_connector_for_encoder_init(encoder);
		1405	else
		1406	connector = radeon_get_connector_for_encoder(encoder);
		1407
		1408	if (connector) {
		1409	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		1410	struct radeon_connector_atom_dig *dig_connector =
		1411	radeon_connector->con_priv;
		1412
		1413	dp_clock = dig_connector->dp_clock;
		1414	dp_lane_count = dig_connector->dp_lane_count;
		1415	connector_object_id =
		1416	(radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
		1417	}
		1418
		1419	memset(&args, 0, sizeof(args));
		1420
		1421	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
		1422	return;
		1423
		1424	switch (frev) {
		1425	case 1:
		1426	/* no params on frev 1 */
		1427	break;
		1428	case 2:
		1429	switch (crev) {
		1430	case 1:
		1431	case 2:
		1432	args.v1.sDigEncoder.ucAction = action;
		1433	args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		1434	args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
		1435
		1436	if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
		1437	if (dp_clock == 270000)
		1438	args.v1.sDigEncoder.ucConfig \|= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
		1439	args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
		1440	} else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		1441	args.v1.sDigEncoder.ucLaneNum = 8;
		1442	else
		1443	args.v1.sDigEncoder.ucLaneNum = 4;
		1444	break;
		1445	case 3:
		1446	args.v3.sExtEncoder.ucAction = action;
		1447	if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
		1448	args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
		1449	else
		1450	args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		1451	args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
		1452
		1453	if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
		1454	if (dp_clock == 270000)
		1455	args.v3.sExtEncoder.ucConfig \|= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
		1456	else if (dp_clock == 540000)
		1457	args.v3.sExtEncoder.ucConfig \|= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
		1458	args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
		1459	} else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		1460	args.v3.sExtEncoder.ucLaneNum = 8;
		1461	else
		1462	args.v3.sExtEncoder.ucLaneNum = 4;
		1463	switch (ext_enum) {
		1464	case GRAPH_OBJECT_ENUM_ID1:
		1465	args.v3.sExtEncoder.ucConfig \|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
		1466	break;
		1467	case GRAPH_OBJECT_ENUM_ID2:
		1468	args.v3.sExtEncoder.ucConfig \|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
		1469	break;
		1470	case GRAPH_OBJECT_ENUM_ID3:
		1471	args.v3.sExtEncoder.ucConfig \|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
		1472	break;
		1473	}
		1474	args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
		1475	break;
		1476	default:
		1477	DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
		1478	return;
		1479	}
		1480	break;
		1481	default:
		1482	DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
		1483	return;
		1484	}
		1485	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1486	}
		1487
		1488	static void
		1489	atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
		1490	{
		1491	struct drm_device *dev = encoder->dev;
		1492	struct radeon_device *rdev = dev->dev_private;
		1493	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1494	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		1495	ENABLE_YUV_PS_ALLOCATION args;
		1496	int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
		1497	uint32_t temp, reg;
		1498
		1499	memset(&args, 0, sizeof(args));
		1500
		1501	if (rdev->family >= CHIP_R600)
		1502	reg = R600_BIOS_3_SCRATCH;
		1503	else
		1504	reg = RADEON_BIOS_3_SCRATCH;
		1505
		1506	/* XXX: fix up scratch reg handling */
		1507	temp = RREG32(reg);
		1508	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
		1509	WREG32(reg, (ATOM_S3_TV1_ACTIVE \|
		1510	(radeon_crtc->crtc_id << 18)));
		1511	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
		1512	WREG32(reg, (ATOM_S3_CV_ACTIVE \| (radeon_crtc->crtc_id << 24)));
		1513	else
		1514	WREG32(reg, 0);
		1515
		1516	if (enable)
		1517	args.ucEnable = ATOM_ENABLE;
		1518	args.ucCRTC = radeon_crtc->crtc_id;
		1519
		1520	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1521
		1522	WREG32(reg, temp);
		1523	}
		1524
		1525	static void
		1526	radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
		1527	{
		1528	struct drm_device *dev = encoder->dev;
		1529	struct radeon_device *rdev = dev->dev_private;
		1530	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1531	DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
		1532	int index = 0;
		1533
		1534	memset(&args, 0, sizeof(args));
		1535
		1536	switch (radeon_encoder->encoder_id) {
		1537	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		1538	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		1539	index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
		1540	break;
		1541	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
		1542	case ENCODER_OBJECT_ID_INTERNAL_DDI:
		1543	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		1544	index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
		1545	break;
		1546	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		1547	index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
		1548	break;
		1549	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		1550	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
		1551	index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
		1552	else
		1553	index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
		1554	break;
		1555	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		1556	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
		1557	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
		1558	index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
		1559	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
		1560	index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
		1561	else
		1562	index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
		1563	break;
		1564	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		1565	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
		1566	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
		1567	index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
		1568	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
		1569	index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
		1570	else
		1571	index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
		1572	break;
		1573	default:
		1574	return;
		1575	}
		1576
		1577	switch (mode) {
		1578	case DRM_MODE_DPMS_ON:
		1579	args.ucAction = ATOM_ENABLE;
		1580	/* workaround for DVOOutputControl on some RS690 systems */
		1581	if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
		1582	u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
		1583	WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
		1584	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1585	WREG32(RADEON_BIOS_3_SCRATCH, reg);
		1586	} else
		1587	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1588	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		1589	args.ucAction = ATOM_LCD_BLON;
		1590	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1591	}
		1592	break;
		1593	case DRM_MODE_DPMS_STANDBY:
		1594	case DRM_MODE_DPMS_SUSPEND:
		1595	case DRM_MODE_DPMS_OFF:
		1596	args.ucAction = ATOM_DISABLE;
		1597	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1598	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		1599	args.ucAction = ATOM_LCD_BLOFF;
		1600	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1601	}
		1602	break;
		1603	}
		1604	}
		1605
		1606	static void
		1607	radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
		1608	{
		1609	struct drm_device *dev = encoder->dev;
		1610	struct radeon_device *rdev = dev->dev_private;
		1611	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1612	struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
		1613	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
		1614	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
		1615	struct radeon_connector *radeon_connector = NULL;
		1616	struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
5078	serge	1617	bool travis_quirk = false;
2997	Serge	1618
		1619	if (connector) {
		1620	radeon_connector = to_radeon_connector(connector);
		1621	radeon_dig_connector = radeon_connector->con_priv;
5078	serge	1622	if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
		1623	ENCODER_OBJECT_ID_TRAVIS) &&
		1624	(radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
		1625	!ASIC_IS_DCE5(rdev))
		1626	travis_quirk = true;
2997	Serge	1627	}
		1628
		1629	switch (mode) {
		1630	case DRM_MODE_DPMS_ON:
		1631	if (ASIC_IS_DCE41(rdev) \|\| ASIC_IS_DCE5(rdev)) {
		1632	if (!connector)
		1633	dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
		1634	else
		1635	dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
		1636
		1637	/* setup and enable the encoder */
		1638	atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
		1639	atombios_dig_encoder_setup(encoder,
		1640	ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
		1641	dig->panel_mode);
		1642	if (ext_encoder) {
		1643	if (ASIC_IS_DCE41(rdev) \|\| ASIC_IS_DCE61(rdev))
		1644	atombios_external_encoder_setup(encoder, ext_encoder,
		1645	EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
		1646	}
		1647	} else if (ASIC_IS_DCE4(rdev)) {
		1648	/* setup and enable the encoder */
		1649	atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
		1650	} else {
		1651	/* setup and enable the encoder and transmitter */
		1652	atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
		1653	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
		1654	}
		1655	if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
		1656	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
		1657	atombios_set_edp_panel_power(connector,
		1658	ATOM_TRANSMITTER_ACTION_POWER_ON);
		1659	radeon_dig_connector->edp_on = true;
		1660	}
5078	serge	1661	}
		1662	/* enable the transmitter */
		1663	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
		1664	if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
		1665	/* DP_SET_POWER_D0 is set in radeon_dp_link_train */
2997	Serge	1666	radeon_dp_link_train(encoder, connector);
		1667	if (ASIC_IS_DCE4(rdev))
		1668	atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
		1669	}
		1670	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
5078	serge	1671	atombios_dig_transmitter_setup(encoder,
		1672	ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
		1673	if (ext_encoder)
		1674	atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
2997	Serge	1675	break;
		1676	case DRM_MODE_DPMS_STANDBY:
		1677	case DRM_MODE_DPMS_SUSPEND:
		1678	case DRM_MODE_DPMS_OFF:
5078	serge	1679	if (ASIC_IS_DCE4(rdev)) {
		1680	if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
		1681	atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
		1682	}
		1683	if (ext_encoder)
		1684	atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
		1685	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
		1686	atombios_dig_transmitter_setup(encoder,
		1687	ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
		1688
		1689	if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
		1690	connector && !travis_quirk)
		1691	radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
		1692	if (ASIC_IS_DCE4(rdev)) {
2997	Serge	1693	/* disable the transmitter */
5078	serge	1694	atombios_dig_transmitter_setup(encoder,
		1695	ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2997	Serge	1696	} else {
		1697	/* disable the encoder and transmitter */
5078	serge	1698	atombios_dig_transmitter_setup(encoder,
		1699	ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2997	Serge	1700	atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
		1701	}
		1702	if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
5078	serge	1703	if (travis_quirk)
		1704	radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
2997	Serge	1705	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
		1706	atombios_set_edp_panel_power(connector,
		1707	ATOM_TRANSMITTER_ACTION_POWER_OFF);
		1708	radeon_dig_connector->edp_on = false;
		1709	}
		1710	}
		1711	break;
		1712	}
		1713	}
		1714
		1715	static void
		1716	radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
		1717	{
		1718	struct drm_device *dev = encoder->dev;
		1719	struct radeon_device *rdev = dev->dev_private;
		1720	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1721
		1722	DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
		1723	radeon_encoder->encoder_id, mode, radeon_encoder->devices,
		1724	radeon_encoder->active_device);
		1725	switch (radeon_encoder->encoder_id) {
		1726	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		1727	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		1728	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		1729	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		1730	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
		1731	case ENCODER_OBJECT_ID_INTERNAL_DDI:
		1732	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		1733	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
		1734	radeon_atom_encoder_dpms_avivo(encoder, mode);
		1735	break;
		1736	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		1737	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		1738	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
5078	serge	1739	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2997	Serge	1740	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		1741	radeon_atom_encoder_dpms_dig(encoder, mode);
		1742	break;
		1743	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		1744	if (ASIC_IS_DCE5(rdev)) {
		1745	switch (mode) {
		1746	case DRM_MODE_DPMS_ON:
		1747	atombios_dvo_setup(encoder, ATOM_ENABLE);
		1748	break;
		1749	case DRM_MODE_DPMS_STANDBY:
		1750	case DRM_MODE_DPMS_SUSPEND:
		1751	case DRM_MODE_DPMS_OFF:
		1752	atombios_dvo_setup(encoder, ATOM_DISABLE);
		1753	break;
		1754	}
		1755	} else if (ASIC_IS_DCE3(rdev))
		1756	radeon_atom_encoder_dpms_dig(encoder, mode);
		1757	else
		1758	radeon_atom_encoder_dpms_avivo(encoder, mode);
		1759	break;
		1760	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		1761	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
		1762	if (ASIC_IS_DCE5(rdev)) {
		1763	switch (mode) {
		1764	case DRM_MODE_DPMS_ON:
		1765	atombios_dac_setup(encoder, ATOM_ENABLE);
		1766	break;
		1767	case DRM_MODE_DPMS_STANDBY:
		1768	case DRM_MODE_DPMS_SUSPEND:
		1769	case DRM_MODE_DPMS_OFF:
		1770	atombios_dac_setup(encoder, ATOM_DISABLE);
		1771	break;
		1772	}
		1773	} else
		1774	radeon_atom_encoder_dpms_avivo(encoder, mode);
		1775	break;
		1776	default:
		1777	return;
		1778	}
		1779
		1780	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		1781
		1782	}
		1783
		1784	union crtc_source_param {
		1785	SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
		1786	SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
		1787	};
		1788
		1789	static void
		1790	atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
		1791	{
		1792	struct drm_device *dev = encoder->dev;
		1793	struct radeon_device *rdev = dev->dev_private;
		1794	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1795	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		1796	union crtc_source_param args;
		1797	int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
		1798	uint8_t frev, crev;
		1799	struct radeon_encoder_atom_dig *dig;
		1800
		1801	memset(&args, 0, sizeof(args));
		1802
		1803	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
		1804	return;
		1805
		1806	switch (frev) {
		1807	case 1:
		1808	switch (crev) {
		1809	case 1:
		1810	default:
		1811	if (ASIC_IS_AVIVO(rdev))
		1812	args.v1.ucCRTC = radeon_crtc->crtc_id;
		1813	else {
		1814	if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
		1815	args.v1.ucCRTC = radeon_crtc->crtc_id;
		1816	} else {
		1817	args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
		1818	}
		1819	}
		1820	switch (radeon_encoder->encoder_id) {
		1821	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		1822	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		1823	args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
		1824	break;
		1825	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		1826	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		1827	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
		1828	args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
		1829	else
		1830	args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
		1831	break;
		1832	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
		1833	case ENCODER_OBJECT_ID_INTERNAL_DDI:
		1834	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		1835	args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
		1836	break;
		1837	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		1838	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
		1839	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
		1840	args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
		1841	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
		1842	args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
		1843	else
		1844	args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
		1845	break;
		1846	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		1847	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
		1848	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
		1849	args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
		1850	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
		1851	args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
		1852	else
		1853	args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
		1854	break;
		1855	}
		1856	break;
		1857	case 2:
		1858	args.v2.ucCRTC = radeon_crtc->crtc_id;
		1859	if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
		1860	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
		1861
		1862	if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
		1863	args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
		1864	else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
		1865	args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
		1866	else
		1867	args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
5078	serge	1868	} else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		1869	args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
		1870	} else {
2997	Serge	1871	args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
5078	serge	1872	}
2997	Serge	1873	switch (radeon_encoder->encoder_id) {
		1874	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		1875	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		1876	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
5078	serge	1877	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2997	Serge	1878	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		1879	dig = radeon_encoder->enc_priv;
		1880	switch (dig->dig_encoder) {
		1881	case 0:
		1882	args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
		1883	break;
		1884	case 1:
		1885	args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
		1886	break;
		1887	case 2:
		1888	args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
		1889	break;
		1890	case 3:
		1891	args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
		1892	break;
		1893	case 4:
		1894	args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
		1895	break;
		1896	case 5:
		1897	args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
		1898	break;
5078	serge	1899	case 6:
		1900	args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
		1901	break;
2997	Serge	1902	}
		1903	break;
		1904	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		1905	args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
		1906	break;
		1907	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
		1908	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
		1909	args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
		1910	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
		1911	args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
		1912	else
		1913	args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
		1914	break;
		1915	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
		1916	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
		1917	args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
		1918	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
		1919	args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
		1920	else
		1921	args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
		1922	break;
		1923	}
		1924	break;
		1925	}
		1926	break;
		1927	default:
		1928	DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
		1929	return;
		1930	}
		1931
		1932	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1933
		1934	/* update scratch regs with new routing */
		1935	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		1936	}
		1937
		1938	static void
		1939	atombios_apply_encoder_quirks(struct drm_encoder *encoder,
		1940	struct drm_display_mode *mode)
		1941	{
		1942	struct drm_device *dev = encoder->dev;
		1943	struct radeon_device *rdev = dev->dev_private;
		1944	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1945	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		1946
		1947	/* Funky macbooks */
		1948	if ((dev->pdev->device == 0x71C5) &&
		1949	(dev->pdev->subsystem_vendor == 0x106b) &&
		1950	(dev->pdev->subsystem_device == 0x0080)) {
		1951	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		1952	uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
		1953
		1954	lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
		1955	lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
		1956
		1957	WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
		1958	}
		1959	}
		1960
		1961	/* set scaler clears this on some chips */
		1962	if (ASIC_IS_AVIVO(rdev) &&
		1963	(!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
5078	serge	1964	if (ASIC_IS_DCE8(rdev)) {
2997	Serge	1965	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
5078	serge	1966	WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
		1967	CIK_INTERLEAVE_EN);
		1968	else
		1969	WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
		1970	} else if (ASIC_IS_DCE4(rdev)) {
		1971	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2997	Serge	1972	WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
		1973	EVERGREEN_INTERLEAVE_EN);
		1974	else
		1975	WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
		1976	} else {
		1977	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		1978	WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
		1979	AVIVO_D1MODE_INTERLEAVE_EN);
		1980	else
		1981	WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
		1982	}
		1983	}
		1984	}
		1985
		1986	static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
		1987	{
		1988	struct drm_device *dev = encoder->dev;
		1989	struct radeon_device *rdev = dev->dev_private;
		1990	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		1991	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1992	struct drm_encoder *test_encoder;
		1993	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
		1994	uint32_t dig_enc_in_use = 0;
		1995
		1996	if (ASIC_IS_DCE6(rdev)) {
		1997	/* DCE6 */
		1998	switch (radeon_encoder->encoder_id) {
		1999	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		2000	if (dig->linkb)
		2001	return 1;
		2002	else
		2003	return 0;
		2004	break;
		2005	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		2006	if (dig->linkb)
		2007	return 3;
		2008	else
		2009	return 2;
		2010	break;
		2011	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		2012	if (dig->linkb)
		2013	return 5;
		2014	else
		2015	return 4;
		2016	break;
5078	serge	2017	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
		2018	return 6;
		2019	break;
2997	Serge	2020	}
		2021	} else if (ASIC_IS_DCE4(rdev)) {
		2022	/* DCE4/5 */
		2023	if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
		2024	/* ontario follows DCE4 */
		2025	if (rdev->family == CHIP_PALM) {
		2026	if (dig->linkb)
		2027	return 1;
		2028	else
		2029	return 0;
		2030	} else
		2031	/* llano follows DCE3.2 */
		2032	return radeon_crtc->crtc_id;
		2033	} else {
		2034	switch (radeon_encoder->encoder_id) {
		2035	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		2036	if (dig->linkb)
		2037	return 1;
		2038	else
		2039	return 0;
		2040	break;
		2041	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		2042	if (dig->linkb)
		2043	return 3;
		2044	else
		2045	return 2;
		2046	break;
		2047	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		2048	if (dig->linkb)
		2049	return 5;
		2050	else
		2051	return 4;
		2052	break;
		2053	}
		2054	}
		2055	}
		2056
		2057	/* on DCE32 and encoder can driver any block so just crtc id */
		2058	if (ASIC_IS_DCE32(rdev)) {
		2059	return radeon_crtc->crtc_id;
		2060	}
		2061
		2062	/* on DCE3 - LVTMA can only be driven by DIGB */
		2063	list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
		2064	struct radeon_encoder *radeon_test_encoder;
		2065
		2066	if (encoder == test_encoder)
		2067	continue;
		2068
		2069	if (!radeon_encoder_is_digital(test_encoder))
		2070	continue;
		2071
		2072	radeon_test_encoder = to_radeon_encoder(test_encoder);
		2073	dig = radeon_test_encoder->enc_priv;
		2074
		2075	if (dig->dig_encoder >= 0)
		2076	dig_enc_in_use \|= (1 << dig->dig_encoder);
		2077	}
		2078
		2079	if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
		2080	if (dig_enc_in_use & 0x2)
		2081	DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
		2082	return 1;
		2083	}
		2084	if (!(dig_enc_in_use & 1))
		2085	return 0;
		2086	return 1;
		2087	}
		2088
		2089	/* This only needs to be called once at startup */
		2090	void
		2091	radeon_atom_encoder_init(struct radeon_device *rdev)
		2092	{
		2093	struct drm_device *dev = rdev->ddev;
		2094	struct drm_encoder *encoder;
		2095
		2096	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		2097	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2098	struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
		2099
		2100	switch (radeon_encoder->encoder_id) {
		2101	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		2102	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		2103	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
5078	serge	2104	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2997	Serge	2105	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		2106	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
		2107	break;
		2108	default:
		2109	break;
		2110	}
		2111
		2112	if (ext_encoder && (ASIC_IS_DCE41(rdev) \|\| ASIC_IS_DCE61(rdev)))
		2113	atombios_external_encoder_setup(encoder, ext_encoder,
		2114	EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
		2115	}
		2116	}
		2117
		2118	static void
		2119	radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
		2120	struct drm_display_mode *mode,
		2121	struct drm_display_mode *adjusted_mode)
		2122	{
		2123	struct drm_device *dev = encoder->dev;
		2124	struct radeon_device *rdev = dev->dev_private;
		2125	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2126
		2127	radeon_encoder->pixel_clock = adjusted_mode->clock;
		2128
		2129	/* need to call this here rather than in prepare() since we need some crtc info */
		2130	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
		2131
		2132	if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
		2133	if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT \| ATOM_DEVICE_TV_SUPPORT))
		2134	atombios_yuv_setup(encoder, true);
		2135	else
		2136	atombios_yuv_setup(encoder, false);
		2137	}
		2138
		2139	switch (radeon_encoder->encoder_id) {
		2140	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		2141	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		2142	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		2143	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		2144	atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
		2145	break;
		2146	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		2147	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		2148	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
5078	serge	2149	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2997	Serge	2150	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		2151	/* handled in dpms */
		2152	break;
		2153	case ENCODER_OBJECT_ID_INTERNAL_DDI:
		2154	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
		2155	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		2156	atombios_dvo_setup(encoder, ATOM_ENABLE);
		2157	break;
		2158	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		2159	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
		2160	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		2161	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
		2162	atombios_dac_setup(encoder, ATOM_ENABLE);
		2163	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT \| ATOM_DEVICE_CV_SUPPORT)) {
		2164	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT \| ATOM_DEVICE_CV_SUPPORT))
		2165	atombios_tv_setup(encoder, ATOM_ENABLE);
		2166	else
		2167	atombios_tv_setup(encoder, ATOM_DISABLE);
		2168	}
		2169	break;
		2170	}
		2171
		2172	atombios_apply_encoder_quirks(encoder, adjusted_mode);
		2173
		2174	if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3764	Serge	2175	if (rdev->asic->display.hdmi_enable)
		2176	radeon_hdmi_enable(rdev, encoder, true);
		2177	if (rdev->asic->display.hdmi_setmode)
		2178	radeon_hdmi_setmode(rdev, encoder, adjusted_mode);
2997	Serge	2179	}
		2180	}
		2181
		2182	static bool
		2183	atombios_dac_load_detect(struct drm_encoder encoder, struct drm_connector connector)
		2184	{
		2185	struct drm_device *dev = encoder->dev;
		2186	struct radeon_device *rdev = dev->dev_private;
		2187	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2188	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		2189
		2190	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT \|
		2191	ATOM_DEVICE_CV_SUPPORT \|
		2192	ATOM_DEVICE_CRT_SUPPORT)) {
		2193	DAC_LOAD_DETECTION_PS_ALLOCATION args;
		2194	int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
		2195	uint8_t frev, crev;
		2196
		2197	memset(&args, 0, sizeof(args));
		2198
		2199	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
		2200	return false;
		2201
		2202	args.sDacload.ucMisc = 0;
		2203
		2204	if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) \|\|
		2205	(radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
		2206	args.sDacload.ucDacType = ATOM_DAC_A;
		2207	else
		2208	args.sDacload.ucDacType = ATOM_DAC_B;
		2209
		2210	if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
		2211	args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
		2212	else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
		2213	args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
		2214	else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
		2215	args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
		2216	if (crev >= 3)
		2217	args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
		2218	} else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
		2219	args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
		2220	if (crev >= 3)
		2221	args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
		2222	}
		2223
		2224	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2225
		2226	return true;
		2227	} else
		2228	return false;
		2229	}
		2230
		2231	static enum drm_connector_status
		2232	radeon_atom_dac_detect(struct drm_encoder encoder, struct drm_connector connector)
		2233	{
		2234	struct drm_device *dev = encoder->dev;
		2235	struct radeon_device *rdev = dev->dev_private;
		2236	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2237	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		2238	uint32_t bios_0_scratch;
		2239
		2240	if (!atombios_dac_load_detect(encoder, connector)) {
		2241	DRM_DEBUG_KMS("detect returned false \n");
		2242	return connector_status_unknown;
		2243	}
		2244
		2245	if (rdev->family >= CHIP_R600)
		2246	bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
		2247	else
		2248	bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
		2249
		2250	DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
		2251	if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
		2252	if (bios_0_scratch & ATOM_S0_CRT1_MASK)
		2253	return connector_status_connected;
		2254	}
		2255	if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
		2256	if (bios_0_scratch & ATOM_S0_CRT2_MASK)
		2257	return connector_status_connected;
		2258	}
		2259	if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
		2260	if (bios_0_scratch & (ATOM_S0_CV_MASK\|ATOM_S0_CV_MASK_A))
		2261	return connector_status_connected;
		2262	}
		2263	if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
		2264	if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE \| ATOM_S0_TV1_COMPOSITE_A))
		2265	return connector_status_connected; /* CTV */
		2266	else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO \| ATOM_S0_TV1_SVIDEO_A))
		2267	return connector_status_connected; /* STV */
		2268	}
		2269	return connector_status_disconnected;
		2270	}
		2271
		2272	static enum drm_connector_status
		2273	radeon_atom_dig_detect(struct drm_encoder encoder, struct drm_connector connector)
		2274	{
		2275	struct drm_device *dev = encoder->dev;
		2276	struct radeon_device *rdev = dev->dev_private;
		2277	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2278	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		2279	struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
		2280	u32 bios_0_scratch;
		2281
		2282	if (!ASIC_IS_DCE4(rdev))
		2283	return connector_status_unknown;
		2284
		2285	if (!ext_encoder)
		2286	return connector_status_unknown;
		2287
		2288	if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
		2289	return connector_status_unknown;
		2290
		2291	/* load detect on the dp bridge */
		2292	atombios_external_encoder_setup(encoder, ext_encoder,
		2293	EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
		2294
		2295	bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
		2296
		2297	DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
		2298	if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
		2299	if (bios_0_scratch & ATOM_S0_CRT1_MASK)
		2300	return connector_status_connected;
		2301	}
		2302	if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
		2303	if (bios_0_scratch & ATOM_S0_CRT2_MASK)
		2304	return connector_status_connected;
		2305	}
		2306	if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
		2307	if (bios_0_scratch & (ATOM_S0_CV_MASK\|ATOM_S0_CV_MASK_A))
		2308	return connector_status_connected;
		2309	}
		2310	if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
		2311	if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE \| ATOM_S0_TV1_COMPOSITE_A))
		2312	return connector_status_connected; /* CTV */
		2313	else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO \| ATOM_S0_TV1_SVIDEO_A))
		2314	return connector_status_connected; /* STV */
		2315	}
		2316	return connector_status_disconnected;
		2317	}
		2318
		2319	void
		2320	radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
		2321	{
		2322	struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
		2323
		2324	if (ext_encoder)
		2325	/* ddc_setup on the dp bridge */
		2326	atombios_external_encoder_setup(encoder, ext_encoder,
		2327	EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
		2328
		2329	}
		2330
		2331	static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
		2332	{
		2333	struct radeon_device *rdev = encoder->dev->dev_private;
		2334	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2335	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
		2336
		2337	if ((radeon_encoder->active_device &
		2338	(ATOM_DEVICE_DFP_SUPPORT \| ATOM_DEVICE_LCD_SUPPORT)) \|\|
		2339	(radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
		2340	ENCODER_OBJECT_ID_NONE)) {
		2341	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
		2342	if (dig) {
		2343	dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
		2344	if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
		2345	if (rdev->family >= CHIP_R600)
		2346	dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
		2347	else
		2348	/* RS600/690/740 have only 1 afmt block */
		2349	dig->afmt = rdev->mode_info.afmt[0];
		2350	}
		2351	}
		2352	}
		2353
		2354	radeon_atom_output_lock(encoder, true);
		2355
		2356	if (connector) {
		2357	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		2358
		2359	/* select the clock/data port if it uses a router */
		2360	if (radeon_connector->router.cd_valid)
		2361	radeon_router_select_cd_port(radeon_connector);
		2362
		2363	/* turn eDP panel on for mode set */
		2364	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
		2365	atombios_set_edp_panel_power(connector,
		2366	ATOM_TRANSMITTER_ACTION_POWER_ON);
		2367	}
		2368
		2369	/* this is needed for the pll/ss setup to work correctly in some cases */
		2370	atombios_set_encoder_crtc_source(encoder);
5078	serge	2371	/* set up the FMT blocks */
		2372	if (ASIC_IS_DCE8(rdev))
		2373	dce8_program_fmt(encoder);
		2374	else if (ASIC_IS_DCE4(rdev))
		2375	dce4_program_fmt(encoder);
		2376	else if (ASIC_IS_DCE3(rdev))
		2377	dce3_program_fmt(encoder);
		2378	else if (ASIC_IS_AVIVO(rdev))
		2379	avivo_program_fmt(encoder);
2997	Serge	2380	}
		2381
		2382	static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
		2383	{
		2384	/* need to call this here as we need the crtc set up */
		2385	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
		2386	radeon_atom_output_lock(encoder, false);
		2387	}
		2388
		2389	static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
		2390	{
		2391	struct drm_device *dev = encoder->dev;
		2392	struct radeon_device *rdev = dev->dev_private;
		2393	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2394	struct radeon_encoder_atom_dig *dig;
		2395
		2396	/* check for pre-DCE3 cards with shared encoders;
		2397	* can't really use the links individually, so don't disable
		2398	* the encoder if it's in use by another connector
		2399	*/
		2400	if (!ASIC_IS_DCE3(rdev)) {
		2401	struct drm_encoder *other_encoder;
		2402	struct radeon_encoder *other_radeon_encoder;
		2403
		2404	list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
		2405	other_radeon_encoder = to_radeon_encoder(other_encoder);
		2406	if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
		2407	drm_helper_encoder_in_use(other_encoder))
		2408	goto disable_done;
		2409	}
		2410	}
		2411
		2412	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
		2413
		2414	switch (radeon_encoder->encoder_id) {
		2415	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		2416	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		2417	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		2418	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		2419	atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
		2420	break;
		2421	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		2422	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		2423	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
5078	serge	2424	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2997	Serge	2425	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		2426	/* handled in dpms */
		2427	break;
		2428	case ENCODER_OBJECT_ID_INTERNAL_DDI:
		2429	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
		2430	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		2431	atombios_dvo_setup(encoder, ATOM_DISABLE);
		2432	break;
		2433	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		2434	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
		2435	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		2436	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
		2437	atombios_dac_setup(encoder, ATOM_DISABLE);
		2438	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT \| ATOM_DEVICE_CV_SUPPORT))
		2439	atombios_tv_setup(encoder, ATOM_DISABLE);
		2440	break;
		2441	}
		2442
		2443	disable_done:
		2444	if (radeon_encoder_is_digital(encoder)) {
3764	Serge	2445	if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
		2446	if (rdev->asic->display.hdmi_enable)
		2447	radeon_hdmi_enable(rdev, encoder, false);
		2448	}
2997	Serge	2449	dig = radeon_encoder->enc_priv;
		2450	dig->dig_encoder = -1;
		2451	}
		2452	radeon_encoder->active_device = 0;
		2453	}
		2454
		2455	/* these are handled by the primary encoders */
		2456	static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
		2457	{
		2458
		2459	}
		2460
		2461	static void radeon_atom_ext_commit(struct drm_encoder *encoder)
		2462	{
		2463
		2464	}
		2465
		2466	static void
		2467	radeon_atom_ext_mode_set(struct drm_encoder *encoder,
		2468	struct drm_display_mode *mode,
		2469	struct drm_display_mode *adjusted_mode)
		2470	{
		2471
		2472	}
		2473
		2474	static void radeon_atom_ext_disable(struct drm_encoder *encoder)
		2475	{
		2476
		2477	}
		2478
		2479	static void
		2480	radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
		2481	{
		2482
		2483	}
		2484
		2485	static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
		2486	const struct drm_display_mode *mode,
		2487	struct drm_display_mode *adjusted_mode)
		2488	{
		2489	return true;
		2490	}
		2491
		2492	static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
		2493	.dpms = radeon_atom_ext_dpms,
		2494	.mode_fixup = radeon_atom_ext_mode_fixup,
		2495	.prepare = radeon_atom_ext_prepare,
		2496	.mode_set = radeon_atom_ext_mode_set,
		2497	.commit = radeon_atom_ext_commit,
		2498	.disable = radeon_atom_ext_disable,
		2499	/* no detect for TMDS/LVDS yet */
		2500	};
		2501
		2502	static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
		2503	.dpms = radeon_atom_encoder_dpms,
		2504	.mode_fixup = radeon_atom_mode_fixup,
		2505	.prepare = radeon_atom_encoder_prepare,
		2506	.mode_set = radeon_atom_encoder_mode_set,
		2507	.commit = radeon_atom_encoder_commit,
		2508	.disable = radeon_atom_encoder_disable,
		2509	.detect = radeon_atom_dig_detect,
		2510	};
		2511
		2512	static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
		2513	.dpms = radeon_atom_encoder_dpms,
		2514	.mode_fixup = radeon_atom_mode_fixup,
		2515	.prepare = radeon_atom_encoder_prepare,
		2516	.mode_set = radeon_atom_encoder_mode_set,
		2517	.commit = radeon_atom_encoder_commit,
		2518	.detect = radeon_atom_dac_detect,
		2519	};
		2520
		2521	void radeon_enc_destroy(struct drm_encoder *encoder)
		2522	{
		2523	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2524	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
		2525	radeon_atom_backlight_exit(radeon_encoder);
		2526	kfree(radeon_encoder->enc_priv);
		2527	drm_encoder_cleanup(encoder);
		2528	kfree(radeon_encoder);
		2529	}
		2530
		2531	static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
		2532	.destroy = radeon_enc_destroy,
		2533	};
		2534
		2535	static struct radeon_encoder_atom_dac *
		2536	radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
		2537	{
		2538	struct drm_device *dev = radeon_encoder->base.dev;
		2539	struct radeon_device *rdev = dev->dev_private;
		2540	struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
		2541
		2542	if (!dac)
		2543	return NULL;
		2544
		2545	dac->tv_std = radeon_atombios_get_tv_info(rdev);
		2546	return dac;
		2547	}
		2548
		2549	static struct radeon_encoder_atom_dig *
		2550	radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
		2551	{
		2552	int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
		2553	struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
		2554
		2555	if (!dig)
		2556	return NULL;
		2557
		2558	/* coherent mode by default */
		2559	dig->coherent_mode = true;
		2560	dig->dig_encoder = -1;
		2561
		2562	if (encoder_enum == 2)
		2563	dig->linkb = true;
		2564	else
		2565	dig->linkb = false;
		2566
		2567	return dig;
		2568	}
		2569
		2570	void
		2571	radeon_add_atom_encoder(struct drm_device *dev,
		2572	uint32_t encoder_enum,
		2573	uint32_t supported_device,
		2574	u16 caps)
		2575	{
		2576	struct radeon_device *rdev = dev->dev_private;
		2577	struct drm_encoder *encoder;
		2578	struct radeon_encoder *radeon_encoder;
		2579
		2580	/* see if we already added it */
		2581	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		2582	radeon_encoder = to_radeon_encoder(encoder);
		2583	if (radeon_encoder->encoder_enum == encoder_enum) {
		2584	radeon_encoder->devices \|= supported_device;
		2585	return;
		2586	}
		2587
		2588	}
		2589
		2590	/* add a new one */
		2591	radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
		2592	if (!radeon_encoder)
		2593	return;
		2594
		2595	encoder = &radeon_encoder->base;
		2596	switch (rdev->num_crtc) {
		2597	case 1:
		2598	encoder->possible_crtcs = 0x1;
		2599	break;
		2600	case 2:
		2601	default:
		2602	encoder->possible_crtcs = 0x3;
		2603	break;
		2604	case 4:
		2605	encoder->possible_crtcs = 0xf;
		2606	break;
		2607	case 6:
		2608	encoder->possible_crtcs = 0x3f;
		2609	break;
		2610	}
		2611
		2612	radeon_encoder->enc_priv = NULL;
		2613
		2614	radeon_encoder->encoder_enum = encoder_enum;
		2615	radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
		2616	radeon_encoder->devices = supported_device;
		2617	radeon_encoder->rmx_type = RMX_OFF;
		2618	radeon_encoder->underscan_type = UNDERSCAN_OFF;
		2619	radeon_encoder->is_ext_encoder = false;
		2620	radeon_encoder->caps = caps;
		2621
		2622	switch (radeon_encoder->encoder_id) {
		2623	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		2624	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		2625	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		2626	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		2627	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		2628	radeon_encoder->rmx_type = RMX_FULL;
		2629	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
		2630	radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
		2631	} else {
		2632	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
		2633	radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
		2634	}
		2635	drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
		2636	break;
		2637	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		2638	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
		2639	radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
		2640	drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
		2641	break;
		2642	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		2643	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
		2644	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
		2645	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
		2646	radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
		2647	drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
		2648	break;
		2649	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
		2650	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		2651	case ENCODER_OBJECT_ID_INTERNAL_DDI:
		2652	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		2653	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		2654	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		2655	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
5078	serge	2656	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2997	Serge	2657	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		2658	radeon_encoder->rmx_type = RMX_FULL;
		2659	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
		2660	radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
		2661	} else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
		2662	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
		2663	radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
		2664	} else {
		2665	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
		2666	radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
		2667	}
		2668	drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
		2669	break;
		2670	case ENCODER_OBJECT_ID_SI170B:
		2671	case ENCODER_OBJECT_ID_CH7303:
		2672	case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
		2673	case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
		2674	case ENCODER_OBJECT_ID_TITFP513:
		2675	case ENCODER_OBJECT_ID_VT1623:
		2676	case ENCODER_OBJECT_ID_HDMI_SI1930:
		2677	case ENCODER_OBJECT_ID_TRAVIS:
		2678	case ENCODER_OBJECT_ID_NUTMEG:
		2679	/* these are handled by the primary encoders */
		2680	radeon_encoder->is_ext_encoder = true;
		2681	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
		2682	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
		2683	else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
		2684	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
		2685	else
		2686	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
		2687	drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
		2688	break;
		2689	}
		2690	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/atombios_encoders.c – Rev 5271