Rev 6938 | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
1403 | serge | 1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
||
3 | * Copyright 2008 Red Hat Inc. |
||
4 | * |
||
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
||
6 | * copy of this software and associated documentation files (the "Software"), |
||
7 | * to deal in the Software without restriction, including without limitation |
||
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
||
9 | * and/or sell copies of the Software, and to permit persons to whom the |
||
10 | * Software is furnished to do so, subject to the following conditions: |
||
11 | * |
||
12 | * The above copyright notice and this permission notice shall be included in |
||
13 | * all copies or substantial portions of the Software. |
||
14 | * |
||
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
||
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
||
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
||
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||
21 | * OTHER DEALINGS IN THE SOFTWARE. |
||
22 | * |
||
23 | * Authors: Dave Airlie |
||
24 | * Alex Deucher |
||
2997 | Serge | 25 | * Jerome Glisse |
1403 | serge | 26 | */ |
2997 | Serge | 27 | #include |
28 | #include |
||
1403 | serge | 29 | #include "radeon.h" |
30 | |||
31 | #include "atom.h" |
||
32 | #include "atom-bits.h" |
||
2997 | Serge | 33 | #include |
1403 | serge | 34 | |
35 | /* move these to drm_dp_helper.c/h */ |
||
36 | #define DP_LINK_CONFIGURATION_SIZE 9 |
||
3192 | Serge | 37 | #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE |
1403 | serge | 38 | |
39 | static char *voltage_names[] = { |
||
7146 | serge | 40 | "0.4V", "0.6V", "0.8V", "1.2V" |
1403 | serge | 41 | }; |
42 | static char *pre_emph_names[] = { |
||
7146 | serge | 43 | "0dB", "3.5dB", "6dB", "9.5dB" |
1403 | serge | 44 | }; |
45 | |||
1963 | serge | 46 | /***** radeon AUX functions *****/ |
5078 | serge | 47 | |
48 | /* Atom needs data in little endian format |
||
49 | * so swap as appropriate when copying data to |
||
50 | * or from atom. Note that atom operates on |
||
51 | * dw units. |
||
52 | */ |
||
53 | void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) |
||
54 | { |
||
55 | #ifdef __BIG_ENDIAN |
||
56 | u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */ |
||
57 | u32 *dst32, *src32; |
||
58 | int i; |
||
59 | |||
60 | memcpy(src_tmp, src, num_bytes); |
||
61 | src32 = (u32 *)src_tmp; |
||
62 | dst32 = (u32 *)dst_tmp; |
||
63 | if (to_le) { |
||
64 | for (i = 0; i < ((num_bytes + 3) / 4); i++) |
||
65 | dst32[i] = cpu_to_le32(src32[i]); |
||
66 | memcpy(dst, dst_tmp, num_bytes); |
||
67 | } else { |
||
68 | u8 dws = num_bytes & ~3; |
||
69 | for (i = 0; i < ((num_bytes + 3) / 4); i++) |
||
70 | dst32[i] = le32_to_cpu(src32[i]); |
||
71 | memcpy(dst, dst_tmp, dws); |
||
72 | if (num_bytes % 4) { |
||
73 | for (i = 0; i < (num_bytes % 4); i++) |
||
74 | dst[dws+i] = dst_tmp[dws+i]; |
||
75 | } |
||
76 | } |
||
77 | #else |
||
78 | memcpy(dst, src, num_bytes); |
||
79 | #endif |
||
80 | } |
||
81 | |||
1963 | serge | 82 | union aux_channel_transaction { |
83 | PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; |
||
84 | PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; |
||
1403 | serge | 85 | }; |
86 | |||
1963 | serge | 87 | static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, |
88 | u8 *send, int send_bytes, |
||
89 | u8 *recv, int recv_size, |
||
90 | u8 delay, u8 *ack) |
||
1403 | serge | 91 | { |
1963 | serge | 92 | struct drm_device *dev = chan->dev; |
93 | struct radeon_device *rdev = dev->dev_private; |
||
94 | union aux_channel_transaction args; |
||
95 | int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); |
||
96 | unsigned char *base; |
||
97 | int recv_bytes; |
||
5078 | serge | 98 | int r = 0; |
1403 | serge | 99 | |
1963 | serge | 100 | memset(&args, 0, sizeof(args)); |
1403 | serge | 101 | |
5078 | serge | 102 | mutex_lock(&chan->mutex); |
5271 | serge | 103 | mutex_lock(&rdev->mode_info.atom_context->scratch_mutex); |
5078 | serge | 104 | |
2997 | Serge | 105 | base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); |
1403 | serge | 106 | |
5078 | serge | 107 | radeon_atom_copy_swap(base, send, send_bytes, true); |
1963 | serge | 108 | |
5078 | serge | 109 | args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4)); |
110 | args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4)); |
||
1963 | serge | 111 | args.v1.ucDataOutLen = 0; |
112 | args.v1.ucChannelID = chan->rec.i2c_id; |
||
113 | args.v1.ucDelay = delay / 10; |
||
114 | if (ASIC_IS_DCE4(rdev)) |
||
115 | args.v2.ucHPD_ID = chan->rec.hpd; |
||
116 | |||
5271 | serge | 117 | atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1963 | serge | 118 | |
119 | *ack = args.v1.ucReplyStatus; |
||
120 | |||
121 | /* timeout */ |
||
122 | if (args.v1.ucReplyStatus == 1) { |
||
123 | DRM_DEBUG_KMS("dp_aux_ch timeout\n"); |
||
5078 | serge | 124 | r = -ETIMEDOUT; |
125 | goto done; |
||
6104 | serge | 126 | } |
1963 | serge | 127 | |
128 | /* flags not zero */ |
||
129 | if (args.v1.ucReplyStatus == 2) { |
||
130 | DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); |
||
5078 | serge | 131 | r = -EIO; |
132 | goto done; |
||
6104 | serge | 133 | } |
1963 | serge | 134 | |
135 | /* error */ |
||
136 | if (args.v1.ucReplyStatus == 3) { |
||
137 | DRM_DEBUG_KMS("dp_aux_ch error\n"); |
||
5078 | serge | 138 | r = -EIO; |
139 | goto done; |
||
6104 | serge | 140 | } |
1963 | serge | 141 | |
142 | recv_bytes = args.v1.ucDataOutLen; |
||
143 | if (recv_bytes > recv_size) |
||
144 | recv_bytes = recv_size; |
||
145 | |||
146 | if (recv && recv_size) |
||
5078 | serge | 147 | radeon_atom_copy_swap(recv, base + 16, recv_bytes, false); |
1963 | serge | 148 | |
5078 | serge | 149 | r = recv_bytes; |
150 | done: |
||
5271 | serge | 151 | mutex_unlock(&rdev->mode_info.atom_context->scratch_mutex); |
5078 | serge | 152 | mutex_unlock(&chan->mutex); |
153 | |||
154 | return r; |
||
1963 | serge | 155 | } |
156 | |||
5078 | serge | 157 | #define BARE_ADDRESS_SIZE 3 |
158 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) |
||
159 | |||
160 | static ssize_t |
||
6104 | serge | 161 | radeon_dp_aux_transfer_atom(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
1963 | serge | 162 | { |
5078 | serge | 163 | struct radeon_i2c_chan *chan = |
164 | container_of(aux, struct radeon_i2c_chan, aux); |
||
1963 | serge | 165 | int ret; |
5078 | serge | 166 | u8 tx_buf[20]; |
167 | size_t tx_size; |
||
168 | u8 ack, delay = 0; |
||
1963 | serge | 169 | |
5078 | serge | 170 | if (WARN_ON(msg->size > 16)) |
171 | return -E2BIG; |
||
1963 | serge | 172 | |
5078 | serge | 173 | tx_buf[0] = msg->address & 0xff; |
6104 | serge | 174 | tx_buf[1] = (msg->address >> 8) & 0xff; |
175 | tx_buf[2] = (msg->request << 4) | |
||
176 | ((msg->address >> 16) & 0xf); |
||
5078 | serge | 177 | tx_buf[3] = msg->size ? (msg->size - 1) : 0; |
1963 | serge | 178 | |
5078 | serge | 179 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
180 | case DP_AUX_NATIVE_WRITE: |
||
181 | case DP_AUX_I2C_WRITE: |
||
6104 | serge | 182 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
183 | /* The atom implementation only supports writes with a max payload of |
||
184 | * 12 bytes since it uses 4 bits for the total count (header + payload) |
||
185 | * in the parameter space. The atom interface supports 16 byte |
||
186 | * payloads for reads. The hw itself supports up to 16 bytes of payload. |
||
187 | */ |
||
188 | if (WARN_ON_ONCE(msg->size > 12)) |
||
189 | return -E2BIG; |
||
5078 | serge | 190 | /* tx_size needs to be 4 even for bare address packets since the atom |
191 | * table needs the info in tx_buf[3]. |
||
192 | */ |
||
193 | tx_size = HEADER_SIZE + msg->size; |
||
194 | if (msg->size == 0) |
||
195 | tx_buf[3] |= BARE_ADDRESS_SIZE << 4; |
||
1963 | serge | 196 | else |
5078 | serge | 197 | tx_buf[3] |= tx_size << 4; |
198 | memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size); |
||
199 | ret = radeon_process_aux_ch(chan, |
||
200 | tx_buf, tx_size, NULL, 0, delay, &ack); |
||
201 | if (ret >= 0) |
||
202 | /* Return payload size. */ |
||
203 | ret = msg->size; |
||
204 | break; |
||
205 | case DP_AUX_NATIVE_READ: |
||
206 | case DP_AUX_I2C_READ: |
||
207 | /* tx_size needs to be 4 even for bare address packets since the atom |
||
208 | * table needs the info in tx_buf[3]. |
||
209 | */ |
||
210 | tx_size = HEADER_SIZE; |
||
211 | if (msg->size == 0) |
||
212 | tx_buf[3] |= BARE_ADDRESS_SIZE << 4; |
||
213 | else |
||
214 | tx_buf[3] |= tx_size << 4; |
||
215 | ret = radeon_process_aux_ch(chan, |
||
216 | tx_buf, tx_size, msg->buffer, msg->size, delay, &ack); |
||
217 | break; |
||
218 | default: |
||
219 | ret = -EINVAL; |
||
220 | break; |
||
6104 | serge | 221 | } |
1963 | serge | 222 | |
5078 | serge | 223 | if (ret >= 0) |
224 | msg->reply = ack >> 4; |
||
1963 | serge | 225 | |
6104 | serge | 226 | return ret; |
1963 | serge | 227 | } |
1403 | serge | 228 | |
5078 | serge | 229 | void radeon_dp_aux_init(struct radeon_connector *radeon_connector) |
1963 | serge | 230 | { |
6104 | serge | 231 | struct drm_device *dev = radeon_connector->base.dev; |
232 | struct radeon_device *rdev = dev->dev_private; |
||
1963 | serge | 233 | int ret; |
234 | |||
5078 | serge | 235 | radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd; |
236 | radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev; |
||
6104 | serge | 237 | if (ASIC_IS_DCE5(rdev)) { |
238 | if (radeon_auxch) |
||
239 | radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_native; |
||
240 | else |
||
241 | radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom; |
||
242 | } else { |
||
243 | radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom; |
||
244 | } |
||
1963 | serge | 245 | |
5078 | serge | 246 | ret = drm_dp_aux_register(&radeon_connector->ddc_bus->aux); |
247 | if (!ret) |
||
248 | radeon_connector->ddc_bus->has_aux = true; |
||
1963 | serge | 249 | |
5078 | serge | 250 | WARN(ret, "drm_dp_aux_register() failed with error %d\n", ret); |
1403 | serge | 251 | } |
252 | |||
1963 | serge | 253 | /***** general DP utility functions *****/ |
1403 | serge | 254 | |
5271 | serge | 255 | #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3 |
256 | #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3 |
||
1403 | serge | 257 | |
6104 | serge | 258 | static void dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE], |
1403 | serge | 259 | int lane_count, |
260 | u8 train_set[4]) |
||
261 | { |
||
262 | u8 v = 0; |
||
263 | u8 p = 0; |
||
264 | int lane; |
||
265 | |||
266 | for (lane = 0; lane < lane_count; lane++) { |
||
3192 | Serge | 267 | u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
268 | u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); |
||
1403 | serge | 269 | |
1963 | serge | 270 | DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", |
1403 | serge | 271 | lane, |
272 | voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
||
273 | pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); |
||
274 | |||
275 | if (this_v > v) |
||
276 | v = this_v; |
||
277 | if (this_p > p) |
||
278 | p = this_p; |
||
279 | } |
||
280 | |||
281 | if (v >= DP_VOLTAGE_MAX) |
||
1963 | serge | 282 | v |= DP_TRAIN_MAX_SWING_REACHED; |
1403 | serge | 283 | |
1963 | serge | 284 | if (p >= DP_PRE_EMPHASIS_MAX) |
285 | p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
||
1403 | serge | 286 | |
1963 | serge | 287 | DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", |
1403 | serge | 288 | voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
289 | pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); |
||
290 | |||
291 | for (lane = 0; lane < 4; lane++) |
||
292 | train_set[lane] = v | p; |
||
293 | } |
||
294 | |||
1963 | serge | 295 | /* convert bits per color to bits per pixel */ |
296 | /* get bpc from the EDID */ |
||
297 | static int convert_bpc_to_bpp(int bpc) |
||
298 | { |
||
299 | if (bpc == 0) |
||
300 | return 24; |
||
301 | else |
||
302 | return bpc * 3; |
||
303 | } |
||
1403 | serge | 304 | |
1963 | serge | 305 | /***** radeon specific DP functions *****/ |
1403 | serge | 306 | |
6661 | serge | 307 | int radeon_dp_get_dp_link_config(struct drm_connector *connector, |
7146 | serge | 308 | const u8 dpcd[DP_DPCD_SIZE], |
6661 | serge | 309 | unsigned pix_clock, |
310 | unsigned *dp_lanes, unsigned *dp_rate) |
||
1963 | serge | 311 | { |
2997 | Serge | 312 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
6661 | serge | 313 | static const unsigned link_rates[3] = { 162000, 270000, 540000 }; |
314 | unsigned max_link_rate = drm_dp_max_link_rate(dpcd); |
||
315 | unsigned max_lane_num = drm_dp_max_lane_count(dpcd); |
||
316 | unsigned lane_num, i, max_pix_clock; |
||
1403 | serge | 317 | |
6938 | serge | 318 | if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == |
319 | ENCODER_OBJECT_ID_NUTMEG) { |
||
7146 | serge | 320 | for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) { |
6938 | serge | 321 | max_pix_clock = (lane_num * 270000 * 8) / bpp; |
322 | if (max_pix_clock >= pix_clock) { |
||
323 | *dp_lanes = lane_num; |
||
324 | *dp_rate = 270000; |
||
325 | return 0; |
||
326 | } |
||
327 | } |
||
328 | } else { |
||
6661 | serge | 329 | for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) { |
6938 | serge | 330 | for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) { |
7146 | serge | 331 | max_pix_clock = (lane_num * link_rates[i] * 8) / bpp; |
332 | if (max_pix_clock >= pix_clock) { |
||
333 | *dp_lanes = lane_num; |
||
334 | *dp_rate = link_rates[i]; |
||
335 | return 0; |
||
336 | } |
||
337 | } |
||
338 | } |
||
1403 | serge | 339 | } |
340 | |||
6661 | serge | 341 | return -EINVAL; |
1403 | serge | 342 | } |
343 | |||
1963 | serge | 344 | static u8 radeon_dp_encoder_service(struct radeon_device *rdev, |
345 | int action, int dp_clock, |
||
346 | u8 ucconfig, u8 lane_num) |
||
1403 | serge | 347 | { |
348 | DP_ENCODER_SERVICE_PARAMETERS args; |
||
349 | int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); |
||
350 | |||
351 | memset(&args, 0, sizeof(args)); |
||
352 | args.ucLinkClock = dp_clock / 10; |
||
353 | args.ucConfig = ucconfig; |
||
354 | args.ucAction = action; |
||
355 | args.ucLaneNum = lane_num; |
||
356 | args.ucStatus = 0; |
||
357 | |||
358 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
359 | return args.ucStatus; |
||
360 | } |
||
361 | |||
362 | u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) |
||
363 | { |
||
364 | struct drm_device *dev = radeon_connector->base.dev; |
||
365 | struct radeon_device *rdev = dev->dev_private; |
||
366 | |||
367 | return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, |
||
5078 | serge | 368 | radeon_connector->ddc_bus->rec.i2c_id, 0); |
1403 | serge | 369 | } |
370 | |||
2997 | Serge | 371 | static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) |
372 | { |
||
373 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
||
374 | u8 buf[3]; |
||
375 | |||
376 | if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
||
377 | return; |
||
378 | |||
5078 | serge | 379 | if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3) |
2997 | Serge | 380 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
381 | buf[0], buf[1], buf[2]); |
||
382 | |||
5078 | serge | 383 | if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3) |
2997 | Serge | 384 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
385 | buf[0], buf[1], buf[2]); |
||
386 | } |
||
387 | |||
1403 | serge | 388 | bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) |
389 | { |
||
390 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
||
3192 | Serge | 391 | u8 msg[DP_DPCD_SIZE]; |
6104 | serge | 392 | int ret, i; |
1403 | serge | 393 | |
6104 | serge | 394 | for (i = 0; i < 7; i++) { |
395 | ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg, |
||
396 | DP_DPCD_SIZE); |
||
397 | if (ret == DP_DPCD_SIZE) { |
||
398 | memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); |
||
2997 | Serge | 399 | |
6104 | serge | 400 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), |
401 | dig_connector->dpcd); |
||
5078 | serge | 402 | |
6104 | serge | 403 | radeon_dp_probe_oui(radeon_connector); |
3764 | Serge | 404 | |
6104 | serge | 405 | return true; |
406 | } |
||
1403 | serge | 407 | } |
408 | dig_connector->dpcd[0] = 0; |
||
409 | return false; |
||
410 | } |
||
411 | |||
2997 | Serge | 412 | int radeon_dp_get_panel_mode(struct drm_encoder *encoder, |
6104 | serge | 413 | struct drm_connector *connector) |
1963 | serge | 414 | { |
415 | struct drm_device *dev = encoder->dev; |
||
416 | struct radeon_device *rdev = dev->dev_private; |
||
2997 | Serge | 417 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
5078 | serge | 418 | struct radeon_connector_atom_dig *dig_connector; |
1963 | serge | 419 | int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
2997 | Serge | 420 | u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); |
421 | u8 tmp; |
||
1963 | serge | 422 | |
423 | if (!ASIC_IS_DCE4(rdev)) |
||
2997 | Serge | 424 | return panel_mode; |
1963 | serge | 425 | |
5078 | serge | 426 | if (!radeon_connector->con_priv) |
427 | return panel_mode; |
||
428 | |||
429 | dig_connector = radeon_connector->con_priv; |
||
430 | |||
2997 | Serge | 431 | if (dp_bridge != ENCODER_OBJECT_ID_NONE) { |
432 | /* DP bridge chips */ |
||
5078 | serge | 433 | if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, |
434 | DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { |
||
6104 | serge | 435 | if (tmp & 1) |
436 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; |
||
437 | else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || |
||
438 | (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) |
||
439 | panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; |
||
440 | else |
||
441 | panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
||
5078 | serge | 442 | } |
2997 | Serge | 443 | } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
444 | /* eDP */ |
||
5078 | serge | 445 | if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, |
446 | DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { |
||
6104 | serge | 447 | if (tmp & 1) |
448 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; |
||
449 | } |
||
2997 | Serge | 450 | } |
1963 | serge | 451 | |
2997 | Serge | 452 | return panel_mode; |
1963 | serge | 453 | } |
454 | |||
1403 | serge | 455 | void radeon_dp_set_link_config(struct drm_connector *connector, |
2997 | Serge | 456 | const struct drm_display_mode *mode) |
1403 | serge | 457 | { |
1963 | serge | 458 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1403 | serge | 459 | struct radeon_connector_atom_dig *dig_connector; |
6661 | serge | 460 | int ret; |
1403 | serge | 461 | |
462 | if (!radeon_connector->con_priv) |
||
463 | return; |
||
464 | dig_connector = radeon_connector->con_priv; |
||
465 | |||
1963 | serge | 466 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
467 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { |
||
6661 | serge | 468 | ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, |
469 | mode->clock, |
||
470 | &dig_connector->dp_lane_count, |
||
471 | &dig_connector->dp_clock); |
||
472 | if (ret) { |
||
473 | dig_connector->dp_clock = 0; |
||
474 | dig_connector->dp_lane_count = 0; |
||
475 | } |
||
1963 | serge | 476 | } |
1403 | serge | 477 | } |
478 | |||
1963 | serge | 479 | int radeon_dp_mode_valid_helper(struct drm_connector *connector, |
1403 | serge | 480 | struct drm_display_mode *mode) |
481 | { |
||
1963 | serge | 482 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
483 | struct radeon_connector_atom_dig *dig_connector; |
||
6661 | serge | 484 | unsigned dp_clock, dp_lanes; |
485 | int ret; |
||
1403 | serge | 486 | |
6104 | serge | 487 | if ((mode->clock > 340000) && |
488 | (!radeon_connector_is_dp12_capable(connector))) |
||
489 | return MODE_CLOCK_HIGH; |
||
490 | |||
1963 | serge | 491 | if (!radeon_connector->con_priv) |
492 | return MODE_CLOCK_HIGH; |
||
493 | dig_connector = radeon_connector->con_priv; |
||
494 | |||
6661 | serge | 495 | ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, |
496 | mode->clock, |
||
497 | &dp_lanes, |
||
498 | &dp_clock); |
||
499 | if (ret) |
||
500 | return MODE_CLOCK_HIGH; |
||
1963 | serge | 501 | |
502 | if ((dp_clock == 540000) && |
||
503 | (!radeon_connector_is_dp12_capable(connector))) |
||
504 | return MODE_CLOCK_HIGH; |
||
505 | |||
506 | return MODE_OK; |
||
1403 | serge | 507 | } |
508 | |||
2997 | Serge | 509 | bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) |
510 | { |
||
511 | u8 link_status[DP_LINK_STATUS_SIZE]; |
||
512 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; |
||
513 | |||
5078 | serge | 514 | if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status) |
515 | <= 0) |
||
2997 | Serge | 516 | return false; |
3192 | Serge | 517 | if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) |
2997 | Serge | 518 | return false; |
519 | return true; |
||
520 | } |
||
521 | |||
5078 | serge | 522 | void radeon_dp_set_rx_power_state(struct drm_connector *connector, |
523 | u8 power_state) |
||
524 | { |
||
525 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
||
526 | struct radeon_connector_atom_dig *dig_connector; |
||
527 | |||
528 | if (!radeon_connector->con_priv) |
||
529 | return; |
||
530 | |||
531 | dig_connector = radeon_connector->con_priv; |
||
532 | |||
533 | /* power up/down the sink */ |
||
534 | if (dig_connector->dpcd[0] >= 0x11) { |
||
535 | drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux, |
||
536 | DP_SET_POWER, power_state); |
||
537 | usleep_range(1000, 2000); |
||
538 | } |
||
539 | } |
||
540 | |||
541 | |||
1963 | serge | 542 | struct radeon_dp_link_train_info { |
543 | struct radeon_device *rdev; |
||
544 | struct drm_encoder *encoder; |
||
545 | struct drm_connector *connector; |
||
546 | int enc_id; |
||
547 | int dp_clock; |
||
548 | int dp_lane_count; |
||
549 | bool tp3_supported; |
||
3192 | Serge | 550 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
1963 | serge | 551 | u8 train_set[4]; |
1403 | serge | 552 | u8 link_status[DP_LINK_STATUS_SIZE]; |
1963 | serge | 553 | u8 tries; |
2160 | serge | 554 | bool use_dpencoder; |
5078 | serge | 555 | struct drm_dp_aux *aux; |
1963 | serge | 556 | }; |
1403 | serge | 557 | |
1963 | serge | 558 | static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) |
559 | { |
||
560 | /* set the initial vs/emph on the source */ |
||
561 | atombios_dig_transmitter_setup(dp_info->encoder, |
||
562 | ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, |
||
563 | 0, dp_info->train_set[0]); /* sets all lanes at once */ |
||
564 | |||
565 | /* set the vs/emph on the sink */ |
||
5078 | serge | 566 | drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET, |
567 | dp_info->train_set, dp_info->dp_lane_count); |
||
1403 | serge | 568 | } |
569 | |||
1963 | serge | 570 | static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) |
1403 | serge | 571 | { |
1963 | serge | 572 | int rtp = 0; |
1403 | serge | 573 | |
1963 | serge | 574 | /* set training pattern on the source */ |
2160 | serge | 575 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { |
1963 | serge | 576 | switch (tp) { |
577 | case DP_TRAINING_PATTERN_1: |
||
578 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; |
||
579 | break; |
||
580 | case DP_TRAINING_PATTERN_2: |
||
581 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; |
||
582 | break; |
||
583 | case DP_TRAINING_PATTERN_3: |
||
584 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; |
||
585 | break; |
||
586 | } |
||
587 | atombios_dig_encoder_setup(dp_info->encoder, rtp, 0); |
||
588 | } else { |
||
589 | switch (tp) { |
||
590 | case DP_TRAINING_PATTERN_1: |
||
591 | rtp = 0; |
||
592 | break; |
||
593 | case DP_TRAINING_PATTERN_2: |
||
594 | rtp = 1; |
||
595 | break; |
||
596 | } |
||
597 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, |
||
598 | dp_info->dp_clock, dp_info->enc_id, rtp); |
||
1403 | serge | 599 | } |
600 | |||
1963 | serge | 601 | /* enable training pattern on the sink */ |
5078 | serge | 602 | drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp); |
1403 | serge | 603 | } |
604 | |||
1963 | serge | 605 | static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) |
1403 | serge | 606 | { |
2997 | Serge | 607 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); |
608 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
||
1963 | serge | 609 | u8 tmp; |
1403 | serge | 610 | |
1963 | serge | 611 | /* power up the sink */ |
5078 | serge | 612 | radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0); |
1403 | serge | 613 | |
1963 | serge | 614 | /* possibly enable downspread on the sink */ |
615 | if (dp_info->dpcd[3] & 0x1) |
||
5078 | serge | 616 | drm_dp_dpcd_writeb(dp_info->aux, |
6104 | serge | 617 | DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); |
1963 | serge | 618 | else |
5078 | serge | 619 | drm_dp_dpcd_writeb(dp_info->aux, |
6104 | serge | 620 | DP_DOWNSPREAD_CTRL, 0); |
1403 | serge | 621 | |
6104 | serge | 622 | if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE) |
5078 | serge | 623 | drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1); |
1403 | serge | 624 | |
1963 | serge | 625 | /* set the lane count on the sink */ |
626 | tmp = dp_info->dp_lane_count; |
||
5078 | serge | 627 | if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) |
1963 | serge | 628 | tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
5078 | serge | 629 | drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp); |
1963 | serge | 630 | |
631 | /* set the link rate on the sink */ |
||
3192 | Serge | 632 | tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); |
5078 | serge | 633 | drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp); |
1963 | serge | 634 | |
635 | /* start training on the source */ |
||
2160 | serge | 636 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
1963 | serge | 637 | atombios_dig_encoder_setup(dp_info->encoder, |
638 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); |
||
639 | else |
||
640 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, |
||
641 | dp_info->dp_clock, dp_info->enc_id, 0); |
||
642 | |||
643 | /* disable the training pattern on the sink */ |
||
5078 | serge | 644 | drm_dp_dpcd_writeb(dp_info->aux, |
6104 | serge | 645 | DP_TRAINING_PATTERN_SET, |
646 | DP_TRAINING_PATTERN_DISABLE); |
||
1963 | serge | 647 | |
648 | return 0; |
||
1403 | serge | 649 | } |
650 | |||
1963 | serge | 651 | static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info) |
1403 | serge | 652 | { |
1963 | serge | 653 | udelay(400); |
1403 | serge | 654 | |
1963 | serge | 655 | /* disable the training pattern on the sink */ |
5078 | serge | 656 | drm_dp_dpcd_writeb(dp_info->aux, |
6104 | serge | 657 | DP_TRAINING_PATTERN_SET, |
658 | DP_TRAINING_PATTERN_DISABLE); |
||
1403 | serge | 659 | |
1963 | serge | 660 | /* disable the training pattern on the source */ |
2160 | serge | 661 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
1963 | serge | 662 | atombios_dig_encoder_setup(dp_info->encoder, |
663 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); |
||
664 | else |
||
665 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, |
||
666 | dp_info->dp_clock, dp_info->enc_id, 0); |
||
1403 | serge | 667 | |
1963 | serge | 668 | return 0; |
669 | } |
||
1403 | serge | 670 | |
1963 | serge | 671 | static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) |
672 | { |
||
673 | bool clock_recovery; |
||
674 | u8 voltage; |
||
675 | int i; |
||
1403 | serge | 676 | |
1963 | serge | 677 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); |
678 | memset(dp_info->train_set, 0, 4); |
||
679 | radeon_dp_update_vs_emph(dp_info); |
||
1403 | serge | 680 | |
681 | udelay(400); |
||
682 | |||
683 | /* clock recovery loop */ |
||
684 | clock_recovery = false; |
||
1963 | serge | 685 | dp_info->tries = 0; |
1403 | serge | 686 | voltage = 0xff; |
1963 | serge | 687 | while (1) { |
3192 | Serge | 688 | drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); |
1963 | serge | 689 | |
5078 | serge | 690 | if (drm_dp_dpcd_read_link_status(dp_info->aux, |
691 | dp_info->link_status) <= 0) { |
||
2997 | Serge | 692 | DRM_ERROR("displayport link status failed\n"); |
1403 | serge | 693 | break; |
2997 | Serge | 694 | } |
1403 | serge | 695 | |
3192 | Serge | 696 | if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
1403 | serge | 697 | clock_recovery = true; |
698 | break; |
||
699 | } |
||
700 | |||
1963 | serge | 701 | for (i = 0; i < dp_info->dp_lane_count; i++) { |
702 | if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
||
1403 | serge | 703 | break; |
704 | } |
||
1963 | serge | 705 | if (i == dp_info->dp_lane_count) { |
1403 | serge | 706 | DRM_ERROR("clock recovery reached max voltage\n"); |
707 | break; |
||
708 | } |
||
709 | |||
1963 | serge | 710 | if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
711 | ++dp_info->tries; |
||
712 | if (dp_info->tries == 5) { |
||
1403 | serge | 713 | DRM_ERROR("clock recovery tried 5 times\n"); |
714 | break; |
||
715 | } |
||
716 | } else |
||
1963 | serge | 717 | dp_info->tries = 0; |
1403 | serge | 718 | |
1963 | serge | 719 | voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
1403 | serge | 720 | |
721 | /* Compute new train_set as requested by sink */ |
||
1963 | serge | 722 | dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); |
723 | |||
724 | radeon_dp_update_vs_emph(dp_info); |
||
1403 | serge | 725 | } |
1963 | serge | 726 | if (!clock_recovery) { |
1403 | serge | 727 | DRM_ERROR("clock recovery failed\n"); |
1963 | serge | 728 | return -1; |
729 | } else { |
||
730 | DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", |
||
731 | dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
||
732 | (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> |
||
1403 | serge | 733 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
1963 | serge | 734 | return 0; |
735 | } |
||
736 | } |
||
1403 | serge | 737 | |
1963 | serge | 738 | static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) |
739 | { |
||
740 | bool channel_eq; |
||
1403 | serge | 741 | |
1963 | serge | 742 | if (dp_info->tp3_supported) |
743 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); |
||
1430 | serge | 744 | else |
1963 | serge | 745 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); |
1403 | serge | 746 | |
747 | /* channel equalization loop */ |
||
1963 | serge | 748 | dp_info->tries = 0; |
1403 | serge | 749 | channel_eq = false; |
1963 | serge | 750 | while (1) { |
3192 | Serge | 751 | drm_dp_link_train_channel_eq_delay(dp_info->dpcd); |
1963 | serge | 752 | |
5078 | serge | 753 | if (drm_dp_dpcd_read_link_status(dp_info->aux, |
754 | dp_info->link_status) <= 0) { |
||
2997 | Serge | 755 | DRM_ERROR("displayport link status failed\n"); |
1403 | serge | 756 | break; |
2997 | Serge | 757 | } |
1403 | serge | 758 | |
3192 | Serge | 759 | if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
1403 | serge | 760 | channel_eq = true; |
761 | break; |
||
762 | } |
||
763 | |||
764 | /* Try 5 times */ |
||
1963 | serge | 765 | if (dp_info->tries > 5) { |
1403 | serge | 766 | DRM_ERROR("channel eq failed: 5 tries\n"); |
767 | break; |
||
768 | } |
||
769 | |||
770 | /* Compute new train_set as requested by sink */ |
||
1963 | serge | 771 | dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); |
1403 | serge | 772 | |
1963 | serge | 773 | radeon_dp_update_vs_emph(dp_info); |
774 | dp_info->tries++; |
||
1403 | serge | 775 | } |
776 | |||
1963 | serge | 777 | if (!channel_eq) { |
1403 | serge | 778 | DRM_ERROR("channel eq failed\n"); |
1963 | serge | 779 | return -1; |
780 | } else { |
||
781 | DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", |
||
782 | dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
||
783 | (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) |
||
1403 | serge | 784 | >> DP_TRAIN_PRE_EMPHASIS_SHIFT); |
1963 | serge | 785 | return 0; |
786 | } |
||
1403 | serge | 787 | } |
788 | |||
1963 | serge | 789 | void radeon_dp_link_train(struct drm_encoder *encoder, |
790 | struct drm_connector *connector) |
||
1403 | serge | 791 | { |
1963 | serge | 792 | struct drm_device *dev = encoder->dev; |
793 | struct radeon_device *rdev = dev->dev_private; |
||
794 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
795 | struct radeon_encoder_atom_dig *dig; |
||
796 | struct radeon_connector *radeon_connector; |
||
797 | struct radeon_connector_atom_dig *dig_connector; |
||
798 | struct radeon_dp_link_train_info dp_info; |
||
2160 | serge | 799 | int index; |
800 | u8 tmp, frev, crev; |
||
1403 | serge | 801 | |
1963 | serge | 802 | if (!radeon_encoder->enc_priv) |
803 | return; |
||
804 | dig = radeon_encoder->enc_priv; |
||
1403 | serge | 805 | |
1963 | serge | 806 | radeon_connector = to_radeon_connector(connector); |
807 | if (!radeon_connector->con_priv) |
||
808 | return; |
||
809 | dig_connector = radeon_connector->con_priv; |
||
1403 | serge | 810 | |
1963 | serge | 811 | if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && |
812 | (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) |
||
813 | return; |
||
1403 | serge | 814 | |
2160 | serge | 815 | /* DPEncoderService newer than 1.1 can't program properly the |
816 | * training pattern. When facing such version use the |
||
817 | * DIGXEncoderControl (X== 1 | 2) |
||
818 | */ |
||
819 | dp_info.use_dpencoder = true; |
||
820 | index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); |
||
821 | if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { |
||
822 | if (crev > 1) { |
||
823 | dp_info.use_dpencoder = false; |
||
824 | } |
||
825 | } |
||
826 | |||
1963 | serge | 827 | dp_info.enc_id = 0; |
828 | if (dig->dig_encoder) |
||
829 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; |
||
830 | else |
||
831 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; |
||
832 | if (dig->linkb) |
||
833 | dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B; |
||
834 | else |
||
835 | dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; |
||
1403 | serge | 836 | |
5078 | serge | 837 | if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp) |
838 | == 1) { |
||
6104 | serge | 839 | if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) |
840 | dp_info.tp3_supported = true; |
||
841 | else |
||
842 | dp_info.tp3_supported = false; |
||
5078 | serge | 843 | } else { |
844 | dp_info.tp3_supported = false; |
||
845 | } |
||
1403 | serge | 846 | |
3192 | Serge | 847 | memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); |
1963 | serge | 848 | dp_info.rdev = rdev; |
849 | dp_info.encoder = encoder; |
||
850 | dp_info.connector = connector; |
||
851 | dp_info.dp_lane_count = dig_connector->dp_lane_count; |
||
852 | dp_info.dp_clock = dig_connector->dp_clock; |
||
5078 | serge | 853 | dp_info.aux = &radeon_connector->ddc_bus->aux; |
1403 | serge | 854 | |
1963 | serge | 855 | if (radeon_dp_link_train_init(&dp_info)) |
856 | goto done; |
||
857 | if (radeon_dp_link_train_cr(&dp_info)) |
||
858 | goto done; |
||
859 | if (radeon_dp_link_train_ce(&dp_info)) |
||
860 | goto done; |
||
861 | done: |
||
862 | if (radeon_dp_link_train_finish(&dp_info)) |
||
863 | return; |
||
1403 | serge | 864 | }=>>=>=>>=><=>=>=>>=><=>=>>>><>><>><>><>><>>>> |