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Rev | Author | Line No. | Line |
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1403 | serge | 1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice shall be included in |
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13 | * all copies or substantial portions of the Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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21 | * OTHER DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: Dave Airlie |
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24 | * Alex Deucher |
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2997 | Serge | 25 | * Jerome Glisse |
1403 | serge | 26 | */ |
2997 | Serge | 27 | #include |
28 | #include |
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1403 | serge | 29 | #include "radeon.h" |
30 | |||
31 | #include "atom.h" |
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32 | #include "atom-bits.h" |
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2997 | Serge | 33 | #include |
1403 | serge | 34 | |
35 | /* move these to drm_dp_helper.c/h */ |
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36 | #define DP_LINK_CONFIGURATION_SIZE 9 |
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3192 | Serge | 37 | #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE |
1403 | serge | 38 | |
39 | static char *voltage_names[] = { |
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40 | "0.4V", "0.6V", "0.8V", "1.2V" |
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41 | }; |
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42 | static char *pre_emph_names[] = { |
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43 | "0dB", "3.5dB", "6dB", "9.5dB" |
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44 | }; |
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45 | |||
1963 | serge | 46 | /***** radeon AUX functions *****/ |
5078 | serge | 47 | |
48 | /* Atom needs data in little endian format |
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49 | * so swap as appropriate when copying data to |
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50 | * or from atom. Note that atom operates on |
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51 | * dw units. |
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52 | */ |
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53 | void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) |
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54 | { |
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55 | #ifdef __BIG_ENDIAN |
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56 | u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */ |
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57 | u32 *dst32, *src32; |
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58 | int i; |
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59 | |||
60 | memcpy(src_tmp, src, num_bytes); |
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61 | src32 = (u32 *)src_tmp; |
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62 | dst32 = (u32 *)dst_tmp; |
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63 | if (to_le) { |
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64 | for (i = 0; i < ((num_bytes + 3) / 4); i++) |
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65 | dst32[i] = cpu_to_le32(src32[i]); |
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66 | memcpy(dst, dst_tmp, num_bytes); |
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67 | } else { |
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68 | u8 dws = num_bytes & ~3; |
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69 | for (i = 0; i < ((num_bytes + 3) / 4); i++) |
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70 | dst32[i] = le32_to_cpu(src32[i]); |
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71 | memcpy(dst, dst_tmp, dws); |
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72 | if (num_bytes % 4) { |
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73 | for (i = 0; i < (num_bytes % 4); i++) |
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74 | dst[dws+i] = dst_tmp[dws+i]; |
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75 | } |
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76 | } |
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77 | #else |
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78 | memcpy(dst, src, num_bytes); |
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79 | #endif |
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80 | } |
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81 | |||
1963 | serge | 82 | union aux_channel_transaction { |
83 | PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; |
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84 | PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; |
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1403 | serge | 85 | }; |
86 | |||
1963 | serge | 87 | static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, |
88 | u8 *send, int send_bytes, |
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89 | u8 *recv, int recv_size, |
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90 | u8 delay, u8 *ack) |
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1403 | serge | 91 | { |
1963 | serge | 92 | struct drm_device *dev = chan->dev; |
93 | struct radeon_device *rdev = dev->dev_private; |
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94 | union aux_channel_transaction args; |
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95 | int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); |
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96 | unsigned char *base; |
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97 | int recv_bytes; |
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5078 | serge | 98 | int r = 0; |
1403 | serge | 99 | |
1963 | serge | 100 | memset(&args, 0, sizeof(args)); |
1403 | serge | 101 | |
5078 | serge | 102 | mutex_lock(&chan->mutex); |
103 | |||
2997 | Serge | 104 | base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); |
1403 | serge | 105 | |
5078 | serge | 106 | radeon_atom_copy_swap(base, send, send_bytes, true); |
1963 | serge | 107 | |
5078 | serge | 108 | args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4)); |
109 | args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4)); |
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1963 | serge | 110 | args.v1.ucDataOutLen = 0; |
111 | args.v1.ucChannelID = chan->rec.i2c_id; |
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112 | args.v1.ucDelay = delay / 10; |
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113 | if (ASIC_IS_DCE4(rdev)) |
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114 | args.v2.ucHPD_ID = chan->rec.hpd; |
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115 | |||
116 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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117 | |||
118 | *ack = args.v1.ucReplyStatus; |
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119 | |||
120 | /* timeout */ |
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121 | if (args.v1.ucReplyStatus == 1) { |
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122 | DRM_DEBUG_KMS("dp_aux_ch timeout\n"); |
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5078 | serge | 123 | r = -ETIMEDOUT; |
124 | goto done; |
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1403 | serge | 125 | } |
1963 | serge | 126 | |
127 | /* flags not zero */ |
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128 | if (args.v1.ucReplyStatus == 2) { |
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129 | DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); |
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5078 | serge | 130 | r = -EIO; |
131 | goto done; |
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1403 | serge | 132 | } |
1963 | serge | 133 | |
134 | /* error */ |
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135 | if (args.v1.ucReplyStatus == 3) { |
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136 | DRM_DEBUG_KMS("dp_aux_ch error\n"); |
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5078 | serge | 137 | r = -EIO; |
138 | goto done; |
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1403 | serge | 139 | } |
1963 | serge | 140 | |
141 | recv_bytes = args.v1.ucDataOutLen; |
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142 | if (recv_bytes > recv_size) |
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143 | recv_bytes = recv_size; |
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144 | |||
145 | if (recv && recv_size) |
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5078 | serge | 146 | radeon_atom_copy_swap(recv, base + 16, recv_bytes, false); |
1963 | serge | 147 | |
5078 | serge | 148 | r = recv_bytes; |
149 | done: |
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150 | mutex_unlock(&chan->mutex); |
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151 | |||
152 | return r; |
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1963 | serge | 153 | } |
154 | |||
5078 | serge | 155 | #define BARE_ADDRESS_SIZE 3 |
156 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) |
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157 | |||
158 | static ssize_t |
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159 | radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
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1963 | serge | 160 | { |
5078 | serge | 161 | struct radeon_i2c_chan *chan = |
162 | container_of(aux, struct radeon_i2c_chan, aux); |
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1963 | serge | 163 | int ret; |
5078 | serge | 164 | u8 tx_buf[20]; |
165 | size_t tx_size; |
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166 | u8 ack, delay = 0; |
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1963 | serge | 167 | |
5078 | serge | 168 | if (WARN_ON(msg->size > 16)) |
169 | return -E2BIG; |
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1963 | serge | 170 | |
5078 | serge | 171 | tx_buf[0] = msg->address & 0xff; |
172 | tx_buf[1] = msg->address >> 8; |
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173 | tx_buf[2] = msg->request << 4; |
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174 | tx_buf[3] = msg->size ? (msg->size - 1) : 0; |
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1963 | serge | 175 | |
5078 | serge | 176 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
177 | case DP_AUX_NATIVE_WRITE: |
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178 | case DP_AUX_I2C_WRITE: |
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179 | /* tx_size needs to be 4 even for bare address packets since the atom |
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180 | * table needs the info in tx_buf[3]. |
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181 | */ |
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182 | tx_size = HEADER_SIZE + msg->size; |
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183 | if (msg->size == 0) |
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184 | tx_buf[3] |= BARE_ADDRESS_SIZE << 4; |
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1963 | serge | 185 | else |
5078 | serge | 186 | tx_buf[3] |= tx_size << 4; |
187 | memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size); |
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188 | ret = radeon_process_aux_ch(chan, |
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189 | tx_buf, tx_size, NULL, 0, delay, &ack); |
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190 | if (ret >= 0) |
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191 | /* Return payload size. */ |
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192 | ret = msg->size; |
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193 | break; |
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194 | case DP_AUX_NATIVE_READ: |
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195 | case DP_AUX_I2C_READ: |
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196 | /* tx_size needs to be 4 even for bare address packets since the atom |
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197 | * table needs the info in tx_buf[3]. |
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198 | */ |
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199 | tx_size = HEADER_SIZE; |
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200 | if (msg->size == 0) |
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201 | tx_buf[3] |= BARE_ADDRESS_SIZE << 4; |
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202 | else |
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203 | tx_buf[3] |= tx_size << 4; |
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204 | ret = radeon_process_aux_ch(chan, |
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205 | tx_buf, tx_size, msg->buffer, msg->size, delay, &ack); |
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206 | break; |
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207 | default: |
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208 | ret = -EINVAL; |
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209 | break; |
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1403 | serge | 210 | } |
1963 | serge | 211 | |
5078 | serge | 212 | if (ret >= 0) |
213 | msg->reply = ack >> 4; |
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1963 | serge | 214 | |
215 | return ret; |
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216 | } |
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1403 | serge | 217 | |
5078 | serge | 218 | void radeon_dp_aux_init(struct radeon_connector *radeon_connector) |
1963 | serge | 219 | { |
220 | int ret; |
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221 | |||
5078 | serge | 222 | radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd; |
223 | radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev; |
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224 | radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer; |
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1963 | serge | 225 | |
5078 | serge | 226 | ret = drm_dp_aux_register(&radeon_connector->ddc_bus->aux); |
227 | if (!ret) |
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228 | radeon_connector->ddc_bus->has_aux = true; |
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1963 | serge | 229 | |
5078 | serge | 230 | WARN(ret, "drm_dp_aux_register() failed with error %d\n", ret); |
1403 | serge | 231 | } |
232 | |||
1963 | serge | 233 | /***** general DP utility functions *****/ |
1403 | serge | 234 | |
235 | #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 |
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1963 | serge | 236 | #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5 |
1403 | serge | 237 | |
238 | static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], |
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239 | int lane_count, |
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240 | u8 train_set[4]) |
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241 | { |
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242 | u8 v = 0; |
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243 | u8 p = 0; |
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244 | int lane; |
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245 | |||
246 | for (lane = 0; lane < lane_count; lane++) { |
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3192 | Serge | 247 | u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
248 | u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); |
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1403 | serge | 249 | |
1963 | serge | 250 | DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", |
1403 | serge | 251 | lane, |
252 | voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
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253 | pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); |
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254 | |||
255 | if (this_v > v) |
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256 | v = this_v; |
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257 | if (this_p > p) |
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258 | p = this_p; |
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259 | } |
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260 | |||
261 | if (v >= DP_VOLTAGE_MAX) |
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1963 | serge | 262 | v |= DP_TRAIN_MAX_SWING_REACHED; |
1403 | serge | 263 | |
1963 | serge | 264 | if (p >= DP_PRE_EMPHASIS_MAX) |
265 | p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
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1403 | serge | 266 | |
1963 | serge | 267 | DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", |
1403 | serge | 268 | voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
269 | pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); |
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270 | |||
271 | for (lane = 0; lane < 4; lane++) |
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272 | train_set[lane] = v | p; |
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273 | } |
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274 | |||
1963 | serge | 275 | /* convert bits per color to bits per pixel */ |
276 | /* get bpc from the EDID */ |
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277 | static int convert_bpc_to_bpp(int bpc) |
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278 | { |
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279 | if (bpc == 0) |
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280 | return 24; |
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281 | else |
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282 | return bpc * 3; |
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283 | } |
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1403 | serge | 284 | |
1963 | serge | 285 | /* get the max pix clock supported by the link rate and lane num */ |
286 | static int dp_get_max_dp_pix_clock(int link_rate, |
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287 | int lane_num, |
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288 | int bpp) |
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1403 | serge | 289 | { |
1963 | serge | 290 | return (link_rate * lane_num * 8) / bpp; |
291 | } |
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1403 | serge | 292 | |
1963 | serge | 293 | /***** radeon specific DP functions *****/ |
1403 | serge | 294 | |
5078 | serge | 295 | static int radeon_dp_get_max_link_rate(struct drm_connector *connector, |
296 | u8 dpcd[DP_DPCD_SIZE]) |
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297 | { |
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298 | int max_link_rate; |
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299 | |||
300 | if (radeon_connector_is_dp12_capable(connector)) |
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301 | max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000); |
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302 | else |
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303 | max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000); |
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304 | |||
305 | return max_link_rate; |
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306 | } |
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307 | |||
1963 | serge | 308 | /* First get the min lane# when low rate is used according to pixel clock |
309 | * (prefer low rate), second check max lane# supported by DP panel, |
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310 | * if the max lane# < low rate lane# then use max lane# instead. |
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311 | */ |
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312 | static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, |
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313 | u8 dpcd[DP_DPCD_SIZE], |
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314 | int pix_clock) |
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315 | { |
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2997 | Serge | 316 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
5078 | serge | 317 | int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd); |
3192 | Serge | 318 | int max_lane_num = drm_dp_max_lane_count(dpcd); |
1963 | serge | 319 | int lane_num; |
320 | int max_dp_pix_clock; |
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1403 | serge | 321 | |
1963 | serge | 322 | for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) { |
323 | max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp); |
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324 | if (pix_clock <= max_dp_pix_clock) |
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325 | break; |
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1403 | serge | 326 | } |
327 | |||
1963 | serge | 328 | return lane_num; |
1403 | serge | 329 | } |
330 | |||
1963 | serge | 331 | static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, |
332 | u8 dpcd[DP_DPCD_SIZE], |
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333 | int pix_clock) |
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1403 | serge | 334 | { |
2997 | Serge | 335 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
1963 | serge | 336 | int lane_num, max_pix_clock; |
1403 | serge | 337 | |
2997 | Serge | 338 | if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == |
339 | ENCODER_OBJECT_ID_NUTMEG) |
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1963 | serge | 340 | return 270000; |
1403 | serge | 341 | |
1963 | serge | 342 | lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock); |
343 | max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp); |
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344 | if (pix_clock <= max_pix_clock) |
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345 | return 162000; |
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346 | max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp); |
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347 | if (pix_clock <= max_pix_clock) |
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348 | return 270000; |
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349 | if (radeon_connector_is_dp12_capable(connector)) { |
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350 | max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp); |
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351 | if (pix_clock <= max_pix_clock) |
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352 | return 540000; |
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353 | } |
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1403 | serge | 354 | |
5078 | serge | 355 | return radeon_dp_get_max_link_rate(connector, dpcd); |
1403 | serge | 356 | } |
357 | |||
1963 | serge | 358 | static u8 radeon_dp_encoder_service(struct radeon_device *rdev, |
359 | int action, int dp_clock, |
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360 | u8 ucconfig, u8 lane_num) |
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1403 | serge | 361 | { |
362 | DP_ENCODER_SERVICE_PARAMETERS args; |
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363 | int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); |
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364 | |||
365 | memset(&args, 0, sizeof(args)); |
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366 | args.ucLinkClock = dp_clock / 10; |
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367 | args.ucConfig = ucconfig; |
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368 | args.ucAction = action; |
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369 | args.ucLaneNum = lane_num; |
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370 | args.ucStatus = 0; |
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371 | |||
372 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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373 | return args.ucStatus; |
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374 | } |
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375 | |||
376 | u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) |
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377 | { |
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378 | struct drm_device *dev = radeon_connector->base.dev; |
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379 | struct radeon_device *rdev = dev->dev_private; |
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380 | |||
381 | return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, |
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5078 | serge | 382 | radeon_connector->ddc_bus->rec.i2c_id, 0); |
1403 | serge | 383 | } |
384 | |||
2997 | Serge | 385 | static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) |
386 | { |
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387 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
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388 | u8 buf[3]; |
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389 | |||
390 | if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
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391 | return; |
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392 | |||
5078 | serge | 393 | if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3) |
2997 | Serge | 394 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
395 | buf[0], buf[1], buf[2]); |
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396 | |||
5078 | serge | 397 | if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3) |
2997 | Serge | 398 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
399 | buf[0], buf[1], buf[2]); |
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400 | } |
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401 | |||
1403 | serge | 402 | bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) |
403 | { |
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404 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
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3192 | Serge | 405 | u8 msg[DP_DPCD_SIZE]; |
5078 | serge | 406 | int ret; |
1403 | serge | 407 | |
5078 | serge | 408 | char dpcd_hex_dump[DP_DPCD_SIZE * 3]; |
409 | |||
410 | ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg, |
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411 | DP_DPCD_SIZE); |
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1963 | serge | 412 | if (ret > 0) { |
3192 | Serge | 413 | memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); |
2997 | Serge | 414 | |
5078 | serge | 415 | hex_dump_to_buffer(dig_connector->dpcd, sizeof(dig_connector->dpcd), |
416 | 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); |
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417 | DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); |
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418 | |||
2997 | Serge | 419 | radeon_dp_probe_oui(radeon_connector); |
3764 | Serge | 420 | |
1403 | serge | 421 | return true; |
422 | } |
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423 | dig_connector->dpcd[0] = 0; |
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424 | return false; |
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425 | } |
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426 | |||
2997 | Serge | 427 | int radeon_dp_get_panel_mode(struct drm_encoder *encoder, |
1963 | serge | 428 | struct drm_connector *connector) |
429 | { |
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430 | struct drm_device *dev = encoder->dev; |
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431 | struct radeon_device *rdev = dev->dev_private; |
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2997 | Serge | 432 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
5078 | serge | 433 | struct radeon_connector_atom_dig *dig_connector; |
1963 | serge | 434 | int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
2997 | Serge | 435 | u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); |
436 | u8 tmp; |
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1963 | serge | 437 | |
438 | if (!ASIC_IS_DCE4(rdev)) |
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2997 | Serge | 439 | return panel_mode; |
1963 | serge | 440 | |
5078 | serge | 441 | if (!radeon_connector->con_priv) |
442 | return panel_mode; |
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443 | |||
444 | dig_connector = radeon_connector->con_priv; |
||
445 | |||
2997 | Serge | 446 | if (dp_bridge != ENCODER_OBJECT_ID_NONE) { |
447 | /* DP bridge chips */ |
||
5078 | serge | 448 | if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, |
449 | DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { |
||
2997 | Serge | 450 | if (tmp & 1) |
451 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; |
||
452 | else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || |
||
453 | (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) |
||
1963 | serge | 454 | panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; |
2997 | Serge | 455 | else |
456 | panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
||
5078 | serge | 457 | } |
2997 | Serge | 458 | } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
459 | /* eDP */ |
||
5078 | serge | 460 | if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, |
461 | DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { |
||
2997 | Serge | 462 | if (tmp & 1) |
463 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; |
||
464 | } |
||
5078 | serge | 465 | } |
1963 | serge | 466 | |
2997 | Serge | 467 | return panel_mode; |
1963 | serge | 468 | } |
469 | |||
1403 | serge | 470 | void radeon_dp_set_link_config(struct drm_connector *connector, |
2997 | Serge | 471 | const struct drm_display_mode *mode) |
1403 | serge | 472 | { |
1963 | serge | 473 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1403 | serge | 474 | struct radeon_connector_atom_dig *dig_connector; |
475 | |||
476 | if (!radeon_connector->con_priv) |
||
477 | return; |
||
478 | dig_connector = radeon_connector->con_priv; |
||
479 | |||
1963 | serge | 480 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
481 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { |
||
1403 | serge | 482 | dig_connector->dp_clock = |
1963 | serge | 483 | radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); |
1403 | serge | 484 | dig_connector->dp_lane_count = |
1963 | serge | 485 | radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock); |
486 | } |
||
1403 | serge | 487 | } |
488 | |||
1963 | serge | 489 | int radeon_dp_mode_valid_helper(struct drm_connector *connector, |
1403 | serge | 490 | struct drm_display_mode *mode) |
491 | { |
||
1963 | serge | 492 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
493 | struct radeon_connector_atom_dig *dig_connector; |
||
494 | int dp_clock; |
||
1403 | serge | 495 | |
1963 | serge | 496 | if (!radeon_connector->con_priv) |
497 | return MODE_CLOCK_HIGH; |
||
498 | dig_connector = radeon_connector->con_priv; |
||
499 | |||
500 | dp_clock = |
||
501 | radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); |
||
502 | |||
503 | if ((dp_clock == 540000) && |
||
504 | (!radeon_connector_is_dp12_capable(connector))) |
||
505 | return MODE_CLOCK_HIGH; |
||
506 | |||
507 | return MODE_OK; |
||
1403 | serge | 508 | } |
509 | |||
2997 | Serge | 510 | bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) |
511 | { |
||
512 | u8 link_status[DP_LINK_STATUS_SIZE]; |
||
513 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; |
||
514 | |||
5078 | serge | 515 | if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status) |
516 | <= 0) |
||
2997 | Serge | 517 | return false; |
3192 | Serge | 518 | if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) |
2997 | Serge | 519 | return false; |
520 | return true; |
||
521 | } |
||
522 | |||
5078 | serge | 523 | void radeon_dp_set_rx_power_state(struct drm_connector *connector, |
524 | u8 power_state) |
||
525 | { |
||
526 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
||
527 | struct radeon_connector_atom_dig *dig_connector; |
||
528 | |||
529 | if (!radeon_connector->con_priv) |
||
530 | return; |
||
531 | |||
532 | dig_connector = radeon_connector->con_priv; |
||
533 | |||
534 | /* power up/down the sink */ |
||
535 | if (dig_connector->dpcd[0] >= 0x11) { |
||
536 | drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux, |
||
537 | DP_SET_POWER, power_state); |
||
538 | usleep_range(1000, 2000); |
||
539 | } |
||
540 | } |
||
541 | |||
542 | |||
1963 | serge | 543 | struct radeon_dp_link_train_info { |
544 | struct radeon_device *rdev; |
||
545 | struct drm_encoder *encoder; |
||
546 | struct drm_connector *connector; |
||
547 | int enc_id; |
||
548 | int dp_clock; |
||
549 | int dp_lane_count; |
||
550 | bool tp3_supported; |
||
3192 | Serge | 551 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
1963 | serge | 552 | u8 train_set[4]; |
1403 | serge | 553 | u8 link_status[DP_LINK_STATUS_SIZE]; |
1963 | serge | 554 | u8 tries; |
2160 | serge | 555 | bool use_dpencoder; |
5078 | serge | 556 | struct drm_dp_aux *aux; |
1963 | serge | 557 | }; |
1403 | serge | 558 | |
1963 | serge | 559 | static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) |
560 | { |
||
561 | /* set the initial vs/emph on the source */ |
||
562 | atombios_dig_transmitter_setup(dp_info->encoder, |
||
563 | ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, |
||
564 | 0, dp_info->train_set[0]); /* sets all lanes at once */ |
||
565 | |||
566 | /* set the vs/emph on the sink */ |
||
5078 | serge | 567 | drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET, |
568 | dp_info->train_set, dp_info->dp_lane_count); |
||
1403 | serge | 569 | } |
570 | |||
1963 | serge | 571 | static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) |
1403 | serge | 572 | { |
1963 | serge | 573 | int rtp = 0; |
1403 | serge | 574 | |
1963 | serge | 575 | /* set training pattern on the source */ |
2160 | serge | 576 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { |
1963 | serge | 577 | switch (tp) { |
578 | case DP_TRAINING_PATTERN_1: |
||
579 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; |
||
580 | break; |
||
581 | case DP_TRAINING_PATTERN_2: |
||
582 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; |
||
583 | break; |
||
584 | case DP_TRAINING_PATTERN_3: |
||
585 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; |
||
586 | break; |
||
587 | } |
||
588 | atombios_dig_encoder_setup(dp_info->encoder, rtp, 0); |
||
589 | } else { |
||
590 | switch (tp) { |
||
591 | case DP_TRAINING_PATTERN_1: |
||
592 | rtp = 0; |
||
593 | break; |
||
594 | case DP_TRAINING_PATTERN_2: |
||
595 | rtp = 1; |
||
596 | break; |
||
597 | } |
||
598 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, |
||
599 | dp_info->dp_clock, dp_info->enc_id, rtp); |
||
1403 | serge | 600 | } |
601 | |||
1963 | serge | 602 | /* enable training pattern on the sink */ |
5078 | serge | 603 | drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp); |
1403 | serge | 604 | } |
605 | |||
1963 | serge | 606 | static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) |
1403 | serge | 607 | { |
2997 | Serge | 608 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); |
609 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
||
1963 | serge | 610 | u8 tmp; |
1403 | serge | 611 | |
1963 | serge | 612 | /* power up the sink */ |
5078 | serge | 613 | radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0); |
1403 | serge | 614 | |
1963 | serge | 615 | /* possibly enable downspread on the sink */ |
616 | if (dp_info->dpcd[3] & 0x1) |
||
5078 | serge | 617 | drm_dp_dpcd_writeb(dp_info->aux, |
1963 | serge | 618 | DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); |
619 | else |
||
5078 | serge | 620 | drm_dp_dpcd_writeb(dp_info->aux, |
1963 | serge | 621 | DP_DOWNSPREAD_CTRL, 0); |
1403 | serge | 622 | |
2997 | Serge | 623 | if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) && |
624 | (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) { |
||
5078 | serge | 625 | drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1); |
2997 | Serge | 626 | } |
1403 | serge | 627 | |
1963 | serge | 628 | /* set the lane count on the sink */ |
629 | tmp = dp_info->dp_lane_count; |
||
5078 | serge | 630 | if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) |
1963 | serge | 631 | tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
5078 | serge | 632 | drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp); |
1963 | serge | 633 | |
634 | /* set the link rate on the sink */ |
||
3192 | Serge | 635 | tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); |
5078 | serge | 636 | drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp); |
1963 | serge | 637 | |
638 | /* start training on the source */ |
||
2160 | serge | 639 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
1963 | serge | 640 | atombios_dig_encoder_setup(dp_info->encoder, |
641 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); |
||
642 | else |
||
643 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, |
||
644 | dp_info->dp_clock, dp_info->enc_id, 0); |
||
645 | |||
646 | /* disable the training pattern on the sink */ |
||
5078 | serge | 647 | drm_dp_dpcd_writeb(dp_info->aux, |
1963 | serge | 648 | DP_TRAINING_PATTERN_SET, |
649 | DP_TRAINING_PATTERN_DISABLE); |
||
650 | |||
651 | return 0; |
||
1403 | serge | 652 | } |
653 | |||
1963 | serge | 654 | static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info) |
1403 | serge | 655 | { |
1963 | serge | 656 | udelay(400); |
1403 | serge | 657 | |
1963 | serge | 658 | /* disable the training pattern on the sink */ |
5078 | serge | 659 | drm_dp_dpcd_writeb(dp_info->aux, |
1963 | serge | 660 | DP_TRAINING_PATTERN_SET, |
661 | DP_TRAINING_PATTERN_DISABLE); |
||
1403 | serge | 662 | |
1963 | serge | 663 | /* disable the training pattern on the source */ |
2160 | serge | 664 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
1963 | serge | 665 | atombios_dig_encoder_setup(dp_info->encoder, |
666 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); |
||
667 | else |
||
668 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, |
||
669 | dp_info->dp_clock, dp_info->enc_id, 0); |
||
1403 | serge | 670 | |
1963 | serge | 671 | return 0; |
672 | } |
||
1403 | serge | 673 | |
1963 | serge | 674 | static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) |
675 | { |
||
676 | bool clock_recovery; |
||
677 | u8 voltage; |
||
678 | int i; |
||
1403 | serge | 679 | |
1963 | serge | 680 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); |
681 | memset(dp_info->train_set, 0, 4); |
||
682 | radeon_dp_update_vs_emph(dp_info); |
||
1403 | serge | 683 | |
684 | udelay(400); |
||
685 | |||
686 | /* clock recovery loop */ |
||
687 | clock_recovery = false; |
||
1963 | serge | 688 | dp_info->tries = 0; |
1403 | serge | 689 | voltage = 0xff; |
1963 | serge | 690 | while (1) { |
3192 | Serge | 691 | drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); |
1963 | serge | 692 | |
5078 | serge | 693 | if (drm_dp_dpcd_read_link_status(dp_info->aux, |
694 | dp_info->link_status) <= 0) { |
||
2997 | Serge | 695 | DRM_ERROR("displayport link status failed\n"); |
1403 | serge | 696 | break; |
2997 | Serge | 697 | } |
1403 | serge | 698 | |
3192 | Serge | 699 | if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
1403 | serge | 700 | clock_recovery = true; |
701 | break; |
||
702 | } |
||
703 | |||
1963 | serge | 704 | for (i = 0; i < dp_info->dp_lane_count; i++) { |
705 | if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
||
1403 | serge | 706 | break; |
707 | } |
||
1963 | serge | 708 | if (i == dp_info->dp_lane_count) { |
1403 | serge | 709 | DRM_ERROR("clock recovery reached max voltage\n"); |
710 | break; |
||
711 | } |
||
712 | |||
1963 | serge | 713 | if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
714 | ++dp_info->tries; |
||
715 | if (dp_info->tries == 5) { |
||
1403 | serge | 716 | DRM_ERROR("clock recovery tried 5 times\n"); |
717 | break; |
||
718 | } |
||
719 | } else |
||
1963 | serge | 720 | dp_info->tries = 0; |
1403 | serge | 721 | |
1963 | serge | 722 | voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
1403 | serge | 723 | |
724 | /* Compute new train_set as requested by sink */ |
||
1963 | serge | 725 | dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); |
726 | |||
727 | radeon_dp_update_vs_emph(dp_info); |
||
1403 | serge | 728 | } |
1963 | serge | 729 | if (!clock_recovery) { |
1403 | serge | 730 | DRM_ERROR("clock recovery failed\n"); |
1963 | serge | 731 | return -1; |
732 | } else { |
||
733 | DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", |
||
734 | dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
||
735 | (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> |
||
1403 | serge | 736 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
1963 | serge | 737 | return 0; |
738 | } |
||
739 | } |
||
1403 | serge | 740 | |
1963 | serge | 741 | static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) |
742 | { |
||
743 | bool channel_eq; |
||
1403 | serge | 744 | |
1963 | serge | 745 | if (dp_info->tp3_supported) |
746 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); |
||
1430 | serge | 747 | else |
1963 | serge | 748 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); |
1403 | serge | 749 | |
750 | /* channel equalization loop */ |
||
1963 | serge | 751 | dp_info->tries = 0; |
1403 | serge | 752 | channel_eq = false; |
1963 | serge | 753 | while (1) { |
3192 | Serge | 754 | drm_dp_link_train_channel_eq_delay(dp_info->dpcd); |
1963 | serge | 755 | |
5078 | serge | 756 | if (drm_dp_dpcd_read_link_status(dp_info->aux, |
757 | dp_info->link_status) <= 0) { |
||
2997 | Serge | 758 | DRM_ERROR("displayport link status failed\n"); |
1403 | serge | 759 | break; |
2997 | Serge | 760 | } |
1403 | serge | 761 | |
3192 | Serge | 762 | if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
1403 | serge | 763 | channel_eq = true; |
764 | break; |
||
765 | } |
||
766 | |||
767 | /* Try 5 times */ |
||
1963 | serge | 768 | if (dp_info->tries > 5) { |
1403 | serge | 769 | DRM_ERROR("channel eq failed: 5 tries\n"); |
770 | break; |
||
771 | } |
||
772 | |||
773 | /* Compute new train_set as requested by sink */ |
||
1963 | serge | 774 | dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); |
1403 | serge | 775 | |
1963 | serge | 776 | radeon_dp_update_vs_emph(dp_info); |
777 | dp_info->tries++; |
||
1403 | serge | 778 | } |
779 | |||
1963 | serge | 780 | if (!channel_eq) { |
1403 | serge | 781 | DRM_ERROR("channel eq failed\n"); |
1963 | serge | 782 | return -1; |
783 | } else { |
||
784 | DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", |
||
785 | dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
||
786 | (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) |
||
1403 | serge | 787 | >> DP_TRAIN_PRE_EMPHASIS_SHIFT); |
1963 | serge | 788 | return 0; |
789 | } |
||
1403 | serge | 790 | } |
791 | |||
1963 | serge | 792 | void radeon_dp_link_train(struct drm_encoder *encoder, |
793 | struct drm_connector *connector) |
||
1403 | serge | 794 | { |
1963 | serge | 795 | struct drm_device *dev = encoder->dev; |
796 | struct radeon_device *rdev = dev->dev_private; |
||
797 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
798 | struct radeon_encoder_atom_dig *dig; |
||
799 | struct radeon_connector *radeon_connector; |
||
800 | struct radeon_connector_atom_dig *dig_connector; |
||
801 | struct radeon_dp_link_train_info dp_info; |
||
2160 | serge | 802 | int index; |
803 | u8 tmp, frev, crev; |
||
1403 | serge | 804 | |
1963 | serge | 805 | if (!radeon_encoder->enc_priv) |
806 | return; |
||
807 | dig = radeon_encoder->enc_priv; |
||
1403 | serge | 808 | |
1963 | serge | 809 | radeon_connector = to_radeon_connector(connector); |
810 | if (!radeon_connector->con_priv) |
||
811 | return; |
||
812 | dig_connector = radeon_connector->con_priv; |
||
1403 | serge | 813 | |
1963 | serge | 814 | if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && |
815 | (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) |
||
816 | return; |
||
1403 | serge | 817 | |
2160 | serge | 818 | /* DPEncoderService newer than 1.1 can't program properly the |
819 | * training pattern. When facing such version use the |
||
820 | * DIGXEncoderControl (X== 1 | 2) |
||
821 | */ |
||
822 | dp_info.use_dpencoder = true; |
||
823 | index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); |
||
824 | if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { |
||
825 | if (crev > 1) { |
||
826 | dp_info.use_dpencoder = false; |
||
827 | } |
||
828 | } |
||
829 | |||
1963 | serge | 830 | dp_info.enc_id = 0; |
831 | if (dig->dig_encoder) |
||
832 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; |
||
833 | else |
||
834 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; |
||
835 | if (dig->linkb) |
||
836 | dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B; |
||
837 | else |
||
838 | dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; |
||
1403 | serge | 839 | |
5078 | serge | 840 | if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp) |
841 | == 1) { |
||
1963 | serge | 842 | if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) |
843 | dp_info.tp3_supported = true; |
||
844 | else |
||
845 | dp_info.tp3_supported = false; |
||
5078 | serge | 846 | } else { |
847 | dp_info.tp3_supported = false; |
||
848 | } |
||
1403 | serge | 849 | |
3192 | Serge | 850 | memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); |
1963 | serge | 851 | dp_info.rdev = rdev; |
852 | dp_info.encoder = encoder; |
||
853 | dp_info.connector = connector; |
||
854 | dp_info.dp_lane_count = dig_connector->dp_lane_count; |
||
855 | dp_info.dp_clock = dig_connector->dp_clock; |
||
5078 | serge | 856 | dp_info.aux = &radeon_connector->ddc_bus->aux; |
1403 | serge | 857 | |
1963 | serge | 858 | if (radeon_dp_link_train_init(&dp_info)) |
859 | goto done; |
||
860 | if (radeon_dp_link_train_cr(&dp_info)) |
||
861 | goto done; |
||
862 | if (radeon_dp_link_train_ce(&dp_info)) |
||
863 | goto done; |
||
864 | done: |
||
865 | if (radeon_dp_link_train_finish(&dp_info)) |
||
866 | return; |
||
1403 | serge | 867 | }=>>=>=>=>=>=>=>=><=>>>>>><>><>><>><>><>>>> |