WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/atombios_crtc.c

Rev	Author	Line No.	Line
1123	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
1179	serge	26	#include
		27	#include
6938	serge	28	#include
1179	serge	29	#include
1963	serge	30	#include
1123	serge	31	#include "radeon.h"
		32	#include "atom.h"
		33	#include "atom-bits.h"
		34
1179	serge	35	static void atombios_overscan_setup(struct drm_crtc *crtc,
		36	struct drm_display_mode *mode,
		37	struct drm_display_mode *adjusted_mode)
		38	{
		39	struct drm_device *dev = crtc->dev;
		40	struct radeon_device *rdev = dev->dev_private;
		41	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		42	SET_CRTC_OVERSCAN_PS_ALLOCATION args;
		43	int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
		44	int a1, a2;
		45
		46	memset(&args, 0, sizeof(args));
		47
		48	args.ucCRTC = radeon_crtc->crtc_id;
		49
		50	switch (radeon_crtc->rmx_type) {
		51	case RMX_CENTER:
1963	serge	52	args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
		53	args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
		54	args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
		55	args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
1179	serge	56	break;
		57	case RMX_ASPECT:
		58	a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
		59	a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
		60
		61	if (a1 > a2) {
1963	serge	62	args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
		63	args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
1179	serge	64	} else if (a2 > a1) {
1963	serge	65	args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
		66	args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
1179	serge	67	}
		68	break;
		69	case RMX_FULL:
		70	default:
1963	serge	71	args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
		72	args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
		73	args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
		74	args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
1179	serge	75	break;
		76	}
1963	serge	77	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1179	serge	78	}
		79
		80	static void atombios_scaler_setup(struct drm_crtc *crtc)
		81	{
		82	struct drm_device *dev = crtc->dev;
		83	struct radeon_device *rdev = dev->dev_private;
		84	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		85	ENABLE_SCALER_PS_ALLOCATION args;
		86	int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
2997	Serge	87	struct radeon_encoder *radeon_encoder =
		88	to_radeon_encoder(radeon_crtc->encoder);
1179	serge	89	/* fixme - fill in enc_priv for atom dac */
		90	enum radeon_tv_std tv_std = TV_STD_NTSC;
		91	bool is_tv = false, is_cv = false;
		92
		93	if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
		94	return;
		95
3031	serge	96	if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
		97	struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
		98	tv_std = tv_dac->tv_std;
		99	is_tv = true;
		100	}
1179	serge	101
		102	memset(&args, 0, sizeof(args));
		103
		104	args.ucScaler = radeon_crtc->crtc_id;
		105
		106	if (is_tv) {
		107	switch (tv_std) {
		108	case TV_STD_NTSC:
		109	default:
		110	args.ucTVStandard = ATOM_TV_NTSC;
		111	break;
		112	case TV_STD_PAL:
		113	args.ucTVStandard = ATOM_TV_PAL;
		114	break;
		115	case TV_STD_PAL_M:
		116	args.ucTVStandard = ATOM_TV_PALM;
		117	break;
		118	case TV_STD_PAL_60:
		119	args.ucTVStandard = ATOM_TV_PAL60;
		120	break;
		121	case TV_STD_NTSC_J:
		122	args.ucTVStandard = ATOM_TV_NTSCJ;
		123	break;
		124	case TV_STD_SCART_PAL:
		125	args.ucTVStandard = ATOM_TV_PAL; /* ??? */
		126	break;
		127	case TV_STD_SECAM:
		128	args.ucTVStandard = ATOM_TV_SECAM;
		129	break;
		130	case TV_STD_PAL_CN:
		131	args.ucTVStandard = ATOM_TV_PALCN;
		132	break;
		133	}
		134	args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
		135	} else if (is_cv) {
		136	args.ucTVStandard = ATOM_TV_CV;
		137	args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
		138	} else {
		139	switch (radeon_crtc->rmx_type) {
		140	case RMX_FULL:
		141	args.ucEnable = ATOM_SCALER_EXPANSION;
		142	break;
		143	case RMX_CENTER:
		144	args.ucEnable = ATOM_SCALER_CENTER;
		145	break;
		146	case RMX_ASPECT:
		147	args.ucEnable = ATOM_SCALER_EXPANSION;
		148	break;
		149	default:
		150	if (ASIC_IS_AVIVO(rdev))
		151	args.ucEnable = ATOM_SCALER_DISABLE;
		152	else
		153	args.ucEnable = ATOM_SCALER_CENTER;
		154	break;
		155	}
		156	}
		157	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		158	if ((is_tv \|\| is_cv)
		159	&& rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
		160	atom_rv515_force_tv_scaler(rdev, radeon_crtc);
		161	}
		162	}
		163
1123	serge	164	static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
		165	{
		166	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		167	struct drm_device *dev = crtc->dev;
		168	struct radeon_device *rdev = dev->dev_private;
		169	int index =
		170	GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
		171	ENABLE_CRTC_PS_ALLOCATION args;
		172
		173	memset(&args, 0, sizeof(args));
		174
		175	args.ucCRTC = radeon_crtc->crtc_id;
		176	args.ucEnable = lock;
		177
		178	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		179	}
		180
		181	static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
		182	{
		183	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		184	struct drm_device *dev = crtc->dev;
		185	struct radeon_device *rdev = dev->dev_private;
		186	int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
		187	ENABLE_CRTC_PS_ALLOCATION args;
		188
		189	memset(&args, 0, sizeof(args));
		190
		191	args.ucCRTC = radeon_crtc->crtc_id;
		192	args.ucEnable = state;
		193
		194	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		195	}
		196
		197	static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
		198	{
		199	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		200	struct drm_device *dev = crtc->dev;
		201	struct radeon_device *rdev = dev->dev_private;
		202	int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
		203	ENABLE_CRTC_PS_ALLOCATION args;
		204
		205	memset(&args, 0, sizeof(args));
		206
		207	args.ucCRTC = radeon_crtc->crtc_id;
		208	args.ucEnable = state;
		209
		210	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		211	}
		212
5078	serge	213	static const u32 vga_control_regs[6] =
		214	{
		215	AVIVO_D1VGA_CONTROL,
		216	AVIVO_D2VGA_CONTROL,
		217	EVERGREEN_D3VGA_CONTROL,
		218	EVERGREEN_D4VGA_CONTROL,
		219	EVERGREEN_D5VGA_CONTROL,
		220	EVERGREEN_D6VGA_CONTROL,
		221	};
		222
1123	serge	223	static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
		224	{
		225	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		226	struct drm_device *dev = crtc->dev;
		227	struct radeon_device *rdev = dev->dev_private;
		228	int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
		229	BLANK_CRTC_PS_ALLOCATION args;
5078	serge	230	u32 vga_control = 0;
1123	serge	231
		232	memset(&args, 0, sizeof(args));
		233
5078	serge	234	if (ASIC_IS_DCE8(rdev)) {
		235	vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
		236	WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control \| 1);
		237	}
		238
1123	serge	239	args.ucCRTC = radeon_crtc->crtc_id;
		240	args.ucBlanking = state;
		241
		242	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
5078	serge	243
		244	if (ASIC_IS_DCE8(rdev)) {
		245	WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
		246	}
1123	serge	247	}
		248
2997	Serge	249	static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
		250	{
		251	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		252	struct drm_device *dev = crtc->dev;
		253	struct radeon_device *rdev = dev->dev_private;
		254	int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
		255	ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
		256
		257	memset(&args, 0, sizeof(args));
		258
		259	args.ucDispPipeId = radeon_crtc->crtc_id;
		260	args.ucEnable = state;
		261
		262	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		263	}
		264
1123	serge	265	void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
		266	{
		267	struct drm_device *dev = crtc->dev;
		268	struct radeon_device *rdev = dev->dev_private;
1321	serge	269	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1123	serge	270
		271	switch (mode) {
		272	case DRM_MODE_DPMS_ON:
1963	serge	273	radeon_crtc->enabled = true;
1430	serge	274	atombios_enable_crtc(crtc, ATOM_ENABLE);
2997	Serge	275	if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
1430	serge	276	atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
		277	atombios_blank_crtc(crtc, ATOM_DISABLE);
3031	serge	278	drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
1321	serge	279	radeon_crtc_load_lut(crtc);
1123	serge	280	break;
		281	case DRM_MODE_DPMS_STANDBY:
		282	case DRM_MODE_DPMS_SUSPEND:
		283	case DRM_MODE_DPMS_OFF:
3031	serge	284	drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
1963	serge	285	if (radeon_crtc->enabled)
3031	serge	286	atombios_blank_crtc(crtc, ATOM_ENABLE);
2997	Serge	287	if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
1430	serge	288	atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
		289	atombios_enable_crtc(crtc, ATOM_DISABLE);
1963	serge	290	radeon_crtc->enabled = false;
1123	serge	291	break;
		292	}
5078	serge	293	/* adjust pm to dpms */
		294	radeon_pm_compute_clocks(rdev);
1123	serge	295	}
		296
		297	static void
		298	atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
1268	serge	299	struct drm_display_mode *mode)
1123	serge	300	{
1268	serge	301	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1123	serge	302	struct drm_device *dev = crtc->dev;
		303	struct radeon_device *rdev = dev->dev_private;
1268	serge	304	SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
1123	serge	305	int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
1268	serge	306	u16 misc = 0;
1123	serge	307
1268	serge	308	memset(&args, 0, sizeof(args));
1963	serge	309	args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
1268	serge	310	args.usH_Blanking_Time =
1963	serge	311	cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
		312	args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
1268	serge	313	args.usV_Blanking_Time =
1963	serge	314	cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
1268	serge	315	args.usH_SyncOffset =
1963	serge	316	cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
1268	serge	317	args.usH_SyncWidth =
		318	cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
		319	args.usV_SyncOffset =
1963	serge	320	cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
1268	serge	321	args.usV_SyncWidth =
		322	cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
1963	serge	323	args.ucH_Border = radeon_crtc->h_border;
		324	args.ucV_Border = radeon_crtc->v_border;
1123	serge	325
1268	serge	326	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
		327	misc \|= ATOM_VSYNC_POLARITY;
		328	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
		329	misc \|= ATOM_HSYNC_POLARITY;
		330	if (mode->flags & DRM_MODE_FLAG_CSYNC)
		331	misc \|= ATOM_COMPOSITESYNC;
		332	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		333	misc \|= ATOM_INTERLACE;
6104	serge	334	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		335	misc \|= ATOM_DOUBLE_CLOCK_MODE;
1268	serge	336	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
6104	serge	337	misc \|= ATOM_H_REPLICATIONBY2 \| ATOM_V_REPLICATIONBY2;
1268	serge	338
		339	args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
		340	args.ucCRTC = radeon_crtc->crtc_id;
		341
		342	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1123	serge	343	}
		344
1268	serge	345	static void atombios_crtc_set_timing(struct drm_crtc *crtc,
		346	struct drm_display_mode *mode)
1123	serge	347	{
1268	serge	348	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1123	serge	349	struct drm_device *dev = crtc->dev;
		350	struct radeon_device *rdev = dev->dev_private;
1268	serge	351	SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
1123	serge	352	int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
1268	serge	353	u16 misc = 0;
1123	serge	354
1268	serge	355	memset(&args, 0, sizeof(args));
		356	args.usH_Total = cpu_to_le16(mode->crtc_htotal);
		357	args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
		358	args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
		359	args.usH_SyncWidth =
		360	cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
		361	args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
		362	args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
		363	args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
		364	args.usV_SyncWidth =
		365	cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
1123	serge	366
1963	serge	367	args.ucOverscanRight = radeon_crtc->h_border;
		368	args.ucOverscanLeft = radeon_crtc->h_border;
		369	args.ucOverscanBottom = radeon_crtc->v_border;
		370	args.ucOverscanTop = radeon_crtc->v_border;
		371
1268	serge	372	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
		373	misc \|= ATOM_VSYNC_POLARITY;
		374	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
		375	misc \|= ATOM_HSYNC_POLARITY;
		376	if (mode->flags & DRM_MODE_FLAG_CSYNC)
		377	misc \|= ATOM_COMPOSITESYNC;
		378	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		379	misc \|= ATOM_INTERLACE;
6104	serge	380	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		381	misc \|= ATOM_DOUBLE_CLOCK_MODE;
1268	serge	382	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
6104	serge	383	misc \|= ATOM_H_REPLICATIONBY2 \| ATOM_V_REPLICATIONBY2;
1268	serge	384
		385	args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
		386	args.ucCRTC = radeon_crtc->crtc_id;
		387
		388	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1123	serge	389	}
		390
2997	Serge	391	static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
1963	serge	392	{
		393	u32 ss_cntl;
		394
		395	if (ASIC_IS_DCE4(rdev)) {
2997	Serge	396	switch (pll_id) {
1963	serge	397	case ATOM_PPLL1:
		398	ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
		399	ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
		400	WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
		401	break;
		402	case ATOM_PPLL2:
		403	ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
		404	ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
		405	WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
		406	break;
		407	case ATOM_DCPLL:
		408	case ATOM_PPLL_INVALID:
		409	return;
		410	}
		411	} else if (ASIC_IS_AVIVO(rdev)) {
2997	Serge	412	switch (pll_id) {
1963	serge	413	case ATOM_PPLL1:
		414	ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
		415	ss_cntl &= ~1;
		416	WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
		417	break;
		418	case ATOM_PPLL2:
		419	ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
		420	ss_cntl &= ~1;
		421	WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
		422	break;
		423	case ATOM_DCPLL:
		424	case ATOM_PPLL_INVALID:
		425	return;
		426	}
		427	}
		428	}
		429
		430
1430	serge	431	union atom_enable_ss {
1963	serge	432	ENABLE_LVDS_SS_PARAMETERS lvds_ss;
		433	ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
1430	serge	434	ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
1963	serge	435	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
		436	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
1430	serge	437	};
		438
2997	Serge	439	static void atombios_crtc_program_ss(struct radeon_device *rdev,
1963	serge	440	int enable,
		441	int pll_id,
2997	Serge	442	int crtc_id,
1963	serge	443	struct radeon_atom_ss *ss)
1268	serge	444	{
2997	Serge	445	unsigned i;
1268	serge	446	int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
1430	serge	447	union atom_enable_ss args;
1268	serge	448
5078	serge	449	if (enable) {
		450	/* Don't mess with SS if percentage is 0 or external ss.
		451	* SS is already disabled previously, and disabling it
		452	* again can cause display problems if the pll is already
		453	* programmed.
		454	*/
		455	if (ss->percentage == 0)
		456	return;
		457	if (ss->type & ATOM_EXTERNAL_SS_MASK)
		458	return;
		459	} else {
2997	Serge	460	for (i = 0; i < rdev->num_crtc; i++) {
		461	if (rdev->mode_info.crtcs[i] &&
		462	rdev->mode_info.crtcs[i]->enabled &&
		463	i != crtc_id &&
		464	pll_id == rdev->mode_info.crtcs[i]->pll_id) {
		465	/* one other crtc is using this pll don't turn
		466	* off spread spectrum as it might turn off
		467	* display on active crtc
		468	*/
		469	return;
		470	}
		471	}
		472	}
		473
1963	serge	474	memset(&args, 0, sizeof(args));
1430	serge	475
1963	serge	476	if (ASIC_IS_DCE5(rdev)) {
		477	args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
		478	args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
		479	switch (pll_id) {
		480	case ATOM_PPLL1:
		481	args.v3.ucSpreadSpectrumType \|= ATOM_PPLL_SS_TYPE_V3_P1PLL;
		482	break;
		483	case ATOM_PPLL2:
		484	args.v3.ucSpreadSpectrumType \|= ATOM_PPLL_SS_TYPE_V3_P2PLL;
		485	break;
		486	case ATOM_DCPLL:
		487	args.v3.ucSpreadSpectrumType \|= ATOM_PPLL_SS_TYPE_V3_DCPLL;
		488	break;
		489	case ATOM_PPLL_INVALID:
		490	return;
		491	}
2997	Serge	492	args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
		493	args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
1963	serge	494	args.v3.ucEnable = enable;
		495	} else if (ASIC_IS_DCE4(rdev)) {
		496	args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
		497	args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
		498	switch (pll_id) {
		499	case ATOM_PPLL1:
		500	args.v2.ucSpreadSpectrumType \|= ATOM_PPLL_SS_TYPE_V2_P1PLL;
		501	break;
		502	case ATOM_PPLL2:
		503	args.v2.ucSpreadSpectrumType \|= ATOM_PPLL_SS_TYPE_V2_P2PLL;
		504	break;
		505	case ATOM_DCPLL:
		506	args.v2.ucSpreadSpectrumType \|= ATOM_PPLL_SS_TYPE_V2_DCPLL;
		507	break;
		508	case ATOM_PPLL_INVALID:
3031	serge	509	return;
1963	serge	510	}
2997	Serge	511	args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
		512	args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
1963	serge	513	args.v2.ucEnable = enable;
		514	} else if (ASIC_IS_DCE3(rdev)) {
		515	args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
		516	args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
		517	args.v1.ucSpreadSpectrumStep = ss->step;
		518	args.v1.ucSpreadSpectrumDelay = ss->delay;
		519	args.v1.ucSpreadSpectrumRange = ss->range;
		520	args.v1.ucPpll = pll_id;
		521	args.v1.ucEnable = enable;
		522	} else if (ASIC_IS_AVIVO(rdev)) {
		523	if ((enable == ATOM_DISABLE) \|\| (ss->percentage == 0) \|\|
		524	(ss->type & ATOM_EXTERNAL_SS_MASK)) {
2997	Serge	525	atombios_disable_ss(rdev, pll_id);
3031	serge	526	return;
1268	serge	527	}
1963	serge	528	args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
		529	args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
		530	args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
		531	args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
		532	args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
		533	args.lvds_ss_2.ucEnable = enable;
1268	serge	534	} else {
5078	serge	535	if (enable == ATOM_DISABLE) {
2997	Serge	536	atombios_disable_ss(rdev, pll_id);
1963	serge	537	return;
3031	serge	538	}
1963	serge	539	args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
		540	args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
		541	args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
		542	args.lvds_ss.ucSpreadSpectrumStepSize_Delay \|= (ss->delay & 7) << 4;
		543	args.lvds_ss.ucEnable = enable;
		544	}
1430	serge	545	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1268	serge	546	}
		547
1404	serge	548	union adjust_pixel_clock {
		549	ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
1430	serge	550	ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
1404	serge	551	};
		552
		553	static u32 atombios_adjust_pll(struct drm_crtc *crtc,
2997	Serge	554	struct drm_display_mode *mode)
1123	serge	555	{
2997	Serge	556	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1123	serge	557	struct drm_device *dev = crtc->dev;
		558	struct radeon_device *rdev = dev->dev_private;
2997	Serge	559	struct drm_encoder *encoder = radeon_crtc->encoder;
		560	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		561	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1404	serge	562	u32 adjusted_clock = mode->clock;
2997	Serge	563	int encoder_mode = atombios_get_encoder_mode(encoder);
1963	serge	564	u32 dp_clock = mode->clock;
5078	serge	565	u32 clock = mode->clock;
		566	int bpc = radeon_crtc->bpc;
2997	Serge	567	bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
1123	serge	568
1404	serge	569	/* reset the pll flags */
2997	Serge	570	radeon_crtc->pll_flags = 0;
1123	serge	571
		572	if (ASIC_IS_AVIVO(rdev)) {
1179	serge	573	if ((rdev->family == CHIP_RS600) \|\|
		574	(rdev->family == CHIP_RS690) \|\|
		575	(rdev->family == CHIP_RS740))
2997	Serge	576	radeon_crtc->pll_flags \|= (/RADEON_PLL_USE_FRAC_FB_DIV \|/
3031	serge	577	RADEON_PLL_PREFER_CLOSEST_LOWER);
1179	serge	578
1123	serge	579	if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
2997	Serge	580	radeon_crtc->pll_flags \|= RADEON_PLL_PREFER_HIGH_FB_DIV;
1123	serge	581	else
2997	Serge	582	radeon_crtc->pll_flags \|= RADEON_PLL_PREFER_LOW_REF_DIV;
1963	serge	583
		584	if (rdev->family < CHIP_RV770)
2997	Serge	585	radeon_crtc->pll_flags \|= RADEON_PLL_PREFER_MINM_OVER_MAXP;
		586	/* use frac fb div on APUs */
5078	serge	587	if (ASIC_IS_DCE41(rdev) \|\| ASIC_IS_DCE61(rdev) \|\| ASIC_IS_DCE8(rdev))
2997	Serge	588	radeon_crtc->pll_flags \|= RADEON_PLL_USE_FRAC_FB_DIV;
3764	Serge	589	/* use frac fb div on RS780/RS880 */
		590	if ((rdev->family == CHIP_RS780) \|\| (rdev->family == CHIP_RS880))
		591	radeon_crtc->pll_flags \|= RADEON_PLL_USE_FRAC_FB_DIV;
3192	Serge	592	if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
		593	radeon_crtc->pll_flags \|= RADEON_PLL_USE_FRAC_FB_DIV;
1123	serge	594	} else {
2997	Serge	595	radeon_crtc->pll_flags \|= RADEON_PLL_LEGACY;
1123	serge	596
		597	if (mode->clock > 200000) /* range limits??? */
2997	Serge	598	radeon_crtc->pll_flags \|= RADEON_PLL_PREFER_HIGH_FB_DIV;
1123	serge	599	else
2997	Serge	600	radeon_crtc->pll_flags \|= RADEON_PLL_PREFER_LOW_REF_DIV;
1123	serge	601	}
		602
3031	serge	603	if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT \| ATOM_DEVICE_DFP_SUPPORT)) \|\|
		604	(radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
		605	if (connector) {
		606	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		607	struct radeon_connector_atom_dig *dig_connector =
		608	radeon_connector->con_priv;
1963	serge	609
3031	serge	610	dp_clock = dig_connector->dp_clock;
		611	}
		612	}
1963	serge	613
6104	serge	614	if (radeon_encoder->is_mst_encoder) {
		615	struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv;
		616	struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv;
		617
		618	dp_clock = dig_connector->dp_clock;
		619	}
		620
3031	serge	621	/* use recommended ref_div for ss */
		622	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2997	Serge	623	if (radeon_crtc->ss_enabled) {
		624	if (radeon_crtc->ss.refdiv) {
		625	radeon_crtc->pll_flags \|= RADEON_PLL_USE_REF_DIV;
		626	radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
3031	serge	627	if (ASIC_IS_AVIVO(rdev))
2997	Serge	628	radeon_crtc->pll_flags \|= RADEON_PLL_USE_FRAC_FB_DIV;
1963	serge	629	}
3031	serge	630	}
		631	}
1963	serge	632
3031	serge	633	if (ASIC_IS_AVIVO(rdev)) {
		634	/* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
		635	if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
		636	adjusted_clock = mode->clock * 2;
		637	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
2997	Serge	638	radeon_crtc->pll_flags \|= RADEON_PLL_PREFER_CLOSEST_LOWER;
3031	serge	639	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2997	Serge	640	radeon_crtc->pll_flags \|= RADEON_PLL_IS_LCD;
3031	serge	641	} else {
		642	if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
2997	Serge	643	radeon_crtc->pll_flags \|= RADEON_PLL_NO_ODD_POST_DIV;
3031	serge	644	if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
2997	Serge	645	radeon_crtc->pll_flags \|= RADEON_PLL_USE_REF_DIV;
1123	serge	646	}
		647
5078	serge	648	/* adjust pll for deep color modes */
		649	if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
		650	switch (bpc) {
		651	case 8:
		652	default:
		653	break;
		654	case 10:
		655	clock = (clock * 5) / 4;
		656	break;
		657	case 12:
		658	clock = (clock * 3) / 2;
		659	break;
		660	case 16:
		661	clock = clock * 2;
		662	break;
		663	}
		664	}
		665
1268	serge	666	/* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
		667	* accordingly based on the encoder/transmitter to work around
		668	* special hw requirements.
		669	*/
		670	if (ASIC_IS_DCE3(rdev)) {
1404	serge	671	union adjust_pixel_clock args;
		672	u8 frev, crev;
		673	int index;
1268	serge	674
1404	serge	675	index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
1963	serge	676	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
		677	&crev))
		678	return adjusted_clock;
1268	serge	679
1404	serge	680	memset(&args, 0, sizeof(args));
		681
		682	switch (frev) {
		683	case 1:
		684	switch (crev) {
		685	case 1:
		686	case 2:
5078	serge	687	args.v1.usPixelClock = cpu_to_le16(clock / 10);
1404	serge	688	args.v1.ucTransmitterID = radeon_encoder->encoder_id;
1430	serge	689	args.v1.ucEncodeMode = encoder_mode;
2997	Serge	690	if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
3031	serge	691	args.v1.ucConfig \|=
		692	ADJUST_DISPLAY_CONFIG_SS_ENABLE;
1404	serge	693
3031	serge	694	atom_execute_table(rdev->mode_info.atom_context,
1404	serge	695	index, (uint32_t *)&args);
		696	adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
		697	break;
1430	serge	698	case 3:
5078	serge	699	args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
1430	serge	700	args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
		701	args.v3.sInput.ucEncodeMode = encoder_mode;
		702	args.v3.sInput.ucDispPllConfig = 0;
2997	Serge	703	if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
1963	serge	704	args.v3.sInput.ucDispPllConfig \|=
		705	DISPPLL_CONFIG_SS_ENABLE;
2997	Serge	706	if (ENCODER_MODE_IS_DP(encoder_mode)) {
3031	serge	707	args.v3.sInput.ucDispPllConfig \|=
		708	DISPPLL_CONFIG_COHERENT_MODE;
		709	/* 16200 or 27000 */
		710	args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
2997	Serge	711	} else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
		712	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3031	serge	713	if (dig->coherent_mode)
		714	args.v3.sInput.ucDispPllConfig \|=
		715	DISPPLL_CONFIG_COHERENT_MODE;
2997	Serge	716	if (is_duallink)
3031	serge	717	args.v3.sInput.ucDispPllConfig \|=
		718	DISPPLL_CONFIG_DUAL_LINK;
		719	}
2997	Serge	720	if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
		721	ENCODER_OBJECT_ID_NONE)
		722	args.v3.sInput.ucExtTransmitterID =
		723	radeon_encoder_get_dp_bridge_encoder_id(encoder);
		724	else
1986	serge	725	args.v3.sInput.ucExtTransmitterID = 0;
		726
1430	serge	727	atom_execute_table(rdev->mode_info.atom_context,
		728	index, (uint32_t *)&args);
		729	adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
		730	if (args.v3.sOutput.ucRefDiv) {
2997	Serge	731	radeon_crtc->pll_flags \|= RADEON_PLL_USE_FRAC_FB_DIV;
		732	radeon_crtc->pll_flags \|= RADEON_PLL_USE_REF_DIV;
		733	radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
1430	serge	734	}
		735	if (args.v3.sOutput.ucPostDiv) {
2997	Serge	736	radeon_crtc->pll_flags \|= RADEON_PLL_USE_FRAC_FB_DIV;
		737	radeon_crtc->pll_flags \|= RADEON_PLL_USE_POST_DIV;
		738	radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
1430	serge	739	}
		740	break;
1404	serge	741	default:
		742	DRM_ERROR("Unknown table version %d %d\n", frev, crev);
		743	return adjusted_clock;
		744	}
		745	break;
		746	default:
		747	DRM_ERROR("Unknown table version %d %d\n", frev, crev);
		748	return adjusted_clock;
		749	}
1268	serge	750	}
1404	serge	751	return adjusted_clock;
		752	}
1268	serge	753
1404	serge	754	union set_pixel_clock {
		755	SET_PIXEL_CLOCK_PS_ALLOCATION base;
		756	PIXEL_CLOCK_PARAMETERS v1;
		757	PIXEL_CLOCK_PARAMETERS_V2 v2;
		758	PIXEL_CLOCK_PARAMETERS_V3 v3;
1430	serge	759	PIXEL_CLOCK_PARAMETERS_V5 v5;
1963	serge	760	PIXEL_CLOCK_PARAMETERS_V6 v6;
1404	serge	761	};
		762
1963	serge	763	/* on DCE5, make sure the voltage is high enough to support the
		764	* required disp clk.
		765	*/
2997	Serge	766	static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
1963	serge	767	u32 dispclk)
1404	serge	768	{
1430	serge	769	u8 frev, crev;
		770	int index;
		771	union set_pixel_clock args;
		772
		773	memset(&args, 0, sizeof(args));
		774
		775	index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
1963	serge	776	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
		777	&crev))
		778	return;
1430	serge	779
		780	switch (frev) {
		781	case 1:
		782	switch (crev) {
		783	case 5:
		784	/* if the default dcpll clock is specified,
		785	* SetPixelClock provides the dividers
		786	*/
		787	args.v5.ucCRTC = ATOM_CRTC_INVALID;
1963	serge	788	args.v5.usPixelClock = cpu_to_le16(dispclk);
1430	serge	789	args.v5.ucPpll = ATOM_DCPLL;
		790	break;
1963	serge	791	case 6:
		792	/* if the default dcpll clock is specified,
		793	* SetPixelClock provides the dividers
		794	*/
		795	args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
5078	serge	796	if (ASIC_IS_DCE61(rdev) \|\| ASIC_IS_DCE8(rdev))
2997	Serge	797	args.v6.ucPpll = ATOM_EXT_PLL1;
		798	else if (ASIC_IS_DCE6(rdev))
		799	args.v6.ucPpll = ATOM_PPLL0;
		800	else
3031	serge	801	args.v6.ucPpll = ATOM_DCPLL;
1963	serge	802	break;
1430	serge	803	default:
		804	DRM_ERROR("Unknown table version %d %d\n", frev, crev);
		805	return;
		806	}
		807	break;
		808	default:
		809	DRM_ERROR("Unknown table version %d %d\n", frev, crev);
		810	return;
		811	}
		812	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		813	}
		814
1963	serge	815	static void atombios_crtc_program_pll(struct drm_crtc *crtc,
2160	serge	816	u32 crtc_id,
1963	serge	817	int pll_id,
		818	u32 encoder_mode,
		819	u32 encoder_id,
		820	u32 clock,
		821	u32 ref_div,
		822	u32 fb_div,
		823	u32 frac_fb_div,
		824	u32 post_div,
		825	int bpc,
		826	bool ss_enabled,
		827	struct radeon_atom_ss *ss)
1430	serge	828	{
1404	serge	829	struct drm_device *dev = crtc->dev;
		830	struct radeon_device *rdev = dev->dev_private;
		831	u8 frev, crev;
1963	serge	832	int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
1404	serge	833	union set_pixel_clock args;
		834
		835	memset(&args, 0, sizeof(args));
		836
1963	serge	837	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
		838	&crev))
1404	serge	839	return;
		840
1123	serge	841	switch (frev) {
		842	case 1:
		843	switch (crev) {
		844	case 1:
1963	serge	845	if (clock == ATOM_DISABLE)
		846	return;
		847	args.v1.usPixelClock = cpu_to_le16(clock / 10);
1404	serge	848	args.v1.usRefDiv = cpu_to_le16(ref_div);
		849	args.v1.usFbDiv = cpu_to_le16(fb_div);
		850	args.v1.ucFracFbDiv = frac_fb_div;
		851	args.v1.ucPostDiv = post_div;
1963	serge	852	args.v1.ucPpll = pll_id;
		853	args.v1.ucCRTC = crtc_id;
1404	serge	854	args.v1.ucRefDivSrc = 1;
1123	serge	855	break;
		856	case 2:
1963	serge	857	args.v2.usPixelClock = cpu_to_le16(clock / 10);
1404	serge	858	args.v2.usRefDiv = cpu_to_le16(ref_div);
		859	args.v2.usFbDiv = cpu_to_le16(fb_div);
		860	args.v2.ucFracFbDiv = frac_fb_div;
		861	args.v2.ucPostDiv = post_div;
1963	serge	862	args.v2.ucPpll = pll_id;
		863	args.v2.ucCRTC = crtc_id;
1404	serge	864	args.v2.ucRefDivSrc = 1;
1123	serge	865	break;
		866	case 3:
1963	serge	867	args.v3.usPixelClock = cpu_to_le16(clock / 10);
1404	serge	868	args.v3.usRefDiv = cpu_to_le16(ref_div);
		869	args.v3.usFbDiv = cpu_to_le16(fb_div);
		870	args.v3.ucFracFbDiv = frac_fb_div;
		871	args.v3.ucPostDiv = post_div;
1963	serge	872	args.v3.ucPpll = pll_id;
2997	Serge	873	if (crtc_id == ATOM_CRTC2)
		874	args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
		875	else
		876	args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
1963	serge	877	if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
		878	args.v3.ucMiscInfo \|= PIXEL_CLOCK_MISC_REF_DIV_SRC;
		879	args.v3.ucTransmitterId = encoder_id;
1430	serge	880	args.v3.ucEncoderMode = encoder_mode;
1123	serge	881	break;
1430	serge	882	case 5:
1963	serge	883	args.v5.ucCRTC = crtc_id;
		884	args.v5.usPixelClock = cpu_to_le16(clock / 10);
1430	serge	885	args.v5.ucRefDiv = ref_div;
		886	args.v5.usFbDiv = cpu_to_le16(fb_div);
		887	args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
		888	args.v5.ucPostDiv = post_div;
		889	args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
1963	serge	890	if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
		891	args.v5.ucMiscInfo \|= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
5078	serge	892	if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
6104	serge	893	switch (bpc) {
		894	case 8:
		895	default:
		896	args.v5.ucMiscInfo \|= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
		897	break;
		898	case 10:
5078	serge	899	/* yes this is correct, the atom define is wrong */
		900	args.v5.ucMiscInfo \|= PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
		901	break;
		902	case 12:
		903	/* yes this is correct, the atom define is wrong */
6104	serge	904	args.v5.ucMiscInfo \|= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
		905	break;
		906	}
1963	serge	907	}
		908	args.v5.ucTransmitterID = encoder_id;
1430	serge	909	args.v5.ucEncoderMode = encoder_mode;
1963	serge	910	args.v5.ucPpll = pll_id;
1430	serge	911	break;
1963	serge	912	case 6:
2160	serge	913	args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 \| clock / 10);
1963	serge	914	args.v6.ucRefDiv = ref_div;
		915	args.v6.usFbDiv = cpu_to_le16(fb_div);
		916	args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
		917	args.v6.ucPostDiv = post_div;
		918	args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
		919	if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
		920	args.v6.ucMiscInfo \|= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
5078	serge	921	if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
6104	serge	922	switch (bpc) {
		923	case 8:
		924	default:
		925	args.v6.ucMiscInfo \|= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
		926	break;
		927	case 10:
5078	serge	928	args.v6.ucMiscInfo \|= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6;
6104	serge	929	break;
		930	case 12:
5078	serge	931	args.v6.ucMiscInfo \|= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6;
6104	serge	932	break;
		933	case 16:
		934	args.v6.ucMiscInfo \|= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
		935	break;
		936	}
1963	serge	937	}
		938	args.v6.ucTransmitterID = encoder_id;
		939	args.v6.ucEncoderMode = encoder_mode;
		940	args.v6.ucPpll = pll_id;
		941	break;
1123	serge	942	default:
		943	DRM_ERROR("Unknown table version %d %d\n", frev, crev);
		944	return;
		945	}
		946	break;
		947	default:
		948	DRM_ERROR("Unknown table version %d %d\n", frev, crev);
		949	return;
		950	}
		951
		952	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		953	}
		954
2997	Serge	955	static bool atombios_crtc_prepare_pll(struct drm_crtc crtc, struct drm_display_mode mode)
1430	serge	956	{
		957	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		958	struct drm_device *dev = crtc->dev;
		959	struct radeon_device *rdev = dev->dev_private;
2997	Serge	960	struct radeon_encoder *radeon_encoder =
		961	to_radeon_encoder(radeon_crtc->encoder);
		962	int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
1963	serge	963
2997	Serge	964	radeon_crtc->bpc = 8;
		965	radeon_crtc->ss_enabled = false;
1963	serge	966
6104	serge	967	if (radeon_encoder->is_mst_encoder) {
		968	radeon_dp_mst_prepare_pll(crtc, mode);
		969	} else if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT \| ATOM_DEVICE_DFP_SUPPORT)) \|\|
2997	Serge	970	(radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
1963	serge	971	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
		972	struct drm_connector *connector =
2997	Serge	973	radeon_get_connector_for_encoder(radeon_crtc->encoder);
1963	serge	974	struct radeon_connector *radeon_connector =
		975	to_radeon_connector(connector);
		976	struct radeon_connector_atom_dig *dig_connector =
		977	radeon_connector->con_priv;
		978	int dp_clock;
5078	serge	979
		980	/* Assign mode clock for hdmi deep color max clock limit check */
		981	radeon_connector->pixelclock_for_modeset = mode->clock;
2997	Serge	982	radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
1963	serge	983
		984	switch (encoder_mode) {
2997	Serge	985	case ATOM_ENCODER_MODE_DP_MST:
1963	serge	986	case ATOM_ENCODER_MODE_DP:
		987	/* DP/eDP */
		988	dp_clock = dig_connector->dp_clock / 10;
3031	serge	989	if (ASIC_IS_DCE4(rdev))
2997	Serge	990	radeon_crtc->ss_enabled =
		991	radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
3031	serge	992	ASIC_INTERNAL_SS_ON_DP,
		993	dp_clock);
		994	else {
		995	if (dp_clock == 16200) {
2997	Serge	996	radeon_crtc->ss_enabled =
		997	radeon_atombios_get_ppll_ss_info(rdev,
		998	&radeon_crtc->ss,
3031	serge	999	ATOM_DP_SS_ID2);
2997	Serge	1000	if (!radeon_crtc->ss_enabled)
		1001	radeon_crtc->ss_enabled =
		1002	radeon_atombios_get_ppll_ss_info(rdev,
		1003	&radeon_crtc->ss,
3031	serge	1004	ATOM_DP_SS_ID1);
5078	serge	1005	} else {
2997	Serge	1006	radeon_crtc->ss_enabled =
		1007	radeon_atombios_get_ppll_ss_info(rdev,
		1008	&radeon_crtc->ss,
3031	serge	1009	ATOM_DP_SS_ID1);
6104	serge	1010	}
5078	serge	1011	/* disable spread spectrum on DCE3 DP */
		1012	radeon_crtc->ss_enabled = false;
		1013	}
1963	serge	1014	break;
		1015	case ATOM_ENCODER_MODE_LVDS:
		1016	if (ASIC_IS_DCE4(rdev))
2997	Serge	1017	radeon_crtc->ss_enabled =
		1018	radeon_atombios_get_asic_ss_info(rdev,
		1019	&radeon_crtc->ss,
3031	serge	1020	dig->lcd_ss_id,
		1021	mode->clock / 10);
1963	serge	1022	else
2997	Serge	1023	radeon_crtc->ss_enabled =
		1024	radeon_atombios_get_ppll_ss_info(rdev,
		1025	&radeon_crtc->ss,
3031	serge	1026	dig->lcd_ss_id);
1963	serge	1027	break;
		1028	case ATOM_ENCODER_MODE_DVI:
		1029	if (ASIC_IS_DCE4(rdev))
2997	Serge	1030	radeon_crtc->ss_enabled =
		1031	radeon_atombios_get_asic_ss_info(rdev,
		1032	&radeon_crtc->ss,
1963	serge	1033	ASIC_INTERNAL_SS_ON_TMDS,
		1034	mode->clock / 10);
		1035	break;
		1036	case ATOM_ENCODER_MODE_HDMI:
		1037	if (ASIC_IS_DCE4(rdev))
2997	Serge	1038	radeon_crtc->ss_enabled =
		1039	radeon_atombios_get_asic_ss_info(rdev,
		1040	&radeon_crtc->ss,
1963	serge	1041	ASIC_INTERNAL_SS_ON_HDMI,
		1042	mode->clock / 10);
		1043	break;
		1044	default:
		1045	break;
		1046	}
		1047	}
		1048
		1049	/* adjust pixel clock as needed */
2997	Serge	1050	radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
1963	serge	1051
2997	Serge	1052	return true;
		1053	}
		1054
		1055	static void atombios_crtc_set_pll(struct drm_crtc crtc, struct drm_display_mode mode)
		1056	{
		1057	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		1058	struct drm_device *dev = crtc->dev;
		1059	struct radeon_device *rdev = dev->dev_private;
		1060	struct radeon_encoder *radeon_encoder =
		1061	to_radeon_encoder(radeon_crtc->encoder);
		1062	u32 pll_clock = mode->clock;
5078	serge	1063	u32 clock = mode->clock;
2997	Serge	1064	u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
		1065	struct radeon_pll *pll;
		1066	int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
		1067
5078	serge	1068	/* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */
		1069	if (ASIC_IS_DCE5(rdev) &&
		1070	(encoder_mode == ATOM_ENCODER_MODE_HDMI) &&
		1071	(radeon_crtc->bpc > 8))
		1072	clock = radeon_crtc->adjusted_clock;
		1073
2997	Serge	1074	switch (radeon_crtc->pll_id) {
		1075	case ATOM_PPLL1:
		1076	pll = &rdev->clock.p1pll;
		1077	break;
		1078	case ATOM_PPLL2:
		1079	pll = &rdev->clock.p2pll;
		1080	break;
		1081	case ATOM_DCPLL:
		1082	case ATOM_PPLL_INVALID:
		1083	default:
		1084	pll = &rdev->clock.dcpll;
		1085	break;
		1086	}
		1087
		1088	/* update pll params */
		1089	pll->flags = radeon_crtc->pll_flags;
		1090	pll->reference_div = radeon_crtc->pll_reference_div;
		1091	pll->post_div = radeon_crtc->pll_post_div;
		1092
1963	serge	1093	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
		1094	/* TV seems to prefer the legacy algo on some boards */
2997	Serge	1095	radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
		1096	&fb_div, &frac_fb_div, &ref_div, &post_div);
1963	serge	1097	else if (ASIC_IS_AVIVO(rdev))
2997	Serge	1098	radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
		1099	&fb_div, &frac_fb_div, &ref_div, &post_div);
1963	serge	1100	else
2997	Serge	1101	radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
		1102	&fb_div, &frac_fb_div, &ref_div, &post_div);
1963	serge	1103
2997	Serge	1104	atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
		1105	radeon_crtc->crtc_id, &radeon_crtc->ss);
1963	serge	1106
		1107	atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
5078	serge	1108	encoder_mode, radeon_encoder->encoder_id, clock,
2997	Serge	1109	ref_div, fb_div, frac_fb_div, post_div,
		1110	radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
1963	serge	1111
2997	Serge	1112	if (radeon_crtc->ss_enabled) {
1963	serge	1113	/* calculate ss amount and step size */
		1114	if (ASIC_IS_DCE4(rdev)) {
		1115	u32 step_size;
5078	serge	1116	u32 amount = (((fb_div * 10) + frac_fb_div) *
		1117	(u32)radeon_crtc->ss.percentage) /
		1118	(100 * (u32)radeon_crtc->ss.percentage_divider);
2997	Serge	1119	radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
		1120	radeon_crtc->ss.amount \|= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1963	serge	1121	ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
2997	Serge	1122	if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
5078	serge	1123	step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1963	serge	1124	(125 * 25 * pll->reference_freq / 100);
		1125	else
5078	serge	1126	step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1963	serge	1127	(125 * 25 * pll->reference_freq / 100);
2997	Serge	1128	radeon_crtc->ss.step = step_size;
1963	serge	1129	}
		1130
6104	serge	1131	atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
		1132	radeon_crtc->crtc_id, &radeon_crtc->ss);
1963	serge	1133	}
		1134	}
		1135
		1136	static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
3031	serge	1137	struct drm_framebuffer *fb,
		1138	int x, int y, int atomic)
1963	serge	1139	{
		1140	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		1141	struct drm_device *dev = crtc->dev;
		1142	struct radeon_device *rdev = dev->dev_private;
1430	serge	1143	struct radeon_framebuffer *radeon_fb;
1963	serge	1144	struct drm_framebuffer *target_fb;
1430	serge	1145	struct drm_gem_object *obj;
		1146	struct radeon_bo *rbo;
		1147	uint64_t fb_location;
		1148	uint32_t fb_format, fb_pitch_pixels, tiling_flags;
2997	Serge	1149	unsigned bankw, bankh, mtaspect, tile_split;
1963	serge	1150	u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
		1151	u32 tmp, viewport_w, viewport_h;
1430	serge	1152	int r;
5078	serge	1153	bool bypass_lut = false;
1430	serge	1154
		1155	/* no fb bound */
5078	serge	1156	if (!atomic && !crtc->primary->fb) {
1963	serge	1157	DRM_DEBUG_KMS("No FB bound\n");
1430	serge	1158	return 0;
		1159	}
		1160
1963	serge	1161	if (atomic) {
		1162	radeon_fb = to_radeon_framebuffer(fb);
		1163	target_fb = fb;
		1164	}
		1165	else {
5078	serge	1166	radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
		1167	target_fb = crtc->primary->fb;
1963	serge	1168	}
1430	serge	1169
1963	serge	1170	/* If atomic, assume fb object is pinned & idle & fenced and
		1171	* just update base pointers
		1172	*/
1430	serge	1173	obj = radeon_fb->obj;
1963	serge	1174	rbo = gem_to_radeon_bo(obj);
6104	serge	1175	r = radeon_bo_reserve(rbo, false);
		1176	if (unlikely(r != 0))
		1177	return r;
1963	serge	1178
		1179	if (atomic)
		1180	fb_location = radeon_bo_gpu_offset(rbo);
		1181	else {
3031	serge	1182	r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
		1183	if (unlikely(r != 0)) {
		1184	radeon_bo_unreserve(rbo);
		1185	return -EINVAL;
		1186	}
1430	serge	1187	}
1963	serge	1188
1430	serge	1189	radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
6104	serge	1190	radeon_bo_unreserve(rbo);
1430	serge	1191
5078	serge	1192	switch (target_fb->pixel_format) {
		1193	case DRM_FORMAT_C8:
1430	serge	1194	fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) \|
		1195	EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
		1196	break;
5078	serge	1197	case DRM_FORMAT_XRGB4444:
		1198	case DRM_FORMAT_ARGB4444:
1430	serge	1199	fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) \|
5078	serge	1200	EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444));
		1201	#ifdef __BIG_ENDIAN
		1202	fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
		1203	#endif
		1204	break;
		1205	case DRM_FORMAT_XRGB1555:
		1206	case DRM_FORMAT_ARGB1555:
		1207	fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) \|
1430	serge	1208	EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
5078	serge	1209	#ifdef __BIG_ENDIAN
		1210	fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
		1211	#endif
1430	serge	1212	break;
5078	serge	1213	case DRM_FORMAT_BGRX5551:
		1214	case DRM_FORMAT_BGRA5551:
1430	serge	1215	fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) \|
5078	serge	1216	EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551));
		1217	#ifdef __BIG_ENDIAN
		1218	fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
		1219	#endif
		1220	break;
		1221	case DRM_FORMAT_RGB565:
		1222	fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) \|
1430	serge	1223	EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1963	serge	1224	#ifdef __BIG_ENDIAN
		1225	fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
		1226	#endif
1430	serge	1227	break;
5078	serge	1228	case DRM_FORMAT_XRGB8888:
		1229	case DRM_FORMAT_ARGB8888:
1430	serge	1230	fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) \|
		1231	EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1963	serge	1232	#ifdef __BIG_ENDIAN
		1233	fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
		1234	#endif
1430	serge	1235	break;
5078	serge	1236	case DRM_FORMAT_XRGB2101010:
		1237	case DRM_FORMAT_ARGB2101010:
		1238	fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) \|
		1239	EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010));
		1240	#ifdef __BIG_ENDIAN
		1241	fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
		1242	#endif
		1243	/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
		1244	bypass_lut = true;
		1245	break;
		1246	case DRM_FORMAT_BGRX1010102:
		1247	case DRM_FORMAT_BGRA1010102:
		1248	fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) \|
		1249	EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102));
		1250	#ifdef __BIG_ENDIAN
		1251	fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
		1252	#endif
		1253	/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
		1254	bypass_lut = true;
		1255	break;
1430	serge	1256	default:
5078	serge	1257	DRM_ERROR("Unsupported screen format %s\n",
		1258	drm_get_format_name(target_fb->pixel_format));
1430	serge	1259	return -EINVAL;
		1260	}
		1261
2997	Serge	1262	if (tiling_flags & RADEON_TILING_MACRO) {
5078	serge	1263	evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
		1264
		1265	/* Set NUM_BANKS. */
		1266	if (rdev->family >= CHIP_TAHITI) {
		1267	unsigned index, num_banks;
		1268
6104	serge	1269	if (rdev->family >= CHIP_BONAIRE) {
5078	serge	1270	unsigned tileb, tile_split_bytes;
		1271
6104	serge	1272	/* Calculate the macrotile mode index. */
		1273	tile_split_bytes = 64 << tile_split;
		1274	tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
		1275	tileb = min(tile_split_bytes, tileb);
5078	serge	1276
		1277	for (index = 0; tileb > 64; index++)
6104	serge	1278	tileb >>= 1;
5078	serge	1279
6104	serge	1280	if (index >= 16) {
		1281	DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
		1282	target_fb->bits_per_pixel, tile_split);
		1283	return -EINVAL;
		1284	}
5078	serge	1285
6104	serge	1286	num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
5078	serge	1287	} else {
		1288	switch (target_fb->bits_per_pixel) {
		1289	case 8:
		1290	index = 10;
		1291	break;
		1292	case 16:
		1293	index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
		1294	break;
		1295	default:
		1296	case 32:
		1297	index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
		1298	break;
		1299	}
		1300
		1301	num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
		1302	}
		1303
		1304	fb_format \|= EVERGREEN_GRPH_NUM_BANKS(num_banks);
		1305	} else {
		1306	/* NI and older. */
		1307	if (rdev->family >= CHIP_CAYMAN)
6104	serge	1308	tmp = rdev->config.cayman.tile_config;
		1309	else
		1310	tmp = rdev->config.evergreen.tile_config;
2997	Serge	1311
6104	serge	1312	switch ((tmp & 0xf0) >> 4) {
		1313	case 0: /* 4 banks */
		1314	fb_format \|= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
		1315	break;
		1316	case 1: /* 8 banks */
		1317	default:
		1318	fb_format \|= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
		1319	break;
		1320	case 2: /* 16 banks */
		1321	fb_format \|= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
		1322	break;
		1323	}
2997	Serge	1324	}
		1325
1963	serge	1326	fb_format \|= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
2997	Serge	1327	fb_format \|= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
		1328	fb_format \|= EVERGREEN_GRPH_BANK_WIDTH(bankw);
		1329	fb_format \|= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
		1330	fb_format \|= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
5078	serge	1331	if (rdev->family >= CHIP_BONAIRE) {
		1332	/* XXX need to know more about the surface tiling mode */
		1333	fb_format \|= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
		1334	}
2997	Serge	1335	} else if (tiling_flags & RADEON_TILING_MICRO)
1963	serge	1336	fb_format \|= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
		1337
5078	serge	1338	if (rdev->family >= CHIP_BONAIRE) {
		1339	/* Read the pipe config from the 2D TILED SCANOUT mode.
		1340	* It should be the same for the other modes too, but not all
		1341	* modes set the pipe config field. */
		1342	u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
		1343
		1344	fb_format \|= CIK_GRPH_PIPE_CONFIG(pipe_config);
		1345	} else if ((rdev->family == CHIP_TAHITI) \|\|
6104	serge	1346	(rdev->family == CHIP_PITCAIRN))
2997	Serge	1347	fb_format \|= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
5078	serge	1348	else if ((rdev->family == CHIP_VERDE) \|\|
		1349	(rdev->family == CHIP_OLAND) \|\|
		1350	(rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */
2997	Serge	1351	fb_format \|= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
		1352
1430	serge	1353	switch (radeon_crtc->crtc_id) {
		1354	case 0:
		1355	WREG32(AVIVO_D1VGA_CONTROL, 0);
		1356	break;
		1357	case 1:
		1358	WREG32(AVIVO_D2VGA_CONTROL, 0);
		1359	break;
		1360	case 2:
		1361	WREG32(EVERGREEN_D3VGA_CONTROL, 0);
		1362	break;
		1363	case 3:
		1364	WREG32(EVERGREEN_D4VGA_CONTROL, 0);
		1365	break;
		1366	case 4:
		1367	WREG32(EVERGREEN_D5VGA_CONTROL, 0);
		1368	break;
		1369	case 5:
		1370	WREG32(EVERGREEN_D6VGA_CONTROL, 0);
		1371	break;
		1372	default:
		1373	break;
		1374	}
		1375
		1376	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
		1377	upper_32_bits(fb_location));
		1378	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
		1379	upper_32_bits(fb_location));
		1380	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
		1381	(u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
		1382	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
		1383	(u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
		1384	WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1963	serge	1385	WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1430	serge	1386
5078	serge	1387	/*
		1388	* The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
		1389	* for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
		1390	* retain the full precision throughout the pipeline.
		1391	*/
		1392	WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,
		1393	(bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0),
		1394	~EVERGREEN_LUT_10BIT_BYPASS_EN);
		1395
		1396	if (bypass_lut)
		1397	DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
		1398
1430	serge	1399	WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
		1400	WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
		1401	WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
		1402	WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1963	serge	1403	WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
		1404	WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1430	serge	1405
2997	Serge	1406	fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1430	serge	1407	WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
		1408	WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
		1409
5078	serge	1410	if (rdev->family >= CHIP_BONAIRE)
		1411	WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
		1412	target_fb->height);
		1413	else
6104	serge	1414	WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
		1415	target_fb->height);
1430	serge	1416	x &= ~3;
		1417	y &= ~1;
		1418	WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
		1419	(x << 16) \| y);
1963	serge	1420	viewport_w = crtc->mode.hdisplay;
		1421	viewport_h = (crtc->mode.vdisplay + 1) & ~1;
6104	serge	1422	if ((rdev->family >= CHIP_BONAIRE) &&
		1423	(crtc->mode.flags & DRM_MODE_FLAG_INTERLACE))
		1424	viewport_h *= 2;
1430	serge	1425	WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1963	serge	1426	(viewport_w << 16) \| viewport_h);
1430	serge	1427
1963	serge	1428	/* pageflip setup */
		1429	/* make sure flip is at vb rather than hb */
		1430	tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
		1431	tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
		1432	WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1430	serge	1433
5078	serge	1434	/* set pageflip to happen only at start of vblank interval (front porch) */
		1435	WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
1963	serge	1436
5078	serge	1437	if (!atomic && fb && fb != crtc->primary->fb) {
1963	serge	1438	radeon_fb = to_radeon_framebuffer(fb);
		1439	rbo = gem_to_radeon_bo(radeon_fb->obj);
1430	serge	1440	r = radeon_bo_reserve(rbo, false);
		1441	if (unlikely(r != 0))
		1442	return r;
		1443	radeon_bo_unpin(rbo);
		1444	radeon_bo_unreserve(rbo);
		1445	}
		1446
		1447	/* Bytes per pixel may have changed */
		1448	radeon_bandwidth_update(rdev);
		1449
		1450	return 0;
		1451	}
		1452
1963	serge	1453	static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
		1454	struct drm_framebuffer *fb,
		1455	int x, int y, int atomic)
1123	serge	1456	{
		1457	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		1458	struct drm_device *dev = crtc->dev;
		1459	struct radeon_device *rdev = dev->dev_private;
		1460	struct radeon_framebuffer *radeon_fb;
		1461	struct drm_gem_object *obj;
1321	serge	1462	struct radeon_bo *rbo;
1963	serge	1463	struct drm_framebuffer *target_fb;
1123	serge	1464	uint64_t fb_location;
1179	serge	1465	uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1963	serge	1466	u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
		1467	u32 tmp, viewport_w, viewport_h;
1321	serge	1468	int r;
5078	serge	1469	bool bypass_lut = false;
1123	serge	1470
1321	serge	1471	/* no fb bound */
5078	serge	1472	if (!atomic && !crtc->primary->fb) {
1963	serge	1473	DRM_DEBUG_KMS("No FB bound\n");
1321	serge	1474	return 0;
		1475	}
1123	serge	1476
1963	serge	1477	if (atomic) {
		1478	radeon_fb = to_radeon_framebuffer(fb);
		1479	target_fb = fb;
		1480	}
		1481	else {
5078	serge	1482	radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
		1483	target_fb = crtc->primary->fb;
1963	serge	1484	}
1123	serge	1485
		1486	obj = radeon_fb->obj;
1963	serge	1487	rbo = gem_to_radeon_bo(obj);
1404	serge	1488	r = radeon_bo_reserve(rbo, false);
		1489	if (unlikely(r != 0))
		1490	return r;
1963	serge	1491
		1492	/* If atomic, assume fb object is pinned & idle & fenced and
		1493	* just update base pointers
		1494	*/
		1495	if (atomic)
		1496	fb_location = radeon_bo_gpu_offset(rbo);
		1497	else {
3031	serge	1498	r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
		1499	if (unlikely(r != 0)) {
		1500	radeon_bo_unreserve(rbo);
		1501	return -EINVAL;
		1502	}
1404	serge	1503	}
		1504	radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
		1505	radeon_bo_unreserve(rbo);
1123	serge	1506
5078	serge	1507	switch (target_fb->pixel_format) {
		1508	case DRM_FORMAT_C8:
1179	serge	1509	fb_format =
		1510	AVIVO_D1GRPH_CONTROL_DEPTH_8BPP \|
		1511	AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
		1512	break;
5078	serge	1513	case DRM_FORMAT_XRGB4444:
		1514	case DRM_FORMAT_ARGB4444:
1123	serge	1515	fb_format =
		1516	AVIVO_D1GRPH_CONTROL_DEPTH_16BPP \|
5078	serge	1517	AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444;
		1518	#ifdef __BIG_ENDIAN
		1519	fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
		1520	#endif
		1521	break;
		1522	case DRM_FORMAT_XRGB1555:
		1523	fb_format =
		1524	AVIVO_D1GRPH_CONTROL_DEPTH_16BPP \|
1123	serge	1525	AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
5078	serge	1526	#ifdef __BIG_ENDIAN
		1527	fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
		1528	#endif
1123	serge	1529	break;
5078	serge	1530	case DRM_FORMAT_RGB565:
1123	serge	1531	fb_format =
		1532	AVIVO_D1GRPH_CONTROL_DEPTH_16BPP \|
		1533	AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1963	serge	1534	#ifdef __BIG_ENDIAN
		1535	fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
		1536	#endif
1123	serge	1537	break;
5078	serge	1538	case DRM_FORMAT_XRGB8888:
		1539	case DRM_FORMAT_ARGB8888:
1123	serge	1540	fb_format =
		1541	AVIVO_D1GRPH_CONTROL_DEPTH_32BPP \|
		1542	AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1963	serge	1543	#ifdef __BIG_ENDIAN
		1544	fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
		1545	#endif
1123	serge	1546	break;
5078	serge	1547	case DRM_FORMAT_XRGB2101010:
		1548	case DRM_FORMAT_ARGB2101010:
		1549	fb_format =
		1550	AVIVO_D1GRPH_CONTROL_DEPTH_32BPP \|
		1551	AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010;
		1552	#ifdef __BIG_ENDIAN
		1553	fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
		1554	#endif
		1555	/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
		1556	bypass_lut = true;
		1557	break;
1123	serge	1558	default:
5078	serge	1559	DRM_ERROR("Unsupported screen format %s\n",
		1560	drm_get_format_name(target_fb->pixel_format));
1123	serge	1561	return -EINVAL;
		1562	}
		1563
1963	serge	1564	if (rdev->family >= CHIP_R600) {
		1565	if (tiling_flags & RADEON_TILING_MACRO)
		1566	fb_format \|= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
		1567	else if (tiling_flags & RADEON_TILING_MICRO)
		1568	fb_format \|= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
		1569	} else {
3031	serge	1570	if (tiling_flags & RADEON_TILING_MACRO)
		1571	fb_format \|= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1179	serge	1572
3031	serge	1573	if (tiling_flags & RADEON_TILING_MICRO)
		1574	fb_format \|= AVIVO_D1GRPH_TILED;
1963	serge	1575	}
1179	serge	1576
1123	serge	1577	if (radeon_crtc->crtc_id == 0)
		1578	WREG32(AVIVO_D1VGA_CONTROL, 0);
		1579	else
		1580	WREG32(AVIVO_D2VGA_CONTROL, 0);
1268	serge	1581
		1582	if (rdev->family >= CHIP_RV770) {
		1583	if (radeon_crtc->crtc_id) {
1963	serge	1584	WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
		1585	WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1268	serge	1586	} else {
1963	serge	1587	WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
		1588	WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1268	serge	1589	}
		1590	}
1123	serge	1591	WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
		1592	(u32) fb_location);
		1593	WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
		1594	radeon_crtc->crtc_offset, (u32) fb_location);
		1595	WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1963	serge	1596	if (rdev->family >= CHIP_R600)
		1597	WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1123	serge	1598
5078	serge	1599	/* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */
		1600	WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,
		1601	(bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN);
		1602
		1603	if (bypass_lut)
		1604	DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
		1605
1123	serge	1606	WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
		1607	WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
		1608	WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
		1609	WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1963	serge	1610	WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
		1611	WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1123	serge	1612
2997	Serge	1613	fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1123	serge	1614	WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
		1615	WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
		1616
		1617	WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
2997	Serge	1618	target_fb->height);
1123	serge	1619	x &= ~3;
		1620	y &= ~1;
		1621	WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
		1622	(x << 16) \| y);
1963	serge	1623	viewport_w = crtc->mode.hdisplay;
		1624	viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1123	serge	1625	WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1963	serge	1626	(viewport_w << 16) \| viewport_h);
1123	serge	1627
1963	serge	1628	/* pageflip setup */
		1629	/* make sure flip is at vb rather than hb */
		1630	tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
		1631	tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
		1632	WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1123	serge	1633
5078	serge	1634	/* set pageflip to happen only at start of vblank interval (front porch) */
		1635	WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
1963	serge	1636
5078	serge	1637	if (!atomic && fb && fb != crtc->primary->fb) {
1963	serge	1638	radeon_fb = to_radeon_framebuffer(fb);
		1639	rbo = gem_to_radeon_bo(radeon_fb->obj);
1404	serge	1640	r = radeon_bo_reserve(rbo, false);
		1641	if (unlikely(r != 0))
		1642	return r;
		1643	radeon_bo_unpin(rbo);
		1644	radeon_bo_unreserve(rbo);
		1645	}
1246	serge	1646
1268	serge	1647	/* Bytes per pixel may have changed */
		1648	radeon_bandwidth_update(rdev);
		1649
1123	serge	1650	return 0;
		1651	}
		1652
1404	serge	1653	int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
		1654	struct drm_framebuffer *old_fb)
		1655	{
		1656	struct drm_device *dev = crtc->dev;
		1657	struct radeon_device *rdev = dev->dev_private;
		1658
1430	serge	1659	if (ASIC_IS_DCE4(rdev))
1963	serge	1660	return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1430	serge	1661	else if (ASIC_IS_AVIVO(rdev))
1963	serge	1662	return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1404	serge	1663	else
1963	serge	1664	return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1404	serge	1665	}
		1666
1963	serge	1667	int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
		1668	struct drm_framebuffer *fb,
		1669	int x, int y, enum mode_set_atomic state)
		1670	{
		1671	struct drm_device *dev = crtc->dev;
		1672	struct radeon_device *rdev = dev->dev_private;
		1673
		1674	if (ASIC_IS_DCE4(rdev))
		1675	return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
		1676	else if (ASIC_IS_AVIVO(rdev))
		1677	return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
		1678	else
		1679	return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
		1680	}
		1681
1404	serge	1682	/* properly set additional regs when using atombios */
		1683	static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
		1684	{
		1685	struct drm_device *dev = crtc->dev;
		1686	struct radeon_device *rdev = dev->dev_private;
		1687	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		1688	u32 disp_merge_cntl;
		1689
		1690	switch (radeon_crtc->crtc_id) {
		1691	case 0:
		1692	disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
		1693	disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
		1694	WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
		1695	break;
		1696	case 1:
		1697	disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
		1698	disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
		1699	WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
		1700	WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
		1701	WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
		1702	break;
		1703	}
		1704	}
		1705
2997	Serge	1706	/**
		1707	* radeon_get_pll_use_mask - look up a mask of which pplls are in use
		1708	*
		1709	* @crtc: drm crtc
		1710	*
		1711	* Returns the mask of which PPLLs (Pixel PLLs) are in use.
		1712	*/
		1713	static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
		1714	{
		1715	struct drm_device *dev = crtc->dev;
		1716	struct drm_crtc *test_crtc;
		1717	struct radeon_crtc *test_radeon_crtc;
		1718	u32 pll_in_use = 0;
		1719
		1720	list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
		1721	if (crtc == test_crtc)
		1722	continue;
		1723
		1724	test_radeon_crtc = to_radeon_crtc(test_crtc);
		1725	if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
		1726	pll_in_use \|= (1 << test_radeon_crtc->pll_id);
		1727	}
		1728	return pll_in_use;
		1729	}
		1730
		1731	/**
		1732	* radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
		1733	*
		1734	* @crtc: drm crtc
		1735	*
		1736	* Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
		1737	* also in DP mode. For DP, a single PPLL can be used for all DP
		1738	* crtcs/encoders.
		1739	*/
		1740	static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
		1741	{
		1742	struct drm_device *dev = crtc->dev;
6661	serge	1743	struct radeon_device *rdev = dev->dev_private;
2997	Serge	1744	struct drm_crtc *test_crtc;
		1745	struct radeon_crtc *test_radeon_crtc;
		1746
		1747	list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
		1748	if (crtc == test_crtc)
		1749	continue;
		1750	test_radeon_crtc = to_radeon_crtc(test_crtc);
		1751	if (test_radeon_crtc->encoder &&
		1752	ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
6661	serge	1753	/* PPLL2 is exclusive to UNIPHYA on DCE61 */
		1754	if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
		1755	test_radeon_crtc->pll_id == ATOM_PPLL2)
		1756	continue;
2997	Serge	1757	/* for DP use the same PLL for all */
		1758	if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
		1759	return test_radeon_crtc->pll_id;
		1760	}
		1761	}
		1762	return ATOM_PPLL_INVALID;
		1763	}
		1764
		1765	/**
		1766	* radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
		1767	*
		1768	* @crtc: drm crtc
		1769	* @encoder: drm encoder
		1770	*
		1771	* Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
		1772	* be shared (i.e., same clock).
		1773	*/
		1774	static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
		1775	{
		1776	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		1777	struct drm_device *dev = crtc->dev;
6661	serge	1778	struct radeon_device *rdev = dev->dev_private;
2997	Serge	1779	struct drm_crtc *test_crtc;
		1780	struct radeon_crtc *test_radeon_crtc;
		1781	u32 adjusted_clock, test_adjusted_clock;
		1782
		1783	adjusted_clock = radeon_crtc->adjusted_clock;
		1784
		1785	if (adjusted_clock == 0)
		1786	return ATOM_PPLL_INVALID;
		1787
		1788	list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
		1789	if (crtc == test_crtc)
		1790	continue;
		1791	test_radeon_crtc = to_radeon_crtc(test_crtc);
		1792	if (test_radeon_crtc->encoder &&
		1793	!ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
6661	serge	1794	/* PPLL2 is exclusive to UNIPHYA on DCE61 */
		1795	if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
		1796	test_radeon_crtc->pll_id == ATOM_PPLL2)
		1797	continue;
2997	Serge	1798	/* check if we are already driving this connector with another crtc */
		1799	if (test_radeon_crtc->connector == radeon_crtc->connector) {
		1800	/* if we are, return that pll */
		1801	if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
		1802	return test_radeon_crtc->pll_id;
		1803	}
		1804	/* for non-DP check the clock */
		1805	test_adjusted_clock = test_radeon_crtc->adjusted_clock;
		1806	if ((crtc->mode.clock == test_crtc->mode.clock) &&
		1807	(adjusted_clock == test_adjusted_clock) &&
		1808	(radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
		1809	(test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
		1810	return test_radeon_crtc->pll_id;
		1811	}
		1812	}
		1813	return ATOM_PPLL_INVALID;
		1814	}
		1815
		1816	/**
		1817	* radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
		1818	*
		1819	* @crtc: drm crtc
		1820	*
		1821	* Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
		1822	* a single PPLL can be used for all DP crtcs/encoders. For non-DP
		1823	* monitors a dedicated PPLL must be used. If a particular board has
		1824	* an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
		1825	* as there is no need to program the PLL itself. If we are not able to
		1826	* allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
		1827	* avoid messing up an existing monitor.
		1828	*
		1829	* Asic specific PLL information
		1830	*
5078	serge	1831	* DCE 8.x
		1832	* KB/KV
		1833	* - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
		1834	* CI
		1835	* - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
		1836	*
2997	Serge	1837	* DCE 6.1
		1838	* - PPLL2 is only available to UNIPHYA (both DP and non-DP)
		1839	* - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
		1840	*
		1841	* DCE 6.0
		1842	* - PPLL0 is available to all UNIPHY (DP only)
		1843	* - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
		1844	*
		1845	* DCE 5.0
		1846	* - DCPLL is available to all UNIPHY (DP only)
		1847	* - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
		1848	*
		1849	* DCE 3.0/4.0/4.1
		1850	* - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
		1851	*
		1852	*/
1430	serge	1853	static int radeon_atom_pick_pll(struct drm_crtc *crtc)
		1854	{
		1855	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		1856	struct drm_device *dev = crtc->dev;
		1857	struct radeon_device *rdev = dev->dev_private;
2997	Serge	1858	struct radeon_encoder *radeon_encoder =
		1859	to_radeon_encoder(radeon_crtc->encoder);
		1860	u32 pll_in_use;
		1861	int pll;
1430	serge	1862
5078	serge	1863	if (ASIC_IS_DCE8(rdev)) {
		1864	if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
		1865	if (rdev->clock.dp_extclk)
		1866	/* skip PPLL programming if using ext clock */
		1867	return ATOM_PPLL_INVALID;
		1868	else {
		1869	/* use the same PPLL for all DP monitors */
		1870	pll = radeon_get_shared_dp_ppll(crtc);
		1871	if (pll != ATOM_PPLL_INVALID)
		1872	return pll;
		1873	}
		1874	} else {
		1875	/* use the same PPLL for all monitors with the same clock */
		1876	pll = radeon_get_shared_nondp_ppll(crtc);
		1877	if (pll != ATOM_PPLL_INVALID)
		1878	return pll;
		1879	}
		1880	/* otherwise, pick one of the plls */
6104	serge	1881	if ((rdev->family == CHIP_KABINI) \|\|
5078	serge	1882	(rdev->family == CHIP_MULLINS)) {
6104	serge	1883	/* KB/ML has PPLL1 and PPLL2 */
5078	serge	1884	pll_in_use = radeon_get_pll_use_mask(crtc);
		1885	if (!(pll_in_use & (1 << ATOM_PPLL2)))
		1886	return ATOM_PPLL2;
		1887	if (!(pll_in_use & (1 << ATOM_PPLL1)))
		1888	return ATOM_PPLL1;
		1889	DRM_ERROR("unable to allocate a PPLL\n");
		1890	return ATOM_PPLL_INVALID;
		1891	} else {
6104	serge	1892	/* CI/KV has PPLL0, PPLL1, and PPLL2 */
5078	serge	1893	pll_in_use = radeon_get_pll_use_mask(crtc);
		1894	if (!(pll_in_use & (1 << ATOM_PPLL2)))
		1895	return ATOM_PPLL2;
		1896	if (!(pll_in_use & (1 << ATOM_PPLL1)))
		1897	return ATOM_PPLL1;
		1898	if (!(pll_in_use & (1 << ATOM_PPLL0)))
		1899	return ATOM_PPLL0;
		1900	DRM_ERROR("unable to allocate a PPLL\n");
		1901	return ATOM_PPLL_INVALID;
		1902	}
		1903	} else if (ASIC_IS_DCE61(rdev)) {
3031	serge	1904	struct radeon_encoder_atom_dig *dig =
2997	Serge	1905	radeon_encoder->enc_priv;
		1906
		1907	if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
		1908	(dig->linkb == false))
		1909	/* UNIPHY A uses PPLL2 */
3031	serge	1910	return ATOM_PPLL2;
2997	Serge	1911	else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
		1912	/* UNIPHY B/C/D/E/F */
		1913	if (rdev->clock.dp_extclk)
		1914	/* skip PPLL programming if using ext clock */
		1915	return ATOM_PPLL_INVALID;
		1916	else {
		1917	/* use the same PPLL for all DP monitors */
		1918	pll = radeon_get_shared_dp_ppll(crtc);
		1919	if (pll != ATOM_PPLL_INVALID)
		1920	return pll;
		1921	}
		1922	} else {
		1923	/* use the same PPLL for all monitors with the same clock */
		1924	pll = radeon_get_shared_nondp_ppll(crtc);
		1925	if (pll != ATOM_PPLL_INVALID)
		1926	return pll;
		1927	}
		1928	/* UNIPHY B/C/D/E/F */
		1929	pll_in_use = radeon_get_pll_use_mask(crtc);
		1930	if (!(pll_in_use & (1 << ATOM_PPLL0)))
		1931	return ATOM_PPLL0;
		1932	if (!(pll_in_use & (1 << ATOM_PPLL1)))
3031	serge	1933	return ATOM_PPLL1;
2997	Serge	1934	DRM_ERROR("unable to allocate a PPLL\n");
		1935	return ATOM_PPLL_INVALID;
5078	serge	1936	} else if (ASIC_IS_DCE41(rdev)) {
		1937	/* Don't share PLLs on DCE4.1 chips */
		1938	if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
		1939	if (rdev->clock.dp_extclk)
		1940	/* skip PPLL programming if using ext clock */
		1941	return ATOM_PPLL_INVALID;
		1942	}
		1943	pll_in_use = radeon_get_pll_use_mask(crtc);
		1944	if (!(pll_in_use & (1 << ATOM_PPLL1)))
		1945	return ATOM_PPLL1;
		1946	if (!(pll_in_use & (1 << ATOM_PPLL2)))
		1947	return ATOM_PPLL2;
		1948	DRM_ERROR("unable to allocate a PPLL\n");
		1949	return ATOM_PPLL_INVALID;
2997	Serge	1950	} else if (ASIC_IS_DCE4(rdev)) {
3031	serge	1951	/* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
		1952	* depending on the asic:
		1953	* DCE4: PPLL or ext clock
2997	Serge	1954	* DCE5: PPLL, DCPLL, or ext clock
		1955	* DCE6: PPLL, PPLL0, or ext clock
3031	serge	1956	*
		1957	* Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
		1958	* PPLL/DCPLL programming and only program the DP DTO for the
		1959	* crtc virtual pixel clock.
		1960	*/
2997	Serge	1961	if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
3031	serge	1962	if (rdev->clock.dp_extclk)
2997	Serge	1963	/* skip PPLL programming if using ext clock */
3031	serge	1964	return ATOM_PPLL_INVALID;
		1965	else if (ASIC_IS_DCE6(rdev))
2997	Serge	1966	/* use PPLL0 for all DP */
3031	serge	1967	return ATOM_PPLL0;
		1968	else if (ASIC_IS_DCE5(rdev))
2997	Serge	1969	/* use DCPLL for all DP */
3031	serge	1970	return ATOM_DCPLL;
2997	Serge	1971	else {
		1972	/* use the same PPLL for all DP monitors */
		1973	pll = radeon_get_shared_dp_ppll(crtc);
		1974	if (pll != ATOM_PPLL_INVALID)
		1975	return pll;
3031	serge	1976	}
2997	Serge	1977	} else {
		1978	/* use the same PPLL for all monitors with the same clock */
		1979	pll = radeon_get_shared_nondp_ppll(crtc);
		1980	if (pll != ATOM_PPLL_INVALID)
		1981	return pll;
3031	serge	1982	}
2997	Serge	1983	/* all other cases */
		1984	pll_in_use = radeon_get_pll_use_mask(crtc);
		1985	if (!(pll_in_use & (1 << ATOM_PPLL1)))
		1986	return ATOM_PPLL1;
		1987	if (!(pll_in_use & (1 << ATOM_PPLL2)))
		1988	return ATOM_PPLL2;
		1989	DRM_ERROR("unable to allocate a PPLL\n");
		1990	return ATOM_PPLL_INVALID;
6104	serge	1991	} else {
3120	serge	1992	/* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
		1993	/* some atombios (observed in some DCE2/DCE3) code have a bug,
		1994	* the matching btw pll and crtc is done through
		1995	* PCLK_CRTC[1\|2]_CNTL (0x480/0x484) but atombios code use the
		1996	* pll (1 or 2) to select which register to write. ie if using
		1997	* pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
		1998	* it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
		1999	* choose which value to write. Which is reverse order from
		2000	* register logic. So only case that works is when pllid is
		2001	* same as crtcid or when both pll and crtc are enabled and
		2002	* both use same clock.
		2003	*
		2004	* So just return crtc id as if crtc and pll were hard linked
		2005	* together even if they aren't
3031	serge	2006	*/
1430	serge	2007	return radeon_crtc->crtc_id;
2997	Serge	2008	}
		2009	}
1430	serge	2010
2997	Serge	2011	void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
		2012	{
		2013	/* always set DCPLL */
		2014	if (ASIC_IS_DCE6(rdev))
		2015	atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
		2016	else if (ASIC_IS_DCE4(rdev)) {
		2017	struct radeon_atom_ss ss;
		2018	bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
		2019	ASIC_INTERNAL_SS_ON_DCPLL,
		2020	rdev->clock.default_dispclk);
		2021	if (ss_enabled)
		2022	atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
		2023	/* XXX: DCE5, make sure voltage, dispclk is high enough */
		2024	atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
		2025	if (ss_enabled)
		2026	atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
		2027	}
		2028
1430	serge	2029	}
		2030
1123	serge	2031	int atombios_crtc_mode_set(struct drm_crtc *crtc,
		2032	struct drm_display_mode *mode,
		2033	struct drm_display_mode *adjusted_mode,
		2034	int x, int y, struct drm_framebuffer *old_fb)
		2035	{
		2036	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		2037	struct drm_device *dev = crtc->dev;
		2038	struct radeon_device *rdev = dev->dev_private;
2997	Serge	2039	struct radeon_encoder *radeon_encoder =
		2040	to_radeon_encoder(radeon_crtc->encoder);
1963	serge	2041	bool is_tvcv = false;
1123	serge	2042
3031	serge	2043	if (radeon_encoder->active_device &
		2044	(ATOM_DEVICE_TV_SUPPORT \| ATOM_DEVICE_CV_SUPPORT))
		2045	is_tvcv = true;
1123	serge	2046
5078	serge	2047	if (!radeon_crtc->adjusted_clock)
		2048	return -EINVAL;
		2049
1123	serge	2050	atombios_crtc_set_pll(crtc, adjusted_mode);
1430	serge	2051
		2052	if (ASIC_IS_DCE4(rdev))
		2053	atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1963	serge	2054	else if (ASIC_IS_AVIVO(rdev)) {
		2055	if (is_tvcv)
		2056	atombios_crtc_set_timing(crtc, adjusted_mode);
		2057	else
		2058	atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
		2059	} else {
1430	serge	2060	atombios_crtc_set_timing(crtc, adjusted_mode);
1268	serge	2061	if (radeon_crtc->crtc_id == 0)
		2062	atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1404	serge	2063	radeon_legacy_atom_fixup(crtc);
1123	serge	2064	}
1430	serge	2065	atombios_crtc_set_base(crtc, x, y, old_fb);
6104	serge	2066	atombios_overscan_setup(crtc, mode, adjusted_mode);
		2067	atombios_scaler_setup(crtc);
		2068	// radeon_cursor_reset(crtc);
5078	serge	2069	/* update the hw version fpr dpm */
		2070	radeon_crtc->hw_mode = *adjusted_mode;
		2071
1123	serge	2072	return 0;
		2073	}
		2074
		2075	static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
2997	Serge	2076	const struct drm_display_mode *mode,
1123	serge	2077	struct drm_display_mode *adjusted_mode)
		2078	{
2997	Serge	2079	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1963	serge	2080	struct drm_device *dev = crtc->dev;
2997	Serge	2081	struct drm_encoder *encoder;
1963	serge	2082
2997	Serge	2083	/* assign the encoder to the radeon crtc to avoid repeated lookups later */
		2084	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		2085	if (encoder->crtc == crtc) {
		2086	radeon_crtc->encoder = encoder;
		2087	radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
		2088	break;
		2089	}
		2090	}
		2091	if ((radeon_crtc->encoder == NULL) \|\| (radeon_crtc->connector == NULL)) {
		2092	radeon_crtc->encoder = NULL;
		2093	radeon_crtc->connector = NULL;
		2094	return false;
		2095	}
6104	serge	2096	if (radeon_crtc->encoder) {
		2097	struct radeon_encoder *radeon_encoder =
		2098	to_radeon_encoder(radeon_crtc->encoder);
		2099
		2100	radeon_crtc->output_csc = radeon_encoder->output_csc;
		2101	}
1179	serge	2102	if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
		2103	return false;
2997	Serge	2104	if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
		2105	return false;
		2106	/* pick pll */
		2107	radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
		2108	/* if we can't get a PPLL for a non-DP encoder, fail */
		2109	if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
		2110	!ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
		2111	return false;
		2112
1123	serge	2113	return true;
		2114	}
		2115
		2116	static void atombios_crtc_prepare(struct drm_crtc *crtc)
		2117	{
2997	Serge	2118	struct drm_device *dev = crtc->dev;
		2119	struct radeon_device *rdev = dev->dev_private;
1963	serge	2120
2997	Serge	2121	/* disable crtc pair power gating before programming */
		2122	if (ASIC_IS_DCE6(rdev))
		2123	atombios_powergate_crtc(crtc, ATOM_DISABLE);
		2124
1430	serge	2125	atombios_lock_crtc(crtc, ATOM_ENABLE);
1123	serge	2126	atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
		2127	}
		2128
		2129	static void atombios_crtc_commit(struct drm_crtc *crtc)
		2130	{
		2131	atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1430	serge	2132	atombios_lock_crtc(crtc, ATOM_DISABLE);
1123	serge	2133	}
		2134
1963	serge	2135	static void atombios_crtc_disable(struct drm_crtc *crtc)
		2136	{
		2137	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2997	Serge	2138	struct drm_device *dev = crtc->dev;
		2139	struct radeon_device *rdev = dev->dev_private;
1963	serge	2140	struct radeon_atom_ss ss;
2997	Serge	2141	int i;
1963	serge	2142
		2143	atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
5078	serge	2144	if (crtc->primary->fb) {
		2145	int r;
		2146	struct radeon_framebuffer *radeon_fb;
		2147	struct radeon_bo *rbo;
		2148
		2149	radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
		2150	rbo = gem_to_radeon_bo(radeon_fb->obj);
		2151	r = radeon_bo_reserve(rbo, false);
		2152	if (unlikely(r))
		2153	DRM_ERROR("failed to reserve rbo before unpin\n");
		2154	else {
		2155	radeon_bo_unpin(rbo);
		2156	radeon_bo_unreserve(rbo);
		2157	}
		2158	}
		2159	/* disable the GRPH */
		2160	if (ASIC_IS_DCE4(rdev))
		2161	WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
		2162	else if (ASIC_IS_AVIVO(rdev))
		2163	WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
		2164
3764	Serge	2165	if (ASIC_IS_DCE6(rdev))
		2166	atombios_powergate_crtc(crtc, ATOM_ENABLE);
1963	serge	2167
2997	Serge	2168	for (i = 0; i < rdev->num_crtc; i++) {
		2169	if (rdev->mode_info.crtcs[i] &&
		2170	rdev->mode_info.crtcs[i]->enabled &&
		2171	i != radeon_crtc->crtc_id &&
		2172	radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
		2173	/* one other crtc is using this pll don't turn
		2174	* off the pll
		2175	*/
		2176	goto done;
		2177	}
		2178	}
		2179
1963	serge	2180	switch (radeon_crtc->pll_id) {
		2181	case ATOM_PPLL1:
		2182	case ATOM_PPLL2:
		2183	/* disable the ppll */
		2184	atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
		2185	0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
		2186	break;
2997	Serge	2187	case ATOM_PPLL0:
		2188	/* disable the ppll */
5078	serge	2189	if ((rdev->family == CHIP_ARUBA) \|\|
6104	serge	2190	(rdev->family == CHIP_KAVERI) \|\|
5078	serge	2191	(rdev->family == CHIP_BONAIRE) \|\|
		2192	(rdev->family == CHIP_HAWAII))
2997	Serge	2193	atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
		2194	0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
		2195	break;
1963	serge	2196	default:
		2197	break;
		2198	}
2997	Serge	2199	done:
		2200	radeon_crtc->pll_id = ATOM_PPLL_INVALID;
		2201	radeon_crtc->adjusted_clock = 0;
		2202	radeon_crtc->encoder = NULL;
		2203	radeon_crtc->connector = NULL;
1963	serge	2204	}
		2205
1123	serge	2206	static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
		2207	.dpms = atombios_crtc_dpms,
		2208	.mode_fixup = atombios_crtc_mode_fixup,
		2209	.mode_set = atombios_crtc_mode_set,
		2210	.mode_set_base = atombios_crtc_set_base,
1963	serge	2211	.mode_set_base_atomic = atombios_crtc_set_base_atomic,
1123	serge	2212	.prepare = atombios_crtc_prepare,
		2213	.commit = atombios_crtc_commit,
1221	serge	2214	.load_lut = radeon_crtc_load_lut,
1963	serge	2215	.disable = atombios_crtc_disable,
1123	serge	2216	};
		2217
		2218	void radeon_atombios_init_crtc(struct drm_device *dev,
		2219	struct radeon_crtc *radeon_crtc)
		2220	{
1430	serge	2221	struct radeon_device *rdev = dev->dev_private;
		2222
		2223	if (ASIC_IS_DCE4(rdev)) {
		2224	switch (radeon_crtc->crtc_id) {
		2225	case 0:
		2226	default:
		2227	radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
		2228	break;
		2229	case 1:
		2230	radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
		2231	break;
		2232	case 2:
		2233	radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
		2234	break;
		2235	case 3:
		2236	radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
		2237	break;
		2238	case 4:
		2239	radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
		2240	break;
		2241	case 5:
		2242	radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
		2243	break;
		2244	}
		2245	} else {
3031	serge	2246	if (radeon_crtc->crtc_id == 1)
		2247	radeon_crtc->crtc_offset =
		2248	AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1430	serge	2249	else
		2250	radeon_crtc->crtc_offset = 0;
		2251	}
2997	Serge	2252	radeon_crtc->pll_id = ATOM_PPLL_INVALID;
		2253	radeon_crtc->adjusted_clock = 0;
		2254	radeon_crtc->encoder = NULL;
		2255	radeon_crtc->connector = NULL;
1123	serge	2256	drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
		2257	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/atombios_crtc.c @ 1986 – Rev 6938