WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/atombios.h

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2006-2007 Advanced Micro Devices, Inc.
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice shall be included in
		12	* all copies or substantial portions of the Software.
		13	*
		14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		20	* OTHER DEALINGS IN THE SOFTWARE.
		21	*/
		22
1430	serge	23
1117	serge	24	/****************************************************************************/
		25	/Portion I: Definitions shared between VBIOS and Driver /
		26	/****************************************************************************/
		27
1430	serge	28
1117	serge	29	#ifndef _ATOMBIOS_H
		30	#define _ATOMBIOS_H
		31
		32	#define ATOM_VERSION_MAJOR 0x00020000
		33	#define ATOM_VERSION_MINOR 0x00000002
		34
		35	#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR \| ATOM_VERSION_MINOR)
		36
		37	/* Endianness should be specified before inclusion,
		38	* default to little endian
		39	*/
		40	#ifndef ATOM_BIG_ENDIAN
		41	#error Endian not specified
		42	#endif
		43
		44	#ifdef _H2INC
1430	serge	45	#ifndef ULONG
		46	typedef unsigned long ULONG;
		47	#endif
1117	serge	48
1430	serge	49	#ifndef UCHAR
		50	typedef unsigned char UCHAR;
		51	#endif
1117	serge	52
1430	serge	53	#ifndef USHORT
		54	typedef unsigned short USHORT;
		55	#endif
1117	serge	56	#endif
		57
		58	#define ATOM_DAC_A 0
		59	#define ATOM_DAC_B 1
		60	#define ATOM_EXT_DAC 2
		61
		62	#define ATOM_CRTC1 0
		63	#define ATOM_CRTC2 1
1430	serge	64	#define ATOM_CRTC3 2
		65	#define ATOM_CRTC4 3
		66	#define ATOM_CRTC5 4
		67	#define ATOM_CRTC6 5
		68	#define ATOM_CRTC_INVALID 0xFF
1117	serge	69
		70	#define ATOM_DIGA 0
		71	#define ATOM_DIGB 1
		72
		73	#define ATOM_PPLL1 0
		74	#define ATOM_PPLL2 1
1430	serge	75	#define ATOM_DCPLL 2
		76	#define ATOM_PPLL_INVALID 0xFF
1117	serge	77
		78	#define ATOM_SCALER1 0
		79	#define ATOM_SCALER2 1
		80
		81	#define ATOM_SCALER_DISABLE 0
		82	#define ATOM_SCALER_CENTER 1
		83	#define ATOM_SCALER_EXPANSION 2
		84	#define ATOM_SCALER_MULTI_EX 3
		85
		86	#define ATOM_DISABLE 0
		87	#define ATOM_ENABLE 1
		88	#define ATOM_LCD_BLOFF (ATOM_DISABLE+2)
		89	#define ATOM_LCD_BLON (ATOM_ENABLE+2)
		90	#define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3)
		91	#define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5)
		92	#define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5)
		93	#define ATOM_ENCODER_INIT (ATOM_DISABLE+7)
1430	serge	94	#define ATOM_GET_STATUS (ATOM_DISABLE+8)
1117	serge	95
		96	#define ATOM_BLANKING 1
		97	#define ATOM_BLANKING_OFF 0
		98
		99	#define ATOM_CURSOR1 0
		100	#define ATOM_CURSOR2 1
		101
		102	#define ATOM_ICON1 0
		103	#define ATOM_ICON2 1
		104
		105	#define ATOM_CRT1 0
		106	#define ATOM_CRT2 1
		107
		108	#define ATOM_TV_NTSC 1
		109	#define ATOM_TV_NTSCJ 2
		110	#define ATOM_TV_PAL 3
		111	#define ATOM_TV_PALM 4
		112	#define ATOM_TV_PALCN 5
		113	#define ATOM_TV_PALN 6
		114	#define ATOM_TV_PAL60 7
		115	#define ATOM_TV_SECAM 8
		116	#define ATOM_TV_CV 16
		117
		118	#define ATOM_DAC1_PS2 1
		119	#define ATOM_DAC1_CV 2
		120	#define ATOM_DAC1_NTSC 3
		121	#define ATOM_DAC1_PAL 4
		122
		123	#define ATOM_DAC2_PS2 ATOM_DAC1_PS2
		124	#define ATOM_DAC2_CV ATOM_DAC1_CV
		125	#define ATOM_DAC2_NTSC ATOM_DAC1_NTSC
		126	#define ATOM_DAC2_PAL ATOM_DAC1_PAL
		127
		128	#define ATOM_PM_ON 0
		129	#define ATOM_PM_STANDBY 1
		130	#define ATOM_PM_SUSPEND 2
		131	#define ATOM_PM_OFF 3
		132
		133	/* Bit0:{=0:single, =1:dual},
		134	Bit1 {=0:666RGB, =1:888RGB},
		135	Bit2:3:{Grey level}
		136	Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/
		137
		138	#define ATOM_PANEL_MISC_DUAL 0x00000001
		139	#define ATOM_PANEL_MISC_888RGB 0x00000002
		140	#define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C
		141	#define ATOM_PANEL_MISC_FPDI 0x00000010
		142	#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2
		143	#define ATOM_PANEL_MISC_SPATIAL 0x00000020
		144	#define ATOM_PANEL_MISC_TEMPORAL 0x00000040
		145	#define ATOM_PANEL_MISC_API_ENABLED 0x00000080
		146
1430	serge	147
1117	serge	148	#define MEMTYPE_DDR1 "DDR1"
		149	#define MEMTYPE_DDR2 "DDR2"
		150	#define MEMTYPE_DDR3 "DDR3"
		151	#define MEMTYPE_DDR4 "DDR4"
		152
		153	#define ASIC_BUS_TYPE_PCI "PCI"
		154	#define ASIC_BUS_TYPE_AGP "AGP"
		155	#define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS"
		156
		157	/* Maximum size of that FireGL flag string */
		158
1430	serge	159	#define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support
		160	#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING )
1117	serge	161
1430	serge	162	#define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop
1117	serge	163	#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING
		164
1430	serge	165	#define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support
		166	#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING )
1117	serge	167
		168	#define HW_ASSISTED_I2C_STATUS_FAILURE 2
		169	#define HW_ASSISTED_I2C_STATUS_SUCCESS 1
		170
		171	#pragma pack(1) /* BIOS data must use byte aligment */
		172
		173	/* Define offset to location of ROM header. */
		174
		175	#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L
		176	#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L
		177
		178	#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94
		179	#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */
		180	#define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f
		181	#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e
		182
		183	/* Common header for all ROM Data tables.
		184	Every table pointed _ATOM_MASTER_DATA_TABLE has this common header.
		185	And the pointer actually points to this header. */
		186
1430	serge	187	typedef struct _ATOM_COMMON_TABLE_HEADER
		188	{
1117	serge	189	USHORT usStructureSize;
		190	UCHAR ucTableFormatRevision; /Change it when the Parser is not backward compatible /
		191	UCHAR ucTableContentRevision; /Change it only when the table needs to change but the firmware /
		192	/Image can't be updated, while Driver needs to carry the new table! /
1430	serge	193	}ATOM_COMMON_TABLE_HEADER;
1117	serge	194
1430	serge	195	typedef struct _ATOM_ROM_HEADER
		196	{
1117	serge	197	ATOM_COMMON_TABLE_HEADER sHeader;
		198	UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
		199	atombios should init it as "ATOM", don't change the position */
		200	USHORT usBiosRuntimeSegmentAddress;
		201	USHORT usProtectedModeInfoOffset;
		202	USHORT usConfigFilenameOffset;
		203	USHORT usCRC_BlockOffset;
		204	USHORT usBIOS_BootupMessageOffset;
		205	USHORT usInt10Offset;
		206	USHORT usPciBusDevInitCode;
		207	USHORT usIoBaseAddress;
		208	USHORT usSubsystemVendorID;
		209	USHORT usSubsystemID;
		210	USHORT usPCI_InfoOffset;
		211	USHORT usMasterCommandTableOffset; /Offset for SW to get all command table offsets, Don't change the position /
		212	USHORT usMasterDataTableOffset; /Offset for SW to get all data table offsets, Don't change the position /
		213	UCHAR ucExtendedFunctionCode;
		214	UCHAR ucReserved;
1430	serge	215	}ATOM_ROM_HEADER;
1117	serge	216
		217	/==============================Command Table Portion==================================== /
		218
		219	#ifdef UEFI_BUILD
1430	serge	220	#define UTEMP USHORT
		221	#define USHORT void*
1117	serge	222	#endif
		223
1430	serge	224	typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
		225	USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1
		226	USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON
		227	USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
		228	USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios
		229	USHORT DIGxEncoderControl; //Only used by Bios
		230	USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
		231	USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1
		232	USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed
		233	USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2
		234	USHORT GPIOPinControl; //Atomic Table, only used by Bios
		235	USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1
		236	USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1
		237	USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2
		238	USHORT DynamicClockGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
		239	USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
		240	USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
1117	serge	241	USHORT MemoryPLLInit;
1430	serge	242	USHORT AdjustDisplayPll; //only used by Bios
		243	USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
		244	USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios
		245	USHORT ASIC_StaticPwrMgtStatusChange; //Obsolete , only used by Bios
		246	USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2
		247	USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3
		248	USHORT LCD1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
		249	USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
		250	USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
		251	USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
		252	USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead
		253	USHORT GetConditionalGoldenSetting; //only used by Bios
		254	USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1
		255	USHORT TMDSAEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3
		256	USHORT LVDSEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3
		257	USHORT TV1OutputControl; //Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead
		258	USHORT EnableScaler; //Atomic Table, used only by Bios
		259	USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
		260	USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
		261	USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1
		262	USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1
		263	USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios
		264	USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1
		265	USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1
		266	USHORT SetCRTC_Replication; //Atomic Table, used only by Bios
		267	USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1
		268	USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios
1117	serge	269	USHORT UpdateCRTC_DoubleBufferRegisters;
1430	serge	270	USHORT LUT_AutoFill; //Atomic Table, only used by Bios
		271	USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios
		272	USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1
		273	USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1
		274	USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1
		275	USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1
		276	USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
		277	USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios
		278	USHORT MemoryCleanUp; //Atomic Table, only used by Bios
		279	USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios
		280	USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components
		281	USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components
		282	USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init
		283	USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1
		284	USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
		285	USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock
		286	USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock
		287	USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios
		288	USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
		289	USHORT MemoryTraining; //Atomic Table, used only by Bios
		290	USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2
		291	USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
		292	USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
		293	USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
		294	USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
		295	USHORT SetupHWAssistedI2CStatus; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C"
		296	USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
		297	USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
		298	USHORT EnableYUV; //Atomic Table, indirectly used by various SW components,called from EnableVGARender
		299	USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
		300	USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
		301	USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
		302	USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
		303	USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios
		304	USHORT DPEncoderService; //Function Table,only used by Bios
		305	}ATOM_MASTER_LIST_OF_COMMAND_TABLES;
1117	serge	306
1430	serge	307	// For backward compatible
1117	serge	308	#define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction
		309	#define UNIPHYTransmitterControl DIG1TransmitterControl
		310	#define LVTMATransmitterControl DIG2TransmitterControl
		311	#define SetCRTC_DPM_State GetConditionalGoldenSetting
		312	#define SetUniphyInstance ASIC_StaticPwrMgtStatusChange
1430	serge	313	#define HPDInterruptService ReadHWAssistedI2CStatus
		314	#define EnableVGA_Access GetSCLKOverMCLKRatio
1117	serge	315
1430	serge	316	typedef struct _ATOM_MASTER_COMMAND_TABLE
		317	{
1117	serge	318	ATOM_COMMON_TABLE_HEADER sHeader;
		319	ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;
1430	serge	320	}ATOM_MASTER_COMMAND_TABLE;
1117	serge	321
		322	/****************************************************************************/
1430	serge	323	// Structures used in every command table
1117	serge	324	/****************************************************************************/
1430	serge	325	typedef struct _ATOM_TABLE_ATTRIBUTE
		326	{
1117	serge	327	#if ATOM_BIG_ENDIAN
1430	serge	328	USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
		329	USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
		330	USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
1117	serge	331	#else
1430	serge	332	USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
		333	USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
		334	USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
1117	serge	335	#endif
1430	serge	336	}ATOM_TABLE_ATTRIBUTE;
1117	serge	337
1430	serge	338	typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS
		339	{
1117	serge	340	ATOM_TABLE_ATTRIBUTE sbfAccess;
		341	USHORT susAccess;
1430	serge	342	}ATOM_TABLE_ATTRIBUTE_ACCESS;
1117	serge	343
		344	/****************************************************************************/
1430	serge	345	// Common header for all command tables.
		346	// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header.
		347	// And the pointer actually points to this header.
1117	serge	348	/****************************************************************************/
1430	serge	349	typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
		350	{
1117	serge	351	ATOM_COMMON_TABLE_HEADER CommonHeader;
		352	ATOM_TABLE_ATTRIBUTE TableAttribute;
1430	serge	353	}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;
1117	serge	354
		355	/****************************************************************************/
1430	serge	356	// Structures used by ComputeMemoryEnginePLLTable
1117	serge	357	/****************************************************************************/
		358	#define COMPUTE_MEMORY_PLL_PARAM 1
		359	#define COMPUTE_ENGINE_PLL_PARAM 2
		360
1430	serge	361	typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
		362	{
		363	ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
		364	UCHAR ucAction; //0:reserved //1:Memory //2:Engine
		365	UCHAR ucReserved; //may expand to return larger Fbdiv later
		366	UCHAR ucFbDiv; //return value
		367	UCHAR ucPostDiv; //return value
		368	}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS;
1117	serge	369
1430	serge	370	typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
		371	{
		372	ULONG ulClock; //When return, [23:0] return real clock
		373	UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
		374	USHORT usFbDiv; //return Feedback value to be written to register
		375	UCHAR ucPostDiv; //return post div to be written to register
		376	}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2;
1117	serge	377	#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
		378
1430	serge	379
		380	#define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value
		381	#define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
		382	#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition
		383	#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
		384	#define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
		385	#define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
1117	serge	386	#define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK
		387
1430	serge	388	#define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
		389	#define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition
		390	#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
		391	#define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
		392	#define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
1117	serge	393
1430	serge	394	typedef struct _ATOM_COMPUTE_CLOCK_FREQ
		395	{
1117	serge	396	#if ATOM_BIG_ENDIAN
1430	serge	397	ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
		398	ULONG ulClockFreq:24; // in unit of 10kHz
1117	serge	399	#else
1430	serge	400	ULONG ulClockFreq:24; // in unit of 10kHz
		401	ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
1117	serge	402	#endif
1430	serge	403	}ATOM_COMPUTE_CLOCK_FREQ;
1117	serge	404
1430	serge	405	typedef struct _ATOM_S_MPLL_FB_DIVIDER
		406	{
1117	serge	407	USHORT usFbDivFrac;
		408	USHORT usFbDiv;
1430	serge	409	}ATOM_S_MPLL_FB_DIVIDER;
1117	serge	410
1430	serge	411	typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
		412	{
		413	union
		414	{
		415	ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
		416	ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
1117	serge	417	};
1430	serge	418	UCHAR ucRefDiv; //Output Parameter
		419	UCHAR ucPostDiv; //Output Parameter
		420	UCHAR ucCntlFlag; //Output Parameter
1117	serge	421	UCHAR ucReserved;
1430	serge	422	}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3;
1117	serge	423
1430	serge	424	// ucCntlFlag
1117	serge	425	#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1
		426	#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2
		427	#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4
1430	serge	428	#define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8
1117	serge	429
1430	serge	430
		431	// V4 are only used for APU which PLL outside GPU
		432	typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4
		433	{
		434	#if ATOM_BIG_ENDIAN
		435	ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly
		436	ULONG ulClock:24; //Input= target clock, output = actual clock
		437	#else
		438	ULONG ulClock:24; //Input= target clock, output = actual clock
		439	ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly
		440	#endif
		441	}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4;
		442
		443	typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER
		444	{
1117	serge	445	ATOM_COMPUTE_CLOCK_FREQ ulClock;
		446	ULONG ulReserved[2];
1430	serge	447	}DYNAMICE_MEMORY_SETTINGS_PARAMETER;
1117	serge	448
1430	serge	449	typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER
		450	{
1117	serge	451	ATOM_COMPUTE_CLOCK_FREQ ulClock;
		452	ULONG ulMemoryClock;
		453	ULONG ulReserved;
1430	serge	454	}DYNAMICE_ENGINE_SETTINGS_PARAMETER;
1117	serge	455
		456	/****************************************************************************/
1430	serge	457	// Structures used by SetEngineClockTable
1117	serge	458	/****************************************************************************/
1430	serge	459	typedef struct _SET_ENGINE_CLOCK_PARAMETERS
		460	{
		461	ULONG ulTargetEngineClock; //In 10Khz unit
		462	}SET_ENGINE_CLOCK_PARAMETERS;
1117	serge	463
1430	serge	464	typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION
		465	{
		466	ULONG ulTargetEngineClock; //In 10Khz unit
1117	serge	467	COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
1430	serge	468	}SET_ENGINE_CLOCK_PS_ALLOCATION;
1117	serge	469
		470	/****************************************************************************/
1430	serge	471	// Structures used by SetMemoryClockTable
1117	serge	472	/****************************************************************************/
1430	serge	473	typedef struct _SET_MEMORY_CLOCK_PARAMETERS
		474	{
		475	ULONG ulTargetMemoryClock; //In 10Khz unit
		476	}SET_MEMORY_CLOCK_PARAMETERS;
1117	serge	477
1430	serge	478	typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION
		479	{
		480	ULONG ulTargetMemoryClock; //In 10Khz unit
1117	serge	481	COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
1430	serge	482	}SET_MEMORY_CLOCK_PS_ALLOCATION;
1117	serge	483
		484	/****************************************************************************/
1430	serge	485	// Structures used by ASIC_Init.ctb
1117	serge	486	/****************************************************************************/
1430	serge	487	typedef struct _ASIC_INIT_PARAMETERS
		488	{
		489	ULONG ulDefaultEngineClock; //In 10Khz unit
		490	ULONG ulDefaultMemoryClock; //In 10Khz unit
		491	}ASIC_INIT_PARAMETERS;
1117	serge	492
1430	serge	493	typedef struct _ASIC_INIT_PS_ALLOCATION
		494	{
1117	serge	495	ASIC_INIT_PARAMETERS sASICInitClocks;
1430	serge	496	SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure
		497	}ASIC_INIT_PS_ALLOCATION;
1117	serge	498
		499	/****************************************************************************/
1430	serge	500	// Structure used by DynamicClockGatingTable.ctb
1117	serge	501	/****************************************************************************/
1430	serge	502	typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS
		503	{
		504	UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1117	serge	505	UCHAR ucPadding[3];
1430	serge	506	}DYNAMIC_CLOCK_GATING_PARAMETERS;
1117	serge	507	#define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS
		508
		509	/****************************************************************************/
1430	serge	510	// Structure used by EnableASIC_StaticPwrMgtTable.ctb
1117	serge	511	/****************************************************************************/
1430	serge	512	typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
		513	{
		514	UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1117	serge	515	UCHAR ucPadding[3];
1430	serge	516	}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS;
1117	serge	517	#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
		518
		519	/****************************************************************************/
1430	serge	520	// Structures used by DAC_LoadDetectionTable.ctb
1117	serge	521	/****************************************************************************/
1430	serge	522	typedef struct _DAC_LOAD_DETECTION_PARAMETERS
		523	{
		524	USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT}
		525	UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
		526	UCHAR ucMisc; //Valid only when table revision =1.3 and above
		527	}DAC_LOAD_DETECTION_PARAMETERS;
1117	serge	528
1430	serge	529	// DAC_LOAD_DETECTION_PARAMETERS.ucMisc
1117	serge	530	#define DAC_LOAD_MISC_YPrPb 0x01
		531
1430	serge	532	typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION
		533	{
1117	serge	534	DAC_LOAD_DETECTION_PARAMETERS sDacload;
1430	serge	535	ULONG Reserved[2];// Don't set this one, allocation for EXT DAC
		536	}DAC_LOAD_DETECTION_PS_ALLOCATION;
1117	serge	537
		538	/****************************************************************************/
1430	serge	539	// Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb
1117	serge	540	/****************************************************************************/
1430	serge	541	typedef struct _DAC_ENCODER_CONTROL_PARAMETERS
		542	{
		543	USHORT usPixelClock; // in 10KHz; for bios convenient
		544	UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
		545	UCHAR ucAction; // 0: turn off encoder
		546	// 1: setup and turn on encoder
		547	// 7: ATOM_ENCODER_INIT Initialize DAC
		548	}DAC_ENCODER_CONTROL_PARAMETERS;
1117	serge	549
		550	#define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS
		551
		552	/****************************************************************************/
1430	serge	553	// Structures used by DIG1EncoderControlTable
		554	// DIG2EncoderControlTable
		555	// ExternalEncoderControlTable
1117	serge	556	/****************************************************************************/
1430	serge	557	typedef struct _DIG_ENCODER_CONTROL_PARAMETERS
		558	{
		559	USHORT usPixelClock; // in 10KHz; for bios convenient
1117	serge	560	UCHAR ucConfig;
1430	serge	561	// [2] Link Select:
		562	// =0: PHY linkA if bfLane<3
		563	// =1: PHY linkB if bfLanes<3
		564	// =0: PHY linkA+B if bfLanes=3
		565	// [3] Transmitter Sel
		566	// =0: UNIPHY or PCIEPHY
		567	// =1: LVTMA
		568	UCHAR ucAction; // =0: turn off encoder
		569	// =1: turn on encoder
1117	serge	570	UCHAR ucEncoderMode;
1430	serge	571	// =0: DP encoder
		572	// =1: LVDS encoder
		573	// =2: DVI encoder
		574	// =3: HDMI encoder
		575	// =4: SDVO encoder
		576	UCHAR ucLaneNum; // how many lanes to enable
1117	serge	577	UCHAR ucReserved[2];
1430	serge	578	}DIG_ENCODER_CONTROL_PARAMETERS;
1117	serge	579	#define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS
		580	#define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS
		581
1430	serge	582	//ucConfig
1117	serge	583	#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01
		584	#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00
		585	#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01
		586	#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04
		587	#define ATOM_ENCODER_CONFIG_LINKA 0x00
		588	#define ATOM_ENCODER_CONFIG_LINKB 0x04
		589	#define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA
		590	#define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB
		591	#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08
		592	#define ATOM_ENCODER_CONFIG_UNIPHY 0x00
		593	#define ATOM_ENCODER_CONFIG_LVTMA 0x08
		594	#define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00
		595	#define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08
1430	serge	596	#define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0
		597	// ucAction
		598	// ATOM_ENABLE: Enable Encoder
		599	// ATOM_DISABLE: Disable Encoder
1117	serge	600
1430	serge	601	//ucEncoderMode
1117	serge	602	#define ATOM_ENCODER_MODE_DP 0
		603	#define ATOM_ENCODER_MODE_LVDS 1
		604	#define ATOM_ENCODER_MODE_DVI 2
		605	#define ATOM_ENCODER_MODE_HDMI 3
		606	#define ATOM_ENCODER_MODE_SDVO 4
1430	serge	607	#define ATOM_ENCODER_MODE_DP_AUDIO 5
1117	serge	608	#define ATOM_ENCODER_MODE_TV 13
		609	#define ATOM_ENCODER_MODE_CV 14
		610	#define ATOM_ENCODER_MODE_CRT 15
		611
1430	serge	612	typedef struct _ATOM_DIG_ENCODER_CONFIG_V2
		613	{
1117	serge	614	#if ATOM_BIG_ENDIAN
		615	UCHAR ucReserved1:2;
1430	serge	616	UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
		617	UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
1117	serge	618	UCHAR ucReserved:1;
1430	serge	619	UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
1117	serge	620	#else
1430	serge	621	UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
1117	serge	622	UCHAR ucReserved:1;
1430	serge	623	UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
		624	UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
1117	serge	625	UCHAR ucReserved1:2;
		626	#endif
1430	serge	627	}ATOM_DIG_ENCODER_CONFIG_V2;
1117	serge	628
1430	serge	629
		630	typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2
		631	{
		632	USHORT usPixelClock; // in 10KHz; for bios convenient
1117	serge	633	ATOM_DIG_ENCODER_CONFIG_V2 acConfig;
		634	UCHAR ucAction;
		635	UCHAR ucEncoderMode;
1430	serge	636	// =0: DP encoder
		637	// =1: LVDS encoder
		638	// =2: DVI encoder
		639	// =3: HDMI encoder
		640	// =4: SDVO encoder
		641	UCHAR ucLaneNum; // how many lanes to enable
		642	UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS
		643	UCHAR ucReserved;
		644	}DIG_ENCODER_CONTROL_PARAMETERS_V2;
1117	serge	645
1430	serge	646	//ucConfig
1117	serge	647	#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01
		648	#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00
		649	#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01
		650	#define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04
		651	#define ATOM_ENCODER_CONFIG_V2_LINKA 0x00
		652	#define ATOM_ENCODER_CONFIG_V2_LINKB 0x04
		653	#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18
		654	#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00
		655	#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08
		656	#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10
		657
1430	serge	658	// ucAction:
		659	// ATOM_DISABLE
		660	// ATOM_ENABLE
		661	#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08
		662	#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09
		663	#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a
		664	#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b
		665	#define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c
		666	#define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d
		667	#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e
		668	#define ATOM_ENCODER_CMD_SETUP 0x0f
		669
		670	// ucStatus
		671	#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10
		672	#define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00
		673
		674	// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
		675	typedef struct _ATOM_DIG_ENCODER_CONFIG_V3
		676	{
		677	#if ATOM_BIG_ENDIAN
		678	UCHAR ucReserved1:1;
		679	UCHAR ucDigSel:3; // =0: DIGA/B/C/D/E/F
		680	UCHAR ucReserved:3;
		681	UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
		682	#else
		683	UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
		684	UCHAR ucReserved:3;
		685	UCHAR ucDigSel:3; // =0: DIGA/B/C/D/E/F
		686	UCHAR ucReserved1:1;
		687	#endif
		688	}ATOM_DIG_ENCODER_CONFIG_V3;
		689
		690	#define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70
		691
		692
		693	typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3
		694	{
		695	USHORT usPixelClock; // in 10KHz; for bios convenient
		696	ATOM_DIG_ENCODER_CONFIG_V3 acConfig;
		697	UCHAR ucAction;
		698	UCHAR ucEncoderMode;
		699	// =0: DP encoder
		700	// =1: LVDS encoder
		701	// =2: DVI encoder
		702	// =3: HDMI encoder
		703	// =4: SDVO encoder
		704	// =5: DP audio
		705	UCHAR ucLaneNum; // how many lanes to enable
		706	UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
		707	UCHAR ucReserved;
		708	}DIG_ENCODER_CONTROL_PARAMETERS_V3;
		709
		710
		711	// define ucBitPerColor:
		712	#define PANEL_BPC_UNDEFINE 0x00
		713	#define PANEL_6BIT_PER_COLOR 0x01
		714	#define PANEL_8BIT_PER_COLOR 0x02
		715	#define PANEL_10BIT_PER_COLOR 0x03
		716	#define PANEL_12BIT_PER_COLOR 0x04
		717	#define PANEL_16BIT_PER_COLOR 0x05
		718
1117	serge	719	/****************************************************************************/
1430	serge	720	// Structures used by UNIPHYTransmitterControlTable
		721	// LVTMATransmitterControlTable
		722	// DVOOutputControlTable
1117	serge	723	/****************************************************************************/
1430	serge	724	typedef struct _ATOM_DP_VS_MODE
		725	{
1117	serge	726	UCHAR ucLaneSel;
		727	UCHAR ucLaneSet;
1430	serge	728	}ATOM_DP_VS_MODE;
1117	serge	729
1430	serge	730	typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS
		731	{
		732	union
		733	{
		734	USHORT usPixelClock; // in 10KHz; for bios convenient
		735	USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
		736	ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1117	serge	737	};
		738	UCHAR ucConfig;
1430	serge	739	// [0]=0: 4 lane Link,
		740	// =1: 8 lane Link ( Dual Links TMDS )
		741	// [1]=0: InCoherent mode
		742	// =1: Coherent Mode
		743	// [2] Link Select:
		744	// =0: PHY linkA if bfLane<3
		745	// =1: PHY linkB if bfLanes<3
		746	// =0: PHY linkA+B if bfLanes=3
		747	// [5:4]PCIE lane Sel
		748	// =0: lane 0~3 or 0~7
		749	// =1: lane 4~7
		750	// =2: lane 8~11 or 8~15
		751	// =3: lane 12~15
		752	UCHAR ucAction; // =0: turn off encoder
		753	// =1: turn on encoder
1117	serge	754	UCHAR ucReserved[4];
1430	serge	755	}DIG_TRANSMITTER_CONTROL_PARAMETERS;
1117	serge	756
		757	#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS
		758
1430	serge	759	//ucInitInfo
1117	serge	760	#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff
		761
1430	serge	762	//ucConfig
1117	serge	763	#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01
		764	#define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02
		765	#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04
		766	#define ATOM_TRANSMITTER_CONFIG_LINKA 0x00
		767	#define ATOM_TRANSMITTER_CONFIG_LINKB 0x04
		768	#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00
		769	#define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04
		770
1430	serge	771	#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
		772	#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
		773	#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
1117	serge	774
		775	#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30
		776	#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00
		777	#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20
		778	#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30
		779	#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0
		780	#define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00
		781	#define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00
		782	#define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40
		783	#define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80
		784	#define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80
		785	#define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0
		786
1430	serge	787	//ucAction
1117	serge	788	#define ATOM_TRANSMITTER_ACTION_DISABLE 0
		789	#define ATOM_TRANSMITTER_ACTION_ENABLE 1
		790	#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2
		791	#define ATOM_TRANSMITTER_ACTION_LCD_BLON 3
		792	#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4
		793	#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5
		794	#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6
		795	#define ATOM_TRANSMITTER_ACTION_INIT 7
		796	#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8
		797	#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9
		798	#define ATOM_TRANSMITTER_ACTION_SETUP 10
		799	#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11
1430	serge	800	#define ATOM_TRANSMITTER_ACTION_POWER_ON 12
		801	#define ATOM_TRANSMITTER_ACTION_POWER_OFF 13
1117	serge	802
1430	serge	803	// Following are used for DigTransmitterControlTable ver1.2
		804	typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2
		805	{
1117	serge	806	#if ATOM_BIG_ENDIAN
1430	serge	807	UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
		808	// =1 Dig Transmitter 2 ( Uniphy CD )
		809	// =2 Dig Transmitter 3 ( Uniphy EF )
1117	serge	810	UCHAR ucReserved:1;
1430	serge	811	UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
		812	UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
		813	UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
		814	// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1117	serge	815
1430	serge	816	UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
		817	UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1117	serge	818	#else
1430	serge	819	UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
		820	UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
		821	UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
		822	// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
		823	UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
		824	UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1117	serge	825	UCHAR ucReserved:1;
1430	serge	826	UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
		827	// =1 Dig Transmitter 2 ( Uniphy CD )
		828	// =2 Dig Transmitter 3 ( Uniphy EF )
1117	serge	829	#endif
1430	serge	830	}ATOM_DIG_TRANSMITTER_CONFIG_V2;
1117	serge	831
1430	serge	832	//ucConfig
		833	//Bit0
1117	serge	834	#define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01
		835
1430	serge	836	//Bit1
1117	serge	837	#define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02
		838
1430	serge	839	//Bit2
1117	serge	840	#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04
		841	#define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00
		842	#define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04
		843
1430	serge	844	// Bit3
1117	serge	845	#define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08
1430	serge	846	#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
		847	#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
1117	serge	848
1430	serge	849	// Bit4
1117	serge	850	#define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10
		851
1430	serge	852	// Bit7:6
1117	serge	853	#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0
1430	serge	854	#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB
		855	#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD
		856	#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF
1117	serge	857
1430	serge	858	typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2
		859	{
		860	union
		861	{
		862	USHORT usPixelClock; // in 10KHz; for bios convenient
		863	USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
		864	ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1117	serge	865	};
		866	ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig;
1430	serge	867	UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1117	serge	868	UCHAR ucReserved[4];
1430	serge	869	}DIG_TRANSMITTER_CONTROL_PARAMETERS_V2;
1117	serge	870
1430	serge	871	typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3
		872	{
		873	#if ATOM_BIG_ENDIAN
		874	UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
		875	// =1 Dig Transmitter 2 ( Uniphy CD )
		876	// =2 Dig Transmitter 3 ( Uniphy EF )
		877	UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
		878	UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
		879	UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
		880	// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
		881	UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
		882	UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
		883	#else
		884	UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
		885	UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
		886	UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
		887	// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
		888	UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
		889	UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
		890	UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
		891	// =1 Dig Transmitter 2 ( Uniphy CD )
		892	// =2 Dig Transmitter 3 ( Uniphy EF )
		893	#endif
		894	}ATOM_DIG_TRANSMITTER_CONFIG_V3;
		895
		896	typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3
		897	{
		898	union
		899	{
		900	USHORT usPixelClock; // in 10KHz; for bios convenient
		901	USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
		902	ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
		903	};
		904	ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig;
		905	UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
		906	UCHAR ucLaneNum;
		907	UCHAR ucReserved[3];
		908	}DIG_TRANSMITTER_CONTROL_PARAMETERS_V3;
		909
		910	//ucConfig
		911	//Bit0
		912	#define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01
		913
		914	//Bit1
		915	#define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02
		916
		917	//Bit2
		918	#define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04
		919	#define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00
		920	#define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04
		921
		922	// Bit3
		923	#define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08
		924	#define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00
		925	#define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08
		926
		927	// Bit5:4
		928	#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30
		929	#define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00
		930	#define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10
		931	#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20
		932
		933	// Bit7:6
		934	#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0
		935	#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB
		936	#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD
		937	#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF
		938
		939	/****************************************************************************/
		940	// Structures used by DAC1OuputControlTable
		941	// DAC2OuputControlTable
		942	// LVTMAOutputControlTable (Before DEC30)
		943	// TMDSAOutputControlTable (Before DEC30)
1117	serge	944	/****************************************************************************/
1430	serge	945	typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
		946	{
		947	UCHAR ucAction; // Possible input:ATOM_ENABLE\|\|ATOMDISABLE
		948	// When the display is LCD, in addition to above:
		949	// ATOM_LCD_BLOFF\|\| ATOM_LCD_BLON \|\|ATOM_LCD_BL_BRIGHTNESS_CONTROL\|\|ATOM_LCD_SELFTEST_START\|\|
		950	// ATOM_LCD_SELFTEST_STOP
1117	serge	951
1430	serge	952	UCHAR aucPadding[3]; // padding to DWORD aligned
		953	}DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS;
1117	serge	954
		955	#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
		956
1430	serge	957
1117	serge	958	#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
		959	#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
		960
		961	#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
		962	#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
		963
		964	#define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
		965	#define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
		966
		967	#define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
		968	#define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
		969
		970	#define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
		971	#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
		972
		973	#define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
		974	#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
		975
		976	#define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
		977	#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
		978
		979	#define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
		980	#define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION
		981	#define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS
		982
		983	/****************************************************************************/
1430	serge	984	// Structures used by BlankCRTCTable
1117	serge	985	/****************************************************************************/
1430	serge	986	typedef struct _BLANK_CRTC_PARAMETERS
		987	{
		988	UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
		989	UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF
1117	serge	990	USHORT usBlackColorRCr;
		991	USHORT usBlackColorGY;
		992	USHORT usBlackColorBCb;
1430	serge	993	}BLANK_CRTC_PARAMETERS;
1117	serge	994	#define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS
		995
		996	/****************************************************************************/
1430	serge	997	// Structures used by EnableCRTCTable
		998	// EnableCRTCMemReqTable
		999	// UpdateCRTC_DoubleBufferRegistersTable
		1000	/****************************************************************************/
		1001	typedef struct _ENABLE_CRTC_PARAMETERS
		1002	{
		1003	UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
		1004	UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1117	serge	1005	UCHAR ucPadding[2];
1430	serge	1006	}ENABLE_CRTC_PARAMETERS;
1117	serge	1007	#define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS
		1008
		1009	/****************************************************************************/
1430	serge	1010	// Structures used by SetCRTC_OverScanTable
1117	serge	1011	/****************************************************************************/
1430	serge	1012	typedef struct _SET_CRTC_OVERSCAN_PARAMETERS
		1013	{
		1014	USHORT usOverscanRight; // right
		1015	USHORT usOverscanLeft; // left
		1016	USHORT usOverscanBottom; // bottom
		1017	USHORT usOverscanTop; // top
		1018	UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1117	serge	1019	UCHAR ucPadding[3];
1430	serge	1020	}SET_CRTC_OVERSCAN_PARAMETERS;
1117	serge	1021	#define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS
		1022
		1023	/****************************************************************************/
1430	serge	1024	// Structures used by SetCRTC_ReplicationTable
1117	serge	1025	/****************************************************************************/
1430	serge	1026	typedef struct _SET_CRTC_REPLICATION_PARAMETERS
		1027	{
		1028	UCHAR ucH_Replication; // horizontal replication
		1029	UCHAR ucV_Replication; // vertical replication
		1030	UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1117	serge	1031	UCHAR ucPadding;
1430	serge	1032	}SET_CRTC_REPLICATION_PARAMETERS;
1117	serge	1033	#define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS
		1034
		1035	/****************************************************************************/
1430	serge	1036	// Structures used by SelectCRTC_SourceTable
1117	serge	1037	/****************************************************************************/
1430	serge	1038	typedef struct _SELECT_CRTC_SOURCE_PARAMETERS
		1039	{
		1040	UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
		1041	UCHAR ucDevice; // ATOM_DEVICE_CRT1\|ATOM_DEVICE_CRT2\|....
1117	serge	1042	UCHAR ucPadding[2];
1430	serge	1043	}SELECT_CRTC_SOURCE_PARAMETERS;
1117	serge	1044	#define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS
		1045
1430	serge	1046	typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2
		1047	{
		1048	UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
		1049	UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
		1050	UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
1117	serge	1051	UCHAR ucPadding;
1430	serge	1052	}SELECT_CRTC_SOURCE_PARAMETERS_V2;
1117	serge	1053
1430	serge	1054	//ucEncoderID
		1055	//#define ASIC_INT_DAC1_ENCODER_ID 0x00
		1056	//#define ASIC_INT_TV_ENCODER_ID 0x02
		1057	//#define ASIC_INT_DIG1_ENCODER_ID 0x03
		1058	//#define ASIC_INT_DAC2_ENCODER_ID 0x04
		1059	//#define ASIC_EXT_TV_ENCODER_ID 0x06
		1060	//#define ASIC_INT_DVO_ENCODER_ID 0x07
		1061	//#define ASIC_INT_DIG2_ENCODER_ID 0x09
		1062	//#define ASIC_EXT_DIG_ENCODER_ID 0x05
1117	serge	1063
1430	serge	1064	//ucEncodeMode
		1065	//#define ATOM_ENCODER_MODE_DP 0
		1066	//#define ATOM_ENCODER_MODE_LVDS 1
		1067	//#define ATOM_ENCODER_MODE_DVI 2
		1068	//#define ATOM_ENCODER_MODE_HDMI 3
		1069	//#define ATOM_ENCODER_MODE_SDVO 4
		1070	//#define ATOM_ENCODER_MODE_TV 13
		1071	//#define ATOM_ENCODER_MODE_CV 14
		1072	//#define ATOM_ENCODER_MODE_CRT 15
1117	serge	1073
1430	serge	1074	/****************************************************************************/
		1075	// Structures used by SetPixelClockTable
		1076	// GetPixelClockTable
		1077	/****************************************************************************/
		1078	//Major revision=1., Minor revision=1
		1079	typedef struct _PIXEL_CLOCK_PARAMETERS
		1080	{
		1081	USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClkFB_Div)/(Ref_DivPost_Div)
		1082	// 0 means disable PPLL
		1083	USHORT usRefDiv; // Reference divider
		1084	USHORT usFbDiv; // feedback divider
		1085	UCHAR ucPostDiv; // post divider
		1086	UCHAR ucFracFbDiv; // fractional feedback divider
		1087	UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
		1088	UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
		1089	UCHAR ucCRTC; // Which CRTC uses this Ppll
1117	serge	1090	UCHAR ucPadding;
1430	serge	1091	}PIXEL_CLOCK_PARAMETERS;
1117	serge	1092
1430	serge	1093	//Major revision=1., Minor revision=2, add ucMiscIfno
		1094	//ucMiscInfo:
1117	serge	1095	#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1
		1096	#define MISC_DEVICE_INDEX_MASK 0xF0
		1097	#define MISC_DEVICE_INDEX_SHIFT 4
		1098
1430	serge	1099	typedef struct _PIXEL_CLOCK_PARAMETERS_V2
		1100	{
		1101	USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClkFB_Div)/(Ref_DivPost_Div)
		1102	// 0 means disable PPLL
		1103	USHORT usRefDiv; // Reference divider
		1104	USHORT usFbDiv; // feedback divider
		1105	UCHAR ucPostDiv; // post divider
		1106	UCHAR ucFracFbDiv; // fractional feedback divider
		1107	UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
		1108	UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
		1109	UCHAR ucCRTC; // Which CRTC uses this Ppll
		1110	UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog
		1111	}PIXEL_CLOCK_PARAMETERS_V2;
1117	serge	1112
1430	serge	1113	//Major revision=1., Minor revision=3, structure/definition change
		1114	//ucEncoderMode:
		1115	//ATOM_ENCODER_MODE_DP
		1116	//ATOM_ENOCDER_MODE_LVDS
		1117	//ATOM_ENOCDER_MODE_DVI
		1118	//ATOM_ENOCDER_MODE_HDMI
		1119	//ATOM_ENOCDER_MODE_SDVO
		1120	//ATOM_ENCODER_MODE_TV 13
		1121	//ATOM_ENCODER_MODE_CV 14
		1122	//ATOM_ENCODER_MODE_CRT 15
1117	serge	1123
1430	serge	1124	//ucDVOConfig
		1125	//#define DVO_ENCODER_CONFIG_RATE_SEL 0x01
		1126	//#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00
		1127	//#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01
		1128	//#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c
		1129	//#define DVO_ENCODER_CONFIG_LOW12BIT 0x00
		1130	//#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04
		1131	//#define DVO_ENCODER_CONFIG_24BIT 0x08
1117	serge	1132
1430	serge	1133	//ucMiscInfo: also changed, see below
1117	serge	1134	#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01
		1135	#define PIXEL_CLOCK_MISC_VGA_MODE 0x02
		1136	#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04
		1137	#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00
		1138	#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04
		1139	#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08
1430	serge	1140	#define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10
		1141	// V1.4 for RoadRunner
		1142	#define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10
		1143	#define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20
1117	serge	1144
1430	serge	1145	typedef struct _PIXEL_CLOCK_PARAMETERS_V3
		1146	{
		1147	USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClkFB_Div)/(Ref_DivPost_Div)
		1148	// 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
		1149	USHORT usRefDiv; // Reference divider
		1150	USHORT usFbDiv; // feedback divider
		1151	UCHAR ucPostDiv; // post divider
		1152	UCHAR ucFracFbDiv; // fractional feedback divider
		1153	UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
		1154	UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h
		1155	union
		1156	{
		1157	UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
		1158	UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit
1117	serge	1159	};
1430	serge	1160	UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel
		1161	// bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
		1162	// bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider
		1163	}PIXEL_CLOCK_PARAMETERS_V3;
1117	serge	1164
		1165	#define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2
		1166	#define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST
		1167
1430	serge	1168	typedef struct _PIXEL_CLOCK_PARAMETERS_V5
		1169	{
		1170	UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to
		1171	// drive the pixel clock. not used for DCPLL case.
		1172	union{
		1173	UCHAR ucReserved;
		1174	UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed.
		1175	};
		1176	USHORT usPixelClock; // target the pixel clock to drive the CRTC timing
		1177	// 0 means disable PPLL/DCPLL.
		1178	USHORT usFbDiv; // feedback divider integer part.
		1179	UCHAR ucPostDiv; // post divider.
		1180	UCHAR ucRefDiv; // Reference divider
		1181	UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
		1182	UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
		1183	// indicate which graphic encoder will be used.
		1184	UCHAR ucEncoderMode; // Encoder mode:
		1185	UCHAR ucMiscInfo; // bit[0]= Force program PPLL
		1186	// bit[1]= when VGA timing is used.
		1187	// bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
		1188	// bit[4]= RefClock source for PPLL.
		1189	// =0: XTLAIN( default mode )
		1190	// =1: other external clock source, which is pre-defined
		1191	// by VBIOS depend on the feature required.
		1192	// bit[7:5]: reserved.
		1193	ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
		1194
		1195	}PIXEL_CLOCK_PARAMETERS_V5;
		1196
		1197	#define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01
		1198	#define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02
		1199	#define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c
		1200	#define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00
		1201	#define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04
		1202	#define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08
		1203	#define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10
		1204
		1205	typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2
		1206	{
		1207	PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput;
		1208	}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2;
		1209
		1210	typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2
		1211	{
		1212	UCHAR ucStatus;
		1213	UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock
		1214	UCHAR ucReserved[2];
		1215	}GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2;
		1216
		1217	typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3
		1218	{
		1219	PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput;
		1220	}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3;
		1221
1117	serge	1222	/****************************************************************************/
1430	serge	1223	// Structures used by AdjustDisplayPllTable
1117	serge	1224	/****************************************************************************/
1430	serge	1225	typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS
		1226	{
1117	serge	1227	USHORT usPixelClock;
		1228	UCHAR ucTransmitterID;
		1229	UCHAR ucEncodeMode;
1430	serge	1230	union
		1231	{
		1232	UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit
		1233	UCHAR ucConfig; //if none DVO, not defined yet
1117	serge	1234	};
		1235	UCHAR ucReserved[3];
1430	serge	1236	}ADJUST_DISPLAY_PLL_PARAMETERS;
1117	serge	1237
		1238	#define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10
		1239	#define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS
		1240
1430	serge	1241	typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3
		1242	{
		1243	USHORT usPixelClock; // target pixel clock
		1244	UCHAR ucTransmitterID; // transmitter id defined in objectid.h
		1245	UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI
		1246	UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX
		1247	UCHAR ucReserved[3];
		1248	}ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3;
		1249
		1250	// usDispPllConfig v1.2 for RoadRunner
		1251	#define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO
		1252	#define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO
		1253	#define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO
		1254	#define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO
		1255	#define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO
		1256	#define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO
		1257	#define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO
		1258	#define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS
		1259	#define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI
		1260	#define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS
		1261
		1262
		1263	typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3
		1264	{
		1265	ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc
		1266	UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given )
		1267	UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider
		1268	UCHAR ucReserved[2];
		1269	}ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3;
		1270
		1271	typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3
		1272	{
		1273	union
		1274	{
		1275	ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput;
		1276	ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput;
		1277	};
		1278	} ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3;
		1279
1117	serge	1280	/****************************************************************************/
1430	serge	1281	// Structures used by EnableYUVTable
1117	serge	1282	/****************************************************************************/
1430	serge	1283	typedef struct _ENABLE_YUV_PARAMETERS
		1284	{
		1285	UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
		1286	UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format
1117	serge	1287	UCHAR ucPadding[2];
1430	serge	1288	}ENABLE_YUV_PARAMETERS;
1117	serge	1289	#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS
		1290
		1291	/****************************************************************************/
1430	serge	1292	// Structures used by GetMemoryClockTable
1117	serge	1293	/****************************************************************************/
1430	serge	1294	typedef struct _GET_MEMORY_CLOCK_PARAMETERS
		1295	{
		1296	ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
1117	serge	1297	} GET_MEMORY_CLOCK_PARAMETERS;
		1298	#define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS
		1299
		1300	/****************************************************************************/
1430	serge	1301	// Structures used by GetEngineClockTable
1117	serge	1302	/****************************************************************************/
1430	serge	1303	typedef struct _GET_ENGINE_CLOCK_PARAMETERS
		1304	{
		1305	ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
1117	serge	1306	} GET_ENGINE_CLOCK_PARAMETERS;
		1307	#define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS
		1308
		1309	/****************************************************************************/
1430	serge	1310	// Following Structures and constant may be obsolete
1117	serge	1311	/****************************************************************************/
1430	serge	1312	//Maxium 8 bytes,the data read in will be placed in the parameter space.
		1313	//Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
		1314	typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
		1315	{
		1316	USHORT usPrescale; //Ratio between Engine clock and I2C clock
		1317	USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID
		1318	USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status
		1319	//WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte
		1320	UCHAR ucSlaveAddr; //Read from which slave
		1321	UCHAR ucLineNumber; //Read from which HW assisted line
		1322	}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS;
1117	serge	1323	#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
		1324
1430	serge	1325
1117	serge	1326	#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0
		1327	#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1
		1328	#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2
		1329	#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3
		1330	#define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4
		1331
1430	serge	1332	typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
		1333	{
		1334	USHORT usPrescale; //Ratio between Engine clock and I2C clock
		1335	USHORT usByteOffset; //Write to which byte
		1336	//Upper portion of usByteOffset is Format of data
		1337	//1bytePS+offsetPS
		1338	//2bytesPS+offsetPS
		1339	//blockID+offsetPS
		1340	//blockID+offsetID
		1341	//blockID+counterID+offsetID
		1342	UCHAR ucData; //PS data1
		1343	UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2
		1344	UCHAR ucSlaveAddr; //Write to which slave
		1345	UCHAR ucLineNumber; //Write from which HW assisted line
		1346	}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS;
1117	serge	1347
		1348	#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
		1349
1430	serge	1350	typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS
		1351	{
		1352	USHORT usPrescale; //Ratio between Engine clock and I2C clock
		1353	UCHAR ucSlaveAddr; //Write to which slave
		1354	UCHAR ucLineNumber; //Write from which HW assisted line
		1355	}SET_UP_HW_I2C_DATA_PARAMETERS;
1117	serge	1356
1430	serge	1357
1117	serge	1358	/**************************************************************************/
		1359	#define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
		1360
		1361	/****************************************************************************/
1430	serge	1362	// Structures used by PowerConnectorDetectionTable
1117	serge	1363	/****************************************************************************/
1430	serge	1364	typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS
		1365	{
		1366	UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
1117	serge	1367	UCHAR ucPwrBehaviorId;
1430	serge	1368	USHORT usPwrBudget; //how much power currently boot to in unit of watt
		1369	}POWER_CONNECTOR_DETECTION_PARAMETERS;
1117	serge	1370
1430	serge	1371	typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION
		1372	{
		1373	UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
1117	serge	1374	UCHAR ucReserved;
1430	serge	1375	USHORT usPwrBudget; //how much power currently boot to in unit of watt
1117	serge	1376	WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
1430	serge	1377	}POWER_CONNECTOR_DETECTION_PS_ALLOCATION;
1117	serge	1378
		1379	/**************************LVDS SS Command Table Definitions********************/
		1380
		1381	/****************************************************************************/
1430	serge	1382	// Structures used by EnableSpreadSpectrumOnPPLLTable
1117	serge	1383	/****************************************************************************/
1430	serge	1384	typedef struct _ENABLE_LVDS_SS_PARAMETERS
		1385	{
1117	serge	1386	USHORT usSpreadSpectrumPercentage;
1430	serge	1387	UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
		1388	UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
		1389	UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
1117	serge	1390	UCHAR ucPadding[3];
1430	serge	1391	}ENABLE_LVDS_SS_PARAMETERS;
1117	serge	1392
1430	serge	1393	//ucTableFormatRevision=1,ucTableContentRevision=2
		1394	typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2
		1395	{
1117	serge	1396	USHORT usSpreadSpectrumPercentage;
1430	serge	1397	UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
		1398	UCHAR ucSpreadSpectrumStep; //
		1399	UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
1117	serge	1400	UCHAR ucSpreadSpectrumDelay;
		1401	UCHAR ucSpreadSpectrumRange;
		1402	UCHAR ucPadding;
1430	serge	1403	}ENABLE_LVDS_SS_PARAMETERS_V2;
1117	serge	1404
1430	serge	1405	//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.
		1406	typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL
		1407	{
1117	serge	1408	USHORT usSpreadSpectrumPercentage;
1430	serge	1409	UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
		1410	UCHAR ucSpreadSpectrumStep; //
		1411	UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1117	serge	1412	UCHAR ucSpreadSpectrumDelay;
		1413	UCHAR ucSpreadSpectrumRange;
1430	serge	1414	UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2
		1415	}ENABLE_SPREAD_SPECTRUM_ON_PPLL;
1117	serge	1416
1430	serge	1417	typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2
		1418	{
		1419	USHORT usSpreadSpectrumPercentage;
		1420	UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
		1421	// Bit[1]: 1-Ext. 0-Int.
		1422	// Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
		1423	// Bits[7:4] reserved
		1424	UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
		1425	USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
		1426	USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC
		1427	}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2;
		1428
		1429	#define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00
		1430	#define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01
		1431	#define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02
		1432	#define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c
		1433	#define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00
		1434	#define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04
		1435	#define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08
		1436	#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF
		1437	#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0
		1438	#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00
		1439	#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8
		1440
1117	serge	1441	#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL
		1442
		1443	/**************************************************************************/
		1444
1430	serge	1445	typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION
		1446	{
1117	serge	1447	PIXEL_CLOCK_PARAMETERS sPCLKInput;
1430	serge	1448	ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion
		1449	}SET_PIXEL_CLOCK_PS_ALLOCATION;
1117	serge	1450
		1451	#define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION
		1452
		1453	/****************************************************************************/
1430	serge	1454	// Structures used by ###
1117	serge	1455	/****************************************************************************/
1430	serge	1456	typedef struct _MEMORY_TRAINING_PARAMETERS
		1457	{
		1458	ULONG ulTargetMemoryClock; //In 10Khz unit
		1459	}MEMORY_TRAINING_PARAMETERS;
1117	serge	1460	#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS
		1461
1430	serge	1462
1117	serge	1463	/**************************LVDS and other encoder command table definitions ********************/
		1464
1430	serge	1465
		1466	/****************************************************************************/
		1467	// Structures used by LVDSEncoderControlTable (Before DCE30)
		1468	// LVTMAEncoderControlTable (Before DCE30)
		1469	// TMDSAEncoderControlTable (Before DCE30)
1117	serge	1470	/****************************************************************************/
1430	serge	1471	typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS
		1472	{
		1473	USHORT usPixelClock; // in 10KHz; for bios convenient
		1474	UCHAR ucMisc; // bit0=0: Enable single link
		1475	// =1: Enable dual link
		1476	// Bit1=0: 666RGB
		1477	// =1: 888RGB
		1478	UCHAR ucAction; // 0: turn off encoder
		1479	// 1: setup and turn on encoder
		1480	}LVDS_ENCODER_CONTROL_PARAMETERS;
1117	serge	1481
		1482	#define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS
		1483
		1484	#define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS
		1485	#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS
		1486
		1487	#define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS
		1488	#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS
		1489
		1490
1430	serge	1491	//ucTableFormatRevision=1,ucTableContentRevision=2
		1492	typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2
		1493	{
		1494	USHORT usPixelClock; // in 10KHz; for bios convenient
		1495	UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below
		1496	UCHAR ucAction; // 0: turn off encoder
		1497	// 1: setup and turn on encoder
		1498	UCHAR ucTruncate; // bit0=0: Disable truncate
		1499	// =1: Enable truncate
		1500	// bit4=0: 666RGB
		1501	// =1: 888RGB
		1502	UCHAR ucSpatial; // bit0=0: Disable spatial dithering
		1503	// =1: Enable spatial dithering
		1504	// bit4=0: 666RGB
		1505	// =1: 888RGB
		1506	UCHAR ucTemporal; // bit0=0: Disable temporal dithering
		1507	// =1: Enable temporal dithering
		1508	// bit4=0: 666RGB
		1509	// =1: 888RGB
		1510	// bit5=0: Gray level 2
		1511	// =1: Gray level 4
		1512	UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E
		1513	// =1: 25FRC_SEL pattern F
		1514	// bit6:5=0: 50FRC_SEL pattern A
		1515	// =1: 50FRC_SEL pattern B
		1516	// =2: 50FRC_SEL pattern C
		1517	// =3: 50FRC_SEL pattern D
		1518	// bit7=0: 75FRC_SEL pattern E
		1519	// =1: 75FRC_SEL pattern F
		1520	}LVDS_ENCODER_CONTROL_PARAMETERS_V2;
		1521
1117	serge	1522	#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
		1523
		1524	#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
		1525	#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
		1526
		1527	#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
		1528	#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2
		1529
		1530	#define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2
		1531	#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
		1532
		1533	#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
		1534	#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3
		1535
		1536	#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
		1537	#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3
		1538
		1539	/****************************************************************************/
1430	serge	1540	// Structures used by ###
1117	serge	1541	/****************************************************************************/
1430	serge	1542	typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS
		1543	{
		1544	UCHAR ucEnable; // Enable or Disable External TMDS encoder
		1545	UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}
1117	serge	1546	UCHAR ucPadding[2];
1430	serge	1547	}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS;
1117	serge	1548
1430	serge	1549	typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION
		1550	{
1117	serge	1551	ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder;
1430	serge	1552	WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
		1553	}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION;
1117	serge	1554
		1555	#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
		1556
1430	serge	1557	typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2
		1558	{
1117	serge	1559	ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder;
1430	serge	1560	WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
		1561	}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2;
1117	serge	1562
1430	serge	1563	typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION
		1564	{
1117	serge	1565	DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder;
		1566	WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
1430	serge	1567	}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION;
1117	serge	1568
		1569	/****************************************************************************/
1430	serge	1570	// Structures used by DVOEncoderControlTable
1117	serge	1571	/****************************************************************************/
1430	serge	1572	//ucTableFormatRevision=1,ucTableContentRevision=3
1117	serge	1573
1430	serge	1574	//ucDVOConfig:
1117	serge	1575	#define DVO_ENCODER_CONFIG_RATE_SEL 0x01
		1576	#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00
		1577	#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01
		1578	#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c
		1579	#define DVO_ENCODER_CONFIG_LOW12BIT 0x00
		1580	#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04
		1581	#define DVO_ENCODER_CONFIG_24BIT 0x08
		1582
1430	serge	1583	typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3
		1584	{
1117	serge	1585	USHORT usPixelClock;
		1586	UCHAR ucDVOConfig;
1430	serge	1587	UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
1117	serge	1588	UCHAR ucReseved[4];
1430	serge	1589	}DVO_ENCODER_CONTROL_PARAMETERS_V3;
1117	serge	1590	#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3
		1591
1430	serge	1592	//ucTableFormatRevision=1
		1593	//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for
		1594	// bit1=0: non-coherent mode
		1595	// =1: coherent mode
1117	serge	1596
1430	serge	1597	//==========================================================================================
		1598	//Only change is here next time when changing encoder parameter definitions again!
1117	serge	1599	#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
		1600	#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST
		1601
		1602	#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
		1603	#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST
		1604
		1605	#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
		1606	#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST
		1607
		1608	#define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS
		1609	#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION
		1610
1430	serge	1611	//==========================================================================================
1117	serge	1612	#define PANEL_ENCODER_MISC_DUAL 0x01
		1613	#define PANEL_ENCODER_MISC_COHERENT 0x02
		1614	#define PANEL_ENCODER_MISC_TMDS_LINKB 0x04
		1615	#define PANEL_ENCODER_MISC_HDMI_TYPE 0x08
		1616
		1617	#define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE
		1618	#define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE
		1619	#define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1)
		1620
		1621	#define PANEL_ENCODER_TRUNCATE_EN 0x01
		1622	#define PANEL_ENCODER_TRUNCATE_DEPTH 0x10
		1623	#define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01
		1624	#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10
		1625	#define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01
		1626	#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10
		1627	#define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20
		1628	#define PANEL_ENCODER_25FRC_MASK 0x10
		1629	#define PANEL_ENCODER_25FRC_E 0x00
		1630	#define PANEL_ENCODER_25FRC_F 0x10
		1631	#define PANEL_ENCODER_50FRC_MASK 0x60
		1632	#define PANEL_ENCODER_50FRC_A 0x00
		1633	#define PANEL_ENCODER_50FRC_B 0x20
		1634	#define PANEL_ENCODER_50FRC_C 0x40
		1635	#define PANEL_ENCODER_50FRC_D 0x60
		1636	#define PANEL_ENCODER_75FRC_MASK 0x80
		1637	#define PANEL_ENCODER_75FRC_E 0x00
		1638	#define PANEL_ENCODER_75FRC_F 0x80
		1639
		1640	/****************************************************************************/
1430	serge	1641	// Structures used by SetVoltageTable
1117	serge	1642	/****************************************************************************/
		1643	#define SET_VOLTAGE_TYPE_ASIC_VDDC 1
		1644	#define SET_VOLTAGE_TYPE_ASIC_MVDDC 2
		1645	#define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3
		1646	#define SET_VOLTAGE_TYPE_ASIC_VDDCI 4
		1647	#define SET_VOLTAGE_INIT_MODE 5
1430	serge	1648	#define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic
1117	serge	1649
		1650	#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1
		1651	#define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2
		1652	#define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4
		1653
		1654	#define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0
		1655	#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1
		1656	#define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2
		1657
1430	serge	1658	typedef struct _SET_VOLTAGE_PARAMETERS
		1659	{
		1660	UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
		1661	UCHAR ucVoltageMode; // To set all, to set source A or source B or ...
		1662	UCHAR ucVoltageIndex; // An index to tell which voltage level
1117	serge	1663	UCHAR ucReserved;
1430	serge	1664	}SET_VOLTAGE_PARAMETERS;
1117	serge	1665
1430	serge	1666	typedef struct _SET_VOLTAGE_PARAMETERS_V2
		1667	{
		1668	UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
		1669	UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode
		1670	USHORT usVoltageLevel; // real voltage level
		1671	}SET_VOLTAGE_PARAMETERS_V2;
1117	serge	1672
1430	serge	1673	typedef struct _SET_VOLTAGE_PS_ALLOCATION
		1674	{
1117	serge	1675	SET_VOLTAGE_PARAMETERS sASICSetVoltage;
		1676	WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
1430	serge	1677	}SET_VOLTAGE_PS_ALLOCATION;
1117	serge	1678
		1679	/****************************************************************************/
1430	serge	1680	// Structures used by TVEncoderControlTable
1117	serge	1681	/****************************************************************************/
1430	serge	1682	typedef struct _TV_ENCODER_CONTROL_PARAMETERS
		1683	{
		1684	USHORT usPixelClock; // in 10KHz; for bios convenient
		1685	UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..."
		1686	UCHAR ucAction; // 0: turn off encoder
		1687	// 1: setup and turn on encoder
		1688	}TV_ENCODER_CONTROL_PARAMETERS;
1117	serge	1689
1430	serge	1690	typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION
		1691	{
1117	serge	1692	TV_ENCODER_CONTROL_PARAMETERS sTVEncoder;
1430	serge	1693	WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one
		1694	}TV_ENCODER_CONTROL_PS_ALLOCATION;
1117	serge	1695
1430	serge	1696	//==============================Data Table Portion====================================
1117	serge	1697
		1698	/****************************************************************************/
1430	serge	1699	// Structure used in Data.mtb
1117	serge	1700	/****************************************************************************/
1430	serge	1701	typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES
		1702	{
		1703	USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position!
		1704	USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios
		1705	USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios
		1706	USHORT StandardVESA_Timing; // Only used by Bios
		1707	USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4
		1708	USHORT DAC_Info; // Will be obsolete from R600
		1709	USHORT LVDS_Info; // Shared by various SW components,latest version 1.1
		1710	USHORT TMDS_Info; // Will be obsolete from R600
		1711	USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1
		1712	USHORT SupportedDevicesInfo; // Will be obsolete from R600
		1713	USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600
		1714	USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600
		1715	USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1
		1716	USHORT VESA_ToInternalModeLUT; // Only used by Bios
		1717	USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600
		1718	USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600
		1719	USHORT CompassionateData; // Will be obsolete from R600
		1720	USHORT SaveRestoreInfo; // Only used by Bios
		1721	USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
		1722	USHORT OemInfo; // Defined and used by external SW, should be obsolete soon
		1723	USHORT XTMDS_Info; // Will be obsolete from R600
		1724	USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
		1725	USHORT Object_Header; // Shared by various SW components,latest version 1.1
		1726	USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!!
		1727	USHORT MC_InitParameter; // Only used by command table
		1728	USHORT ASIC_VDDC_Info; // Will be obsolete from R600
		1729	USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info"
		1730	USHORT TV_VideoMode; // Only used by command table
		1731	USHORT VRAM_Info; // Only used by command table, latest version 1.3
		1732	USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1
		1733	USHORT IntegratedSystemInfo; // Shared by various SW components
		1734	USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
		1735	USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1
		1736	USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1
		1737	}ATOM_MASTER_LIST_OF_DATA_TABLES;
1117	serge	1738
1430	serge	1739	typedef struct _ATOM_MASTER_DATA_TABLE
		1740	{
1117	serge	1741	ATOM_COMMON_TABLE_HEADER sHeader;
		1742	ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables;
1430	serge	1743	}ATOM_MASTER_DATA_TABLE;
1117	serge	1744
		1745	/****************************************************************************/
1430	serge	1746	// Structure used in MultimediaCapabilityInfoTable
1117	serge	1747	/****************************************************************************/
1430	serge	1748	typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO
		1749	{
1117	serge	1750	ATOM_COMMON_TABLE_HEADER sHeader;
1430	serge	1751	ULONG ulSignature; // HW info table signature string "$ATI"
		1752	UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)
		1753	UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
		1754	UCHAR ucVideoPortInfo; // Provides the video port capabilities
		1755	UCHAR ucHostPortInfo; // Provides host port configuration information
		1756	}ATOM_MULTIMEDIA_CAPABILITY_INFO;
1117	serge	1757
		1758	/****************************************************************************/
1430	serge	1759	// Structure used in MultimediaConfigInfoTable
1117	serge	1760	/****************************************************************************/
1430	serge	1761	typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
		1762	{
1117	serge	1763	ATOM_COMMON_TABLE_HEADER sHeader;
1430	serge	1764	ULONG ulSignature; // MM info table signature sting "$MMT"
		1765	UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
		1766	UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
		1767	UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting
		1768	UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
		1769	UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
		1770	UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
		1771	UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3)
		1772	UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
		1773	UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
		1774	UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
		1775	UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
		1776	UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
		1777	}ATOM_MULTIMEDIA_CONFIG_INFO;
1117	serge	1778
1430	serge	1779	/****************************************************************************/
		1780	// Structures used in FirmwareInfoTable
		1781	/****************************************************************************/
1117	serge	1782
1430	serge	1783	// usBIOSCapability Defintion:
		1784	// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted;
		1785	// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported;
		1786	// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
		1787	// Others: Reserved
1117	serge	1788	#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001
		1789	#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002
		1790	#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004
1430	serge	1791	#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable.
		1792	#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable.
1117	serge	1793	#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020
		1794	#define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040
		1795	#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080
		1796	#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100
		1797	#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00
		1798	#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000
		1799	#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000
1430	serge	1800	#define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip
		1801	#define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip
1117	serge	1802
		1803	#ifndef _H2INC
		1804
1430	serge	1805	//Please don't add or expand this bitfield structure below, this one will retire soon.!
		1806	typedef struct _ATOM_FIRMWARE_CAPABILITY
		1807	{
1117	serge	1808	#if ATOM_BIG_ENDIAN
		1809	USHORT Reserved:3;
		1810	USHORT HyperMemory_Size:4;
		1811	USHORT HyperMemory_Support:1;
		1812	USHORT PPMode_Assigned:1;
		1813	USHORT WMI_SUPPORT:1;
		1814	USHORT GPUControlsBL:1;
		1815	USHORT EngineClockSS_Support:1;
		1816	USHORT MemoryClockSS_Support:1;
		1817	USHORT ExtendedDesktopSupport:1;
		1818	USHORT DualCRTC_Support:1;
		1819	USHORT FirmwarePosted:1;
		1820	#else
		1821	USHORT FirmwarePosted:1;
		1822	USHORT DualCRTC_Support:1;
		1823	USHORT ExtendedDesktopSupport:1;
		1824	USHORT MemoryClockSS_Support:1;
		1825	USHORT EngineClockSS_Support:1;
		1826	USHORT GPUControlsBL:1;
		1827	USHORT WMI_SUPPORT:1;
		1828	USHORT PPMode_Assigned:1;
		1829	USHORT HyperMemory_Support:1;
		1830	USHORT HyperMemory_Size:4;
		1831	USHORT Reserved:3;
		1832	#endif
1430	serge	1833	}ATOM_FIRMWARE_CAPABILITY;
1117	serge	1834
1430	serge	1835	typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
		1836	{
1117	serge	1837	ATOM_FIRMWARE_CAPABILITY sbfAccess;
		1838	USHORT susAccess;
1430	serge	1839	}ATOM_FIRMWARE_CAPABILITY_ACCESS;
1117	serge	1840
		1841	#else
		1842
1430	serge	1843	typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
		1844	{
1117	serge	1845	USHORT susAccess;
1430	serge	1846	}ATOM_FIRMWARE_CAPABILITY_ACCESS;
1117	serge	1847
		1848	#endif
		1849
1430	serge	1850	typedef struct _ATOM_FIRMWARE_INFO
		1851	{
1117	serge	1852	ATOM_COMMON_TABLE_HEADER sHeader;
		1853	ULONG ulFirmwareRevision;
1430	serge	1854	ULONG ulDefaultEngineClock; //In 10Khz unit
		1855	ULONG ulDefaultMemoryClock; //In 10Khz unit
		1856	ULONG ulDriverTargetEngineClock; //In 10Khz unit
		1857	ULONG ulDriverTargetMemoryClock; //In 10Khz unit
		1858	ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
		1859	ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
		1860	ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
		1861	ULONG ulASICMaxEngineClock; //In 10Khz unit
		1862	ULONG ulASICMaxMemoryClock; //In 10Khz unit
1117	serge	1863	UCHAR ucASICMaxTemperature;
1430	serge	1864	UCHAR ucPadding[3]; //Don't use them
		1865	ULONG aulReservedForBIOS[3]; //Don't use them
		1866	USHORT usMinEngineClockPLL_Input; //In 10Khz unit
		1867	USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
		1868	USHORT usMinEngineClockPLL_Output; //In 10Khz unit
		1869	USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
		1870	USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
		1871	USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
		1872	USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
		1873	USHORT usMinPixelClockPLL_Input; //In 10Khz unit
		1874	USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
		1875	USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!!
1117	serge	1876	ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
1430	serge	1877	USHORT usReferenceClock; //In 10Khz unit
		1878	USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
		1879	UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
		1880	UCHAR ucDesign_ID; //Indicate what is the board design
		1881	UCHAR ucMemoryModule_ID; //Indicate what is the board design
		1882	}ATOM_FIRMWARE_INFO;
1117	serge	1883
1430	serge	1884	typedef struct _ATOM_FIRMWARE_INFO_V1_2
		1885	{
1117	serge	1886	ATOM_COMMON_TABLE_HEADER sHeader;
		1887	ULONG ulFirmwareRevision;
1430	serge	1888	ULONG ulDefaultEngineClock; //In 10Khz unit
		1889	ULONG ulDefaultMemoryClock; //In 10Khz unit
		1890	ULONG ulDriverTargetEngineClock; //In 10Khz unit
		1891	ULONG ulDriverTargetMemoryClock; //In 10Khz unit
		1892	ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
		1893	ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
		1894	ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
		1895	ULONG ulASICMaxEngineClock; //In 10Khz unit
		1896	ULONG ulASICMaxMemoryClock; //In 10Khz unit
1117	serge	1897	UCHAR ucASICMaxTemperature;
		1898	UCHAR ucMinAllowedBL_Level;
1430	serge	1899	UCHAR ucPadding[2]; //Don't use them
		1900	ULONG aulReservedForBIOS[2]; //Don't use them
		1901	ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
		1902	USHORT usMinEngineClockPLL_Input; //In 10Khz unit
		1903	USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
		1904	USHORT usMinEngineClockPLL_Output; //In 10Khz unit
		1905	USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
		1906	USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
		1907	USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
		1908	USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
		1909	USHORT usMinPixelClockPLL_Input; //In 10Khz unit
		1910	USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
		1911	USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
1117	serge	1912	ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
1430	serge	1913	USHORT usReferenceClock; //In 10Khz unit
		1914	USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
		1915	UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
		1916	UCHAR ucDesign_ID; //Indicate what is the board design
		1917	UCHAR ucMemoryModule_ID; //Indicate what is the board design
		1918	}ATOM_FIRMWARE_INFO_V1_2;
1117	serge	1919
1430	serge	1920	typedef struct _ATOM_FIRMWARE_INFO_V1_3
		1921	{
1117	serge	1922	ATOM_COMMON_TABLE_HEADER sHeader;
		1923	ULONG ulFirmwareRevision;
1430	serge	1924	ULONG ulDefaultEngineClock; //In 10Khz unit
		1925	ULONG ulDefaultMemoryClock; //In 10Khz unit
		1926	ULONG ulDriverTargetEngineClock; //In 10Khz unit
		1927	ULONG ulDriverTargetMemoryClock; //In 10Khz unit
		1928	ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
		1929	ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
		1930	ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
		1931	ULONG ulASICMaxEngineClock; //In 10Khz unit
		1932	ULONG ulASICMaxMemoryClock; //In 10Khz unit
1117	serge	1933	UCHAR ucASICMaxTemperature;
		1934	UCHAR ucMinAllowedBL_Level;
1430	serge	1935	UCHAR ucPadding[2]; //Don't use them
		1936	ULONG aulReservedForBIOS; //Don't use them
		1937	ULONG ul3DAccelerationEngineClock;//In 10Khz unit
		1938	ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
		1939	USHORT usMinEngineClockPLL_Input; //In 10Khz unit
		1940	USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
		1941	USHORT usMinEngineClockPLL_Output; //In 10Khz unit
		1942	USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
		1943	USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
		1944	USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
		1945	USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
		1946	USHORT usMinPixelClockPLL_Input; //In 10Khz unit
		1947	USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
		1948	USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
1117	serge	1949	ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
1430	serge	1950	USHORT usReferenceClock; //In 10Khz unit
		1951	USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
		1952	UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
		1953	UCHAR ucDesign_ID; //Indicate what is the board design
		1954	UCHAR ucMemoryModule_ID; //Indicate what is the board design
		1955	}ATOM_FIRMWARE_INFO_V1_3;
1117	serge	1956
1430	serge	1957	typedef struct _ATOM_FIRMWARE_INFO_V1_4
		1958	{
1117	serge	1959	ATOM_COMMON_TABLE_HEADER sHeader;
		1960	ULONG ulFirmwareRevision;
1430	serge	1961	ULONG ulDefaultEngineClock; //In 10Khz unit
		1962	ULONG ulDefaultMemoryClock; //In 10Khz unit
		1963	ULONG ulDriverTargetEngineClock; //In 10Khz unit
		1964	ULONG ulDriverTargetMemoryClock; //In 10Khz unit
		1965	ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
		1966	ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
		1967	ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
		1968	ULONG ulASICMaxEngineClock; //In 10Khz unit
		1969	ULONG ulASICMaxMemoryClock; //In 10Khz unit
1117	serge	1970	UCHAR ucASICMaxTemperature;
		1971	UCHAR ucMinAllowedBL_Level;
1430	serge	1972	USHORT usBootUpVDDCVoltage; //In MV unit
		1973	USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
		1974	USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
		1975	ULONG ul3DAccelerationEngineClock;//In 10Khz unit
		1976	ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
		1977	USHORT usMinEngineClockPLL_Input; //In 10Khz unit
		1978	USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
		1979	USHORT usMinEngineClockPLL_Output; //In 10Khz unit
		1980	USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
		1981	USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
		1982	USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
		1983	USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
		1984	USHORT usMinPixelClockPLL_Input; //In 10Khz unit
		1985	USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
		1986	USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
		1987	ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
		1988	USHORT usReferenceClock; //In 10Khz unit
		1989	USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
		1990	UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
		1991	UCHAR ucDesign_ID; //Indicate what is the board design
		1992	UCHAR ucMemoryModule_ID; //Indicate what is the board design
		1993	}ATOM_FIRMWARE_INFO_V1_4;
		1994
		1995	//the structure below to be used from Cypress
		1996	typedef struct _ATOM_FIRMWARE_INFO_V2_1
		1997	{
		1998	ATOM_COMMON_TABLE_HEADER sHeader;
		1999	ULONG ulFirmwareRevision;
		2000	ULONG ulDefaultEngineClock; //In 10Khz unit
		2001	ULONG ulDefaultMemoryClock; //In 10Khz unit
		2002	ULONG ulReserved1;
		2003	ULONG ulReserved2;
		2004	ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
		2005	ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
		2006	ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
		2007	ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock
		2008	ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit
		2009	UCHAR ucReserved1; //Was ucASICMaxTemperature;
		2010	UCHAR ucMinAllowedBL_Level;
		2011	USHORT usBootUpVDDCVoltage; //In MV unit
		2012	USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
		2013	USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
		2014	ULONG ulReserved4; //Was ulAsicMaximumVoltage
		2015	ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
		2016	USHORT usMinEngineClockPLL_Input; //In 10Khz unit
		2017	USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
		2018	USHORT usMinEngineClockPLL_Output; //In 10Khz unit
		2019	USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
		2020	USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
		2021	USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
		2022	USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
		2023	USHORT usMinPixelClockPLL_Input; //In 10Khz unit
		2024	USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
		2025	USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
1117	serge	2026	ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
1430	serge	2027	USHORT usCoreReferenceClock; //In 10Khz unit
		2028	USHORT usMemoryReferenceClock; //In 10Khz unit
		2029	USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
		2030	UCHAR ucMemoryModule_ID; //Indicate what is the board design
		2031	UCHAR ucReserved4[3];
		2032	}ATOM_FIRMWARE_INFO_V2_1;
1117	serge	2033
		2034
1430	serge	2035	#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_1
		2036
1117	serge	2037	/****************************************************************************/
1430	serge	2038	// Structures used in IntegratedSystemInfoTable
1117	serge	2039	/****************************************************************************/
		2040	#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2
		2041	#define IGP_CAP_FLAG_AC_CARD 0x4
		2042	#define IGP_CAP_FLAG_SDVO_CARD 0x8
		2043	#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10
		2044
1430	serge	2045	typedef struct _ATOM_INTEGRATED_SYSTEM_INFO
		2046	{
1117	serge	2047	ATOM_COMMON_TABLE_HEADER sHeader;
1430	serge	2048	ULONG ulBootUpEngineClock; //in 10kHz unit
		2049	ULONG ulBootUpMemoryClock; //in 10kHz unit
		2050	ULONG ulMaxSystemMemoryClock; //in 10kHz unit
		2051	ULONG ulMinSystemMemoryClock; //in 10kHz unit
1117	serge	2052	UCHAR ucNumberOfCyclesInPeriodHi;
1430	serge	2053	UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID.
1117	serge	2054	USHORT usReserved1;
1430	serge	2055	USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage
		2056	USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage
1117	serge	2057	ULONG ulReserved[2];
		2058
1430	serge	2059	USHORT usFSBClock; //In MHz unit
		2060	USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable
		2061	//Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
		2062	//Bit[4]==1: P/2 mode, ==0: P/1 mode
		2063	USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal
		2064	USHORT usK8MemoryClock; //in MHz unit
		2065	USHORT usK8SyncStartDelay; //in 0.01 us unit
		2066	USHORT usK8DataReturnTime; //in 0.01 us unit
1117	serge	2067	UCHAR ucMaxNBVoltage;
		2068	UCHAR ucMinNBVoltage;
1430	serge	2069	UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
		2070	UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod
		2071	UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime
		2072	UCHAR ucHTLinkWidth; //16 bit vs. 8 bit
1117	serge	2073	UCHAR ucMaxNBVoltageHigh;
		2074	UCHAR ucMinNBVoltageHigh;
1430	serge	2075	}ATOM_INTEGRATED_SYSTEM_INFO;
1117	serge	2076
		2077	/* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO
		2078	ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock
		2079	For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
		2080	ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
		2081	For AMD IGP,for now this can be 0
		2082	ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
		2083	For AMD IGP,for now this can be 0
		2084
		2085	usFSBClock: For Intel IGP,it's FSB Freq
		2086	For AMD IGP,it's HT Link Speed
		2087
		2088	usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200
		2089	usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation
		2090	usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation
		2091
		2092	VC:Voltage Control
		2093	ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
		2094	ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
		2095
		2096	ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value.
		2097	ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0
		2098
		2099	ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
		2100	ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
		2101
1430	serge	2102
1117	serge	2103	usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
		2104	usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
		2105	*/
		2106
1430	serge	2107
1117	serge	2108	/*
		2109	The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST;
		2110	Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need.
		2111	The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.
		2112
		2113	SW components can access the IGP system infor structure in the same way as before
		2114	*/
		2115
1430	serge	2116
		2117	typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
		2118	{
1117	serge	2119	ATOM_COMMON_TABLE_HEADER sHeader;
1430	serge	2120	ULONG ulBootUpEngineClock; //in 10kHz unit
		2121	ULONG ulReserved1[2]; //must be 0x0 for the reserved
		2122	ULONG ulBootUpUMAClock; //in 10kHz unit
		2123	ULONG ulBootUpSidePortClock; //in 10kHz unit
		2124	ULONG ulMinSidePortClock; //in 10kHz unit
		2125	ULONG ulReserved2[6]; //must be 0x0 for the reserved
		2126	ULONG ulSystemConfig; //see explanation below
1117	serge	2127	ULONG ulBootUpReqDisplayVector;
		2128	ULONG ulOtherDisplayMisc;
		2129	ULONG ulDDISlot1Config;
		2130	ULONG ulDDISlot2Config;
1430	serge	2131	UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
1117	serge	2132	UCHAR ucUMAChannelNumber;
		2133	UCHAR ucDockingPinBit;
		2134	UCHAR ucDockingPinPolarity;
		2135	ULONG ulDockingPinCFGInfo;
		2136	ULONG ulCPUCapInfo;
		2137	USHORT usNumberOfCyclesInPeriod;
		2138	USHORT usMaxNBVoltage;
		2139	USHORT usMinNBVoltage;
		2140	USHORT usBootUpNBVoltage;
1430	serge	2141	ULONG ulHTLinkFreq; //in 10Khz
1117	serge	2142	USHORT usMinHTLinkWidth;
		2143	USHORT usMaxHTLinkWidth;
		2144	USHORT usUMASyncStartDelay;
		2145	USHORT usUMADataReturnTime;
		2146	USHORT usLinkStatusZeroTime;
1430	serge	2147	USHORT usDACEfuse; //for storing badgap value (for RS880 only)
		2148	ULONG ulHighVoltageHTLinkFreq; // in 10Khz
		2149	ULONG ulLowVoltageHTLinkFreq; // in 10Khz
1117	serge	2150	USHORT usMaxUpStreamHTLinkWidth;
		2151	USHORT usMaxDownStreamHTLinkWidth;
		2152	USHORT usMinUpStreamHTLinkWidth;
		2153	USHORT usMinDownStreamHTLinkWidth;
1430	serge	2154	USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW.
		2155	USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
		2156	ULONG ulReserved3[96]; //must be 0x0
		2157	}ATOM_INTEGRATED_SYSTEM_INFO_V2;
1117	serge	2158
		2159	/*
		2160	ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
		2161	ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
		2162	ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock
		2163
		2164	ulSystemConfig:
		2165	Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
		2166	Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state
		2167	=0: system boots up at driver control state. Power state depends on PowerPlay table.
		2168	Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
		2169	Bit[3]=1: Only one power state(Performance) will be supported.
		2170	=0: Multiple power states supported from PowerPlay table.
		2171	Bit[4]=1: CLMC is supported and enabled on current system.
		2172	=0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface.
		2173	Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement.
		2174	=0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied.
		2175	Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored.
		2176	=0: Voltage settings is determined by powerplay table.
		2177	Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue.
		2178	=0: Enable CLMC as regular mode, CDLD and CILR will be enabled.
1430	serge	2179	Bit[8]=1: CDLF is supported and enabled on current system.
		2180	=0: CDLF is not supported or enabled on current system.
		2181	Bit[9]=1: DLL Shut Down feature is enabled on current system.
		2182	=0: DLL Shut Down feature is not enabled or supported on current system.
1117	serge	2183
		2184	ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions.
		2185
		2186	ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
1430	serge	2187	[7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSupportedStd definition;
1117	serge	2188
		2189	ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design).
		2190	[3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
1430	serge	2191	[7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12)
		2192	When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time.
		2193	in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example:
		2194	one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2.
		2195
1117	serge	2196	[15:8] - Lane configuration attribute;
		2197	[23:16]- Connector type, possible value:
		2198	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
		2199	CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
		2200	CONNECTOR_OBJECT_ID_HDMI_TYPE_A
		2201	CONNECTOR_OBJECT_ID_DISPLAYPORT
1430	serge	2202	CONNECTOR_OBJECT_ID_eDP
1117	serge	2203	[31:24]- Reserved
		2204
		2205	ulDDISlot2Config: Same as Slot1.
		2206	ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC.
		2207	For IGP, Hypermemory is the only memory type showed in CCC.
		2208
		2209	ucUMAChannelNumber: how many channels for the UMA;
		2210
		2211	ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin
		2212	ucDockingPinBit: which bit in this register to read the pin status;
		2213	ucDockingPinPolarity:Polarity of the pin when docked;
		2214
		2215	ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, other bits reserved for now and must be 0x0
		2216
		2217	usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
1430	serge	2218
1117	serge	2219	usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode.
		2220	usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.
		2221	GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0
		2222	PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1
		2223	GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE
1430	serge	2224
1117	serge	2225	usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
		2226
		2227	ulHTLinkFreq: Bootup HT link Frequency in 10Khz.
		2228	usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth.
		2229	If CDLW enabled, both upstream and downstream width should be the same during bootup.
		2230	usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth.
		2231	If CDLW enabled, both upstream and downstream width should be the same during bootup.
		2232
		2233	usUMASyncStartDelay: Memory access latency, required for watermark calculation
		2234	usUMADataReturnTime: Memory access latency, required for watermark calculation
		2235	usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us
		2236	for Griffin or Greyhound. SBIOS needs to convert to actual time by:
		2237	if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us)
		2238	if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us)
		2239	if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us)
		2240	if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us)
		2241
		2242	ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0.
		2243	This must be less than or equal to ulHTLinkFreq(bootup frequency).
		2244	ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0.
		2245	This must be less than or equal to ulHighVoltageHTLinkFreq.
		2246
		2247	usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now.
		2248	usMaxDownStreamHTLinkWidth: same as above.
		2249	usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now.
		2250	usMinDownStreamHTLinkWidth: same as above.
		2251	*/
		2252
1430	serge	2253
1117	serge	2254	#define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001
		2255	#define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002
		2256	#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004
		2257	#define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008
		2258	#define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010
		2259	#define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020
		2260	#define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040
		2261	#define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080
1430	serge	2262	#define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100
		2263	#define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200
1117	serge	2264
		2265	#define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF
		2266
		2267	#define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F
		2268	#define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0
		2269	#define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01
		2270	#define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02
		2271	#define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04
		2272	#define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08
		2273
		2274	#define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00
		2275	#define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100
		2276	#define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01
		2277
		2278	#define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000
		2279
1430	serge	2280	// IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR
		2281	typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5
		2282	{
		2283	ATOM_COMMON_TABLE_HEADER sHeader;
		2284	ULONG ulBootUpEngineClock; //in 10kHz unit
		2285	ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK.
		2286	ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge
		2287	ULONG ulBootUpUMAClock; //in 10kHz unit
		2288	ULONG ulReserved1[8]; //must be 0x0 for the reserved
		2289	ULONG ulBootUpReqDisplayVector;
		2290	ULONG ulOtherDisplayMisc;
		2291	ULONG ulReserved2[4]; //must be 0x0 for the reserved
		2292	ULONG ulSystemConfig; //TBD
		2293	ULONG ulCPUCapInfo; //TBD
		2294	USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
		2295	USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
		2296	USHORT usBootUpNBVoltage; //boot up NB voltage
		2297	UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD
		2298	UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD
		2299	ULONG ulReserved3[4]; //must be 0x0 for the reserved
		2300	ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition
		2301	ULONG ulDDISlot2Config;
		2302	ULONG ulDDISlot3Config;
		2303	ULONG ulDDISlot4Config;
		2304	ULONG ulReserved4[4]; //must be 0x0 for the reserved
		2305	UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
		2306	UCHAR ucUMAChannelNumber;
		2307	USHORT usReserved;
		2308	ULONG ulReserved5[4]; //must be 0x0 for the reserved
		2309	ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default
		2310	ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback
		2311	ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications
		2312	ULONG ulReserved6[61]; //must be 0x0
		2313	}ATOM_INTEGRATED_SYSTEM_INFO_V5;
		2314
1117	serge	2315	#define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000
		2316	#define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001
		2317	#define ATOM_TV_INT_ENCODER1_INDEX 0x00000002
		2318	#define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003
		2319	#define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004
		2320	#define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005
		2321	#define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006
		2322	#define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007
		2323	#define ATOM_CV_INT_ENCODER1_INDEX 0x00000008
		2324	#define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009
		2325	#define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A
		2326	#define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B
		2327	#define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C
		2328	#define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D
		2329
1430	serge	2330	// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable
1117	serge	2331	#define ASIC_INT_DAC1_ENCODER_ID 0x00
		2332	#define ASIC_INT_TV_ENCODER_ID 0x02
		2333	#define ASIC_INT_DIG1_ENCODER_ID 0x03
		2334	#define ASIC_INT_DAC2_ENCODER_ID 0x04
		2335	#define ASIC_EXT_TV_ENCODER_ID 0x06
		2336	#define ASIC_INT_DVO_ENCODER_ID 0x07
		2337	#define ASIC_INT_DIG2_ENCODER_ID 0x09
		2338	#define ASIC_EXT_DIG_ENCODER_ID 0x05
1430	serge	2339	#define ASIC_EXT_DIG2_ENCODER_ID 0x08
		2340	#define ASIC_INT_DIG3_ENCODER_ID 0x0a
		2341	#define ASIC_INT_DIG4_ENCODER_ID 0x0b
		2342	#define ASIC_INT_DIG5_ENCODER_ID 0x0c
		2343	#define ASIC_INT_DIG6_ENCODER_ID 0x0d
1117	serge	2344
1430	serge	2345	//define Encoder attribute
1117	serge	2346	#define ATOM_ANALOG_ENCODER 0
		2347	#define ATOM_DIGITAL_ENCODER 1
1430	serge	2348	#define ATOM_DP_ENCODER 2
1117	serge	2349
1430	serge	2350	#define ATOM_ENCODER_ENUM_MASK 0x70
		2351	#define ATOM_ENCODER_ENUM_ID1 0x00
		2352	#define ATOM_ENCODER_ENUM_ID2 0x10
		2353	#define ATOM_ENCODER_ENUM_ID3 0x20
		2354	#define ATOM_ENCODER_ENUM_ID4 0x30
		2355	#define ATOM_ENCODER_ENUM_ID5 0x40
		2356	#define ATOM_ENCODER_ENUM_ID6 0x50
		2357
1117	serge	2358	#define ATOM_DEVICE_CRT1_INDEX 0x00000000
		2359	#define ATOM_DEVICE_LCD1_INDEX 0x00000001
		2360	#define ATOM_DEVICE_TV1_INDEX 0x00000002
		2361	#define ATOM_DEVICE_DFP1_INDEX 0x00000003
		2362	#define ATOM_DEVICE_CRT2_INDEX 0x00000004
		2363	#define ATOM_DEVICE_LCD2_INDEX 0x00000005
1430	serge	2364	#define ATOM_DEVICE_DFP6_INDEX 0x00000006
1117	serge	2365	#define ATOM_DEVICE_DFP2_INDEX 0x00000007
		2366	#define ATOM_DEVICE_CV_INDEX 0x00000008
		2367	#define ATOM_DEVICE_DFP3_INDEX 0x00000009
		2368	#define ATOM_DEVICE_DFP4_INDEX 0x0000000A
		2369	#define ATOM_DEVICE_DFP5_INDEX 0x0000000B
1430	serge	2370
1117	serge	2371	#define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C
		2372	#define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D
		2373	#define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E
		2374	#define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F
		2375	#define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1)
		2376	#define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO
1430	serge	2377	#define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 )
1117	serge	2378
		2379	#define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1)
		2380
1430	serge	2381	#define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX )
		2382	#define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX )
		2383	#define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX )
		2384	#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX )
		2385	#define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX )
		2386	#define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX )
		2387	#define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX )
		2388	#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX )
		2389	#define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX )
		2390	#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX )
1117	serge	2391	#define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX )
1430	serge	2392	#define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX )
1117	serge	2393
1430	serge	2394	#define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT \| ATOM_DEVICE_CRT2_SUPPORT)
		2395	#define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT \| ATOM_DEVICE_DFP2_SUPPORT \| ATOM_DEVICE_DFP3_SUPPORT \| ATOM_DEVICE_DFP4_SUPPORT \| ATOM_DEVICE_DFP5_SUPPORT \| ATOM_DEVICE_DFP6_SUPPORT)
		2396	#define ATOM_DEVICE_TV_SUPPORT (ATOM_DEVICE_TV1_SUPPORT)
		2397	#define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT \| ATOM_DEVICE_LCD2_SUPPORT)
1117	serge	2398
		2399	#define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0
		2400	#define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004
		2401	#define ATOM_DEVICE_CONNECTOR_VGA 0x00000001
		2402	#define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002
		2403	#define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003
		2404	#define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004
		2405	#define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005
		2406	#define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006
		2407	#define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007
		2408	#define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008
		2409	#define ATOM_DEVICE_CONNECTOR_SCART 0x00000009
		2410	#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A
		2411	#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B
		2412	#define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E
		2413	#define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F
		2414
1430	serge	2415
1117	serge	2416	#define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F
		2417	#define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000
		2418	#define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000
		2419	#define ATOM_DEVICE_DAC_INFO_DACA 0x00000001
		2420	#define ATOM_DEVICE_DAC_INFO_DACB 0x00000002
		2421	#define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003
		2422
		2423	#define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000
		2424
		2425	#define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F
		2426	#define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000
		2427
		2428	#define ATOM_DEVICE_I2C_ID_MASK 0x00000070
		2429	#define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004
		2430	#define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001
		2431	#define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002
1430	serge	2432	#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600
		2433	#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690
1117	serge	2434
		2435	#define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080
		2436	#define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007
		2437	#define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000
		2438	#define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001
		2439
1430	serge	2440	// usDeviceSupport:
		2441	// Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
		2442	// Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
		2443	// Bit 2 = 0 - no TV1 support= 1- TV1 is supported
		2444	// Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
		2445	// Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
		2446	// Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
		2447	// Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported
		2448	// Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
		2449	// Bit 8 = 0 - no CV support= 1- CV is supported
		2450	// Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
		2451	// Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported
		2452	// Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported
		2453	//
		2454	//
1117	serge	2455
1430	serge	2456	/****************************************************************************/
		2457	/* Structure used in MclkSS_InfoTable */
		2458	/****************************************************************************/
		2459	// ucI2C_ConfigID
		2460	// [7:0] - I2C LINE Associate ID
		2461	// = 0 - no I2C
		2462	// [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
		2463	// = 0, [6:0]=SW assisted I2C ID
		2464	// [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
		2465	// = 2, HW engine for Multimedia use
		2466	// = 3-7 Reserved for future I2C engines
		2467	// [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
1117	serge	2468
1430	serge	2469	typedef struct _ATOM_I2C_ID_CONFIG
		2470	{
1117	serge	2471	#if ATOM_BIG_ENDIAN
		2472	UCHAR bfHW_Capable:1;
		2473	UCHAR bfHW_EngineID:3;
		2474	UCHAR bfI2C_LineMux:4;
		2475	#else
		2476	UCHAR bfI2C_LineMux:4;
		2477	UCHAR bfHW_EngineID:3;
		2478	UCHAR bfHW_Capable:1;
		2479	#endif
1430	serge	2480	}ATOM_I2C_ID_CONFIG;
1117	serge	2481
1430	serge	2482	typedef union _ATOM_I2C_ID_CONFIG_ACCESS
		2483	{
1117	serge	2484	ATOM_I2C_ID_CONFIG sbfAccess;
		2485	UCHAR ucAccess;
1430	serge	2486	}ATOM_I2C_ID_CONFIG_ACCESS;
		2487
1117	serge	2488
		2489	/****************************************************************************/
1430	serge	2490	// Structure used in GPIO_I2C_InfoTable
1117	serge	2491	/****************************************************************************/
1430	serge	2492	typedef struct _ATOM_GPIO_I2C_ASSIGMENT
		2493	{
1117	serge	2494	USHORT usClkMaskRegisterIndex;
		2495	USHORT usClkEnRegisterIndex;
		2496	USHORT usClkY_RegisterIndex;
		2497	USHORT usClkA_RegisterIndex;
		2498	USHORT usDataMaskRegisterIndex;
		2499	USHORT usDataEnRegisterIndex;
		2500	USHORT usDataY_RegisterIndex;
		2501	USHORT usDataA_RegisterIndex;
		2502	ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
		2503	UCHAR ucClkMaskShift;
		2504	UCHAR ucClkEnShift;
		2505	UCHAR ucClkY_Shift;
		2506	UCHAR ucClkA_Shift;
		2507	UCHAR ucDataMaskShift;
		2508	UCHAR ucDataEnShift;
		2509	UCHAR ucDataY_Shift;
		2510	UCHAR ucDataA_Shift;
		2511	UCHAR ucReserved1;
		2512	UCHAR ucReserved2;
1430	serge	2513	}ATOM_GPIO_I2C_ASSIGMENT;
1117	serge	2514
1430	serge	2515	typedef struct _ATOM_GPIO_I2C_INFO
		2516	{
1117	serge	2517	ATOM_COMMON_TABLE_HEADER sHeader;
		2518	ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE];
1430	serge	2519	}ATOM_GPIO_I2C_INFO;
1117	serge	2520
		2521	/****************************************************************************/
1430	serge	2522	// Common Structure used in other structures
1117	serge	2523	/****************************************************************************/
		2524
		2525	#ifndef _H2INC
		2526
1430	serge	2527	//Please don't add or expand this bitfield structure below, this one will retire soon.!
		2528	typedef struct _ATOM_MODE_MISC_INFO
		2529	{
1117	serge	2530	#if ATOM_BIG_ENDIAN
		2531	USHORT Reserved:6;
		2532	USHORT RGB888:1;
		2533	USHORT DoubleClock:1;
		2534	USHORT Interlace:1;
		2535	USHORT CompositeSync:1;
		2536	USHORT V_ReplicationBy2:1;
		2537	USHORT H_ReplicationBy2:1;
		2538	USHORT VerticalCutOff:1;
1430	serge	2539	USHORT VSyncPolarity:1; //0=Active High, 1=Active Low
		2540	USHORT HSyncPolarity:1; //0=Active High, 1=Active Low
1117	serge	2541	USHORT HorizontalCutOff:1;
		2542	#else
		2543	USHORT HorizontalCutOff:1;
1430	serge	2544	USHORT HSyncPolarity:1; //0=Active High, 1=Active Low
		2545	USHORT VSyncPolarity:1; //0=Active High, 1=Active Low
1117	serge	2546	USHORT VerticalCutOff:1;
		2547	USHORT H_ReplicationBy2:1;
		2548	USHORT V_ReplicationBy2:1;
		2549	USHORT CompositeSync:1;
		2550	USHORT Interlace:1;
		2551	USHORT DoubleClock:1;
		2552	USHORT RGB888:1;
		2553	USHORT Reserved:6;
		2554	#endif
1430	serge	2555	}ATOM_MODE_MISC_INFO;
1117	serge	2556
1430	serge	2557	typedef union _ATOM_MODE_MISC_INFO_ACCESS
		2558	{
1117	serge	2559	ATOM_MODE_MISC_INFO sbfAccess;
		2560	USHORT usAccess;
1430	serge	2561	}ATOM_MODE_MISC_INFO_ACCESS;
1117	serge	2562
		2563	#else
		2564
1430	serge	2565	typedef union _ATOM_MODE_MISC_INFO_ACCESS
		2566	{
1117	serge	2567	USHORT usAccess;
1430	serge	2568	}ATOM_MODE_MISC_INFO_ACCESS;
1117	serge	2569
		2570	#endif
		2571
1430	serge	2572	// usModeMiscInfo-
1117	serge	2573	#define ATOM_H_CUTOFF 0x01
1430	serge	2574	#define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low
		2575	#define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low
1117	serge	2576	#define ATOM_V_CUTOFF 0x08
		2577	#define ATOM_H_REPLICATIONBY2 0x10
		2578	#define ATOM_V_REPLICATIONBY2 0x20
		2579	#define ATOM_COMPOSITESYNC 0x40
		2580	#define ATOM_INTERLACE 0x80
		2581	#define ATOM_DOUBLE_CLOCK_MODE 0x100
		2582	#define ATOM_RGB888_MODE 0x200
		2583
1430	serge	2584	//usRefreshRate-
1117	serge	2585	#define ATOM_REFRESH_43 43
		2586	#define ATOM_REFRESH_47 47
		2587	#define ATOM_REFRESH_56 56
		2588	#define ATOM_REFRESH_60 60
		2589	#define ATOM_REFRESH_65 65
		2590	#define ATOM_REFRESH_70 70
		2591	#define ATOM_REFRESH_72 72
		2592	#define ATOM_REFRESH_75 75
		2593	#define ATOM_REFRESH_85 85
		2594
1430	serge	2595	// ATOM_MODE_TIMING data are exactly the same as VESA timing data.
		2596	// Translation from EDID to ATOM_MODE_TIMING, use the following formula.
		2597	//
		2598	// VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK
		2599	// = EDID_HA + EDID_HBL
		2600	// VESA_HDISP = VESA_ACTIVE = EDID_HA
		2601	// VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH
		2602	// = EDID_HA + EDID_HSO
		2603	// VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW
		2604	// VESA_BORDER = EDID_BORDER
1117	serge	2605
		2606	/****************************************************************************/
1430	serge	2607	// Structure used in SetCRTC_UsingDTDTimingTable
1117	serge	2608	/****************************************************************************/
1430	serge	2609	typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS
		2610	{
1117	serge	2611	USHORT usH_Size;
		2612	USHORT usH_Blanking_Time;
		2613	USHORT usV_Size;
		2614	USHORT usV_Blanking_Time;
		2615	USHORT usH_SyncOffset;
		2616	USHORT usH_SyncWidth;
		2617	USHORT usV_SyncOffset;
		2618	USHORT usV_SyncWidth;
		2619	ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
1430	serge	2620	UCHAR ucH_Border; // From DFP EDID
1117	serge	2621	UCHAR ucV_Border;
1430	serge	2622	UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1117	serge	2623	UCHAR ucPadding[3];
1430	serge	2624	}SET_CRTC_USING_DTD_TIMING_PARAMETERS;
1117	serge	2625
		2626	/****************************************************************************/
1430	serge	2627	// Structure used in SetCRTC_TimingTable
1117	serge	2628	/****************************************************************************/
1430	serge	2629	typedef struct _SET_CRTC_TIMING_PARAMETERS
		2630	{
		2631	USHORT usH_Total; // horizontal total
		2632	USHORT usH_Disp; // horizontal display
		2633	USHORT usH_SyncStart; // horozontal Sync start
		2634	USHORT usH_SyncWidth; // horizontal Sync width
		2635	USHORT usV_Total; // vertical total
		2636	USHORT usV_Disp; // vertical display
		2637	USHORT usV_SyncStart; // vertical Sync start
		2638	USHORT usV_SyncWidth; // vertical Sync width
1117	serge	2639	ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
1430	serge	2640	UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
		2641	UCHAR ucOverscanRight; // right
		2642	UCHAR ucOverscanLeft; // left
		2643	UCHAR ucOverscanBottom; // bottom
		2644	UCHAR ucOverscanTop; // top
1117	serge	2645	UCHAR ucReserved;
1430	serge	2646	}SET_CRTC_TIMING_PARAMETERS;
1117	serge	2647	#define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS
		2648
		2649	/****************************************************************************/
1430	serge	2650	// Structure used in StandardVESA_TimingTable
		2651	// AnalogTV_InfoTable
		2652	// ComponentVideoInfoTable
1117	serge	2653	/****************************************************************************/
1430	serge	2654	typedef struct _ATOM_MODE_TIMING
		2655	{
1117	serge	2656	USHORT usCRTC_H_Total;
		2657	USHORT usCRTC_H_Disp;
		2658	USHORT usCRTC_H_SyncStart;
		2659	USHORT usCRTC_H_SyncWidth;
		2660	USHORT usCRTC_V_Total;
		2661	USHORT usCRTC_V_Disp;
		2662	USHORT usCRTC_V_SyncStart;
		2663	USHORT usCRTC_V_SyncWidth;
1430	serge	2664	USHORT usPixelClock; //in 10Khz unit
1117	serge	2665	ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
		2666	USHORT usCRTC_OverscanRight;
		2667	USHORT usCRTC_OverscanLeft;
		2668	USHORT usCRTC_OverscanBottom;
		2669	USHORT usCRTC_OverscanTop;
		2670	USHORT usReserve;
		2671	UCHAR ucInternalModeNumber;
		2672	UCHAR ucRefreshRate;
1430	serge	2673	}ATOM_MODE_TIMING;
1117	serge	2674
1430	serge	2675	typedef struct _ATOM_DTD_FORMAT
		2676	{
1117	serge	2677	USHORT usPixClk;
		2678	USHORT usHActive;
		2679	USHORT usHBlanking_Time;
		2680	USHORT usVActive;
		2681	USHORT usVBlanking_Time;
		2682	USHORT usHSyncOffset;
		2683	USHORT usHSyncWidth;
		2684	USHORT usVSyncOffset;
		2685	USHORT usVSyncWidth;
		2686	USHORT usImageHSize;
		2687	USHORT usImageVSize;
		2688	UCHAR ucHBorder;
		2689	UCHAR ucVBorder;
		2690	ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
		2691	UCHAR ucInternalModeNumber;
		2692	UCHAR ucRefreshRate;
1430	serge	2693	}ATOM_DTD_FORMAT;
1117	serge	2694
		2695	/****************************************************************************/
1430	serge	2696	// Structure used in LVDS_InfoTable
		2697	// * Need a document to describe this table
1117	serge	2698	/****************************************************************************/
		2699	#define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
		2700	#define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
		2701	#define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
		2702	#define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
		2703
1430	serge	2704	//ucTableFormatRevision=1
		2705	//ucTableContentRevision=1
		2706	typedef struct _ATOM_LVDS_INFO
		2707	{
1117	serge	2708	ATOM_COMMON_TABLE_HEADER sHeader;
		2709	ATOM_DTD_FORMAT sLCDTiming;
		2710	USHORT usModePatchTableOffset;
1430	serge	2711	USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
1117	serge	2712	USHORT usOffDelayInMs;
		2713	UCHAR ucPowerSequenceDigOntoDEin10Ms;
		2714	UCHAR ucPowerSequenceDEtoBLOnin10Ms;
1430	serge	2715	UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
		2716	// Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
		2717	// Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
		2718	// Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
1117	serge	2719	UCHAR ucPanelDefaultRefreshRate;
		2720	UCHAR ucPanelIdentification;
		2721	UCHAR ucSS_Id;
1430	serge	2722	}ATOM_LVDS_INFO;
1117	serge	2723
1430	serge	2724	//ucTableFormatRevision=1
		2725	//ucTableContentRevision=2
		2726	typedef struct _ATOM_LVDS_INFO_V12
		2727	{
1117	serge	2728	ATOM_COMMON_TABLE_HEADER sHeader;
		2729	ATOM_DTD_FORMAT sLCDTiming;
		2730	USHORT usExtInfoTableOffset;
1430	serge	2731	USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
1117	serge	2732	USHORT usOffDelayInMs;
		2733	UCHAR ucPowerSequenceDigOntoDEin10Ms;
		2734	UCHAR ucPowerSequenceDEtoBLOnin10Ms;
1430	serge	2735	UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
		2736	// Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
		2737	// Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
		2738	// Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
1117	serge	2739	UCHAR ucPanelDefaultRefreshRate;
		2740	UCHAR ucPanelIdentification;
		2741	UCHAR ucSS_Id;
		2742	USHORT usLCDVenderID;
		2743	USHORT usLCDProductID;
		2744	UCHAR ucLCDPanel_SpecialHandlingCap;
1430	serge	2745	UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
1117	serge	2746	UCHAR ucReserved[2];
1430	serge	2747	}ATOM_LVDS_INFO_V12;
1117	serge	2748
1430	serge	2749	//Definitions for ucLCDPanel_SpecialHandlingCap:
		2750
		2751	//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
		2752	//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
		2753	#define LCDPANEL_CAP_READ_EDID 0x1
		2754
		2755	//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
		2756	//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
		2757	//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
		2758	#define LCDPANEL_CAP_DRR_SUPPORTED 0x2
		2759
		2760	//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
		2761	#define LCDPANEL_CAP_eDP 0x4
		2762
		2763
		2764	//Color Bit Depth definition in EDID V1.4 @BYTE 14h
		2765	//Bit 6 5 4
		2766	// 0 0 0 - Color bit depth is undefined
		2767	// 0 0 1 - 6 Bits per Primary Color
		2768	// 0 1 0 - 8 Bits per Primary Color
		2769	// 0 1 1 - 10 Bits per Primary Color
		2770	// 1 0 0 - 12 Bits per Primary Color
		2771	// 1 0 1 - 14 Bits per Primary Color
		2772	// 1 1 0 - 16 Bits per Primary Color
		2773	// 1 1 1 - Reserved
		2774
		2775	#define PANEL_COLOR_BIT_DEPTH_MASK 0x70
		2776
		2777	// Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled}
		2778	#define PANEL_RANDOM_DITHER 0x80
		2779	#define PANEL_RANDOM_DITHER_MASK 0x80
		2780
		2781
1117	serge	2782	#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12
		2783
1430	serge	2784	typedef struct _ATOM_PATCH_RECORD_MODE
		2785	{
1117	serge	2786	UCHAR ucRecordType;
		2787	USHORT usHDisp;
		2788	USHORT usVDisp;
1430	serge	2789	}ATOM_PATCH_RECORD_MODE;
1117	serge	2790
1430	serge	2791	typedef struct _ATOM_LCD_RTS_RECORD
		2792	{
1117	serge	2793	UCHAR ucRecordType;
		2794	UCHAR ucRTSValue;
1430	serge	2795	}ATOM_LCD_RTS_RECORD;
1117	serge	2796
1430	serge	2797	//!! If the record below exits, it shoud always be the first record for easy use in command table!!!
		2798	// The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead.
		2799	typedef struct _ATOM_LCD_MODE_CONTROL_CAP
		2800	{
1117	serge	2801	UCHAR ucRecordType;
		2802	USHORT usLCDCap;
1430	serge	2803	}ATOM_LCD_MODE_CONTROL_CAP;
1117	serge	2804
		2805	#define LCD_MODE_CAP_BL_OFF 1
		2806	#define LCD_MODE_CAP_CRTC_OFF 2
		2807	#define LCD_MODE_CAP_PANEL_OFF 4
		2808
1430	serge	2809	typedef struct _ATOM_FAKE_EDID_PATCH_RECORD
		2810	{
1117	serge	2811	UCHAR ucRecordType;
		2812	UCHAR ucFakeEDIDLength;
1430	serge	2813	UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements.
1117	serge	2814	} ATOM_FAKE_EDID_PATCH_RECORD;
		2815
1430	serge	2816	typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD
		2817	{
1117	serge	2818	UCHAR ucRecordType;
		2819	USHORT usHSize;
		2820	USHORT usVSize;
1430	serge	2821	}ATOM_PANEL_RESOLUTION_PATCH_RECORD;
1117	serge	2822
		2823	#define LCD_MODE_PATCH_RECORD_MODE_TYPE 1
		2824	#define LCD_RTS_RECORD_TYPE 2
		2825	#define LCD_CAP_RECORD_TYPE 3
		2826	#define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4
		2827	#define LCD_PANEL_RESOLUTION_RECORD_TYPE 5
		2828	#define ATOM_RECORD_END_TYPE 0xFF
		2829
		2830	/**************************Spread Spectrum Info Table Definitions ********************/
		2831
1430	serge	2832	//ucTableFormatRevision=1
		2833	//ucTableContentRevision=2
		2834	typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
		2835	{
1117	serge	2836	USHORT usSpreadSpectrumPercentage;
1430	serge	2837	UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD
1117	serge	2838	UCHAR ucSS_Step;
		2839	UCHAR ucSS_Delay;
		2840	UCHAR ucSS_Id;
1268	serge	2841	UCHAR ucRecommendedRef_Div;
1430	serge	2842	UCHAR ucSS_Range; //it was reserved for V11
		2843	}ATOM_SPREAD_SPECTRUM_ASSIGNMENT;
1117	serge	2844
		2845	#define ATOM_MAX_SS_ENTRY 16
1430	serge	2846	#define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well.
		2847	#define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable.
		2848	#define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz
		2849	#define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz
1117	serge	2850
1430	serge	2851
1117	serge	2852	#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000
		2853	#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000
		2854	#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001
		2855	#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001
		2856	#define ATOM_INTERNAL_SS_MASK 0x00000000
		2857	#define ATOM_EXTERNAL_SS_MASK 0x00000002
		2858	#define EXEC_SS_STEP_SIZE_SHIFT 2
		2859	#define EXEC_SS_DELAY_SHIFT 4
		2860	#define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4
		2861
1430	serge	2862	typedef struct _ATOM_SPREAD_SPECTRUM_INFO
		2863	{
1117	serge	2864	ATOM_COMMON_TABLE_HEADER sHeader;
		2865	ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY];
1430	serge	2866	}ATOM_SPREAD_SPECTRUM_INFO;
1117	serge	2867
		2868	/****************************************************************************/
1430	serge	2869	// Structure used in AnalogTV_InfoTable (Top level)
1117	serge	2870	/****************************************************************************/
1430	serge	2871	//ucTVBootUpDefaultStd definiton:
1117	serge	2872
1430	serge	2873	//ATOM_TV_NTSC 1
		2874	//ATOM_TV_NTSCJ 2
		2875	//ATOM_TV_PAL 3
		2876	//ATOM_TV_PALM 4
		2877	//ATOM_TV_PALCN 5
		2878	//ATOM_TV_PALN 6
		2879	//ATOM_TV_PAL60 7
		2880	//ATOM_TV_SECAM 8
1117	serge	2881
1430	serge	2882	//ucTVSupportedStd definition:
1117	serge	2883	#define NTSC_SUPPORT 0x1
		2884	#define NTSCJ_SUPPORT 0x2
		2885
		2886	#define PAL_SUPPORT 0x4
		2887	#define PALM_SUPPORT 0x8
		2888	#define PALCN_SUPPORT 0x10
		2889	#define PALN_SUPPORT 0x20
		2890	#define PAL60_SUPPORT 0x40
		2891	#define SECAM_SUPPORT 0x80
		2892
		2893	#define MAX_SUPPORTED_TV_TIMING 2
		2894
1430	serge	2895	typedef struct _ATOM_ANALOG_TV_INFO
		2896	{
1117	serge	2897	ATOM_COMMON_TABLE_HEADER sHeader;
		2898	UCHAR ucTV_SupportedStandard;
		2899	UCHAR ucTV_BootUpDefaultStandard;
		2900	UCHAR ucExt_TV_ASIC_ID;
		2901	UCHAR ucExt_TV_ASIC_SlaveAddr;
1430	serge	2902	/ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];/
1117	serge	2903	ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING];
1430	serge	2904	}ATOM_ANALOG_TV_INFO;
1117	serge	2905
1179	serge	2906	#define MAX_SUPPORTED_TV_TIMING_V1_2 3
		2907
1430	serge	2908	typedef struct _ATOM_ANALOG_TV_INFO_V1_2
		2909	{
1179	serge	2910	ATOM_COMMON_TABLE_HEADER sHeader;
		2911	UCHAR ucTV_SupportedStandard;
		2912	UCHAR ucTV_BootUpDefaultStandard;
		2913	UCHAR ucExt_TV_ASIC_ID;
		2914	UCHAR ucExt_TV_ASIC_SlaveAddr;
		2915	ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];
1430	serge	2916	}ATOM_ANALOG_TV_INFO_V1_2;
1179	serge	2917
1430	serge	2918	typedef struct _ATOM_DPCD_INFO
		2919	{
		2920	UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1
		2921	UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane
		2922	UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
		2923	UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec)
		2924	}ATOM_DPCD_INFO;
		2925
		2926	#define ATOM_DPCD_MAX_LANE_MASK 0x1F
		2927
1117	serge	2928	/**************************************************************************/
1430	serge	2929	// VRAM usage and their defintions
1117	serge	2930
1430	serge	2931	// One chunk of VRAM used by Bios are for HWICON surfaces,EDID data.
		2932	// Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below.
		2933	// All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned!
		2934	// To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR
		2935	// To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
1117	serge	2936
		2937	#ifndef VESA_MEMORY_IN_64K_BLOCK
1430	serge	2938	#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!)
1117	serge	2939	#endif
		2940
1430	serge	2941	#define ATOM_EDID_RAW_DATASIZE 256 //In Bytes
		2942	#define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes
1117	serge	2943	#define ATOM_HWICON_INFOTABLE_SIZE 32
		2944	#define MAX_DTD_MODE_IN_VRAM 6
1430	serge	2945	#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT)
		2946	#define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT)
1117	serge	2947	#define DFP_ENCODER_TYPE_OFFSET 0x80
		2948	#define DP_ENCODER_LANE_NUM_OFFSET 0x84
		2949	#define DP_ENCODER_LINK_RATE_OFFSET 0x88
		2950
		2951	#define ATOM_HWICON1_SURFACE_ADDR 0
		2952	#define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
		2953	#define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
		2954	#define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE)
		2955	#define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
		2956	#define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
		2957
		2958	#define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
		2959	#define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
		2960	#define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
		2961
		2962	#define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
		2963
		2964	#define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
		2965	#define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
		2966	#define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
		2967
		2968	#define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
		2969	#define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
		2970	#define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
		2971
		2972	#define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
		2973	#define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
		2974	#define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
		2975
1430	serge	2976	#define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
		2977	#define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
		2978	#define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
1117	serge	2979
1430	serge	2980	#define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
1117	serge	2981	#define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
		2982	#define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
		2983
		2984	#define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
		2985	#define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
		2986	#define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
		2987
		2988	#define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
		2989	#define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
		2990	#define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
		2991
		2992	#define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
		2993	#define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
		2994	#define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
		2995
		2996	#define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
		2997	#define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
		2998	#define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
		2999
		3000	#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR+ATOM_STD_MODE_SUPPORT_TBL_SIZE)
		3001
1430	serge	3002	#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR+256)
		3003	#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START+512
1117	serge	3004
1430	serge	3005	//The size below is in Kb!
1117	serge	3006	#define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC)
		3007
		3008	#define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L
		3009	#define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30
		3010	#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1
		3011	#define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0
		3012
		3013	/***********************************************************************************/
1430	serge	3014	// Structure used in VRAM_UsageByFirmwareTable
		3015	// Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm
		3016	// at running time.
		3017	// note2: From RV770, the memory is more than 32bit addressable, so we will change
		3018	// ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains
		3019	// exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware
		3020	// (in offset to start of memory address) is KB aligned instead of byte aligend.
1117	serge	3021	/***********************************************************************************/
1430	serge	3022	// Note3:
		3023	/* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter,
		3024	for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have:
		3025
		3026	If (ulStartAddrUsedByFirmware!=0)
		3027	FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
		3028	Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose
		3029	else //Non VGA case
		3030	if (FB_Size<=2Gb)
		3031	FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
		3032	else
		3033	FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
		3034
		3035	CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/
		3036
1117	serge	3037	#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1
		3038
1430	serge	3039	typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO
		3040	{
1117	serge	3041	ULONG ulStartAddrUsedByFirmware;
		3042	USHORT usFirmwareUseInKb;
		3043	USHORT usReserved;
1430	serge	3044	}ATOM_FIRMWARE_VRAM_RESERVE_INFO;
1117	serge	3045
1430	serge	3046	typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE
		3047	{
		3048	ATOM_COMMON_TABLE_HEADER sHeader;
		3049	ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
		3050	}ATOM_VRAM_USAGE_BY_FIRMWARE;
		3051
		3052	// change verion to 1.5, when allow driver to allocate the vram area for command table access.
		3053	typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5
		3054	{
		3055	ULONG ulStartAddrUsedByFirmware;
		3056	USHORT usFirmwareUseInKb;
		3057	USHORT usFBUsedByDrvInKb;
		3058	}ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5;
		3059
		3060	typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5
		3061	{
1117	serge	3062	ATOM_COMMON_TABLE_HEADER sHeader;
1430	serge	3063	ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
		3064	}ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5;
1117	serge	3065
		3066	/****************************************************************************/
1430	serge	3067	// Structure used in GPIO_Pin_LUTTable
1117	serge	3068	/****************************************************************************/
1430	serge	3069	typedef struct _ATOM_GPIO_PIN_ASSIGNMENT
		3070	{
1117	serge	3071	USHORT usGpioPin_AIndex;
		3072	UCHAR ucGpioPinBitShift;
		3073	UCHAR ucGPIO_ID;
1430	serge	3074	}ATOM_GPIO_PIN_ASSIGNMENT;
1117	serge	3075
1430	serge	3076	typedef struct _ATOM_GPIO_PIN_LUT
		3077	{
1117	serge	3078	ATOM_COMMON_TABLE_HEADER sHeader;
		3079	ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1];
1430	serge	3080	}ATOM_GPIO_PIN_LUT;
1117	serge	3081
		3082	/****************************************************************************/
1430	serge	3083	// Structure used in ComponentVideoInfoTable
1117	serge	3084	/****************************************************************************/
		3085	#define GPIO_PIN_ACTIVE_HIGH 0x1
		3086
		3087	#define MAX_SUPPORTED_CV_STANDARDS 5
		3088
1430	serge	3089	// definitions for ATOM_D_INFO.ucSettings
		3090	#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0]
		3091	#define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out
		3092	#define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7]
1117	serge	3093
1430	serge	3094	typedef struct _ATOM_GPIO_INFO
		3095	{
1117	serge	3096	USHORT usAOffset;
		3097	UCHAR ucSettings;
		3098	UCHAR ucReserved;
1430	serge	3099	}ATOM_GPIO_INFO;
1117	serge	3100
1430	serge	3101	// definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector)
1117	serge	3102	#define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2
		3103
1430	serge	3104	// definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i
		3105	#define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7];
		3106	#define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0]
1117	serge	3107
1430	serge	3108	// definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode
		3109	//Line 3 out put 5V.
		3110	#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9
		3111	#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9
1117	serge	3112	#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0
		3113
1430	serge	3114	//Line 3 out put 2.2V
		3115	#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box
		3116	#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box
1117	serge	3117	#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2
		3118
1430	serge	3119	//Line 3 out put 0V
		3120	#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3
		3121	#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3
1117	serge	3122	#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4
		3123
1430	serge	3124	#define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0]
1117	serge	3125
1430	serge	3126	#define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7
1117	serge	3127
1430	serge	3128	//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks.
		3129	#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
		3130	#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
1117	serge	3131
1430	serge	3132
		3133	typedef struct _ATOM_COMPONENT_VIDEO_INFO
		3134	{
1117	serge	3135	ATOM_COMMON_TABLE_HEADER sHeader;
		3136	USHORT usMask_PinRegisterIndex;
		3137	USHORT usEN_PinRegisterIndex;
		3138	USHORT usY_PinRegisterIndex;
		3139	USHORT usA_PinRegisterIndex;
		3140	UCHAR ucBitShift;
1430	serge	3141	UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low
		3142	ATOM_DTD_FORMAT sReserved; // must be zeroed out
1117	serge	3143	UCHAR ucMiscInfo;
		3144	UCHAR uc480i;
		3145	UCHAR uc480p;
		3146	UCHAR uc720p;
		3147	UCHAR uc1080i;
		3148	UCHAR ucLetterBoxMode;
		3149	UCHAR ucReserved[3];
1430	serge	3150	UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
1117	serge	3151	ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
		3152	ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
1430	serge	3153	}ATOM_COMPONENT_VIDEO_INFO;
1117	serge	3154
1430	serge	3155	//ucTableFormatRevision=2
		3156	//ucTableContentRevision=1
		3157	typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21
		3158	{
1117	serge	3159	ATOM_COMMON_TABLE_HEADER sHeader;
		3160	UCHAR ucMiscInfo;
		3161	UCHAR uc480i;
		3162	UCHAR uc480p;
		3163	UCHAR uc720p;
		3164	UCHAR uc1080i;
		3165	UCHAR ucReserved;
		3166	UCHAR ucLetterBoxMode;
1430	serge	3167	UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
1117	serge	3168	ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
		3169	ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
1430	serge	3170	}ATOM_COMPONENT_VIDEO_INFO_V21;
1117	serge	3171
		3172	#define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21
		3173
		3174	/****************************************************************************/
1430	serge	3175	// Structure used in object_InfoTable
1117	serge	3176	/****************************************************************************/
1430	serge	3177	typedef struct _ATOM_OBJECT_HEADER
		3178	{
1117	serge	3179	ATOM_COMMON_TABLE_HEADER sHeader;
		3180	USHORT usDeviceSupport;
		3181	USHORT usConnectorObjectTableOffset;
		3182	USHORT usRouterObjectTableOffset;
		3183	USHORT usEncoderObjectTableOffset;
1430	serge	3184	USHORT usProtectionObjectTableOffset; //only available when Protection block is independent.
1117	serge	3185	USHORT usDisplayPathTableOffset;
1430	serge	3186	}ATOM_OBJECT_HEADER;
1117	serge	3187
1430	serge	3188	typedef struct _ATOM_OBJECT_HEADER_V3
		3189	{
		3190	ATOM_COMMON_TABLE_HEADER sHeader;
		3191	USHORT usDeviceSupport;
		3192	USHORT usConnectorObjectTableOffset;
		3193	USHORT usRouterObjectTableOffset;
		3194	USHORT usEncoderObjectTableOffset;
		3195	USHORT usProtectionObjectTableOffset; //only available when Protection block is independent.
		3196	USHORT usDisplayPathTableOffset;
		3197	USHORT usMiscObjectTableOffset;
		3198	}ATOM_OBJECT_HEADER_V3;
1117	serge	3199
1430	serge	3200	typedef struct _ATOM_DISPLAY_OBJECT_PATH
		3201	{
		3202	USHORT usDeviceTag; //supported device
		3203	USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH
		3204	USHORT usConnObjectId; //Connector Object ID
		3205	USHORT usGPUObjectId; //GPU ID
		3206	USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector.
		3207	}ATOM_DISPLAY_OBJECT_PATH;
		3208
		3209	typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE
		3210	{
1117	serge	3211	UCHAR ucNumOfDispPath;
		3212	UCHAR ucVersion;
		3213	UCHAR ucPadding[2];
		3214	ATOM_DISPLAY_OBJECT_PATH asDispPath[1];
1430	serge	3215	}ATOM_DISPLAY_OBJECT_PATH_TABLE;
1117	serge	3216
1430	serge	3217
		3218	typedef struct _ATOM_OBJECT //each object has this structure
1117	serge	3219	{
		3220	USHORT usObjectID;
		3221	USHORT usSrcDstTableOffset;
1430	serge	3222	USHORT usRecordOffset; //this pointing to a bunch of records defined below
1117	serge	3223	USHORT usReserved;
1430	serge	3224	}ATOM_OBJECT;
1117	serge	3225
1430	serge	3226	typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure
1117	serge	3227	{
		3228	UCHAR ucNumberOfObjects;
		3229	UCHAR ucPadding[3];
		3230	ATOM_OBJECT asObjects[1];
1430	serge	3231	}ATOM_OBJECT_TABLE;
1117	serge	3232
1430	serge	3233	typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure
1117	serge	3234	{
		3235	UCHAR ucNumberOfSrc;
		3236	USHORT usSrcObjectID[1];
		3237	UCHAR ucNumberOfDst;
		3238	USHORT usDstObjectID[1];
1430	serge	3239	}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT;
1117	serge	3240
		3241
1430	serge	3242	//Two definitions below are for OPM on MXM module designs
		3243
		3244	#define EXT_HPDPIN_LUTINDEX_0 0
		3245	#define EXT_HPDPIN_LUTINDEX_1 1
		3246	#define EXT_HPDPIN_LUTINDEX_2 2
		3247	#define EXT_HPDPIN_LUTINDEX_3 3
		3248	#define EXT_HPDPIN_LUTINDEX_4 4
		3249	#define EXT_HPDPIN_LUTINDEX_5 5
		3250	#define EXT_HPDPIN_LUTINDEX_6 6
		3251	#define EXT_HPDPIN_LUTINDEX_7 7
		3252	#define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1)
		3253
		3254	#define EXT_AUXDDC_LUTINDEX_0 0
		3255	#define EXT_AUXDDC_LUTINDEX_1 1
		3256	#define EXT_AUXDDC_LUTINDEX_2 2
		3257	#define EXT_AUXDDC_LUTINDEX_3 3
		3258	#define EXT_AUXDDC_LUTINDEX_4 4
		3259	#define EXT_AUXDDC_LUTINDEX_5 5
		3260	#define EXT_AUXDDC_LUTINDEX_6 6
		3261	#define EXT_AUXDDC_LUTINDEX_7 7
		3262	#define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1)
		3263
		3264	typedef struct _EXT_DISPLAY_PATH
		3265	{
		3266	USHORT usDeviceTag; //A bit vector to show what devices are supported
		3267	USHORT usDeviceACPIEnum; //16bit device ACPI id.
		3268	USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions
		3269	UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT
		3270	UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT
		3271	USHORT usExtEncoderObjId; //external encoder object id
		3272	USHORT usReserved[3];
		3273	}EXT_DISPLAY_PATH;
		3274
		3275	#define NUMBER_OF_UCHAR_FOR_GUID 16
		3276	#define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7
		3277
		3278	typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO
		3279	{
		3280	ATOM_COMMON_TABLE_HEADER sHeader;
		3281	UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string
		3282	EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries.
		3283	UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0.
		3284	UCHAR Reserved [7]; // for potential expansion
		3285	}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO;
		3286
		3287	//Related definitions, all records are differnt but they have a commond header
		3288	typedef struct _ATOM_COMMON_RECORD_HEADER
		3289	{
		3290	UCHAR ucRecordType; //An emun to indicate the record type
		3291	UCHAR ucRecordSize; //The size of the whole record in byte
		3292	}ATOM_COMMON_RECORD_HEADER;
		3293
		3294
1117	serge	3295	#define ATOM_I2C_RECORD_TYPE 1
		3296	#define ATOM_HPD_INT_RECORD_TYPE 2
		3297	#define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3
		3298	#define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4
1430	serge	3299	#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
		3300	#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
1117	serge	3301	#define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7
1430	serge	3302	#define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
1117	serge	3303	#define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9
		3304	#define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10
		3305	#define ATOM_CONNECTOR_CF_RECORD_TYPE 11
		3306	#define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12
		3307	#define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13
		3308	#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14
		3309	#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15
1430	serge	3310	#define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table
		3311	#define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table
		3312	#define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record
		3313	#define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19
1117	serge	3314
		3315
1430	serge	3316	//Must be updated when new record type is added,equal to that record definition!
		3317	#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE
		3318
		3319	typedef struct _ATOM_I2C_RECORD
		3320	{
1117	serge	3321	ATOM_COMMON_RECORD_HEADER sheader;
		3322	ATOM_I2C_ID_CONFIG sucI2cId;
1430	serge	3323	UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC
		3324	}ATOM_I2C_RECORD;
1117	serge	3325
1430	serge	3326	typedef struct _ATOM_HPD_INT_RECORD
		3327	{
1117	serge	3328	ATOM_COMMON_RECORD_HEADER sheader;
1430	serge	3329	UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
1321	serge	3330	UCHAR ucPlugged_PinState;
1430	serge	3331	}ATOM_HPD_INT_RECORD;
1117	serge	3332
1430	serge	3333
		3334	typedef struct _ATOM_OUTPUT_PROTECTION_RECORD
		3335	{
1117	serge	3336	ATOM_COMMON_RECORD_HEADER sheader;
		3337	UCHAR ucProtectionFlag;
		3338	UCHAR ucReserved;
1430	serge	3339	}ATOM_OUTPUT_PROTECTION_RECORD;
1117	serge	3340
1430	serge	3341	typedef struct _ATOM_CONNECTOR_DEVICE_TAG
		3342	{
		3343	ULONG ulACPIDeviceEnum; //Reserved for now
		3344	USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT"
1117	serge	3345	USHORT usPadding;
1430	serge	3346	}ATOM_CONNECTOR_DEVICE_TAG;
1117	serge	3347
1430	serge	3348	typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD
		3349	{
1117	serge	3350	ATOM_COMMON_RECORD_HEADER sheader;
		3351	UCHAR ucNumberOfDevice;
		3352	UCHAR ucReserved;
1430	serge	3353	ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation
		3354	}ATOM_CONNECTOR_DEVICE_TAG_RECORD;
1117	serge	3355
1430	serge	3356
		3357	typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD
		3358	{
1117	serge	3359	ATOM_COMMON_RECORD_HEADER sheader;
		3360	UCHAR ucConfigGPIOID;
1430	serge	3361	UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in
1117	serge	3362	UCHAR ucFlowinGPIPID;
		3363	UCHAR ucExtInGPIPID;
1430	serge	3364	}ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD;
1117	serge	3365
1430	serge	3366	typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD
		3367	{
1117	serge	3368	ATOM_COMMON_RECORD_HEADER sheader;
		3369	UCHAR ucCTL1GPIO_ID;
1430	serge	3370	UCHAR ucCTL1GPIOState; //Set to 1 when it's active high
1117	serge	3371	UCHAR ucCTL2GPIO_ID;
1430	serge	3372	UCHAR ucCTL2GPIOState; //Set to 1 when it's active high
1117	serge	3373	UCHAR ucCTL3GPIO_ID;
1430	serge	3374	UCHAR ucCTL3GPIOState; //Set to 1 when it's active high
1117	serge	3375	UCHAR ucCTLFPGA_IN_ID;
		3376	UCHAR ucPadding[3];
1430	serge	3377	}ATOM_ENCODER_FPGA_CONTROL_RECORD;
1117	serge	3378
1430	serge	3379	typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD
		3380	{
1117	serge	3381	ATOM_COMMON_RECORD_HEADER sheader;
1430	serge	3382	UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
		3383	UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected
		3384	}ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD;
1117	serge	3385
1430	serge	3386	typedef struct _ATOM_JTAG_RECORD
		3387	{
1117	serge	3388	ATOM_COMMON_RECORD_HEADER sheader;
		3389	UCHAR ucTMSGPIO_ID;
1430	serge	3390	UCHAR ucTMSGPIOState; //Set to 1 when it's active high
1117	serge	3391	UCHAR ucTCKGPIO_ID;
1430	serge	3392	UCHAR ucTCKGPIOState; //Set to 1 when it's active high
1117	serge	3393	UCHAR ucTDOGPIO_ID;
1430	serge	3394	UCHAR ucTDOGPIOState; //Set to 1 when it's active high
1117	serge	3395	UCHAR ucTDIGPIO_ID;
1430	serge	3396	UCHAR ucTDIGPIOState; //Set to 1 when it's active high
1117	serge	3397	UCHAR ucPadding[2];
1430	serge	3398	}ATOM_JTAG_RECORD;
1117	serge	3399
		3400
1430	serge	3401	//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
		3402	typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR
		3403	{
		3404	UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table
		3405	UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
		3406	}ATOM_GPIO_PIN_CONTROL_PAIR;
		3407
		3408	typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD
		3409	{
1117	serge	3410	ATOM_COMMON_RECORD_HEADER sheader;
1430	serge	3411	UCHAR ucFlags; // Future expnadibility
		3412	UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object
		3413	ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins
		3414	}ATOM_OBJECT_GPIO_CNTL_RECORD;
1117	serge	3415
1430	serge	3416	//Definitions for GPIO pin state
1117	serge	3417	#define GPIO_PIN_TYPE_INPUT 0x00
		3418	#define GPIO_PIN_TYPE_OUTPUT 0x10
		3419	#define GPIO_PIN_TYPE_HW_CONTROL 0x20
		3420
1430	serge	3421	//For GPIO_PIN_TYPE_OUTPUT the following is defined
1117	serge	3422	#define GPIO_PIN_OUTPUT_STATE_MASK 0x01
		3423	#define GPIO_PIN_OUTPUT_STATE_SHIFT 0
		3424	#define GPIO_PIN_STATE_ACTIVE_LOW 0x0
		3425	#define GPIO_PIN_STATE_ACTIVE_HIGH 0x1
		3426
1430	serge	3427	// Indexes to GPIO array in GLSync record
		3428	#define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0
		3429	#define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1
		3430	#define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2
		3431	#define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3
		3432	#define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4
		3433	#define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5
		3434	#define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6
		3435	#define ATOM_GPIO_INDEX_GLSYNC_MAX 7
		3436
		3437	typedef struct _ATOM_ENCODER_DVO_CF_RECORD
		3438	{
1117	serge	3439	ATOM_COMMON_RECORD_HEADER sheader;
1430	serge	3440	ULONG ulStrengthControl; // DVOA strength control for CF
1117	serge	3441	UCHAR ucPadding[2];
1430	serge	3442	}ATOM_ENCODER_DVO_CF_RECORD;
1117	serge	3443
1430	serge	3444	// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle
1117	serge	3445	#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1
		3446	#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2
		3447
1430	serge	3448	typedef struct _ATOM_CONNECTOR_CF_RECORD
		3449	{
1117	serge	3450	ATOM_COMMON_RECORD_HEADER sheader;
		3451	USHORT usMaxPixClk;
		3452	UCHAR ucFlowCntlGpioId;
		3453	UCHAR ucSwapCntlGpioId;
		3454	UCHAR ucConnectedDvoBundle;
		3455	UCHAR ucPadding;
1430	serge	3456	}ATOM_CONNECTOR_CF_RECORD;
1117	serge	3457
1430	serge	3458	typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD
		3459	{
1117	serge	3460	ATOM_COMMON_RECORD_HEADER sheader;
		3461	ATOM_DTD_FORMAT asTiming;
1430	serge	3462	}ATOM_CONNECTOR_HARDCODE_DTD_RECORD;
1117	serge	3463
1430	serge	3464	typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD
		3465	{
		3466	ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE
		3467	UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D\|X_ID_DUAL_LINK_DVI_D\|HDMI_TYPE_A
1117	serge	3468	UCHAR ucReserved;
1430	serge	3469	}ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD;
1117	serge	3470
1430	serge	3471
		3472	typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD
		3473	{
1117	serge	3474	ATOM_COMMON_RECORD_HEADER sheader;
1430	serge	3475	UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state
1117	serge	3476	UCHAR ucMuxControlPin;
1430	serge	3477	UCHAR ucMuxState[2]; //for alligment purpose
		3478	}ATOM_ROUTER_DDC_PATH_SELECT_RECORD;
1117	serge	3479
1430	serge	3480	typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
		3481	{
1117	serge	3482	ATOM_COMMON_RECORD_HEADER sheader;
		3483	UCHAR ucMuxType;
		3484	UCHAR ucMuxControlPin;
1430	serge	3485	UCHAR ucMuxState[2]; //for alligment purpose
		3486	}ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD;
1117	serge	3487
1430	serge	3488	// define ucMuxType
1117	serge	3489	#define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f
		3490	#define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01
		3491
1430	serge	3492	typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
		3493	{
		3494	ATOM_COMMON_RECORD_HEADER sheader;
		3495	UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table
		3496	}ATOM_CONNECTOR_HPDPIN_LUT_RECORD;
		3497
		3498	typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
		3499	{
		3500	ATOM_COMMON_RECORD_HEADER sheader;
		3501	ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID
		3502	}ATOM_CONNECTOR_AUXDDC_LUT_RECORD;
		3503
		3504	typedef struct _ATOM_OBJECT_LINK_RECORD
		3505	{
		3506	ATOM_COMMON_RECORD_HEADER sheader;
		3507	USHORT usObjectID; //could be connector, encorder or other object in object.h
		3508	}ATOM_OBJECT_LINK_RECORD;
		3509
		3510	typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD
		3511	{
		3512	ATOM_COMMON_RECORD_HEADER sheader;
		3513	USHORT usReserved;
		3514	}ATOM_CONNECTOR_REMOTE_CAP_RECORD;
		3515
1117	serge	3516	/****************************************************************************/
1430	serge	3517	// ASIC voltage data table
1117	serge	3518	/****************************************************************************/
1430	serge	3519	typedef struct _ATOM_VOLTAGE_INFO_HEADER
		3520	{
		3521	USHORT usVDDCBaseLevel; //In number of 50mv unit
		3522	USHORT usReserved; //For possible extension table offset
1117	serge	3523	UCHAR ucNumOfVoltageEntries;
		3524	UCHAR ucBytesPerVoltageEntry;
1430	serge	3525	UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit
1117	serge	3526	UCHAR ucDefaultVoltageEntry;
		3527	UCHAR ucVoltageControlI2cLine;
		3528	UCHAR ucVoltageControlAddress;
		3529	UCHAR ucVoltageControlOffset;
1430	serge	3530	}ATOM_VOLTAGE_INFO_HEADER;
1117	serge	3531
1430	serge	3532	typedef struct _ATOM_VOLTAGE_INFO
		3533	{
1117	serge	3534	ATOM_COMMON_TABLE_HEADER sHeader;
		3535	ATOM_VOLTAGE_INFO_HEADER viHeader;
1430	serge	3536	UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry
		3537	}ATOM_VOLTAGE_INFO;
1117	serge	3538
1430	serge	3539
		3540	typedef struct _ATOM_VOLTAGE_FORMULA
		3541	{
		3542	USHORT usVoltageBaseLevel; // In number of 1mv unit
		3543	USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit
		3544	UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
		3545	UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv
		3546	UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep
1117	serge	3547	UCHAR ucReserved;
1430	serge	3548	UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries
		3549	}ATOM_VOLTAGE_FORMULA;
1117	serge	3550
1430	serge	3551	typedef struct _VOLTAGE_LUT_ENTRY
		3552	{
		3553	USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code
		3554	USHORT usVoltageValue; // The corresponding Voltage Value, in mV
		3555	}VOLTAGE_LUT_ENTRY;
		3556
		3557	typedef struct _ATOM_VOLTAGE_FORMULA_V2
		3558	{
		3559	UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
		3560	UCHAR ucReserved[3];
		3561	VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries
		3562	}ATOM_VOLTAGE_FORMULA_V2;
		3563
		3564	typedef struct _ATOM_VOLTAGE_CONTROL
		3565	{
		3566	UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine
1117	serge	3567	UCHAR ucVoltageControlI2cLine;
		3568	UCHAR ucVoltageControlAddress;
		3569	UCHAR ucVoltageControlOffset;
1430	serge	3570	USHORT usGpioPin_AIndex; //GPIO_PAD register index
		3571	UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff
1117	serge	3572	UCHAR ucReserved;
1430	serge	3573	}ATOM_VOLTAGE_CONTROL;
1117	serge	3574
1430	serge	3575	// Define ucVoltageControlId
1117	serge	3576	#define VOLTAGE_CONTROLLED_BY_HW 0x00
		3577	#define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F
		3578	#define VOLTAGE_CONTROLLED_BY_GPIO 0x80
1430	serge	3579	#define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage
		3580	#define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI
		3581	#define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage
1117	serge	3582	#define VOLTAGE_CONTROL_ID_DS4402 0x04
		3583
1430	serge	3584	typedef struct _ATOM_VOLTAGE_OBJECT
		3585	{
		3586	UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
		3587	UCHAR ucSize; //Size of Object
		3588	ATOM_VOLTAGE_CONTROL asControl; //describ how to control
		3589	ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID
		3590	}ATOM_VOLTAGE_OBJECT;
1117	serge	3591
1430	serge	3592	typedef struct _ATOM_VOLTAGE_OBJECT_V2
		3593	{
		3594	UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
		3595	UCHAR ucSize; //Size of Object
		3596	ATOM_VOLTAGE_CONTROL asControl; //describ how to control
		3597	ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID
		3598	}ATOM_VOLTAGE_OBJECT_V2;
		3599
		3600	typedef struct _ATOM_VOLTAGE_OBJECT_INFO
		3601	{
		3602	ATOM_COMMON_TABLE_HEADER sHeader;
		3603	ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control
		3604	}ATOM_VOLTAGE_OBJECT_INFO;
		3605
		3606	typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2
		3607	{
1117	serge	3608	ATOM_COMMON_TABLE_HEADER sHeader;
1430	serge	3609	ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control
		3610	}ATOM_VOLTAGE_OBJECT_INFO_V2;
1117	serge	3611
1430	serge	3612	typedef struct _ATOM_LEAKID_VOLTAGE
		3613	{
1117	serge	3614	UCHAR ucLeakageId;
		3615	UCHAR ucReserved;
		3616	USHORT usVoltage;
1430	serge	3617	}ATOM_LEAKID_VOLTAGE;
1117	serge	3618
1430	serge	3619	typedef struct _ATOM_ASIC_PROFILE_VOLTAGE
		3620	{
1117	serge	3621	UCHAR ucProfileId;
		3622	UCHAR ucReserved;
		3623	USHORT usSize;
		3624	USHORT usEfuseSpareStartAddr;
1430	serge	3625	USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id,
		3626	ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage
		3627	}ATOM_ASIC_PROFILE_VOLTAGE;
1117	serge	3628
1430	serge	3629	//ucProfileId
1117	serge	3630	#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1
		3631	#define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1
		3632	#define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2
		3633
1430	serge	3634	typedef struct _ATOM_ASIC_PROFILING_INFO
		3635	{
1117	serge	3636	ATOM_COMMON_TABLE_HEADER asHeader;
		3637	ATOM_ASIC_PROFILE_VOLTAGE asVoltage;
1430	serge	3638	}ATOM_ASIC_PROFILING_INFO;
1117	serge	3639
1430	serge	3640	typedef struct _ATOM_POWER_SOURCE_OBJECT
		3641	{
		3642	UCHAR ucPwrSrcId; // Power source
		3643	UCHAR ucPwrSensorType; // GPIO, I2C or none
		3644	UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id
		3645	UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect
		3646	UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect
		3647	UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect
		3648	UCHAR ucPwrSensActiveState; // high active or low active
		3649	UCHAR ucReserve[3]; // reserve
		3650	USHORT usSensPwr; // in unit of watt
		3651	}ATOM_POWER_SOURCE_OBJECT;
1117	serge	3652
1430	serge	3653	typedef struct _ATOM_POWER_SOURCE_INFO
		3654	{
1117	serge	3655	ATOM_COMMON_TABLE_HEADER asHeader;
		3656	UCHAR asPwrbehave[16];
		3657	ATOM_POWER_SOURCE_OBJECT asPwrObj[1];
1430	serge	3658	}ATOM_POWER_SOURCE_INFO;
1117	serge	3659
1430	serge	3660
		3661	//Define ucPwrSrcId
1117	serge	3662	#define POWERSOURCE_PCIE_ID1 0x00
		3663	#define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01
		3664	#define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02
		3665	#define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04
		3666	#define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08
		3667
1430	serge	3668	//define ucPwrSensorId
1117	serge	3669	#define POWER_SENSOR_ALWAYS 0x00
		3670	#define POWER_SENSOR_GPIO 0x01
		3671	#define POWER_SENSOR_I2C 0x02
		3672
1430	serge	3673	typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6
		3674	{
		3675	ATOM_COMMON_TABLE_HEADER sHeader;
		3676	ULONG ulBootUpEngineClock;
		3677	ULONG ulDentistVCOFreq;
		3678	ULONG ulBootUpUMAClock;
		3679	ULONG ulReserved1[8];
		3680	ULONG ulBootUpReqDisplayVector;
		3681	ULONG ulOtherDisplayMisc;
		3682	ULONG ulGPUCapInfo;
		3683	ULONG ulReserved2[3];
		3684	ULONG ulSystemConfig;
		3685	ULONG ulCPUCapInfo;
		3686	USHORT usMaxNBVoltage;
		3687	USHORT usMinNBVoltage;
		3688	USHORT usBootUpNBVoltage;
		3689	USHORT usExtDispConnInfoOffset;
		3690	UCHAR ucHtcTmpLmt;
		3691	UCHAR ucTjOffset;
		3692	UCHAR ucMemoryType;
		3693	UCHAR ucUMAChannelNumber;
		3694	ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];
		3695	ULONG ulCSR_M3_ARB_CNTL_UVD[10];
		3696	ULONG ulCSR_M3_ARB_CNTL_FS3D[10];
		3697	ULONG ulReserved3[42];
		3698	ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
		3699	}ATOM_INTEGRATED_SYSTEM_INFO_V6;
		3700
		3701	/**********************************************************************************************************************
		3702	// ATOM_INTEGRATED_SYSTEM_INFO_V6 Description
		3703	//ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit.
		3704	//ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
		3705	//ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
		3706	//ulReserved1[8] Reserved by now, must be 0x0.
		3707	//ulBootUpReqDisplayVector VBIOS boot up display IDs
		3708	// ATOM_DEVICE_CRT1_SUPPORT 0x0001
		3709	// ATOM_DEVICE_CRT2_SUPPORT 0x0010
		3710	// ATOM_DEVICE_DFP1_SUPPORT 0x0008
		3711	// ATOM_DEVICE_DFP6_SUPPORT 0x0040
		3712	// ATOM_DEVICE_DFP2_SUPPORT 0x0080
		3713	// ATOM_DEVICE_DFP3_SUPPORT 0x0200
		3714	// ATOM_DEVICE_DFP4_SUPPORT 0x0400
		3715	// ATOM_DEVICE_DFP5_SUPPORT 0x0800
		3716	// ATOM_DEVICE_LCD1_SUPPORT 0x0002
		3717	//ulOtherDisplayMisc Other display related flags, not defined yet.
		3718	//ulGPUCapInfo TBD
		3719	//ulReserved2[3] must be 0x0 for the reserved.
		3720	//ulSystemConfig TBD
		3721	//ulCPUCapInfo TBD
		3722	//usMaxNBVoltage High NB voltage in unit of mv, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse.
		3723	//usMinNBVoltage Low NB voltage in unit of mv, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse.
		3724	//usBootUpNBVoltage Boot up NB voltage in unit of mv.
		3725	//ucHtcTmpLmt Bit [22:16] of D24F3x64 Thermal Control (HTC) Register.
		3726	//ucTjOffset Bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed.
		3727	//ucMemoryType [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
		3728	//ucUMAChannelNumber System memory channel numbers.
		3729	//usExtDispConnectionInfoOffset ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO offset relative to beginning of this table.
		3730	//ulCSR_M3_ARB_CNTL_DEFAULT[10] Arrays with values for CSR M3 arbiter for default
		3731	//ulCSR_M3_ARB_CNTL_UVD[10] Arrays with values for CSR M3 arbiter for UVD playback.
		3732	//ulCSR_M3_ARB_CNTL_FS3D[10] Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
		3733	**********************************************************************************************************************/
		3734
1117	serge	3735	/**************************************************************************/
1430	serge	3736	// This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design
		3737	//Memory SS Info Table
		3738	//Define Memory Clock SS chip ID
1117	serge	3739	#define ICS91719 1
		3740	#define ICS91720 2
		3741
1430	serge	3742	//Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol
		3743	typedef struct _ATOM_I2C_DATA_RECORD
		3744	{
		3745	UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop"
		3746	UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually
		3747	}ATOM_I2C_DATA_RECORD;
1117	serge	3748
1430	serge	3749
		3750	//Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information
		3751	typedef struct _ATOM_I2C_DEVICE_SETUP_INFO
		3752	{
		3753	ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap.
		3754	UCHAR ucSSChipID; //SS chip being used
		3755	UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip
		3756	UCHAR ucNumOfI2CDataRecords; //number of data block
1117	serge	3757	ATOM_I2C_DATA_RECORD asI2CData[1];
1430	serge	3758	}ATOM_I2C_DEVICE_SETUP_INFO;
1117	serge	3759
1430	serge	3760	//==========================================================================================
		3761	typedef struct _ATOM_ASIC_MVDD_INFO
		3762	{
1117	serge	3763	ATOM_COMMON_TABLE_HEADER sHeader;
		3764	ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1];
1430	serge	3765	}ATOM_ASIC_MVDD_INFO;
1117	serge	3766
1430	serge	3767	//==========================================================================================
1117	serge	3768	#define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO
		3769
1430	serge	3770	//==========================================================================================
1117	serge	3771	/**************************************************************************/
		3772
1430	serge	3773	typedef struct _ATOM_ASIC_SS_ASSIGNMENT
		3774	{
		3775	ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz
		3776	USHORT usSpreadSpectrumPercentage; //in unit of 0.01%
		3777	USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq
		3778	UCHAR ucClockIndication; //Indicate which clock source needs SS
		3779	UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread.
1117	serge	3780	UCHAR ucReserved[2];
1430	serge	3781	}ATOM_ASIC_SS_ASSIGNMENT;
1117	serge	3782
1430	serge	3783	//Define ucClockIndication, SW uses the IDs below to search if the SS is requried/enabled on a clock branch/signal type.
		3784	//SS is not required or enabled if a match is not found.
1117	serge	3785	#define ASIC_INTERNAL_MEMORY_SS 1
		3786	#define ASIC_INTERNAL_ENGINE_SS 2
		3787	#define ASIC_INTERNAL_UVD_SS 3
1430	serge	3788	#define ASIC_INTERNAL_SS_ON_TMDS 4
		3789	#define ASIC_INTERNAL_SS_ON_HDMI 5
		3790	#define ASIC_INTERNAL_SS_ON_LVDS 6
		3791	#define ASIC_INTERNAL_SS_ON_DP 7
		3792	#define ASIC_INTERNAL_SS_ON_DCPLL 8
1117	serge	3793
1430	serge	3794	typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2
		3795	{
		3796	ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
		3797	//For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
		3798	USHORT usSpreadSpectrumPercentage; //in unit of 0.01%
		3799	USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq
		3800	UCHAR ucClockIndication; //Indicate which clock source needs SS
		3801	UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
		3802	UCHAR ucReserved[2];
		3803	}ATOM_ASIC_SS_ASSIGNMENT_V2;
		3804
		3805	//ucSpreadSpectrumMode
		3806	//#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000
		3807	//#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000
		3808	//#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001
		3809	//#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001
		3810	//#define ATOM_INTERNAL_SS_MASK 0x00000000
		3811	//#define ATOM_EXTERNAL_SS_MASK 0x00000002
		3812
		3813	typedef struct _ATOM_ASIC_INTERNAL_SS_INFO
		3814	{
1117	serge	3815	ATOM_COMMON_TABLE_HEADER sHeader;
		3816	ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4];
1430	serge	3817	}ATOM_ASIC_INTERNAL_SS_INFO;
1117	serge	3818
1430	serge	3819	typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2
		3820	{
		3821	ATOM_COMMON_TABLE_HEADER sHeader;
		3822	ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only.
		3823	}ATOM_ASIC_INTERNAL_SS_INFO_V2;
		3824
		3825	typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3
		3826	{
		3827	ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
		3828	//For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
		3829	USHORT usSpreadSpectrumPercentage; //in unit of 0.01%
		3830	USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq
		3831	UCHAR ucClockIndication; //Indicate which clock source needs SS
		3832	UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
		3833	UCHAR ucReserved[2];
		3834	}ATOM_ASIC_SS_ASSIGNMENT_V3;
		3835
		3836	typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
		3837	{
		3838	ATOM_COMMON_TABLE_HEADER sHeader;
		3839	ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only.
		3840	}ATOM_ASIC_INTERNAL_SS_INFO_V3;
		3841
		3842
		3843	//==============================Scratch Pad Definition Portion===============================
1117	serge	3844	#define ATOM_DEVICE_CONNECT_INFO_DEF 0
		3845	#define ATOM_ROM_LOCATION_DEF 1
		3846	#define ATOM_TV_STANDARD_DEF 2
		3847	#define ATOM_ACTIVE_INFO_DEF 3
		3848	#define ATOM_LCD_INFO_DEF 4
		3849	#define ATOM_DOS_REQ_INFO_DEF 5
		3850	#define ATOM_ACC_CHANGE_INFO_DEF 6
		3851	#define ATOM_DOS_MODE_INFO_DEF 7
		3852	#define ATOM_I2C_CHANNEL_STATUS_DEF 8
		3853	#define ATOM_I2C_CHANNEL_STATUS1_DEF 9
		3854
1430	serge	3855
		3856	// BIOS_0_SCRATCH Definition
1117	serge	3857	#define ATOM_S0_CRT1_MONO 0x00000001L
		3858	#define ATOM_S0_CRT1_COLOR 0x00000002L
		3859	#define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR)
		3860
		3861	#define ATOM_S0_TV1_COMPOSITE_A 0x00000004L
		3862	#define ATOM_S0_TV1_SVIDEO_A 0x00000008L
		3863	#define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A)
		3864
		3865	#define ATOM_S0_CV_A 0x00000010L
		3866	#define ATOM_S0_CV_DIN_A 0x00000020L
		3867	#define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A)
		3868
1430	serge	3869
1117	serge	3870	#define ATOM_S0_CRT2_MONO 0x00000100L
		3871	#define ATOM_S0_CRT2_COLOR 0x00000200L
		3872	#define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR)
		3873
		3874	#define ATOM_S0_TV1_COMPOSITE 0x00000400L
		3875	#define ATOM_S0_TV1_SVIDEO 0x00000800L
		3876	#define ATOM_S0_TV1_SCART 0x00004000L
		3877	#define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART)
		3878
		3879	#define ATOM_S0_CV 0x00001000L
		3880	#define ATOM_S0_CV_DIN 0x00002000L
		3881	#define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN)
		3882
		3883	#define ATOM_S0_DFP1 0x00010000L
		3884	#define ATOM_S0_DFP2 0x00020000L
		3885	#define ATOM_S0_LCD1 0x00040000L
		3886	#define ATOM_S0_LCD2 0x00080000L
1430	serge	3887	#define ATOM_S0_DFP6 0x00100000L
1117	serge	3888	#define ATOM_S0_DFP3 0x00200000L
		3889	#define ATOM_S0_DFP4 0x00400000L
		3890	#define ATOM_S0_DFP5 0x00800000L
		3891
1430	serge	3892	#define ATOM_S0_DFP_MASK ATOM_S0_DFP1 \| ATOM_S0_DFP2 \| ATOM_S0_DFP3 \| ATOM_S0_DFP4 \| ATOM_S0_DFP5 \| ATOM_S0_DFP6
1117	serge	3893
1430	serge	3894	#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with
		3895	// the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx
1117	serge	3896
		3897	#define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L
		3898	#define ATOM_S0_THERMAL_STATE_SHIFT 26
		3899
		3900	#define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L
		3901	#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29
		3902
		3903	#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1
		3904	#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2
		3905	#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3
		3906
1430	serge	3907	//Byte aligned defintion for BIOS usage
1117	serge	3908	#define ATOM_S0_CRT1_MONOb0 0x01
		3909	#define ATOM_S0_CRT1_COLORb0 0x02
		3910	#define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0)
		3911
		3912	#define ATOM_S0_TV1_COMPOSITEb0 0x04
		3913	#define ATOM_S0_TV1_SVIDEOb0 0x08
		3914	#define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0)
		3915
		3916	#define ATOM_S0_CVb0 0x10
		3917	#define ATOM_S0_CV_DINb0 0x20
		3918	#define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0)
		3919
		3920	#define ATOM_S0_CRT2_MONOb1 0x01
		3921	#define ATOM_S0_CRT2_COLORb1 0x02
		3922	#define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1)
		3923
		3924	#define ATOM_S0_TV1_COMPOSITEb1 0x04
		3925	#define ATOM_S0_TV1_SVIDEOb1 0x08
		3926	#define ATOM_S0_TV1_SCARTb1 0x40
		3927	#define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1)
		3928
		3929	#define ATOM_S0_CVb1 0x10
		3930	#define ATOM_S0_CV_DINb1 0x20
		3931	#define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1)
		3932
		3933	#define ATOM_S0_DFP1b2 0x01
		3934	#define ATOM_S0_DFP2b2 0x02
		3935	#define ATOM_S0_LCD1b2 0x04
		3936	#define ATOM_S0_LCD2b2 0x08
1430	serge	3937	#define ATOM_S0_DFP6b2 0x10
1117	serge	3938	#define ATOM_S0_DFP3b2 0x20
1430	serge	3939	#define ATOM_S0_DFP4b2 0x40
		3940	#define ATOM_S0_DFP5b2 0x80
1117	serge	3941
1430	serge	3942
1117	serge	3943	#define ATOM_S0_THERMAL_STATE_MASKb3 0x1C
		3944	#define ATOM_S0_THERMAL_STATE_SHIFTb3 2
		3945
		3946	#define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0
		3947	#define ATOM_S0_LCD1_SHIFT 18
		3948
1430	serge	3949	// BIOS_1_SCRATCH Definition
1117	serge	3950	#define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL
		3951	#define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L
		3952
1430	serge	3953	// BIOS_2_SCRATCH Definition
1117	serge	3954	#define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL
		3955	#define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L
		3956	#define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8
		3957
		3958	#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L
		3959	#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26
		3960	#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L
		3961
1430	serge	3962	#define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L
1117	serge	3963	#define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L
		3964
		3965	#define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0
		3966	#define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1
		3967	#define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2
		3968	#define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3
		3969	#define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30
		3970	#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L
		3971
1430	serge	3972
		3973	//Byte aligned defintion for BIOS usage
1117	serge	3974	#define ATOM_S2_TV1_STANDARD_MASKb0 0x0F
		3975	#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF
1430	serge	3976	#define ATOM_S2_DEVICE_DPMS_STATEb2 0x01
1117	serge	3977
		3978	#define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF
		3979	#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C
		3980	#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3 0x10
		3981	#define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20
		3982	#define ATOM_S2_ROTATION_STATE_MASKb3 0xC0
		3983
1430	serge	3984
		3985	// BIOS_3_SCRATCH Definition
1117	serge	3986	#define ATOM_S3_CRT1_ACTIVE 0x00000001L
		3987	#define ATOM_S3_LCD1_ACTIVE 0x00000002L
		3988	#define ATOM_S3_TV1_ACTIVE 0x00000004L
		3989	#define ATOM_S3_DFP1_ACTIVE 0x00000008L
		3990	#define ATOM_S3_CRT2_ACTIVE 0x00000010L
		3991	#define ATOM_S3_LCD2_ACTIVE 0x00000020L
1430	serge	3992	#define ATOM_S3_DFP6_ACTIVE 0x00000040L
1117	serge	3993	#define ATOM_S3_DFP2_ACTIVE 0x00000080L
		3994	#define ATOM_S3_CV_ACTIVE 0x00000100L
		3995	#define ATOM_S3_DFP3_ACTIVE 0x00000200L
		3996	#define ATOM_S3_DFP4_ACTIVE 0x00000400L
		3997	#define ATOM_S3_DFP5_ACTIVE 0x00000800L
		3998
1430	serge	3999	#define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL
1117	serge	4000
		4001	#define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L
		4002	#define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L
		4003
		4004	#define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L
		4005	#define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L
		4006	#define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L
		4007	#define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L
		4008	#define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L
		4009	#define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L
1430	serge	4010	#define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L
1117	serge	4011	#define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L
		4012	#define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L
		4013	#define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L
		4014	#define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L
		4015	#define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L
		4016
		4017	#define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L
		4018	#define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L
1430	serge	4019	//Below two definitions are not supported in pplib, but in the old powerplay in DAL
1117	serge	4020	#define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L
		4021	#define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L
		4022
1430	serge	4023	//Byte aligned defintion for BIOS usage
1117	serge	4024	#define ATOM_S3_CRT1_ACTIVEb0 0x01
		4025	#define ATOM_S3_LCD1_ACTIVEb0 0x02
		4026	#define ATOM_S3_TV1_ACTIVEb0 0x04
		4027	#define ATOM_S3_DFP1_ACTIVEb0 0x08
		4028	#define ATOM_S3_CRT2_ACTIVEb0 0x10
		4029	#define ATOM_S3_LCD2_ACTIVEb0 0x20
1430	serge	4030	#define ATOM_S3_DFP6_ACTIVEb0 0x40
1117	serge	4031	#define ATOM_S3_DFP2_ACTIVEb0 0x80
		4032	#define ATOM_S3_CV_ACTIVEb1 0x01
		4033	#define ATOM_S3_DFP3_ACTIVEb1 0x02
		4034	#define ATOM_S3_DFP4_ACTIVEb1 0x04
		4035	#define ATOM_S3_DFP5_ACTIVEb1 0x08
		4036
		4037	#define ATOM_S3_ACTIVE_CRTC1w0 0xFFF
		4038
		4039	#define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01
		4040	#define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02
		4041	#define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04
		4042	#define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08
		4043	#define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10
		4044	#define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20
1430	serge	4045	#define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40
1117	serge	4046	#define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80
		4047	#define ATOM_S3_CV_CRTC_ACTIVEb3 0x01
		4048	#define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02
		4049	#define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04
		4050	#define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08
		4051
		4052	#define ATOM_S3_ACTIVE_CRTC2w1 0xFFF
		4053
1430	serge	4054	// BIOS_4_SCRATCH Definition
1117	serge	4055	#define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL
		4056	#define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L
		4057	#define ATOM_S4_LCD1_REFRESH_SHIFT 8
		4058
1430	serge	4059	//Byte aligned defintion for BIOS usage
1117	serge	4060	#define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF
		4061	#define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0
		4062	#define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0
		4063
1430	serge	4064	// BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!!
1117	serge	4065	#define ATOM_S5_DOS_REQ_CRT1b0 0x01
		4066	#define ATOM_S5_DOS_REQ_LCD1b0 0x02
		4067	#define ATOM_S5_DOS_REQ_TV1b0 0x04
		4068	#define ATOM_S5_DOS_REQ_DFP1b0 0x08
		4069	#define ATOM_S5_DOS_REQ_CRT2b0 0x10
		4070	#define ATOM_S5_DOS_REQ_LCD2b0 0x20
1430	serge	4071	#define ATOM_S5_DOS_REQ_DFP6b0 0x40
1117	serge	4072	#define ATOM_S5_DOS_REQ_DFP2b0 0x80
		4073	#define ATOM_S5_DOS_REQ_CVb1 0x01
		4074	#define ATOM_S5_DOS_REQ_DFP3b1 0x02
		4075	#define ATOM_S5_DOS_REQ_DFP4b1 0x04
		4076	#define ATOM_S5_DOS_REQ_DFP5b1 0x08
		4077
1430	serge	4078	#define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF
1117	serge	4079
		4080	#define ATOM_S5_DOS_REQ_CRT1 0x0001
		4081	#define ATOM_S5_DOS_REQ_LCD1 0x0002
		4082	#define ATOM_S5_DOS_REQ_TV1 0x0004
		4083	#define ATOM_S5_DOS_REQ_DFP1 0x0008
		4084	#define ATOM_S5_DOS_REQ_CRT2 0x0010
		4085	#define ATOM_S5_DOS_REQ_LCD2 0x0020
1430	serge	4086	#define ATOM_S5_DOS_REQ_DFP6 0x0040
1117	serge	4087	#define ATOM_S5_DOS_REQ_DFP2 0x0080
		4088	#define ATOM_S5_DOS_REQ_CV 0x0100
		4089	#define ATOM_S5_DOS_REQ_DFP3 0x0200
		4090	#define ATOM_S5_DOS_REQ_DFP4 0x0400
		4091	#define ATOM_S5_DOS_REQ_DFP5 0x0800
		4092
		4093	#define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0
		4094	#define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0
		4095	#define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0
		4096	#define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1
1430	serge	4097	#define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\
		4098	(ATOM_S5_DOS_FORCE_CVb3<<8))
1117	serge	4099
1430	serge	4100	// BIOS_6_SCRATCH Definition
1117	serge	4101	#define ATOM_S6_DEVICE_CHANGE 0x00000001L
		4102	#define ATOM_S6_SCALER_CHANGE 0x00000002L
		4103	#define ATOM_S6_LID_CHANGE 0x00000004L
		4104	#define ATOM_S6_DOCKING_CHANGE 0x00000008L
		4105	#define ATOM_S6_ACC_MODE 0x00000010L
		4106	#define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L
		4107	#define ATOM_S6_LID_STATE 0x00000040L
		4108	#define ATOM_S6_DOCK_STATE 0x00000080L
		4109	#define ATOM_S6_CRITICAL_STATE 0x00000100L
		4110	#define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L
		4111	#define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L
		4112	#define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L
1430	serge	4113	#define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD
		4114	#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD
1117	serge	4115
1430	serge	4116	#define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion
		4117	#define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion
1117	serge	4118
		4119	#define ATOM_S6_ACC_REQ_CRT1 0x00010000L
		4120	#define ATOM_S6_ACC_REQ_LCD1 0x00020000L
		4121	#define ATOM_S6_ACC_REQ_TV1 0x00040000L
		4122	#define ATOM_S6_ACC_REQ_DFP1 0x00080000L
		4123	#define ATOM_S6_ACC_REQ_CRT2 0x00100000L
		4124	#define ATOM_S6_ACC_REQ_LCD2 0x00200000L
1430	serge	4125	#define ATOM_S6_ACC_REQ_DFP6 0x00400000L
1117	serge	4126	#define ATOM_S6_ACC_REQ_DFP2 0x00800000L
		4127	#define ATOM_S6_ACC_REQ_CV 0x01000000L
		4128	#define ATOM_S6_ACC_REQ_DFP3 0x02000000L
		4129	#define ATOM_S6_ACC_REQ_DFP4 0x04000000L
		4130	#define ATOM_S6_ACC_REQ_DFP5 0x08000000L
		4131
		4132	#define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L
		4133	#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L
		4134	#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L
		4135	#define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L
		4136	#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L
		4137
1430	serge	4138	//Byte aligned defintion for BIOS usage
1117	serge	4139	#define ATOM_S6_DEVICE_CHANGEb0 0x01
		4140	#define ATOM_S6_SCALER_CHANGEb0 0x02
		4141	#define ATOM_S6_LID_CHANGEb0 0x04
		4142	#define ATOM_S6_DOCKING_CHANGEb0 0x08
		4143	#define ATOM_S6_ACC_MODEb0 0x10
		4144	#define ATOM_S6_EXT_DESKTOP_MODEb0 0x20
		4145	#define ATOM_S6_LID_STATEb0 0x40
		4146	#define ATOM_S6_DOCK_STATEb0 0x80
		4147	#define ATOM_S6_CRITICAL_STATEb1 0x01
		4148	#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02
		4149	#define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04
		4150	#define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08
		4151	#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10
		4152	#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20
		4153
		4154	#define ATOM_S6_ACC_REQ_CRT1b2 0x01
		4155	#define ATOM_S6_ACC_REQ_LCD1b2 0x02
		4156	#define ATOM_S6_ACC_REQ_TV1b2 0x04
		4157	#define ATOM_S6_ACC_REQ_DFP1b2 0x08
		4158	#define ATOM_S6_ACC_REQ_CRT2b2 0x10
		4159	#define ATOM_S6_ACC_REQ_LCD2b2 0x20
1430	serge	4160	#define ATOM_S6_ACC_REQ_DFP6b2 0x40
1117	serge	4161	#define ATOM_S6_ACC_REQ_DFP2b2 0x80
		4162	#define ATOM_S6_ACC_REQ_CVb3 0x01
		4163	#define ATOM_S6_ACC_REQ_DFP3b3 0x02
		4164	#define ATOM_S6_ACC_REQ_DFP4b3 0x04
		4165	#define ATOM_S6_ACC_REQ_DFP5b3 0x08
		4166
		4167	#define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0
		4168	#define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10
		4169	#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20
		4170	#define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40
		4171	#define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80
		4172
		4173	#define ATOM_S6_DEVICE_CHANGE_SHIFT 0
		4174	#define ATOM_S6_SCALER_CHANGE_SHIFT 1
		4175	#define ATOM_S6_LID_CHANGE_SHIFT 2
		4176	#define ATOM_S6_DOCKING_CHANGE_SHIFT 3
		4177	#define ATOM_S6_ACC_MODE_SHIFT 4
		4178	#define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5
		4179	#define ATOM_S6_LID_STATE_SHIFT 6
		4180	#define ATOM_S6_DOCK_STATE_SHIFT 7
		4181	#define ATOM_S6_CRITICAL_STATE_SHIFT 8
		4182	#define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9
		4183	#define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10
		4184	#define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11
		4185	#define ATOM_S6_REQ_SCALER_SHIFT 12
		4186	#define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13
		4187	#define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14
		4188	#define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15
		4189	#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28
		4190	#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29
		4191	#define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30
		4192	#define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31
		4193
1430	serge	4194	// BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!!
1117	serge	4195	#define ATOM_S7_DOS_MODE_TYPEb0 0x03
		4196	#define ATOM_S7_DOS_MODE_VGAb0 0x00
		4197	#define ATOM_S7_DOS_MODE_VESAb0 0x01
		4198	#define ATOM_S7_DOS_MODE_EXTb0 0x02
		4199	#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C
		4200	#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0
		4201	#define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01
		4202	#define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF
		4203
		4204	#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8
		4205
1430	serge	4206	// BIOS_8_SCRATCH Definition
1117	serge	4207	#define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF
		4208	#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000
		4209
		4210	#define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0
		4211	#define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16
		4212
1430	serge	4213	// BIOS_9_SCRATCH Definition
1117	serge	4214	#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK
		4215	#define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF
		4216	#endif
		4217	#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK
		4218	#define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000
		4219	#endif
		4220	#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT
		4221	#define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0
		4222	#endif
		4223	#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT
		4224	#define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16
		4225	#endif
		4226
1430	serge	4227
1117	serge	4228	#define ATOM_FLAG_SET 0x20
		4229	#define ATOM_FLAG_CLEAR 0
1430	serge	4230	#define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )\|ATOM_S6_ACC_MODE_SHIFT \| ATOM_FLAG_CLEAR)
		4231	#define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )\|ATOM_S6_DEVICE_CHANGE_SHIFT \| ATOM_FLAG_SET)
		4232	#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )\|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT \| ATOM_FLAG_SET)
		4233	#define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )\|ATOM_S6_SCALER_CHANGE_SHIFT \| ATOM_FLAG_SET)
		4234	#define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )\|ATOM_S6_LID_CHANGE_SHIFT \| ATOM_FLAG_SET)
1117	serge	4235
1430	serge	4236	#define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )\|ATOM_S6_LID_STATE_SHIFT \| ATOM_FLAG_SET)
		4237	#define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )\|ATOM_S6_LID_STATE_SHIFT \| ATOM_FLAG_CLEAR)
1117	serge	4238
1430	serge	4239	#define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )\|ATOM_S6_DOCKING_CHANGE_SHIFT \| ATOM_FLAG_SET)
		4240	#define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )\|ATOM_S6_DOCK_STATE_SHIFT \| ATOM_FLAG_SET)
		4241	#define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )\|ATOM_S6_DOCK_STATE_SHIFT \| ATOM_FLAG_CLEAR)
1117	serge	4242
1430	serge	4243	#define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )\|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT \| ATOM_FLAG_SET)
		4244	#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )\|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT \| ATOM_FLAG_SET)
		4245	#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )\|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT \| ATOM_FLAG_SET)
1117	serge	4246
1430	serge	4247	#define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )\|ATOM_S6_CRITICAL_STATE_SHIFT \| ATOM_FLAG_SET)
		4248	#define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )\|ATOM_S6_CRITICAL_STATE_SHIFT \| ATOM_FLAG_CLEAR)
1117	serge	4249
1430	serge	4250	#define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )\|ATOM_S6_REQ_SCALER_SHIFT \| ATOM_FLAG_SET)
		4251	#define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )\|ATOM_S6_REQ_SCALER_SHIFT \| ATOM_FLAG_CLEAR )
1117	serge	4252
1430	serge	4253	#define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )\|ATOM_S6_REQ_SCALER_ARATIO_SHIFT \| ATOM_FLAG_SET )
		4254	#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )\|ATOM_S6_REQ_SCALER_ARATIO_SHIFT \| ATOM_FLAG_CLEAR )
1117	serge	4255
1430	serge	4256	#define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )\|ATOM_S6_I2C_STATE_CHANGE_SHIFT \| ATOM_FLAG_SET )
1117	serge	4257
1430	serge	4258	#define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )\|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT \| ATOM_FLAG_SET )
1117	serge	4259
1430	serge	4260	#define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )\|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT \| ATOM_FLAG_SET)
		4261	#define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )\| ATOM_S0_LCD1_SHIFT \| ATOM_FLAG_CLEAR )
		4262	#define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )\|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT \| ATOM_FLAG_SET )
		4263	#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )\|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT \| ATOM_FLAG_CLEAR )
1117	serge	4264
		4265	/****************************************************************************/
1430	serge	4266	//Portion II: Definitinos only used in Driver
1117	serge	4267	/****************************************************************************/
		4268
1430	serge	4269	// Macros used by driver
		4270	#ifdef __cplusplus
		4271	#define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast(&(static_cast(0))->FieldName)-static_cast(0))/sizeof(USHORT))
1117	serge	4272
1430	serge	4273	#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F)
		4274	#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F)
		4275	#else // not __cplusplus
		4276	#define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES)0)->FieldName)-(char*)0)/sizeof(USHORT))
1117	serge	4277
		4278	#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F)
		4279	#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F)
1430	serge	4280	#endif // __cplusplus
1117	serge	4281
		4282	#define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION
		4283	#define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION
		4284
		4285	/****************************************************************************/
1430	serge	4286	//Portion III: Definitinos only used in VBIOS
1117	serge	4287	/****************************************************************************/
		4288	#define ATOM_DAC_SRC 0x80
		4289	#define ATOM_SRC_DAC1 0
		4290	#define ATOM_SRC_DAC2 0x80
		4291
1430	serge	4292	typedef struct _MEMORY_PLLINIT_PARAMETERS
		4293	{
		4294	ULONG ulTargetMemoryClock; //In 10Khz unit
		4295	UCHAR ucAction; //not define yet
		4296	UCHAR ucFbDiv_Hi; //Fbdiv Hi byte
		4297	UCHAR ucFbDiv; //FB value
		4298	UCHAR ucPostDiv; //Post div
		4299	}MEMORY_PLLINIT_PARAMETERS;
1117	serge	4300
		4301	#define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS
		4302
1430	serge	4303
1117	serge	4304	#define GPIO_PIN_WRITE 0x01
		4305	#define GPIO_PIN_READ 0x00
		4306
1430	serge	4307	typedef struct _GPIO_PIN_CONTROL_PARAMETERS
		4308	{
		4309	UCHAR ucGPIO_ID; //return value, read from GPIO pins
		4310	UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update
		4311	UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask
		4312	UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write
		4313	}GPIO_PIN_CONTROL_PARAMETERS;
1117	serge	4314
1430	serge	4315	typedef struct _ENABLE_SCALER_PARAMETERS
		4316	{
		4317	UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2
		4318	UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION
		4319	UCHAR ucTVStandard; //
1117	serge	4320	UCHAR ucPadding[1];
1430	serge	4321	}ENABLE_SCALER_PARAMETERS;
1117	serge	4322	#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS
		4323
1430	serge	4324	//ucEnable:
1117	serge	4325	#define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0
		4326	#define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1
		4327	#define SCALER_ENABLE_2TAP_ALPHA_MODE 2
		4328	#define SCALER_ENABLE_MULTITAP_MODE 3
		4329
1430	serge	4330	typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS
		4331	{
		4332	ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position
		4333	UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset
		4334	UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset
		4335	UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2
		4336	UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
		4337	}ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS;
1117	serge	4338
1430	serge	4339	typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION
		4340	{
1117	serge	4341	ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon;
		4342	ENABLE_CRTC_PARAMETERS sReserved;
1430	serge	4343	}ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION;
1117	serge	4344
1430	serge	4345	typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS
		4346	{
		4347	USHORT usHight; // Image Hight
		4348	USHORT usWidth; // Image Width
		4349	UCHAR ucSurface; // Surface 1 or 2
1117	serge	4350	UCHAR ucPadding[3];
1430	serge	4351	}ENABLE_GRAPH_SURFACE_PARAMETERS;
1117	serge	4352
1430	serge	4353	typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2
		4354	{
		4355	USHORT usHight; // Image Hight
		4356	USHORT usWidth; // Image Width
		4357	UCHAR ucSurface; // Surface 1 or 2
		4358	UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1117	serge	4359	UCHAR ucPadding[2];
1430	serge	4360	}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2;
1117	serge	4361
1430	serge	4362	typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3
		4363	{
		4364	USHORT usHight; // Image Hight
		4365	USHORT usWidth; // Image Width
		4366	UCHAR ucSurface; // Surface 1 or 2
		4367	UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
		4368	USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0.
		4369	}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3;
		4370
		4371	typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION
		4372	{
1117	serge	4373	ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface;
1430	serge	4374	ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one
		4375	}ENABLE_GRAPH_SURFACE_PS_ALLOCATION;
1117	serge	4376
1430	serge	4377	typedef struct _MEMORY_CLEAN_UP_PARAMETERS
		4378	{
		4379	USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address
		4380	USHORT usMemorySize; //8Kb blocks aligned
		4381	}MEMORY_CLEAN_UP_PARAMETERS;
1117	serge	4382	#define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS
		4383
1430	serge	4384	typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS
		4385	{
		4386	USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC
1117	serge	4387	USHORT usY_Size;
1430	serge	4388	}GET_DISPLAY_SURFACE_SIZE_PARAMETERS;
1117	serge	4389
1430	serge	4390	typedef struct _INDIRECT_IO_ACCESS
		4391	{
1117	serge	4392	ATOM_COMMON_TABLE_HEADER sHeader;
		4393	UCHAR IOAccessSequence[256];
		4394	} INDIRECT_IO_ACCESS;
		4395
		4396	#define INDIRECT_READ 0x00
		4397	#define INDIRECT_WRITE 0x80
		4398
		4399	#define INDIRECT_IO_MM 0
		4400	#define INDIRECT_IO_PLL 1
		4401	#define INDIRECT_IO_MC 2
		4402	#define INDIRECT_IO_PCIE 3
		4403	#define INDIRECT_IO_PCIEP 4
		4404	#define INDIRECT_IO_NBMISC 5
		4405
		4406	#define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL \| INDIRECT_READ
		4407	#define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL \| INDIRECT_WRITE
		4408	#define INDIRECT_IO_MC_READ INDIRECT_IO_MC \| INDIRECT_READ
		4409	#define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC \| INDIRECT_WRITE
		4410	#define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE \| INDIRECT_READ
		4411	#define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE \| INDIRECT_WRITE
		4412	#define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP \| INDIRECT_READ
		4413	#define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP \| INDIRECT_WRITE
		4414	#define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC \| INDIRECT_READ
		4415	#define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC \| INDIRECT_WRITE
		4416
1430	serge	4417	typedef struct _ATOM_OEM_INFO
		4418	{
1117	serge	4419	ATOM_COMMON_TABLE_HEADER sHeader;
		4420	ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
1430	serge	4421	}ATOM_OEM_INFO;
1117	serge	4422
1430	serge	4423	typedef struct _ATOM_TV_MODE
		4424	{
		4425	UCHAR ucVMode_Num; //Video mode number
		4426	UCHAR ucTV_Mode_Num; //Internal TV mode number
		4427	}ATOM_TV_MODE;
1117	serge	4428
1430	serge	4429	typedef struct _ATOM_BIOS_INT_TVSTD_MODE
		4430	{
		4431	ATOM_COMMON_TABLE_HEADER sHeader;
		4432	USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table
		4433	USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table
		4434	USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table
		4435	USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table
		4436	USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table
		4437	}ATOM_BIOS_INT_TVSTD_MODE;
1117	serge	4438
1430	serge	4439
		4440	typedef struct _ATOM_TV_MODE_SCALER_PTR
		4441	{
		4442	USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients
		4443	USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients
1117	serge	4444	UCHAR ucTV_Mode_Num;
1430	serge	4445	}ATOM_TV_MODE_SCALER_PTR;
1117	serge	4446
1430	serge	4447	typedef struct _ATOM_STANDARD_VESA_TIMING
		4448	{
1117	serge	4449	ATOM_COMMON_TABLE_HEADER sHeader;
1430	serge	4450	ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation
		4451	}ATOM_STANDARD_VESA_TIMING;
1117	serge	4452
1430	serge	4453
		4454	typedef struct _ATOM_STD_FORMAT
		4455	{
1117	serge	4456	USHORT usSTD_HDisp;
		4457	USHORT usSTD_VDisp;
		4458	USHORT usSTD_RefreshRate;
		4459	USHORT usReserved;
1430	serge	4460	}ATOM_STD_FORMAT;
1117	serge	4461
1430	serge	4462	typedef struct _ATOM_VESA_TO_EXTENDED_MODE
		4463	{
1117	serge	4464	USHORT usVESA_ModeNumber;
		4465	USHORT usExtendedModeNumber;
1430	serge	4466	}ATOM_VESA_TO_EXTENDED_MODE;
1117	serge	4467
1430	serge	4468	typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT
		4469	{
1117	serge	4470	ATOM_COMMON_TABLE_HEADER sHeader;
		4471	ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76];
1430	serge	4472	}ATOM_VESA_TO_INTENAL_MODE_LUT;
1117	serge	4473
		4474	/************* ATOM Memory Related Data Structure *********************/
1430	serge	4475	typedef struct _ATOM_MEMORY_VENDOR_BLOCK{
1117	serge	4476	UCHAR ucMemoryType;
		4477	UCHAR ucMemoryVendor;
		4478	UCHAR ucAdjMCId;
		4479	UCHAR ucDynClkId;
		4480	ULONG ulDllResetClkRange;
1430	serge	4481	}ATOM_MEMORY_VENDOR_BLOCK;
1117	serge	4482
1430	serge	4483
		4484	typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{
1117	serge	4485	#if ATOM_BIG_ENDIAN
		4486	ULONG ucMemBlkId:8;
		4487	ULONG ulMemClockRange:24;
		4488	#else
		4489	ULONG ulMemClockRange:24;
		4490	ULONG ucMemBlkId:8;
		4491	#endif
1430	serge	4492	}ATOM_MEMORY_SETTING_ID_CONFIG;
1117	serge	4493
1430	serge	4494	typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS
		4495	{
1117	serge	4496	ATOM_MEMORY_SETTING_ID_CONFIG slAccess;
		4497	ULONG ulAccess;
1430	serge	4498	}ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS;
1117	serge	4499
1430	serge	4500
		4501	typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{
1117	serge	4502	ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID;
		4503	ULONG aulMemData[1];
1430	serge	4504	}ATOM_MEMORY_SETTING_DATA_BLOCK;
1117	serge	4505
		4506
1430	serge	4507	typedef struct _ATOM_INIT_REG_INDEX_FORMAT{
		4508	USHORT usRegIndex; // MC register index
		4509	UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf
		4510	}ATOM_INIT_REG_INDEX_FORMAT;
		4511
		4512
		4513	typedef struct _ATOM_INIT_REG_BLOCK{
		4514	USHORT usRegIndexTblSize; //size of asRegIndexBuf
		4515	USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK
1117	serge	4516	ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1];
		4517	ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1];
1430	serge	4518	}ATOM_INIT_REG_BLOCK;
1117	serge	4519
		4520	#define END_OF_REG_INDEX_BLOCK 0x0ffff
		4521	#define END_OF_REG_DATA_BLOCK 0x00000000
		4522	#define ATOM_INIT_REG_MASK_FLAG 0x80
		4523	#define CLOCK_RANGE_HIGHEST 0x00ffffff
		4524
		4525	#define VALUE_DWORD SIZEOF ULONG
		4526	#define VALUE_SAME_AS_ABOVE 0
		4527	#define VALUE_MASK_DWORD 0x84
		4528
		4529	#define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1)
		4530	#define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1)
		4531	#define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1)
		4532
1430	serge	4533
		4534	typedef struct _ATOM_MC_INIT_PARAM_TABLE
		4535	{
1117	serge	4536	ATOM_COMMON_TABLE_HEADER sHeader;
		4537	USHORT usAdjustARB_SEQDataOffset;
		4538	USHORT usMCInitMemTypeTblOffset;
		4539	USHORT usMCInitCommonTblOffset;
		4540	USHORT usMCInitPowerDownTblOffset;
		4541	ULONG ulARB_SEQDataBuf[32];
		4542	ATOM_INIT_REG_BLOCK asMCInitMemType;
		4543	ATOM_INIT_REG_BLOCK asMCInitCommon;
1430	serge	4544	}ATOM_MC_INIT_PARAM_TABLE;
1117	serge	4545
1430	serge	4546
1117	serge	4547	#define _4Mx16 0x2
		4548	#define _4Mx32 0x3
		4549	#define _8Mx16 0x12
		4550	#define _8Mx32 0x13
		4551	#define _16Mx16 0x22
		4552	#define _16Mx32 0x23
		4553	#define _32Mx16 0x32
		4554	#define _32Mx32 0x33
		4555	#define _64Mx8 0x41
		4556	#define _64Mx16 0x42
		4557
		4558	#define SAMSUNG 0x1
		4559	#define INFINEON 0x2
		4560	#define ELPIDA 0x3
		4561	#define ETRON 0x4
		4562	#define NANYA 0x5
		4563	#define HYNIX 0x6
		4564	#define MOSEL 0x7
		4565	#define WINBOND 0x8
		4566	#define ESMT 0x9
		4567	#define MICRON 0xF
		4568
		4569	#define QIMONDA INFINEON
		4570	#define PROMOS MOSEL
1430	serge	4571	#define KRETON INFINEON
1117	serge	4572
1430	serge	4573	/////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM/////////////
1117	serge	4574
		4575	#define UCODE_ROM_START_ADDRESS 0x1c000
1430	serge	4576	#define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode
1117	serge	4577
1430	serge	4578	//uCode block header for reference
1117	serge	4579
1430	serge	4580	typedef struct _MCuCodeHeader
		4581	{
1117	serge	4582	ULONG ulSignature;
		4583	UCHAR ucRevision;
		4584	UCHAR ucChecksum;
		4585	UCHAR ucReserved1;
		4586	UCHAR ucReserved2;
		4587	USHORT usParametersLength;
		4588	USHORT usUCodeLength;
		4589	USHORT usReserved1;
		4590	USHORT usReserved2;
		4591	} MCuCodeHeader;
		4592
1430	serge	4593	//////////////////////////////////////////////////////////////////////////////////
1117	serge	4594
		4595	#define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16
		4596
		4597	#define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF
1430	serge	4598	typedef struct _ATOM_VRAM_MODULE_V1
		4599	{
1117	serge	4600	ULONG ulReserved;
		4601	USHORT usEMRSValue;
		4602	USHORT usMRSValue;
		4603	USHORT usReserved;
1430	serge	4604	UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
		4605	UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved;
		4606	UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender
		4607	UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
		4608	UCHAR ucRow; // Number of Row,in power of 2;
		4609	UCHAR ucColumn; // Number of Column,in power of 2;
		4610	UCHAR ucBank; // Nunber of Bank;
		4611	UCHAR ucRank; // Number of Rank, in power of 2
		4612	UCHAR ucChannelNum; // Number of channel;
		4613	UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
		4614	UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
		4615	UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
1117	serge	4616	UCHAR ucReserved[2];
1430	serge	4617	}ATOM_VRAM_MODULE_V1;
1117	serge	4618
1430	serge	4619
		4620	typedef struct _ATOM_VRAM_MODULE_V2
		4621	{
1117	serge	4622	ULONG ulReserved;
1430	serge	4623	ULONG ulFlags; // To enable/disable functionalities based on memory type
		4624	ULONG ulEngineClock; // Override of default engine clock for particular memory type
		4625	ULONG ulMemoryClock; // Override of default memory clock for particular memory type
		4626	USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
		4627	USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
1117	serge	4628	USHORT usEMRSValue;
		4629	USHORT usMRSValue;
		4630	USHORT usReserved;
1430	serge	4631	UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
		4632	UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
		4633	UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
		4634	UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
		4635	UCHAR ucRow; // Number of Row,in power of 2;
		4636	UCHAR ucColumn; // Number of Column,in power of 2;
		4637	UCHAR ucBank; // Nunber of Bank;
		4638	UCHAR ucRank; // Number of Rank, in power of 2
		4639	UCHAR ucChannelNum; // Number of channel;
		4640	UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
		4641	UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
		4642	UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
1117	serge	4643	UCHAR ucRefreshRateFactor;
		4644	UCHAR ucReserved[3];
1430	serge	4645	}ATOM_VRAM_MODULE_V2;
1117	serge	4646
1430	serge	4647
		4648	typedef struct _ATOM_MEMORY_TIMING_FORMAT
		4649	{
		4650	ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
		4651	union{
		4652	USHORT usMRS; // mode register
1117	serge	4653	USHORT usDDR3_MR0;
		4654	};
1430	serge	4655	union{
		4656	USHORT usEMRS; // extended mode register
1117	serge	4657	USHORT usDDR3_MR1;
		4658	};
1430	serge	4659	UCHAR ucCL; // CAS latency
		4660	UCHAR ucWL; // WRITE Latency
		4661	UCHAR uctRAS; // tRAS
		4662	UCHAR uctRC; // tRC
		4663	UCHAR uctRFC; // tRFC
		4664	UCHAR uctRCDR; // tRCDR
		4665	UCHAR uctRCDW; // tRCDW
		4666	UCHAR uctRP; // tRP
		4667	UCHAR uctRRD; // tRRD
		4668	UCHAR uctWR; // tWR
		4669	UCHAR uctWTR; // tWTR
		4670	UCHAR uctPDIX; // tPDIX
		4671	UCHAR uctFAW; // tFAW
		4672	UCHAR uctAOND; // tAOND
		4673	union
		4674	{
1117	serge	4675	struct {
1430	serge	4676	UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
1117	serge	4677	UCHAR ucReserved;
		4678	};
		4679	USHORT usDDR3_MR2;
		4680	};
1430	serge	4681	}ATOM_MEMORY_TIMING_FORMAT;
1117	serge	4682
1430	serge	4683
		4684	typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1
		4685	{
		4686	ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
		4687	USHORT usMRS; // mode register
		4688	USHORT usEMRS; // extended mode register
		4689	UCHAR ucCL; // CAS latency
		4690	UCHAR ucWL; // WRITE Latency
		4691	UCHAR uctRAS; // tRAS
		4692	UCHAR uctRC; // tRC
		4693	UCHAR uctRFC; // tRFC
		4694	UCHAR uctRCDR; // tRCDR
		4695	UCHAR uctRCDW; // tRCDW
		4696	UCHAR uctRP; // tRP
		4697	UCHAR uctRRD; // tRRD
		4698	UCHAR uctWR; // tWR
		4699	UCHAR uctWTR; // tWTR
		4700	UCHAR uctPDIX; // tPDIX
		4701	UCHAR uctFAW; // tFAW
		4702	UCHAR uctAOND; // tAOND
		4703	UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
		4704	////////////////////////////////////GDDR parameters///////////////////////////////////
		4705	UCHAR uctCCDL; //
		4706	UCHAR uctCRCRL; //
		4707	UCHAR uctCRCWL; //
		4708	UCHAR uctCKE; //
		4709	UCHAR uctCKRSE; //
		4710	UCHAR uctCKRSX; //
		4711	UCHAR uctFAW32; //
		4712	UCHAR ucMR5lo; //
		4713	UCHAR ucMR5hi; //
		4714	UCHAR ucTerminator;
		4715	}ATOM_MEMORY_TIMING_FORMAT_V1;
		4716
		4717	typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2
		4718	{
		4719	ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
		4720	USHORT usMRS; // mode register
		4721	USHORT usEMRS; // extended mode register
		4722	UCHAR ucCL; // CAS latency
		4723	UCHAR ucWL; // WRITE Latency
		4724	UCHAR uctRAS; // tRAS
		4725	UCHAR uctRC; // tRC
		4726	UCHAR uctRFC; // tRFC
		4727	UCHAR uctRCDR; // tRCDR
		4728	UCHAR uctRCDW; // tRCDW
		4729	UCHAR uctRP; // tRP
		4730	UCHAR uctRRD; // tRRD
		4731	UCHAR uctWR; // tWR
		4732	UCHAR uctWTR; // tWTR
		4733	UCHAR uctPDIX; // tPDIX
		4734	UCHAR uctFAW; // tFAW
		4735	UCHAR uctAOND; // tAOND
		4736	UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
		4737	////////////////////////////////////GDDR parameters///////////////////////////////////
		4738	UCHAR uctCCDL; //
		4739	UCHAR uctCRCRL; //
		4740	UCHAR uctCRCWL; //
		4741	UCHAR uctCKE; //
		4742	UCHAR uctCKRSE; //
		4743	UCHAR uctCKRSX; //
		4744	UCHAR uctFAW32; //
		4745	UCHAR ucMR4lo; //
		4746	UCHAR ucMR4hi; //
		4747	UCHAR ucMR5lo; //
		4748	UCHAR ucMR5hi; //
1117	serge	4749	UCHAR ucTerminator;
1430	serge	4750	UCHAR ucReserved;
		4751	}ATOM_MEMORY_TIMING_FORMAT_V2;
1117	serge	4752
1430	serge	4753	typedef struct _ATOM_MEMORY_FORMAT
		4754	{
		4755	ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock
		4756	union{
		4757	USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
		4758	USHORT usDDR3_Reserved; // Not used for DDR3 memory
1117	serge	4759	};
1430	serge	4760	union{
		4761	USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
		4762	USHORT usDDR3_MR3; // Used for DDR3 memory
1117	serge	4763	};
1430	serge	4764	UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
		4765	UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
		4766	UCHAR ucRow; // Number of Row,in power of 2;
		4767	UCHAR ucColumn; // Number of Column,in power of 2;
		4768	UCHAR ucBank; // Nunber of Bank;
		4769	UCHAR ucRank; // Number of Rank, in power of 2
		4770	UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8
		4771	UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register )
		4772	UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms
		4773	UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
		4774	UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble
		4775	UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc
		4776	ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; //Memory Timing block sort from lower clock to higher clock
		4777	}ATOM_MEMORY_FORMAT;
1117	serge	4778
		4779
1430	serge	4780	typedef struct _ATOM_VRAM_MODULE_V3
		4781	{
		4782	ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination
		4783	USHORT usSize; // size of ATOM_VRAM_MODULE_V3
		4784	USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage
		4785	USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage
		4786	UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
		4787	UCHAR ucChannelNum; // board dependent parameter:Number of channel;
		4788	UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit
		4789	UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
		4790	UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
		4791	UCHAR ucFlag; // To enable/disable functionalities based on memory type
		4792	ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec
		4793	}ATOM_VRAM_MODULE_V3;
		4794
		4795
		4796	//ATOM_VRAM_MODULE_V3.ucNPL_RT
1117	serge	4797	#define NPL_RT_MASK 0x0f
		4798	#define BATTERY_ODT_MASK 0xc0
		4799
		4800	#define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3
		4801
1430	serge	4802	typedef struct _ATOM_VRAM_MODULE_V4
		4803	{
		4804	ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
		4805	USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
		4806	USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
		4807	// MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
1117	serge	4808	USHORT usReserved;
1430	serge	4809	UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
		4810	UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
		4811	UCHAR ucChannelNum; // Number of channels present in this module config
		4812	UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
		4813	UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
		4814	UCHAR ucFlag; // To enable/disable functionalities based on memory type
		4815	UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
		4816	UCHAR ucVREFI; // board dependent parameter
		4817	UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
		4818	UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
		4819	UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
		4820	// Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
1117	serge	4821	UCHAR ucReserved[3];
		4822
1430	serge	4823	//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
		4824	union{
		4825	USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
1117	serge	4826	USHORT usDDR3_Reserved;
		4827	};
1430	serge	4828	union{
		4829	USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
		4830	USHORT usDDR3_MR3; // Used for DDR3 memory
1117	serge	4831	};
1430	serge	4832	UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
		4833	UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
1117	serge	4834	UCHAR ucReserved2[2];
1430	serge	4835	ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
		4836	}ATOM_VRAM_MODULE_V4;
1117	serge	4837
		4838	#define VRAM_MODULE_V4_MISC_RANK_MASK 0x3
		4839	#define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1
		4840	#define VRAM_MODULE_V4_MISC_BL_MASK 0x4
		4841	#define VRAM_MODULE_V4_MISC_BL8 0x4
		4842	#define VRAM_MODULE_V4_MISC_DUAL_CS 0x10
		4843
1430	serge	4844	typedef struct _ATOM_VRAM_MODULE_V5
		4845	{
		4846	ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
		4847	USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
		4848	USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
		4849	// MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
		4850	USHORT usReserved;
		4851	UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
		4852	UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
		4853	UCHAR ucChannelNum; // Number of channels present in this module config
		4854	UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
		4855	UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
		4856	UCHAR ucFlag; // To enable/disable functionalities based on memory type
		4857	UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
		4858	UCHAR ucVREFI; // board dependent parameter
		4859	UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
		4860	UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
		4861	UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
		4862	// Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
		4863	UCHAR ucReserved[3];
		4864
		4865	//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
		4866	USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
		4867	USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
		4868	UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
		4869	UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
		4870	UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
		4871	UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
		4872	ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
		4873	}ATOM_VRAM_MODULE_V5;
		4874
		4875	typedef struct _ATOM_VRAM_MODULE_V6
		4876	{
		4877	ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
		4878	USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
		4879	USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
		4880	// MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
1117	serge	4881	USHORT usReserved;
1430	serge	4882	UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
		4883	UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
		4884	UCHAR ucChannelNum; // Number of channels present in this module config
		4885	UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
		4886	UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
		4887	UCHAR ucFlag; // To enable/disable functionalities based on memory type
		4888	UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
		4889	UCHAR ucVREFI; // board dependent parameter
		4890	UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
		4891	UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
		4892	UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
		4893	// Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
1117	serge	4894	UCHAR ucReserved[3];
		4895
1430	serge	4896	//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
		4897	USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
		4898	USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
		4899	UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
		4900	UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
		4901	UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
		4902	UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
		4903	ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
		4904	}ATOM_VRAM_MODULE_V6;
1117	serge	4905
1430	serge	4906
		4907
		4908	typedef struct _ATOM_VRAM_INFO_V2
		4909	{
1117	serge	4910	ATOM_COMMON_TABLE_HEADER sHeader;
		4911	UCHAR ucNumOfVRAMModule;
1430	serge	4912	ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
		4913	}ATOM_VRAM_INFO_V2;
1117	serge	4914
1430	serge	4915	typedef struct _ATOM_VRAM_INFO_V3
		4916	{
1117	serge	4917	ATOM_COMMON_TABLE_HEADER sHeader;
1430	serge	4918	USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
		4919	USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
1117	serge	4920	USHORT usRerseved;
1430	serge	4921	UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator
1117	serge	4922	UCHAR ucNumOfVRAMModule;
1430	serge	4923	ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
		4924	ATOM_INIT_REG_BLOCK asMemPatch; // for allocation
		4925	// ATOM_INIT_REG_BLOCK aMemAdjust;
		4926	}ATOM_VRAM_INFO_V3;
1117	serge	4927
		4928	#define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3
		4929
1430	serge	4930	typedef struct _ATOM_VRAM_INFO_V4
		4931	{
1117	serge	4932	ATOM_COMMON_TABLE_HEADER sHeader;
1430	serge	4933	USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
		4934	USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
1117	serge	4935	USHORT usRerseved;
1430	serge	4936	UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3
		4937	ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21]
1117	serge	4938	UCHAR ucReservde[4];
		4939	UCHAR ucNumOfVRAMModule;
1430	serge	4940	ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
		4941	ATOM_INIT_REG_BLOCK asMemPatch; // for allocation
		4942	// ATOM_INIT_REG_BLOCK aMemAdjust;
		4943	}ATOM_VRAM_INFO_V4;
1117	serge	4944
1430	serge	4945	typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO
		4946	{
1117	serge	4947	ATOM_COMMON_TABLE_HEADER sHeader;
1430	serge	4948	UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator
		4949	}ATOM_VRAM_GPIO_DETECTION_INFO;
1117	serge	4950
1430	serge	4951
		4952	typedef struct _ATOM_MEMORY_TRAINING_INFO
		4953	{
1117	serge	4954	ATOM_COMMON_TABLE_HEADER sHeader;
		4955	UCHAR ucTrainingLoop;
		4956	UCHAR ucReserved[3];
		4957	ATOM_INIT_REG_BLOCK asMemTrainingSetting;
1430	serge	4958	}ATOM_MEMORY_TRAINING_INFO;
1117	serge	4959
1430	serge	4960
		4961	typedef struct SW_I2C_CNTL_DATA_PARAMETERS
		4962	{
1117	serge	4963	UCHAR ucControl;
		4964	UCHAR ucData;
		4965	UCHAR ucSatus;
		4966	UCHAR ucTemp;
		4967	} SW_I2C_CNTL_DATA_PARAMETERS;
		4968
		4969	#define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS
		4970
1430	serge	4971	typedef struct _SW_I2C_IO_DATA_PARAMETERS
		4972	{
1117	serge	4973	USHORT GPIO_Info;
		4974	UCHAR ucAct;
		4975	UCHAR ucData;
1430	serge	4976	} SW_I2C_IO_DATA_PARAMETERS;
1117	serge	4977
		4978	#define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS
		4979
		4980	/**************************SW I2C CNTL DEFINITIONS********************/
		4981	#define SW_I2C_IO_RESET 0
		4982	#define SW_I2C_IO_GET 1
		4983	#define SW_I2C_IO_DRIVE 2
		4984	#define SW_I2C_IO_SET 3
		4985	#define SW_I2C_IO_START 4
		4986
		4987	#define SW_I2C_IO_CLOCK 0
		4988	#define SW_I2C_IO_DATA 0x80
		4989
		4990	#define SW_I2C_IO_ZERO 0
		4991	#define SW_I2C_IO_ONE 0x100
		4992
		4993	#define SW_I2C_CNTL_READ 0
		4994	#define SW_I2C_CNTL_WRITE 1
		4995	#define SW_I2C_CNTL_START 2
		4996	#define SW_I2C_CNTL_STOP 3
		4997	#define SW_I2C_CNTL_OPEN 4
		4998	#define SW_I2C_CNTL_CLOSE 5
		4999	#define SW_I2C_CNTL_WRITE1BIT 6
		5000
1430	serge	5001	//==============================VESA definition Portion===============================
1117	serge	5002	#define VESA_OEM_PRODUCT_REV '01.00'
1430	serge	5003	#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support
1117	serge	5004	#define VESA_MODE_WIN_ATTRIBUTE 7
		5005	#define VESA_WIN_SIZE 64
		5006
1430	serge	5007	typedef struct _PTR_32_BIT_STRUCTURE
		5008	{
1117	serge	5009	USHORT Offset16;
		5010	USHORT Segment16;
		5011	} PTR_32_BIT_STRUCTURE;
		5012
1430	serge	5013	typedef union _PTR_32_BIT_UNION
		5014	{
1117	serge	5015	PTR_32_BIT_STRUCTURE SegmentOffset;
		5016	ULONG Ptr32_Bit;
		5017	} PTR_32_BIT_UNION;
		5018
1430	serge	5019	typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE
		5020	{
1117	serge	5021	UCHAR VbeSignature[4];
		5022	USHORT VbeVersion;
		5023	PTR_32_BIT_UNION OemStringPtr;
		5024	UCHAR Capabilities[4];
		5025	PTR_32_BIT_UNION VideoModePtr;
		5026	USHORT TotalMemory;
		5027	} VBE_1_2_INFO_BLOCK_UPDATABLE;
		5028
1430	serge	5029
		5030	typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE
		5031	{
1117	serge	5032	VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock;
		5033	USHORT OemSoftRev;
		5034	PTR_32_BIT_UNION OemVendorNamePtr;
		5035	PTR_32_BIT_UNION OemProductNamePtr;
		5036	PTR_32_BIT_UNION OemProductRevPtr;
		5037	} VBE_2_0_INFO_BLOCK_UPDATABLE;
		5038
1430	serge	5039	typedef union _VBE_VERSION_UNION
		5040	{
1117	serge	5041	VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock;
		5042	VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock;
		5043	} VBE_VERSION_UNION;
		5044
1430	serge	5045	typedef struct _VBE_INFO_BLOCK
		5046	{
1117	serge	5047	VBE_VERSION_UNION UpdatableVBE_Info;
		5048	UCHAR Reserved[222];
		5049	UCHAR OemData[256];
		5050	} VBE_INFO_BLOCK;
		5051
1430	serge	5052	typedef struct _VBE_FP_INFO
		5053	{
1117	serge	5054	USHORT HSize;
		5055	USHORT VSize;
		5056	USHORT FPType;
		5057	UCHAR RedBPP;
		5058	UCHAR GreenBPP;
		5059	UCHAR BlueBPP;
		5060	UCHAR ReservedBPP;
		5061	ULONG RsvdOffScrnMemSize;
		5062	ULONG RsvdOffScrnMEmPtr;
		5063	UCHAR Reserved[14];
		5064	} VBE_FP_INFO;
		5065
1430	serge	5066	typedef struct _VESA_MODE_INFO_BLOCK
		5067	{
		5068	// Mandatory information for all VBE revisions
		5069	USHORT ModeAttributes; // dw ? ; mode attributes
		5070	UCHAR WinAAttributes; // db ? ; window A attributes
		5071	UCHAR WinBAttributes; // db ? ; window B attributes
		5072	USHORT WinGranularity; // dw ? ; window granularity
		5073	USHORT WinSize; // dw ? ; window size
		5074	USHORT WinASegment; // dw ? ; window A start segment
		5075	USHORT WinBSegment; // dw ? ; window B start segment
		5076	ULONG WinFuncPtr; // dd ? ; real mode pointer to window function
		5077	USHORT BytesPerScanLine;// dw ? ; bytes per scan line
1117	serge	5078
1430	serge	5079	//; Mandatory information for VBE 1.2 and above
		5080	USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters
		5081	USHORT YResolution; // dw ? ; vertical resolution in pixels or characters
		5082	UCHAR XCharSize; // db ? ; character cell width in pixels
		5083	UCHAR YCharSize; // db ? ; character cell height in pixels
		5084	UCHAR NumberOfPlanes; // db ? ; number of memory planes
		5085	UCHAR BitsPerPixel; // db ? ; bits per pixel
		5086	UCHAR NumberOfBanks; // db ? ; number of banks
		5087	UCHAR MemoryModel; // db ? ; memory model type
		5088	UCHAR BankSize; // db ? ; bank size in KB
		5089	UCHAR NumberOfImagePages;// db ? ; number of images
		5090	UCHAR ReservedForPageFunction;//db 1 ; reserved for page function
1117	serge	5091
1430	serge	5092	//; Direct Color fields(required for direct/6 and YUV/7 memory models)
		5093	UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits
		5094	UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask
		5095	UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits
		5096	UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask
		5097	UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits
		5098	UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask
		5099	UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits
		5100	UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask
		5101	UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes
1117	serge	5102
1430	serge	5103	//; Mandatory information for VBE 2.0 and above
		5104	ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer
		5105	ULONG Reserved_1; // dd 0 ; reserved - always set to 0
		5106	USHORT Reserved_2; // dw 0 ; reserved - always set to 0
1117	serge	5107
1430	serge	5108	//; Mandatory information for VBE 3.0 and above
		5109	USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes
		5110	UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes
		5111	UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes
		5112	UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes)
		5113	UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes)
		5114	UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes)
		5115	UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes)
		5116	UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes)
		5117	UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes)
		5118	UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes)
		5119	UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes)
		5120	ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode
		5121	UCHAR Reserved; // db 190 dup (0)
1117	serge	5122	} VESA_MODE_INFO_BLOCK;
		5123
1430	serge	5124	// BIOS function CALLS
		5125	#define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code
1117	serge	5126	#define ATOM_BIOS_FUNCTION_COP_MODE 0x00
		5127	#define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04
		5128	#define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05
		5129	#define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06
		5130	#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B
		5131	#define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E
		5132	#define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F
		5133	#define ATOM_BIOS_FUNCTION_STV_STD 0x16
		5134	#define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17
		5135	#define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18
		5136
		5137	#define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82
		5138	#define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83
		5139	#define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84
		5140	#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A
		5141	#define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B
1430	serge	5142	#define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80
		5143	#define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80
1117	serge	5144
		5145	#define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D
		5146	#define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E
		5147	#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F
1430	serge	5148	#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03
		5149	#define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7
		5150	#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state
		5151	#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state
		5152	#define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85
		5153	#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89
		5154	#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported
		5155
1117	serge	5156
1430	serge	5157	#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS
		5158	#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01
		5159	#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02
		5160	#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON.
		5161	#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY
		5162	#define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND
		5163	#define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF
		5164	#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED)
1117	serge	5165
		5166	#define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L
		5167	#define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L
		5168	#define ATOM_BIOS_REG_LOW_MASK 0x000000FFL
		5169
1430	serge	5170	// structure used for VBIOS only
1117	serge	5171
1430	serge	5172	//DispOutInfoTable
		5173	typedef struct _ASIC_TRANSMITTER_INFO
		5174	{
1117	serge	5175	USHORT usTransmitterObjId;
		5176	USHORT usSupportDevice;
		5177	UCHAR ucTransmitterCmdTblId;
		5178	UCHAR ucConfig;
1430	serge	5179	UCHAR ucEncoderID; //available 1st encoder ( default )
		5180	UCHAR ucOptionEncoderID; //available 2nd encoder ( optional )
1117	serge	5181	UCHAR uc2ndEncoderID;
		5182	UCHAR ucReserved;
1430	serge	5183	}ASIC_TRANSMITTER_INFO;
1117	serge	5184
1430	serge	5185	typedef struct _ASIC_ENCODER_INFO
		5186	{
1117	serge	5187	UCHAR ucEncoderID;
		5188	UCHAR ucEncoderConfig;
		5189	USHORT usEncoderCmdTblId;
1430	serge	5190	}ASIC_ENCODER_INFO;
1117	serge	5191
1430	serge	5192	typedef struct _ATOM_DISP_OUT_INFO
		5193	{
		5194	ATOM_COMMON_TABLE_HEADER sHeader;
		5195	USHORT ptrTransmitterInfo;
		5196	USHORT ptrEncoderInfo;
		5197	ASIC_TRANSMITTER_INFO asTransmitterInfo[1];
		5198	ASIC_ENCODER_INFO asEncoderInfo[1];
		5199	}ATOM_DISP_OUT_INFO;
		5200
		5201	typedef struct _ATOM_DISP_OUT_INFO_V2
		5202	{
1117	serge	5203	ATOM_COMMON_TABLE_HEADER sHeader;
		5204	USHORT ptrTransmitterInfo;
		5205	USHORT ptrEncoderInfo;
1430	serge	5206	USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary.
1117	serge	5207	ASIC_TRANSMITTER_INFO asTransmitterInfo[1];
		5208	ASIC_ENCODER_INFO asEncoderInfo[1];
1430	serge	5209	}ATOM_DISP_OUT_INFO_V2;
1117	serge	5210
1430	serge	5211	// DispDevicePriorityInfo
		5212	typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO
		5213	{
1117	serge	5214	ATOM_COMMON_TABLE_HEADER sHeader;
		5215	USHORT asDevicePriority[16];
1430	serge	5216	}ATOM_DISPLAY_DEVICE_PRIORITY_INFO;
1117	serge	5217
1430	serge	5218	//ProcessAuxChannelTransactionTable
		5219	typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
		5220	{
1117	serge	5221	USHORT lpAuxRequest;
		5222	USHORT lpDataOut;
		5223	UCHAR ucChannelID;
1430	serge	5224	union
		5225	{
1117	serge	5226	UCHAR ucReplyStatus;
		5227	UCHAR ucDelay;
		5228	};
		5229	UCHAR ucDataOutLen;
		5230	UCHAR ucReserved;
1430	serge	5231	}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS;
1117	serge	5232
1430	serge	5233	//ProcessAuxChannelTransactionTable
		5234	typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2
		5235	{
		5236	USHORT lpAuxRequest;
		5237	USHORT lpDataOut;
		5238	UCHAR ucChannelID;
		5239	union
		5240	{
		5241	UCHAR ucReplyStatus;
		5242	UCHAR ucDelay;
		5243	};
		5244	UCHAR ucDataOutLen;
		5245	UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
		5246	}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2;
		5247
1117	serge	5248	#define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
		5249
1430	serge	5250	//GetSinkType
1117	serge	5251
1430	serge	5252	typedef struct _DP_ENCODER_SERVICE_PARAMETERS
		5253	{
1117	serge	5254	USHORT ucLinkClock;
1430	serge	5255	union
		5256	{
		5257	UCHAR ucConfig; // for DP training command
		5258	UCHAR ucI2cId; // use for GET_SINK_TYPE command
1117	serge	5259	};
		5260	UCHAR ucAction;
		5261	UCHAR ucStatus;
		5262	UCHAR ucLaneNum;
		5263	UCHAR ucReserved[2];
1430	serge	5264	}DP_ENCODER_SERVICE_PARAMETERS;
1117	serge	5265
1430	serge	5266	// ucAction
1117	serge	5267	#define ATOM_DP_ACTION_GET_SINK_TYPE 0x01
1430	serge	5268	/* obselete */
1117	serge	5269	#define ATOM_DP_ACTION_TRAINING_START 0x02
		5270	#define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03
		5271	#define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04
		5272	#define ATOM_DP_ACTION_SET_VSWING_PREEMP 0x05
		5273	#define ATOM_DP_ACTION_GET_VSWING_PREEMP 0x06
		5274	#define ATOM_DP_ACTION_BLANKING 0x07
		5275
1430	serge	5276	// ucConfig
1117	serge	5277	#define ATOM_DP_CONFIG_ENCODER_SEL_MASK 0x03
		5278	#define ATOM_DP_CONFIG_DIG1_ENCODER 0x00
		5279	#define ATOM_DP_CONFIG_DIG2_ENCODER 0x01
		5280	#define ATOM_DP_CONFIG_EXTERNAL_ENCODER 0x02
		5281	#define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04
		5282	#define ATOM_DP_CONFIG_LINK_A 0x00
		5283	#define ATOM_DP_CONFIG_LINK_B 0x04
1430	serge	5284	/* /obselete */
1117	serge	5285	#define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
		5286
1430	serge	5287	// DP_TRAINING_TABLE
1117	serge	5288	#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR
		5289	#define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 )
1430	serge	5290	#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 )
		5291	#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 )
1117	serge	5292	#define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32)
		5293	#define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40)
		5294	#define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48)
		5295	#define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60)
		5296	#define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64)
		5297	#define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72)
		5298	#define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76)
1430	serge	5299	#define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80)
		5300	#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84)
1117	serge	5301
1430	serge	5302	typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
		5303	{
1117	serge	5304	UCHAR ucI2CSpeed;
1430	serge	5305	union
		5306	{
1117	serge	5307	UCHAR ucRegIndex;
		5308	UCHAR ucStatus;
		5309	};
		5310	USHORT lpI2CDataOut;
		5311	UCHAR ucFlag;
		5312	UCHAR ucTransBytes;
		5313	UCHAR ucSlaveAddr;
		5314	UCHAR ucLineNumber;
1430	serge	5315	}PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS;
1117	serge	5316
		5317	#define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
		5318
1430	serge	5319	//ucFlag
1117	serge	5320	#define HW_I2C_WRITE 1
		5321	#define HW_I2C_READ 0
1430	serge	5322	#define I2C_2BYTE_ADDR 0x02
1117	serge	5323
1430	serge	5324	typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2
		5325	{
		5326	UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ...
		5327	UCHAR ucReserved[3];
		5328	}SET_HWBLOCK_INSTANCE_PARAMETER_V2;
		5329
		5330	#define HWBLKINST_INSTANCE_MASK 0x07
		5331	#define HWBLKINST_HWBLK_MASK 0xF0
		5332	#define HWBLKINST_HWBLK_SHIFT 0x04
		5333
		5334	//ucHWBlock
		5335	#define SELECT_DISP_ENGINE 0
		5336	#define SELECT_DISP_PLL 1
		5337	#define SELECT_DCIO_UNIPHY_LINK0 2
		5338	#define SELECT_DCIO_UNIPHY_LINK1 3
		5339	#define SELECT_DCIO_IMPCAL 4
		5340	#define SELECT_DCIO_DIG 6
		5341	#define SELECT_CRTC_PIXEL_RATE 7
		5342
		5343	/****************************************************************************/
		5344	//Portion VI: Definitinos for vbios MC scratch registers that driver used
1117	serge	5345	/****************************************************************************/
1430	serge	5346
		5347	#define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000
		5348	#define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000
		5349	#define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000
		5350	#define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000
		5351	#define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000
		5352	#define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000
		5353	#define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000
		5354
1117	serge	5355	/****************************************************************************/
1430	serge	5356	//Portion VI: Definitinos being oboselete
		5357	/****************************************************************************/
1117	serge	5358
1430	serge	5359	//==========================================================================================
		5360	//Remove the definitions below when driver is ready!
		5361	typedef struct _ATOM_DAC_INFO
		5362	{
1117	serge	5363	ATOM_COMMON_TABLE_HEADER sHeader;
1430	serge	5364	USHORT usMaxFrequency; // in 10kHz unit
1117	serge	5365	USHORT usReserved;
1430	serge	5366	}ATOM_DAC_INFO;
1117	serge	5367
1430	serge	5368
		5369	typedef struct _COMPASSIONATE_DATA
		5370	{
1117	serge	5371	ATOM_COMMON_TABLE_HEADER sHeader;
		5372
1430	serge	5373	//============================== DAC1 portion
1117	serge	5374	UCHAR ucDAC1_BG_Adjustment;
		5375	UCHAR ucDAC1_DAC_Adjustment;
		5376	USHORT usDAC1_FORCE_Data;
1430	serge	5377	//============================== DAC2 portion
1117	serge	5378	UCHAR ucDAC2_CRT2_BG_Adjustment;
		5379	UCHAR ucDAC2_CRT2_DAC_Adjustment;
		5380	USHORT usDAC2_CRT2_FORCE_Data;
		5381	USHORT usDAC2_CRT2_MUX_RegisterIndex;
1430	serge	5382	UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
1117	serge	5383	UCHAR ucDAC2_NTSC_BG_Adjustment;
		5384	UCHAR ucDAC2_NTSC_DAC_Adjustment;
		5385	USHORT usDAC2_TV1_FORCE_Data;
		5386	USHORT usDAC2_TV1_MUX_RegisterIndex;
1430	serge	5387	UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
1117	serge	5388	UCHAR ucDAC2_CV_BG_Adjustment;
		5389	UCHAR ucDAC2_CV_DAC_Adjustment;
		5390	USHORT usDAC2_CV_FORCE_Data;
		5391	USHORT usDAC2_CV_MUX_RegisterIndex;
1430	serge	5392	UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
1117	serge	5393	UCHAR ucDAC2_PAL_BG_Adjustment;
		5394	UCHAR ucDAC2_PAL_DAC_Adjustment;
		5395	USHORT usDAC2_TV2_FORCE_Data;
1430	serge	5396	}COMPASSIONATE_DATA;
1117	serge	5397
		5398	/**************************Supported Device Info Table Definitions********************/
1430	serge	5399	// ucConnectInfo:
		5400	// [7:4] - connector type
		5401	// = 1 - VGA connector
		5402	// = 2 - DVI-I
		5403	// = 3 - DVI-D
		5404	// = 4 - DVI-A
		5405	// = 5 - SVIDEO
		5406	// = 6 - COMPOSITE
		5407	// = 7 - LVDS
		5408	// = 8 - DIGITAL LINK
		5409	// = 9 - SCART
		5410	// = 0xA - HDMI_type A
		5411	// = 0xB - HDMI_type B
		5412	// = 0xE - Special case1 (DVI+DIN)
		5413	// Others=TBD
		5414	// [3:0] - DAC Associated
		5415	// = 0 - no DAC
		5416	// = 1 - DACA
		5417	// = 2 - DACB
		5418	// = 3 - External DAC
		5419	// Others=TBD
		5420	//
1117	serge	5421
1430	serge	5422	typedef struct _ATOM_CONNECTOR_INFO
		5423	{
1117	serge	5424	#if ATOM_BIG_ENDIAN
		5425	UCHAR bfConnectorType:4;
		5426	UCHAR bfAssociatedDAC:4;
		5427	#else
		5428	UCHAR bfAssociatedDAC:4;
		5429	UCHAR bfConnectorType:4;
		5430	#endif
1430	serge	5431	}ATOM_CONNECTOR_INFO;
1117	serge	5432
1430	serge	5433	typedef union _ATOM_CONNECTOR_INFO_ACCESS
		5434	{
1117	serge	5435	ATOM_CONNECTOR_INFO sbfAccess;
		5436	UCHAR ucAccess;
1430	serge	5437	}ATOM_CONNECTOR_INFO_ACCESS;
1117	serge	5438
1430	serge	5439	typedef struct _ATOM_CONNECTOR_INFO_I2C
		5440	{
1117	serge	5441	ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo;
		5442	ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
1430	serge	5443	}ATOM_CONNECTOR_INFO_I2C;
1117	serge	5444
1430	serge	5445
		5446	typedef struct _ATOM_SUPPORTED_DEVICES_INFO
		5447	{
1117	serge	5448	ATOM_COMMON_TABLE_HEADER sHeader;
		5449	USHORT usDeviceSupport;
		5450	ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO];
1430	serge	5451	}ATOM_SUPPORTED_DEVICES_INFO;
1117	serge	5452
		5453	#define NO_INT_SRC_MAPPED 0xFF
		5454
1430	serge	5455	typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP
		5456	{
1117	serge	5457	UCHAR ucIntSrcBitmap;
1430	serge	5458	}ATOM_CONNECTOR_INC_SRC_BITMAP;
1117	serge	5459
1430	serge	5460	typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2
		5461	{
1117	serge	5462	ATOM_COMMON_TABLE_HEADER sHeader;
		5463	USHORT usDeviceSupport;
		5464	ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
1430	serge	5465	ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
		5466	}ATOM_SUPPORTED_DEVICES_INFO_2;
1117	serge	5467
1430	serge	5468	typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1
		5469	{
1117	serge	5470	ATOM_COMMON_TABLE_HEADER sHeader;
		5471	USHORT usDeviceSupport;
		5472	ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE];
		5473	ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE];
1430	serge	5474	}ATOM_SUPPORTED_DEVICES_INFO_2d1;
1117	serge	5475
		5476	#define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1
		5477
1430	serge	5478
		5479
		5480	typedef struct _ATOM_MISC_CONTROL_INFO
		5481	{
1117	serge	5482	USHORT usFrequency;
1430	serge	5483	UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
		5484	UCHAR ucPLL_DutyCycle; // PLL duty cycle control
		5485	UCHAR ucPLL_VCO_Gain; // PLL VCO gain control
		5486	UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control
		5487	}ATOM_MISC_CONTROL_INFO;
1117	serge	5488
1430	serge	5489
1117	serge	5490	#define ATOM_MAX_MISC_INFO 4
		5491
1430	serge	5492	typedef struct _ATOM_TMDS_INFO
		5493	{
1117	serge	5494	ATOM_COMMON_TABLE_HEADER sHeader;
1430	serge	5495	USHORT usMaxFrequency; // in 10Khz
1117	serge	5496	ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO];
1430	serge	5497	}ATOM_TMDS_INFO;
1117	serge	5498
1430	serge	5499
		5500	typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE
		5501	{
		5502	UCHAR ucTVStandard; //Same as TV standards defined above,
1117	serge	5503	UCHAR ucPadding[1];
1430	serge	5504	}ATOM_ENCODER_ANALOG_ATTRIBUTE;
1117	serge	5505
1430	serge	5506	typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE
		5507	{
		5508	UCHAR ucAttribute; //Same as other digital encoder attributes defined above
1117	serge	5509	UCHAR ucPadding[1];
1430	serge	5510	}ATOM_ENCODER_DIGITAL_ATTRIBUTE;
1117	serge	5511
1430	serge	5512	typedef union _ATOM_ENCODER_ATTRIBUTE
		5513	{
1117	serge	5514	ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib;
		5515	ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib;
1430	serge	5516	}ATOM_ENCODER_ATTRIBUTE;
1117	serge	5517
1430	serge	5518
		5519	typedef struct _DVO_ENCODER_CONTROL_PARAMETERS
		5520	{
1117	serge	5521	USHORT usPixelClock;
		5522	USHORT usEncoderID;
1430	serge	5523	UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only.
		5524	UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
1117	serge	5525	ATOM_ENCODER_ATTRIBUTE usDevAttr;
1430	serge	5526	}DVO_ENCODER_CONTROL_PARAMETERS;
1117	serge	5527
1430	serge	5528	typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION
		5529	{
1117	serge	5530	DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder;
1430	serge	5531	WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
		5532	}DVO_ENCODER_CONTROL_PS_ALLOCATION;
1117	serge	5533
1430	serge	5534
1117	serge	5535	#define ATOM_XTMDS_ASIC_SI164_ID 1
		5536	#define ATOM_XTMDS_ASIC_SI178_ID 2
		5537	#define ATOM_XTMDS_ASIC_TFP513_ID 3
		5538	#define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001
		5539	#define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002
		5540	#define ATOM_XTMDS_MVPU_FPGA 0x00000004
		5541
1430	serge	5542
		5543	typedef struct _ATOM_XTMDS_INFO
		5544	{
1117	serge	5545	ATOM_COMMON_TABLE_HEADER sHeader;
		5546	USHORT usSingleLinkMaxFrequency;
1430	serge	5547	ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip
1117	serge	5548	UCHAR ucXtransimitterID;
1430	serge	5549	UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported
		5550	UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters
		5551	// due to design. This ID is used to alert driver that the sequence is not "standard"!
		5552	UCHAR ucMasterAddress; // Address to control Master xTMDS Chip
		5553	UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip
		5554	}ATOM_XTMDS_INFO;
1117	serge	5555
1430	serge	5556	typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS
		5557	{
		5558	UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off
		5559	UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX....
1117	serge	5560	UCHAR ucPadding[2];
1430	serge	5561	}DFP_DPMS_STATUS_CHANGE_PARAMETERS;
1117	serge	5562
		5563	/**************************Legacy Power Play Table Definitions ********************/
		5564
1430	serge	5565	//Definitions for ulPowerPlayMiscInfo
1117	serge	5566	#define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L
		5567	#define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L
		5568	#define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L
		5569
		5570	#define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L
		5571	#define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L
		5572
		5573	#define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L
		5574
		5575	#define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L
		5576	#define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L
1430	serge	5577	#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program
1117	serge	5578
		5579	#define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L
		5580	#define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L
		5581	#define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L
		5582	#define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L
		5583	#define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L
		5584	#define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L
		5585	#define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L
		5586
		5587	#define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L
		5588	#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L
		5589	#define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L
		5590	#define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L
		5591	#define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L
		5592
1430	serge	5593	#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved
1117	serge	5594	#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20
		5595
		5596	#define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L
		5597	#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L
		5598	#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L
1430	serge	5599	#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic
		5600	#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic
		5601	#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode
1117	serge	5602
1430	serge	5603	#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks)
1117	serge	5604	#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28
		5605	#define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L
		5606
		5607	#define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L
		5608	#define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L
		5609	#define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L
		5610	#define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L
		5611	#define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L
		5612	#define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L
1430	serge	5613	#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption.
		5614	//If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback
1117	serge	5615	#define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L
		5616	#define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L
		5617	#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L
		5618
1430	serge	5619	//ucTableFormatRevision=1
		5620	//ucTableContentRevision=1
		5621	typedef struct _ATOM_POWERMODE_INFO
		5622	{
		5623	ULONG ulMiscInfo; //The power level should be arranged in ascending order
		5624	ULONG ulReserved1; // must set to 0
		5625	ULONG ulReserved2; // must set to 0
1117	serge	5626	USHORT usEngineClock;
		5627	USHORT usMemoryClock;
1430	serge	5628	UCHAR ucVoltageDropIndex; // index to GPIO table
		5629	UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
1117	serge	5630	UCHAR ucMinTemperature;
		5631	UCHAR ucMaxTemperature;
1430	serge	5632	UCHAR ucNumPciELanes; // number of PCIE lanes
		5633	}ATOM_POWERMODE_INFO;
1117	serge	5634
1430	serge	5635	//ucTableFormatRevision=2
		5636	//ucTableContentRevision=1
		5637	typedef struct _ATOM_POWERMODE_INFO_V2
		5638	{
		5639	ULONG ulMiscInfo; //The power level should be arranged in ascending order
1117	serge	5640	ULONG ulMiscInfo2;
		5641	ULONG ulEngineClock;
		5642	ULONG ulMemoryClock;
1430	serge	5643	UCHAR ucVoltageDropIndex; // index to GPIO table
		5644	UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
1117	serge	5645	UCHAR ucMinTemperature;
		5646	UCHAR ucMaxTemperature;
1430	serge	5647	UCHAR ucNumPciELanes; // number of PCIE lanes
		5648	}ATOM_POWERMODE_INFO_V2;
1117	serge	5649
1430	serge	5650	//ucTableFormatRevision=2
		5651	//ucTableContentRevision=2
		5652	typedef struct _ATOM_POWERMODE_INFO_V3
		5653	{
		5654	ULONG ulMiscInfo; //The power level should be arranged in ascending order
1117	serge	5655	ULONG ulMiscInfo2;
		5656	ULONG ulEngineClock;
		5657	ULONG ulMemoryClock;
1430	serge	5658	UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table
		5659	UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
1117	serge	5660	UCHAR ucMinTemperature;
		5661	UCHAR ucMaxTemperature;
1430	serge	5662	UCHAR ucNumPciELanes; // number of PCIE lanes
		5663	UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table
		5664	}ATOM_POWERMODE_INFO_V3;
1117	serge	5665
1430	serge	5666
1117	serge	5667	#define ATOM_MAX_NUMBEROF_POWER_BLOCK 8
		5668
		5669	#define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01
		5670	#define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02
		5671
		5672	#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01
		5673	#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02
		5674	#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03
		5675	#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04
		5676	#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05
		5677	#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06
1430	serge	5678	#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog
1117	serge	5679
1430	serge	5680
		5681	typedef struct _ATOM_POWERPLAY_INFO
		5682	{
1117	serge	5683	ATOM_COMMON_TABLE_HEADER sHeader;
		5684	UCHAR ucOverdriveThermalController;
		5685	UCHAR ucOverdriveI2cLine;
		5686	UCHAR ucOverdriveIntBitmap;
		5687	UCHAR ucOverdriveControllerAddress;
		5688	UCHAR ucSizeOfPowerModeEntry;
		5689	UCHAR ucNumOfPowerModeEntries;
		5690	ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
1430	serge	5691	}ATOM_POWERPLAY_INFO;
1117	serge	5692
1430	serge	5693	typedef struct _ATOM_POWERPLAY_INFO_V2
		5694	{
1117	serge	5695	ATOM_COMMON_TABLE_HEADER sHeader;
		5696	UCHAR ucOverdriveThermalController;
		5697	UCHAR ucOverdriveI2cLine;
		5698	UCHAR ucOverdriveIntBitmap;
		5699	UCHAR ucOverdriveControllerAddress;
		5700	UCHAR ucSizeOfPowerModeEntry;
		5701	UCHAR ucNumOfPowerModeEntries;
		5702	ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
1430	serge	5703	}ATOM_POWERPLAY_INFO_V2;
1117	serge	5704
1430	serge	5705	typedef struct _ATOM_POWERPLAY_INFO_V3
		5706	{
1117	serge	5707	ATOM_COMMON_TABLE_HEADER sHeader;
		5708	UCHAR ucOverdriveThermalController;
		5709	UCHAR ucOverdriveI2cLine;
		5710	UCHAR ucOverdriveIntBitmap;
		5711	UCHAR ucOverdriveControllerAddress;
		5712	UCHAR ucSizeOfPowerModeEntry;
		5713	UCHAR ucNumOfPowerModeEntries;
		5714	ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
1430	serge	5715	}ATOM_POWERPLAY_INFO_V3;
1117	serge	5716
1403	serge	5717	/* New PPlib */
1117	serge	5718	/**************************************************************************/
1403	serge	5719	typedef struct _ATOM_PPLIB_THERMALCONTROLLER
1117	serge	5720
1403	serge	5721	{
		5722	UCHAR ucType; // one of ATOM_PP_THERMALCONTROLLER_*
		5723	UCHAR ucI2cLine; // as interpreted by DAL I2C
		5724	UCHAR ucI2cAddress;
		5725	UCHAR ucFanParameters; // Fan Control Parameters.
		5726	UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only.
		5727	UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only.
		5728	UCHAR ucReserved; // ----
		5729	UCHAR ucFlags; // to be defined
		5730	} ATOM_PPLIB_THERMALCONTROLLER;
		5731
		5732	#define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f
		5733	#define ATOM_PP_FANPARAMETERS_NOFAN 0x80 // No fan is connected to this controller.
		5734
		5735	#define ATOM_PP_THERMALCONTROLLER_NONE 0
		5736	#define ATOM_PP_THERMALCONTROLLER_LM63 1 // Not used by PPLib
		5737	#define ATOM_PP_THERMALCONTROLLER_ADM1032 2 // Not used by PPLib
		5738	#define ATOM_PP_THERMALCONTROLLER_ADM1030 3 // Not used by PPLib
		5739	#define ATOM_PP_THERMALCONTROLLER_MUA6649 4 // Not used by PPLib
		5740	#define ATOM_PP_THERMALCONTROLLER_LM64 5
		5741	#define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib
		5742	#define ATOM_PP_THERMALCONTROLLER_RV6xx 7
		5743	#define ATOM_PP_THERMALCONTROLLER_RV770 8
		5744	#define ATOM_PP_THERMALCONTROLLER_ADT7473 9
		5745
		5746	typedef struct _ATOM_PPLIB_STATE
		5747	{
		5748	UCHAR ucNonClockStateIndex;
		5749	UCHAR ucClockStateIndices[1]; // variable-sized
		5750	} ATOM_PPLIB_STATE;
		5751
		5752	//// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps
		5753	#define ATOM_PP_PLATFORM_CAP_BACKBIAS 1
		5754	#define ATOM_PP_PLATFORM_CAP_POWERPLAY 2
		5755	#define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4
		5756	#define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8
		5757	#define ATOM_PP_PLATFORM_CAP_ASPM_L1 16
		5758	#define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32
		5759	#define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64
		5760	#define ATOM_PP_PLATFORM_CAP_STEPVDDC 128
		5761	#define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256
		5762	#define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512
		5763	#define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024
		5764	#define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048
		5765
		5766	typedef struct _ATOM_PPLIB_POWERPLAYTABLE
		5767	{
		5768	ATOM_COMMON_TABLE_HEADER sHeader;
		5769
		5770	UCHAR ucDataRevision;
		5771
		5772	UCHAR ucNumStates;
		5773	UCHAR ucStateEntrySize;
		5774	UCHAR ucClockInfoSize;
		5775	UCHAR ucNonClockSize;
		5776
		5777	// offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures
		5778	USHORT usStateArrayOffset;
		5779
		5780	// offset from start of this table to array of ASIC-specific structures,
		5781	// currently ATOM_PPLIB_CLOCK_INFO.
		5782	USHORT usClockInfoArrayOffset;
		5783
		5784	// offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO
		5785	USHORT usNonClockInfoArrayOffset;
		5786
		5787	USHORT usBackbiasTime; // in microseconds
		5788	USHORT usVoltageTime; // in microseconds
		5789	USHORT usTableSize; //the size of this structure, or the extended structure
		5790
		5791	ULONG ulPlatformCaps; // See ATOM_PPLIB_CAPS_*
		5792
		5793	ATOM_PPLIB_THERMALCONTROLLER sThermalController;
		5794
		5795	USHORT usBootClockInfoOffset;
		5796	USHORT usBootNonClockInfoOffset;
		5797
		5798	} ATOM_PPLIB_POWERPLAYTABLE;
		5799
		5800	//// ATOM_PPLIB_NONCLOCK_INFO::usClassification
		5801	#define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007
		5802	#define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0
		5803	#define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0
		5804	#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1
		5805	#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3
		5806	#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5
		5807	// 2, 4, 6, 7 are reserved
		5808
		5809	#define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008
		5810	#define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010
		5811	#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020
		5812	#define ATOM_PPLIB_CLASSIFICATION_REST 0x0040
		5813	#define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080
		5814	#define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100
		5815	#define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200
		5816	#define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400
		5817	#define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800
		5818	#define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000
		5819	// remaining 3 bits are reserved
		5820
		5821	//// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings
		5822	#define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001
		5823	#define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002
		5824
		5825	// 0 is 2.5Gb/s, 1 is 5Gb/s
		5826	#define ATOM_PPLIB_PCIE_LINK_SPEED_MASK 0x00000004
		5827	#define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT 2
		5828
		5829	// lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec
		5830	#define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK 0x000000F8
		5831	#define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT 3
		5832
		5833	// lookup into reduced refresh-rate table
		5834	#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK 0x00000F00
		5835	#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8
		5836
		5837	#define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED 0
		5838	#define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1
		5839	// 2-15 TBD as needed.
		5840
		5841	#define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000
		5842	#define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000
		5843	#define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000
		5844
		5845	#define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000
		5846
		5847	// Contained in an array starting at the offset
		5848	// in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset.
		5849	// referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex
		5850	typedef struct _ATOM_PPLIB_NONCLOCK_INFO
		5851	{
		5852	USHORT usClassification;
		5853	UCHAR ucMinTemperature;
		5854	UCHAR ucMaxTemperature;
		5855	ULONG ulCapsAndSettings;
		5856	UCHAR ucRequiredPower;
		5857	UCHAR ucUnused1[3];
		5858	} ATOM_PPLIB_NONCLOCK_INFO;
		5859
		5860	// Contained in an array starting at the offset
		5861	// in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset.
		5862	// referenced from ATOM_PPLIB_STATE::ucClockStateIndices
		5863	typedef struct _ATOM_PPLIB_R600_CLOCK_INFO
		5864	{
		5865	USHORT usEngineClockLow;
		5866	UCHAR ucEngineClockHigh;
		5867
		5868	USHORT usMemoryClockLow;
		5869	UCHAR ucMemoryClockHigh;
		5870
		5871	USHORT usVDDC;
		5872	USHORT usUnused1;
		5873	USHORT usUnused2;
		5874
		5875	ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_*
		5876
		5877	} ATOM_PPLIB_R600_CLOCK_INFO;
		5878
		5879	// ulFlags in ATOM_PPLIB_R600_CLOCK_INFO
		5880	#define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1
		5881	#define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2
		5882	#define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4
		5883	#define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8
		5884	#define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16
		5885
		5886	typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
		5887
		5888	{
		5889	USHORT usLowEngineClockLow; // Low Engine clock in MHz (the same way as on the R600).
		5890	UCHAR ucLowEngineClockHigh;
		5891	USHORT usHighEngineClockLow; // High Engine clock in MHz.
		5892	UCHAR ucHighEngineClockHigh;
		5893	USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants.
		5894	UCHAR ucMemoryClockHigh; // Currentyl unused.
		5895	UCHAR ucPadding; // For proper alignment and size.
		5896	USHORT usVDDC; // For the 780, use: None, Low, High, Variable
		5897	UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16}
		5898	UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requriement.
		5899	USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200).
		5900	ULONG ulFlags;
		5901	} ATOM_PPLIB_RS780_CLOCK_INFO;
		5902
		5903	#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0
		5904	#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1
		5905	#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2
		5906	#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3
		5907
		5908	#define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is.
		5909	#define ATOM_PPLIB_RS780_SPMCLK_LOW 1
		5910	#define ATOM_PPLIB_RS780_SPMCLK_HIGH 2
		5911
		5912	#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0
		5913	#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1
		5914	#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2
		5915
		5916	/**************************************************************************/
		5917
1430	serge	5918
		5919	// Following definitions are for compatiblity issue in different SW components.
1117	serge	5920	#define ATOM_MASTER_DATA_TABLE_REVISION 0x01
		5921	#define Object_Info Object_Header
		5922	#define AdjustARB_SEQ MC_InitParameter
		5923	#define VRAM_GPIO_DetectionInfo VoltageObjectInfo
		5924	#define ASIC_VDDCI_Info ASIC_ProfilingInfo
		5925	#define ASIC_MVDDQ_Info MemoryTrainingInfo
		5926	#define SS_Info PPLL_SS_Info
		5927	#define ASIC_MVDDC_Info ASIC_InternalSS_Info
		5928	#define DispDevicePriorityInfo SaveRestoreInfo
		5929	#define DispOutInfo TV_VideoMode
		5930
1430	serge	5931
1117	serge	5932	#define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE
		5933	#define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE
		5934
1430	serge	5935	//New device naming, remove them when both DAL/VBIOS is ready
1117	serge	5936	#define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS
		5937	#define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS
		5938
		5939	#define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS
		5940	#define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS
		5941
		5942	#define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS
		5943	#define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION
		5944
		5945	#define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT
		5946	#define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT
		5947
		5948	#define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX
		5949	#define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX
		5950
		5951	#define ATOM_DEVICE_DFP2I_INDEX 0x00000009
		5952	#define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX)
		5953
		5954	#define ATOM_S0_DFP1I ATOM_S0_DFP1
		5955	#define ATOM_S0_DFP1X ATOM_S0_DFP2
		5956
		5957	#define ATOM_S0_DFP2I 0x00200000L
		5958	#define ATOM_S0_DFP2Ib2 0x20
		5959
		5960	#define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE
		5961	#define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE
		5962
		5963	#define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L
		5964	#define ATOM_S2_DFP2I_DPMS_STATEb3 0x02
		5965
		5966	#define ATOM_S3_DFP2I_ACTIVEb1 0x02
		5967
		5968	#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE
		5969	#define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE
		5970
		5971	#define ATOM_S3_DFP2I_ACTIVE 0x00000200L
		5972
		5973	#define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE
		5974	#define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE
		5975	#define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L
		5976
		5977	#define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02
		5978	#define ATOM_S5_DOS_REQ_DFP2Ib1 0x02
		5979
		5980	#define ATOM_S5_DOS_REQ_DFP2I 0x0200
		5981	#define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1
		5982	#define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2
		5983
		5984	#define ATOM_S6_ACC_REQ_DFP2Ib3 0x02
		5985	#define ATOM_S6_ACC_REQ_DFP2I 0x02000000L
		5986
		5987	#define TMDS1XEncoderControl DVOEncoderControl
		5988	#define DFP1XOutputControl DVOOutputControl
		5989
		5990	#define ExternalDFPOutputControl DFP1XOutputControl
		5991	#define EnableExternalTMDS_Encoder TMDS1XEncoderControl
		5992
		5993	#define DFP1IOutputControl TMDSAOutputControl
		5994	#define DFP2IOutputControl LVTMAOutputControl
		5995
		5996	#define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS
		5997	#define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
		5998
		5999	#define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS
		6000	#define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
		6001
		6002	#define ucDac1Standard ucDacStandard
		6003	#define ucDac2Standard ucDacStandard
		6004
		6005	#define TMDS1EncoderControl TMDSAEncoderControl
		6006	#define TMDS2EncoderControl LVTMAEncoderControl
		6007
		6008	#define DFP1OutputControl TMDSAOutputControl
		6009	#define DFP2OutputControl LVTMAOutputControl
		6010	#define CRT1OutputControl DAC1OutputControl
		6011	#define CRT2OutputControl DAC2OutputControl
		6012
1430	serge	6013	//These two lines will be removed for sure in a few days, will follow up with Michael V.
1117	serge	6014	#define EnableLVDS_SS EnableSpreadSpectrumOnPPLL
		6015	#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL
		6016
1430	serge	6017	//#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L
		6018	//#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
		6019	//#define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
		6020	//#define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
		6021	//#define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
		6022
		6023	#define ATOM_S6_ACC_REQ_TV2 0x00400000L
		6024	#define ATOM_DEVICE_TV2_INDEX 0x00000006
		6025	#define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX)
		6026	#define ATOM_S0_TV2 0x00100000L
		6027	#define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE
		6028	#define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE
		6029
		6030	//
		6031	#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L
		6032	#define ATOM_S2_LCD1_DPMS_STATE 0x00020000L
		6033	#define ATOM_S2_TV1_DPMS_STATE 0x00040000L
		6034	#define ATOM_S2_DFP1_DPMS_STATE 0x00080000L
		6035	#define ATOM_S2_CRT2_DPMS_STATE 0x00100000L
		6036	#define ATOM_S2_LCD2_DPMS_STATE 0x00200000L
		6037	#define ATOM_S2_TV2_DPMS_STATE 0x00400000L
		6038	#define ATOM_S2_DFP2_DPMS_STATE 0x00800000L
		6039	#define ATOM_S2_CV_DPMS_STATE 0x01000000L
		6040	#define ATOM_S2_DFP3_DPMS_STATE 0x02000000L
		6041	#define ATOM_S2_DFP4_DPMS_STATE 0x04000000L
		6042	#define ATOM_S2_DFP5_DPMS_STATE 0x08000000L
		6043
		6044	#define ATOM_S2_CRT1_DPMS_STATEb2 0x01
		6045	#define ATOM_S2_LCD1_DPMS_STATEb2 0x02
		6046	#define ATOM_S2_TV1_DPMS_STATEb2 0x04
		6047	#define ATOM_S2_DFP1_DPMS_STATEb2 0x08
		6048	#define ATOM_S2_CRT2_DPMS_STATEb2 0x10
		6049	#define ATOM_S2_LCD2_DPMS_STATEb2 0x20
		6050	#define ATOM_S2_TV2_DPMS_STATEb2 0x40
		6051	#define ATOM_S2_DFP2_DPMS_STATEb2 0x80
		6052	#define ATOM_S2_CV_DPMS_STATEb3 0x01
		6053	#define ATOM_S2_DFP3_DPMS_STATEb3 0x02
		6054	#define ATOM_S2_DFP4_DPMS_STATEb3 0x04
		6055	#define ATOM_S2_DFP5_DPMS_STATEb3 0x08
		6056
		6057	#define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20
		6058	#define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40
		6059	#define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80
		6060
1117	serge	6061	/*********************************************************************************/
		6062
1430	serge	6063	#pragma pack() // BIOS data must use byte aligment
1117	serge	6064
		6065	#endif /* _ATOMBIOS_H */

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/atombios.h – Rev 1430