WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/atombios.h

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2006-2007 Advanced Micro Devices, Inc.
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice shall be included in
		12	* all copies or substantial portions of the Software.
		13	*
		14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		20	* OTHER DEALINGS IN THE SOFTWARE.
		21	*/
		22
		23	/****************************************************************************/
		24	/Portion I: Definitions shared between VBIOS and Driver /
		25	/****************************************************************************/
		26
		27	#ifndef _ATOMBIOS_H
		28	#define _ATOMBIOS_H
		29
		30	#define ATOM_VERSION_MAJOR 0x00020000
		31	#define ATOM_VERSION_MINOR 0x00000002
		32
		33	#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR \| ATOM_VERSION_MINOR)
		34
		35	/* Endianness should be specified before inclusion,
		36	* default to little endian
		37	*/
		38	#ifndef ATOM_BIG_ENDIAN
		39	#error Endian not specified
		40	#endif
		41
		42	#ifdef _H2INC
		43	#ifndef ULONG
		44	typedef unsigned long ULONG;
		45	#endif
		46
		47	#ifndef UCHAR
		48	typedef unsigned char UCHAR;
		49	#endif
		50
		51	#ifndef USHORT
		52	typedef unsigned short USHORT;
		53	#endif
		54	#endif
		55
		56	#define ATOM_DAC_A 0
		57	#define ATOM_DAC_B 1
		58	#define ATOM_EXT_DAC 2
		59
		60	#define ATOM_CRTC1 0
		61	#define ATOM_CRTC2 1
		62
		63	#define ATOM_DIGA 0
		64	#define ATOM_DIGB 1
		65
		66	#define ATOM_PPLL1 0
		67	#define ATOM_PPLL2 1
		68
		69	#define ATOM_SCALER1 0
		70	#define ATOM_SCALER2 1
		71
		72	#define ATOM_SCALER_DISABLE 0
		73	#define ATOM_SCALER_CENTER 1
		74	#define ATOM_SCALER_EXPANSION 2
		75	#define ATOM_SCALER_MULTI_EX 3
		76
		77	#define ATOM_DISABLE 0
		78	#define ATOM_ENABLE 1
		79	#define ATOM_LCD_BLOFF (ATOM_DISABLE+2)
		80	#define ATOM_LCD_BLON (ATOM_ENABLE+2)
		81	#define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3)
		82	#define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5)
		83	#define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5)
		84	#define ATOM_ENCODER_INIT (ATOM_DISABLE+7)
		85
		86	#define ATOM_BLANKING 1
		87	#define ATOM_BLANKING_OFF 0
		88
		89	#define ATOM_CURSOR1 0
		90	#define ATOM_CURSOR2 1
		91
		92	#define ATOM_ICON1 0
		93	#define ATOM_ICON2 1
		94
		95	#define ATOM_CRT1 0
		96	#define ATOM_CRT2 1
		97
		98	#define ATOM_TV_NTSC 1
		99	#define ATOM_TV_NTSCJ 2
		100	#define ATOM_TV_PAL 3
		101	#define ATOM_TV_PALM 4
		102	#define ATOM_TV_PALCN 5
		103	#define ATOM_TV_PALN 6
		104	#define ATOM_TV_PAL60 7
		105	#define ATOM_TV_SECAM 8
		106	#define ATOM_TV_CV 16
		107
		108	#define ATOM_DAC1_PS2 1
		109	#define ATOM_DAC1_CV 2
		110	#define ATOM_DAC1_NTSC 3
		111	#define ATOM_DAC1_PAL 4
		112
		113	#define ATOM_DAC2_PS2 ATOM_DAC1_PS2
		114	#define ATOM_DAC2_CV ATOM_DAC1_CV
		115	#define ATOM_DAC2_NTSC ATOM_DAC1_NTSC
		116	#define ATOM_DAC2_PAL ATOM_DAC1_PAL
		117
		118	#define ATOM_PM_ON 0
		119	#define ATOM_PM_STANDBY 1
		120	#define ATOM_PM_SUSPEND 2
		121	#define ATOM_PM_OFF 3
		122
		123	/* Bit0:{=0:single, =1:dual},
		124	Bit1 {=0:666RGB, =1:888RGB},
		125	Bit2:3:{Grey level}
		126	Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/
		127
		128	#define ATOM_PANEL_MISC_DUAL 0x00000001
		129	#define ATOM_PANEL_MISC_888RGB 0x00000002
		130	#define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C
		131	#define ATOM_PANEL_MISC_FPDI 0x00000010
		132	#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2
		133	#define ATOM_PANEL_MISC_SPATIAL 0x00000020
		134	#define ATOM_PANEL_MISC_TEMPORAL 0x00000040
		135	#define ATOM_PANEL_MISC_API_ENABLED 0x00000080
		136
		137	#define MEMTYPE_DDR1 "DDR1"
		138	#define MEMTYPE_DDR2 "DDR2"
		139	#define MEMTYPE_DDR3 "DDR3"
		140	#define MEMTYPE_DDR4 "DDR4"
		141
		142	#define ASIC_BUS_TYPE_PCI "PCI"
		143	#define ASIC_BUS_TYPE_AGP "AGP"
		144	#define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS"
		145
		146	/* Maximum size of that FireGL flag string */
		147
		148	#define ATOM_FIREGL_FLAG_STRING "FGL" /* Flag used to enable FireGL Support */
		149	#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 /* sizeof( ATOM_FIREGL_FLAG_STRING ) */
		150
		151	#define ATOM_FAKE_DESKTOP_STRING "DSK" /* Flag used to enable mobile ASIC on Desktop */
		152	#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING
		153
		154	#define ATOM_M54T_FLAG_STRING "M54T" /* Flag used to enable M54T Support */
		155	#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 /* sizeof( ATOM_M54T_FLAG_STRING ) */
		156
		157	#define HW_ASSISTED_I2C_STATUS_FAILURE 2
		158	#define HW_ASSISTED_I2C_STATUS_SUCCESS 1
		159
		160	#pragma pack(1) /* BIOS data must use byte aligment */
		161
		162	/* Define offset to location of ROM header. */
		163
		164	#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L
		165	#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L
		166
		167	#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94
		168	#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */
		169	#define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f
		170	#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e
		171
		172	/* Common header for all ROM Data tables.
		173	Every table pointed _ATOM_MASTER_DATA_TABLE has this common header.
		174	And the pointer actually points to this header. */
		175
		176	typedef struct _ATOM_COMMON_TABLE_HEADER {
		177	USHORT usStructureSize;
		178	UCHAR ucTableFormatRevision; /Change it when the Parser is not backward compatible /
		179	UCHAR ucTableContentRevision; /Change it only when the table needs to change but the firmware /
		180	/Image can't be updated, while Driver needs to carry the new table! /
		181	} ATOM_COMMON_TABLE_HEADER;
		182
		183	typedef struct _ATOM_ROM_HEADER {
		184	ATOM_COMMON_TABLE_HEADER sHeader;
		185	UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
		186	atombios should init it as "ATOM", don't change the position */
		187	USHORT usBiosRuntimeSegmentAddress;
		188	USHORT usProtectedModeInfoOffset;
		189	USHORT usConfigFilenameOffset;
		190	USHORT usCRC_BlockOffset;
		191	USHORT usBIOS_BootupMessageOffset;
		192	USHORT usInt10Offset;
		193	USHORT usPciBusDevInitCode;
		194	USHORT usIoBaseAddress;
		195	USHORT usSubsystemVendorID;
		196	USHORT usSubsystemID;
		197	USHORT usPCI_InfoOffset;
		198	USHORT usMasterCommandTableOffset; /Offset for SW to get all command table offsets, Don't change the position /
		199	USHORT usMasterDataTableOffset; /Offset for SW to get all data table offsets, Don't change the position /
		200	UCHAR ucExtendedFunctionCode;
		201	UCHAR ucReserved;
		202	} ATOM_ROM_HEADER;
		203
		204	/==============================Command Table Portion==================================== /
		205
		206	#ifdef UEFI_BUILD
		207	#define UTEMP USHORT
		208	#define USHORT void*
		209	#endif
		210
		211	typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES {
		212	USHORT ASIC_Init; /* Function Table, used by various SW components,latest version 1.1 */
		213	USHORT GetDisplaySurfaceSize; /* Atomic Table, Used by Bios when enabling HW ICON */
		214	USHORT ASIC_RegistersInit; /* Atomic Table, indirectly used by various SW components,called from ASIC_Init */
		215	USHORT VRAM_BlockVenderDetection; /* Atomic Table, used only by Bios */
		216	USHORT DIGxEncoderControl; /* Only used by Bios */
		217	USHORT MemoryControllerInit; /* Atomic Table, indirectly used by various SW components,called from ASIC_Init */
		218	USHORT EnableCRTCMemReq; /* Function Table,directly used by various SW components,latest version 2.1 */
		219	USHORT MemoryParamAdjust; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed */
		220	USHORT DVOEncoderControl; /* Function Table,directly used by various SW components,latest version 1.2 */
		221	USHORT GPIOPinControl; /* Atomic Table, only used by Bios */
		222	USHORT SetEngineClock; /Function Table,directly used by various SW components,latest version 1.1 /
		223	USHORT SetMemoryClock; /* Function Table,directly used by various SW components,latest version 1.1 */
		224	USHORT SetPixelClock; /Function Table,directly used by various SW components,latest version 1.2 /
		225	USHORT DynamicClockGating; /* Atomic Table, indirectly used by various SW components,called from ASIC_Init */
		226	USHORT ResetMemoryDLL; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */
		227	USHORT ResetMemoryDevice; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */
		228	USHORT MemoryPLLInit;
		229	USHORT AdjustDisplayPll; /* only used by Bios */
		230	USHORT AdjustMemoryController; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */
		231	USHORT EnableASIC_StaticPwrMgt; /* Atomic Table, only used by Bios */
		232	USHORT ASIC_StaticPwrMgtStatusChange; /* Obsolete, only used by Bios */
		233	USHORT DAC_LoadDetection; /* Atomic Table, directly used by various SW components,latest version 1.2 */
		234	USHORT LVTMAEncoderControl; /* Atomic Table,directly used by various SW components,latest version 1.3 */
		235	USHORT LCD1OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */
		236	USHORT DAC1EncoderControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */
		237	USHORT DAC2EncoderControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */
		238	USHORT DVOOutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */
		239	USHORT CV1OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */
		240	USHORT GetConditionalGoldenSetting; /* only used by Bios */
		241	USHORT TVEncoderControl; /* Function Table,directly used by various SW components,latest version 1.1 */
		242	USHORT TMDSAEncoderControl; /* Atomic Table, directly used by various SW components,latest version 1.3 */
		243	USHORT LVDSEncoderControl; /* Atomic Table, directly used by various SW components,latest version 1.3 */
		244	USHORT TV1OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */
		245	USHORT EnableScaler; /* Atomic Table, used only by Bios */
		246	USHORT BlankCRTC; /* Atomic Table, directly used by various SW components,latest version 1.1 */
		247	USHORT EnableCRTC; /* Atomic Table, directly used by various SW components,latest version 1.1 */
		248	USHORT GetPixelClock; /* Atomic Table, directly used by various SW components,latest version 1.1 */
		249	USHORT EnableVGA_Render; /* Function Table,directly used by various SW components,latest version 1.1 */
		250	USHORT EnableVGA_Access; /* Obsolete , only used by Bios */
		251	USHORT SetCRTC_Timing; /* Atomic Table, directly used by various SW components,latest version 1.1 */
		252	USHORT SetCRTC_OverScan; /* Atomic Table, used by various SW components,latest version 1.1 */
		253	USHORT SetCRTC_Replication; /* Atomic Table, used only by Bios */
		254	USHORT SelectCRTC_Source; /* Atomic Table, directly used by various SW components,latest version 1.1 */
		255	USHORT EnableGraphSurfaces; /* Atomic Table, used only by Bios */
		256	USHORT UpdateCRTC_DoubleBufferRegisters;
		257	USHORT LUT_AutoFill; /* Atomic Table, only used by Bios */
		258	USHORT EnableHW_IconCursor; /* Atomic Table, only used by Bios */
		259	USHORT GetMemoryClock; /* Atomic Table, directly used by various SW components,latest version 1.1 */
		260	USHORT GetEngineClock; /* Atomic Table, directly used by various SW components,latest version 1.1 */
		261	USHORT SetCRTC_UsingDTDTiming; /* Atomic Table, directly used by various SW components,latest version 1.1 */
		262	USHORT ExternalEncoderControl; /* Atomic Table, directly used by various SW components,latest version 2.1 */
		263	USHORT LVTMAOutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */
		264	USHORT VRAM_BlockDetectionByStrap; /* Atomic Table, used only by Bios */
		265	USHORT MemoryCleanUp; /* Atomic Table, only used by Bios */
		266	USHORT ProcessI2cChannelTransaction; /* Function Table,only used by Bios */
		267	USHORT WriteOneByteToHWAssistedI2C; /* Function Table,indirectly used by various SW components */
		268	USHORT ReadHWAssistedI2CStatus; /* Atomic Table, indirectly used by various SW components */
		269	USHORT SpeedFanControl; /* Function Table,indirectly used by various SW components,called from ASIC_Init */
		270	USHORT PowerConnectorDetection; /* Atomic Table, directly used by various SW components,latest version 1.1 */
		271	USHORT MC_Synchronization; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */
		272	USHORT ComputeMemoryEnginePLL; /* Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock */
		273	USHORT MemoryRefreshConversion; /* Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock */
		274	USHORT VRAM_GetCurrentInfoBlock; /* Atomic Table, used only by Bios */
		275	USHORT DynamicMemorySettings; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */
		276	USHORT MemoryTraining; /* Atomic Table, used only by Bios */
		277	USHORT EnableSpreadSpectrumOnPPLL; /* Atomic Table, directly used by various SW components,latest version 1.2 */
		278	USHORT TMDSAOutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */
		279	USHORT SetVoltage; /* Function Table,directly and/or indirectly used by various SW components,latest version 1.1 */
		280	USHORT DAC1OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */
		281	USHORT DAC2OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */
		282	USHORT SetupHWAssistedI2CStatus; /* Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" */
		283	USHORT ClockSource; /* Atomic Table, indirectly used by various SW components,called from ASIC_Init */
		284	USHORT MemoryDeviceInit; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */
		285	USHORT EnableYUV; /* Atomic Table, indirectly used by various SW components,called from EnableVGARender */
		286	USHORT DIG1EncoderControl; /* Atomic Table,directly used by various SW components,latest version 1.1 */
		287	USHORT DIG2EncoderControl; /* Atomic Table,directly used by various SW components,latest version 1.1 */
		288	USHORT DIG1TransmitterControl; /* Atomic Table,directly used by various SW components,latest version 1.1 */
		289	USHORT DIG2TransmitterControl; /* Atomic Table,directly used by various SW components,latest version 1.1 */
		290	USHORT ProcessAuxChannelTransaction; /* Function Table,only used by Bios */
		291	USHORT DPEncoderService; /* Function Table,only used by Bios */
		292	} ATOM_MASTER_LIST_OF_COMMAND_TABLES;
		293
		294	/* For backward compatible */
		295	#define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction
		296	#define UNIPHYTransmitterControl DIG1TransmitterControl
		297	#define LVTMATransmitterControl DIG2TransmitterControl
		298	#define SetCRTC_DPM_State GetConditionalGoldenSetting
		299	#define SetUniphyInstance ASIC_StaticPwrMgtStatusChange
		300
		301	typedef struct _ATOM_MASTER_COMMAND_TABLE {
		302	ATOM_COMMON_TABLE_HEADER sHeader;
		303	ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;
		304	} ATOM_MASTER_COMMAND_TABLE;
		305
		306	/****************************************************************************/
		307	/* Structures used in every command table */
		308	/****************************************************************************/
		309	typedef struct _ATOM_TABLE_ATTRIBUTE {
		310	#if ATOM_BIG_ENDIAN
		311	USHORT UpdatedByUtility:1; /* [15]=Table updated by utility flag */
		312	USHORT PS_SizeInBytes:7; /* [14:8]=Size of parameter space in Bytes (multiple of a dword), */
		313	USHORT WS_SizeInBytes:8; /* [7:0]=Size of workspace in Bytes (in multiple of a dword), */
		314	#else
		315	USHORT WS_SizeInBytes:8; /* [7:0]=Size of workspace in Bytes (in multiple of a dword), */
		316	USHORT PS_SizeInBytes:7; /* [14:8]=Size of parameter space in Bytes (multiple of a dword), */
		317	USHORT UpdatedByUtility:1; /* [15]=Table updated by utility flag */
		318	#endif
		319	} ATOM_TABLE_ATTRIBUTE;
		320
		321	typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS {
		322	ATOM_TABLE_ATTRIBUTE sbfAccess;
		323	USHORT susAccess;
		324	} ATOM_TABLE_ATTRIBUTE_ACCESS;
		325
		326	/****************************************************************************/
		327	/* Common header for all command tables. */
		328	/* Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. */
		329	/* And the pointer actually points to this header. */
		330	/****************************************************************************/
		331	typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER {
		332	ATOM_COMMON_TABLE_HEADER CommonHeader;
		333	ATOM_TABLE_ATTRIBUTE TableAttribute;
		334	} ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;
		335
		336	/****************************************************************************/
		337	/* Structures used by ComputeMemoryEnginePLLTable */
		338	/****************************************************************************/
		339	#define COMPUTE_MEMORY_PLL_PARAM 1
		340	#define COMPUTE_ENGINE_PLL_PARAM 2
		341
		342	typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS {
		343	ULONG ulClock; /* When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div */
		344	UCHAR ucAction; /* 0:reserved //1:Memory //2:Engine */
		345	UCHAR ucReserved; /* may expand to return larger Fbdiv later */
		346	UCHAR ucFbDiv; /* return value */
		347	UCHAR ucPostDiv; /* return value */
		348	} COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS;
		349
		350	typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 {
		351	ULONG ulClock; /* When return, [23:0] return real clock */
		352	UCHAR ucAction; /* 0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register */
		353	USHORT usFbDiv; /* return Feedback value to be written to register */
		354	UCHAR ucPostDiv; /* return post div to be written to register */
		355	} COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2;
		356	#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
		357
		358	#define SET_CLOCK_FREQ_MASK 0x00FFFFFF /* Clock change tables only take bit [23:0] as the requested clock value */
		359	#define USE_NON_BUS_CLOCK_MASK 0x01000000 /* Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) */
		360	#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 /* Only applicable to memory clock change, when set, using memory self refresh during clock transition */
		361	#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 /* Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change */
		362	#define FIRST_TIME_CHANGE_CLOCK 0x08000000 /* Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup */
		363	#define SKIP_SW_PROGRAM_PLL 0x10000000 /* Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL */
		364	#define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK
		365
		366	#define b3USE_NON_BUS_CLOCK_MASK 0x01 /* Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) */
		367	#define b3USE_MEMORY_SELF_REFRESH 0x02 /* Only applicable to memory clock change, when set, using memory self refresh during clock transition */
		368	#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 /* Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change */
		369	#define b3FIRST_TIME_CHANGE_CLOCK 0x08 /* Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup */
		370	#define b3SKIP_SW_PROGRAM_PLL 0x10 /* Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL */
		371
		372	typedef struct _ATOM_COMPUTE_CLOCK_FREQ {
		373	#if ATOM_BIG_ENDIAN
		374	ULONG ulComputeClockFlag:8; /* =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM */
		375	ULONG ulClockFreq:24; /* in unit of 10kHz */
		376	#else
		377	ULONG ulClockFreq:24; /* in unit of 10kHz */
		378	ULONG ulComputeClockFlag:8; /* =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM */
		379	#endif
		380	} ATOM_COMPUTE_CLOCK_FREQ;
		381
		382	typedef struct _ATOM_S_MPLL_FB_DIVIDER {
		383	USHORT usFbDivFrac;
		384	USHORT usFbDiv;
		385	} ATOM_S_MPLL_FB_DIVIDER;
		386
		387	typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 {
		388	union {
		389	ATOM_COMPUTE_CLOCK_FREQ ulClock; /* Input Parameter */
		390	ATOM_S_MPLL_FB_DIVIDER ulFbDiv; /* Output Parameter */
		391	};
		392	UCHAR ucRefDiv; /* Output Parameter */
		393	UCHAR ucPostDiv; /* Output Parameter */
		394	UCHAR ucCntlFlag; /* Output Parameter */
		395	UCHAR ucReserved;
		396	} COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3;
		397
		398	/* ucCntlFlag */
		399	#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1
		400	#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2
		401	#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4
		402
		403	typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER {
		404	ATOM_COMPUTE_CLOCK_FREQ ulClock;
		405	ULONG ulReserved[2];
		406	} DYNAMICE_MEMORY_SETTINGS_PARAMETER;
		407
		408	typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER {
		409	ATOM_COMPUTE_CLOCK_FREQ ulClock;
		410	ULONG ulMemoryClock;
		411	ULONG ulReserved;
		412	} DYNAMICE_ENGINE_SETTINGS_PARAMETER;
		413
		414	/****************************************************************************/
		415	/* Structures used by SetEngineClockTable */
		416	/****************************************************************************/
		417	typedef struct _SET_ENGINE_CLOCK_PARAMETERS {
		418	ULONG ulTargetEngineClock; /* In 10Khz unit */
		419	} SET_ENGINE_CLOCK_PARAMETERS;
		420
		421	typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION {
		422	ULONG ulTargetEngineClock; /* In 10Khz unit */
		423	COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
		424	} SET_ENGINE_CLOCK_PS_ALLOCATION;
		425
		426	/****************************************************************************/
		427	/* Structures used by SetMemoryClockTable */
		428	/****************************************************************************/
		429	typedef struct _SET_MEMORY_CLOCK_PARAMETERS {
		430	ULONG ulTargetMemoryClock; /* In 10Khz unit */
		431	} SET_MEMORY_CLOCK_PARAMETERS;
		432
		433	typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION {
		434	ULONG ulTargetMemoryClock; /* In 10Khz unit */
		435	COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
		436	} SET_MEMORY_CLOCK_PS_ALLOCATION;
		437
		438	/****************************************************************************/
		439	/* Structures used by ASIC_Init.ctb */
		440	/****************************************************************************/
		441	typedef struct _ASIC_INIT_PARAMETERS {
		442	ULONG ulDefaultEngineClock; /* In 10Khz unit */
		443	ULONG ulDefaultMemoryClock; /* In 10Khz unit */
		444	} ASIC_INIT_PARAMETERS;
		445
		446	typedef struct _ASIC_INIT_PS_ALLOCATION {
		447	ASIC_INIT_PARAMETERS sASICInitClocks;
		448	SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; /* Caller doesn't need to init this structure */
		449	} ASIC_INIT_PS_ALLOCATION;
		450
		451	/****************************************************************************/
		452	/* Structure used by DynamicClockGatingTable.ctb */
		453	/****************************************************************************/
		454	typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS {
		455	UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */
		456	UCHAR ucPadding[3];
		457	} DYNAMIC_CLOCK_GATING_PARAMETERS;
		458	#define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS
		459
		460	/****************************************************************************/
		461	/* Structure used by EnableASIC_StaticPwrMgtTable.ctb */
		462	/****************************************************************************/
		463	typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS {
		464	UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */
		465	UCHAR ucPadding[3];
		466	} ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS;
		467	#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
		468
		469	/****************************************************************************/
		470	/* Structures used by DAC_LoadDetectionTable.ctb */
		471	/****************************************************************************/
		472	typedef struct _DAC_LOAD_DETECTION_PARAMETERS {
		473	USHORT usDeviceID; /* {ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} */
		474	UCHAR ucDacType; /* {ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} */
		475	UCHAR ucMisc; /* Valid only when table revision =1.3 and above */
		476	} DAC_LOAD_DETECTION_PARAMETERS;
		477
		478	/* DAC_LOAD_DETECTION_PARAMETERS.ucMisc */
		479	#define DAC_LOAD_MISC_YPrPb 0x01
		480
		481	typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION {
		482	DAC_LOAD_DETECTION_PARAMETERS sDacload;
		483	ULONG Reserved[2]; /* Don't set this one, allocation for EXT DAC */
		484	} DAC_LOAD_DETECTION_PS_ALLOCATION;
		485
		486	/****************************************************************************/
		487	/* Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb */
		488	/****************************************************************************/
		489	typedef struct _DAC_ENCODER_CONTROL_PARAMETERS {
		490	USHORT usPixelClock; /* in 10KHz; for bios convenient */
		491	UCHAR ucDacStandard; /* See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) */
		492	UCHAR ucAction; /* 0: turn off encoder */
		493	/* 1: setup and turn on encoder */
		494	/* 7: ATOM_ENCODER_INIT Initialize DAC */
		495	} DAC_ENCODER_CONTROL_PARAMETERS;
		496
		497	#define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS
		498
		499	/****************************************************************************/
		500	/* Structures used by DIG1EncoderControlTable */
		501	/* DIG2EncoderControlTable */
		502	/* ExternalEncoderControlTable */
		503	/****************************************************************************/
		504	typedef struct _DIG_ENCODER_CONTROL_PARAMETERS {
		505	USHORT usPixelClock; /* in 10KHz; for bios convenient */
		506	UCHAR ucConfig;
		507	/* [2] Link Select: */
		508	/* =0: PHY linkA if bfLane<3 */
		509	/* =1: PHY linkB if bfLanes<3 */
		510	/* =0: PHY linkA+B if bfLanes=3 */
		511	/* [3] Transmitter Sel */
		512	/* =0: UNIPHY or PCIEPHY */
		513	/* =1: LVTMA */
		514	UCHAR ucAction; /* =0: turn off encoder */
		515	/* =1: turn on encoder */
		516	UCHAR ucEncoderMode;
		517	/* =0: DP encoder */
		518	/* =1: LVDS encoder */
		519	/* =2: DVI encoder */
		520	/* =3: HDMI encoder */
		521	/* =4: SDVO encoder */
		522	UCHAR ucLaneNum; /* how many lanes to enable */
		523	UCHAR ucReserved[2];
		524	} DIG_ENCODER_CONTROL_PARAMETERS;
		525	#define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS
		526	#define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS
		527
		528	/* ucConfig */
		529	#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01
		530	#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00
		531	#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01
		532	#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04
		533	#define ATOM_ENCODER_CONFIG_LINKA 0x00
		534	#define ATOM_ENCODER_CONFIG_LINKB 0x04
		535	#define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA
		536	#define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB
		537	#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08
		538	#define ATOM_ENCODER_CONFIG_UNIPHY 0x00
		539	#define ATOM_ENCODER_CONFIG_LVTMA 0x08
		540	#define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00
		541	#define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08
		542	#define ATOM_ENCODER_CONFIG_DIGB 0x80 /* VBIOS Internal use, outside SW should set this bit=0 */
		543	/* ucAction */
		544	/* ATOM_ENABLE: Enable Encoder */
		545	/* ATOM_DISABLE: Disable Encoder */
		546
		547	/* ucEncoderMode */
		548	#define ATOM_ENCODER_MODE_DP 0
		549	#define ATOM_ENCODER_MODE_LVDS 1
		550	#define ATOM_ENCODER_MODE_DVI 2
		551	#define ATOM_ENCODER_MODE_HDMI 3
		552	#define ATOM_ENCODER_MODE_SDVO 4
		553	#define ATOM_ENCODER_MODE_TV 13
		554	#define ATOM_ENCODER_MODE_CV 14
		555	#define ATOM_ENCODER_MODE_CRT 15
		556
		557	typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 {
		558	#if ATOM_BIG_ENDIAN
		559	UCHAR ucReserved1:2;
		560	UCHAR ucTransmitterSel:2; /* =0: UniphyAB, =1: UniphyCD =2: UniphyEF */
		561	UCHAR ucLinkSel:1; /* =0: linkA/C/E =1: linkB/D/F */
		562	UCHAR ucReserved:1;
		563	UCHAR ucDPLinkRate:1; /* =0: 1.62Ghz, =1: 2.7Ghz */
		564	#else
		565	UCHAR ucDPLinkRate:1; /* =0: 1.62Ghz, =1: 2.7Ghz */
		566	UCHAR ucReserved:1;
		567	UCHAR ucLinkSel:1; /* =0: linkA/C/E =1: linkB/D/F */
		568	UCHAR ucTransmitterSel:2; /* =0: UniphyAB, =1: UniphyCD =2: UniphyEF */
		569	UCHAR ucReserved1:2;
		570	#endif
		571	} ATOM_DIG_ENCODER_CONFIG_V2;
		572
		573	typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 {
		574	USHORT usPixelClock; /* in 10KHz; for bios convenient */
		575	ATOM_DIG_ENCODER_CONFIG_V2 acConfig;
		576	UCHAR ucAction;
		577	UCHAR ucEncoderMode;
		578	/* =0: DP encoder */
		579	/* =1: LVDS encoder */
		580	/* =2: DVI encoder */
		581	/* =3: HDMI encoder */
		582	/* =4: SDVO encoder */
		583	UCHAR ucLaneNum; /* how many lanes to enable */
		584	UCHAR ucReserved[2];
		585	} DIG_ENCODER_CONTROL_PARAMETERS_V2;
		586
		587	/* ucConfig */
		588	#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01
		589	#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00
		590	#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01
		591	#define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04
		592	#define ATOM_ENCODER_CONFIG_V2_LINKA 0x00
		593	#define ATOM_ENCODER_CONFIG_V2_LINKB 0x04
		594	#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18
		595	#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00
		596	#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08
		597	#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10
		598
		599	/****************************************************************************/
		600	/* Structures used by UNIPHYTransmitterControlTable */
		601	/* LVTMATransmitterControlTable */
		602	/* DVOOutputControlTable */
		603	/****************************************************************************/
		604	typedef struct _ATOM_DP_VS_MODE {
		605	UCHAR ucLaneSel;
		606	UCHAR ucLaneSet;
		607	} ATOM_DP_VS_MODE;
		608
		609	typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS {
		610	union {
		611	USHORT usPixelClock; /* in 10KHz; for bios convenient */
		612	USHORT usInitInfo; /* when init uniphy,lower 8bit is used for connector type defined in objectid.h */
		613	ATOM_DP_VS_MODE asMode; /* DP Voltage swing mode */
		614	};
		615	UCHAR ucConfig;
		616	/* [0]=0: 4 lane Link, */
		617	/* =1: 8 lane Link ( Dual Links TMDS ) */
		618	/* [1]=0: InCoherent mode */
		619	/* =1: Coherent Mode */
		620	/* [2] Link Select: */
		621	/* =0: PHY linkA if bfLane<3 */
		622	/* =1: PHY linkB if bfLanes<3 */
		623	/* =0: PHY linkA+B if bfLanes=3 */
		624	/* [5:4]PCIE lane Sel */
		625	/* =0: lane 0~3 or 0~7 */
		626	/* =1: lane 4~7 */
		627	/* =2: lane 8~11 or 8~15 */
		628	/* =3: lane 12~15 */
		629	UCHAR ucAction; /* =0: turn off encoder */
		630	/* =1: turn on encoder */
		631	UCHAR ucReserved[4];
		632	} DIG_TRANSMITTER_CONTROL_PARAMETERS;
		633
		634	#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS
		635
		636	/* ucInitInfo */
		637	#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff
		638
		639	/* ucConfig */
		640	#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01
		641	#define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02
		642	#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04
		643	#define ATOM_TRANSMITTER_CONFIG_LINKA 0x00
		644	#define ATOM_TRANSMITTER_CONFIG_LINKB 0x04
		645	#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00
		646	#define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04
		647
		648	#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 /* only used when ATOM_TRANSMITTER_ACTION_ENABLE */
		649	#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 /* only used when ATOM_TRANSMITTER_ACTION_ENABLE */
		650	#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 /* only used when ATOM_TRANSMITTER_ACTION_ENABLE */
		651
		652	#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30
		653	#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00
		654	#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20
		655	#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30
		656	#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0
		657	#define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00
		658	#define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00
		659	#define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40
		660	#define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80
		661	#define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80
		662	#define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0
		663
		664	/* ucAction */
		665	#define ATOM_TRANSMITTER_ACTION_DISABLE 0
		666	#define ATOM_TRANSMITTER_ACTION_ENABLE 1
		667	#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2
		668	#define ATOM_TRANSMITTER_ACTION_LCD_BLON 3
		669	#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4
		670	#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5
		671	#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6
		672	#define ATOM_TRANSMITTER_ACTION_INIT 7
		673	#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8
		674	#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9
		675	#define ATOM_TRANSMITTER_ACTION_SETUP 10
		676	#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11
		677
		678	/* Following are used for DigTransmitterControlTable ver1.2 */
		679	typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 {
		680	#if ATOM_BIG_ENDIAN
		681	UCHAR ucTransmitterSel:2; /* bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) */
		682	/* =1 Dig Transmitter 2 ( Uniphy CD ) */
		683	/* =2 Dig Transmitter 3 ( Uniphy EF ) */
		684	UCHAR ucReserved:1;
		685	UCHAR fDPConnector:1; /* bit4=0: DP connector =1: None DP connector */
		686	UCHAR ucEncoderSel:1; /* bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) */
		687	UCHAR ucLinkSel:1; /* bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E */
		688	/* =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F */
		689
		690	UCHAR fCoherentMode:1; /* bit1=1: Coherent Mode ( for DVI/HDMI mode ) */
		691	UCHAR fDualLinkConnector:1; /* bit0=1: Dual Link DVI connector */
		692	#else
		693	UCHAR fDualLinkConnector:1; /* bit0=1: Dual Link DVI connector */
		694	UCHAR fCoherentMode:1; /* bit1=1: Coherent Mode ( for DVI/HDMI mode ) */
		695	UCHAR ucLinkSel:1; /* bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E */
		696	/* =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F */
		697	UCHAR ucEncoderSel:1; /* bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) */
		698	UCHAR fDPConnector:1; /* bit4=0: DP connector =1: None DP connector */
		699	UCHAR ucReserved:1;
		700	UCHAR ucTransmitterSel:2; /* bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) */
		701	/* =1 Dig Transmitter 2 ( Uniphy CD ) */
		702	/* =2 Dig Transmitter 3 ( Uniphy EF ) */
		703	#endif
		704	} ATOM_DIG_TRANSMITTER_CONFIG_V2;
		705
		706	/* ucConfig */
		707	/* Bit0 */
		708	#define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01
		709
		710	/* Bit1 */
		711	#define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02
		712
		713	/* Bit2 */
		714	#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04
		715	#define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00
		716	#define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04
		717
		718	/* Bit3 */
		719	#define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08
		720	#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 /* only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP */
		721	#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 /* only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP */
		722
		723	/* Bit4 */
		724	#define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10
		725
		726	/* Bit7:6 */
		727	#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0
		728	#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 /* AB */
		729	#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 /* CD */
		730	#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 /* EF */
		731
		732	typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 {
		733	union {
		734	USHORT usPixelClock; /* in 10KHz; for bios convenient */
		735	USHORT usInitInfo; /* when init uniphy,lower 8bit is used for connector type defined in objectid.h */
		736	ATOM_DP_VS_MODE asMode; /* DP Voltage swing mode */
		737	};
		738	ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig;
		739	UCHAR ucAction; /* define as ATOM_TRANSMITER_ACTION_XXX */
		740	UCHAR ucReserved[4];
		741	} DIG_TRANSMITTER_CONTROL_PARAMETERS_V2;
		742
		743	/****************************************************************************/
		744	/* Structures used by DAC1OuputControlTable */
		745	/* DAC2OuputControlTable */
		746	/* LVTMAOutputControlTable (Before DEC30) */
		747	/* TMDSAOutputControlTable (Before DEC30) */
		748	/****************************************************************************/
		749	typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS {
		750	UCHAR ucAction; /* Possible input:ATOM_ENABLE\|\|ATOMDISABLE */
		751	/* When the display is LCD, in addition to above: */
		752	/* ATOM_LCD_BLOFF\|\| ATOM_LCD_BLON \|\|ATOM_LCD_BL_BRIGHTNESS_CONTROL\|\|ATOM_LCD_SELFTEST_START\|\| */
		753	/* ATOM_LCD_SELFTEST_STOP */
		754
		755	UCHAR aucPadding[3]; /* padding to DWORD aligned */
		756	} DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS;
		757
		758	#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
		759
		760	#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
		761	#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
		762
		763	#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
		764	#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
		765
		766	#define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
		767	#define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
		768
		769	#define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
		770	#define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
		771
		772	#define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
		773	#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
		774
		775	#define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
		776	#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
		777
		778	#define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
		779	#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
		780
		781	#define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
		782	#define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION
		783	#define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS
		784
		785	/****************************************************************************/
		786	/* Structures used by BlankCRTCTable */
		787	/****************************************************************************/
		788	typedef struct _BLANK_CRTC_PARAMETERS {
		789	UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */
		790	UCHAR ucBlanking; /* ATOM_BLANKING or ATOM_BLANKINGOFF */
		791	USHORT usBlackColorRCr;
		792	USHORT usBlackColorGY;
		793	USHORT usBlackColorBCb;
		794	} BLANK_CRTC_PARAMETERS;
		795	#define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS
		796
		797	/****************************************************************************/
		798	/* Structures used by EnableCRTCTable */
		799	/* EnableCRTCMemReqTable */
		800	/* UpdateCRTC_DoubleBufferRegistersTable */
		801	/****************************************************************************/
		802	typedef struct _ENABLE_CRTC_PARAMETERS {
		803	UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */
		804	UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */
		805	UCHAR ucPadding[2];
		806	} ENABLE_CRTC_PARAMETERS;
		807	#define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS
		808
		809	/****************************************************************************/
		810	/* Structures used by SetCRTC_OverScanTable */
		811	/****************************************************************************/
		812	typedef struct _SET_CRTC_OVERSCAN_PARAMETERS {
		813	USHORT usOverscanRight; /* right */
		814	USHORT usOverscanLeft; /* left */
		815	USHORT usOverscanBottom; /* bottom */
		816	USHORT usOverscanTop; /* top */
		817	UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */
		818	UCHAR ucPadding[3];
		819	} SET_CRTC_OVERSCAN_PARAMETERS;
		820	#define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS
		821
		822	/****************************************************************************/
		823	/* Structures used by SetCRTC_ReplicationTable */
		824	/****************************************************************************/
		825	typedef struct _SET_CRTC_REPLICATION_PARAMETERS {
		826	UCHAR ucH_Replication; /* horizontal replication */
		827	UCHAR ucV_Replication; /* vertical replication */
		828	UCHAR usCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */
		829	UCHAR ucPadding;
		830	} SET_CRTC_REPLICATION_PARAMETERS;
		831	#define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS
		832
		833	/****************************************************************************/
		834	/* Structures used by SelectCRTC_SourceTable */
		835	/****************************************************************************/
		836	typedef struct _SELECT_CRTC_SOURCE_PARAMETERS {
		837	UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */
		838	UCHAR ucDevice; /* ATOM_DEVICE_CRT1\|ATOM_DEVICE_CRT2\|.... */
		839	UCHAR ucPadding[2];
		840	} SELECT_CRTC_SOURCE_PARAMETERS;
		841	#define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS
		842
		843	typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 {
		844	UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */
		845	UCHAR ucEncoderID; /* DAC1/DAC2/TVOUT/DIG1/DIG2/DVO */
		846	UCHAR ucEncodeMode; /* Encoding mode, only valid when using DIG1/DIG2/DVO */
		847	UCHAR ucPadding;
		848	} SELECT_CRTC_SOURCE_PARAMETERS_V2;
		849
		850	/* ucEncoderID */
		851	/* #define ASIC_INT_DAC1_ENCODER_ID 0x00 */
		852	/* #define ASIC_INT_TV_ENCODER_ID 0x02 */
		853	/* #define ASIC_INT_DIG1_ENCODER_ID 0x03 */
		854	/* #define ASIC_INT_DAC2_ENCODER_ID 0x04 */
		855	/* #define ASIC_EXT_TV_ENCODER_ID 0x06 */
		856	/* #define ASIC_INT_DVO_ENCODER_ID 0x07 */
		857	/* #define ASIC_INT_DIG2_ENCODER_ID 0x09 */
		858	/* #define ASIC_EXT_DIG_ENCODER_ID 0x05 */
		859
		860	/* ucEncodeMode */
		861	/* #define ATOM_ENCODER_MODE_DP 0 */
		862	/* #define ATOM_ENCODER_MODE_LVDS 1 */
		863	/* #define ATOM_ENCODER_MODE_DVI 2 */
		864	/* #define ATOM_ENCODER_MODE_HDMI 3 */
		865	/* #define ATOM_ENCODER_MODE_SDVO 4 */
		866	/* #define ATOM_ENCODER_MODE_TV 13 */
		867	/* #define ATOM_ENCODER_MODE_CV 14 */
		868	/* #define ATOM_ENCODER_MODE_CRT 15 */
		869
		870	/****************************************************************************/
		871	/* Structures used by SetPixelClockTable */
		872	/* GetPixelClockTable */
		873	/****************************************************************************/
		874	/* Major revision=1., Minor revision=1 */
		875	typedef struct _PIXEL_CLOCK_PARAMETERS {
		876	USHORT usPixelClock; /* in 10kHz unit; for bios convenient = (RefClkFB_Div)/(Ref_DivPost_Div) */
		877	/* 0 means disable PPLL */
		878	USHORT usRefDiv; /* Reference divider */
		879	USHORT usFbDiv; /* feedback divider */
		880	UCHAR ucPostDiv; /* post divider */
		881	UCHAR ucFracFbDiv; /* fractional feedback divider */
		882	UCHAR ucPpll; /* ATOM_PPLL1 or ATOM_PPL2 */
		883	UCHAR ucRefDivSrc; /* ATOM_PJITTER or ATO_NONPJITTER */
		884	UCHAR ucCRTC; /* Which CRTC uses this Ppll */
		885	UCHAR ucPadding;
		886	} PIXEL_CLOCK_PARAMETERS;
		887
		888	/* Major revision=1., Minor revision=2, add ucMiscIfno */
		889	/* ucMiscInfo: */
		890	#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1
		891	#define MISC_DEVICE_INDEX_MASK 0xF0
		892	#define MISC_DEVICE_INDEX_SHIFT 4
		893
		894	typedef struct _PIXEL_CLOCK_PARAMETERS_V2 {
		895	USHORT usPixelClock; /* in 10kHz unit; for bios convenient = (RefClkFB_Div)/(Ref_DivPost_Div) */
		896	/* 0 means disable PPLL */
		897	USHORT usRefDiv; /* Reference divider */
		898	USHORT usFbDiv; /* feedback divider */
		899	UCHAR ucPostDiv; /* post divider */
		900	UCHAR ucFracFbDiv; /* fractional feedback divider */
		901	UCHAR ucPpll; /* ATOM_PPLL1 or ATOM_PPL2 */
		902	UCHAR ucRefDivSrc; /* ATOM_PJITTER or ATO_NONPJITTER */
		903	UCHAR ucCRTC; /* Which CRTC uses this Ppll */
		904	UCHAR ucMiscInfo; /* Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog */
		905	} PIXEL_CLOCK_PARAMETERS_V2;
		906
		907	/* Major revision=1., Minor revision=3, structure/definition change */
		908	/* ucEncoderMode: */
		909	/* ATOM_ENCODER_MODE_DP */
		910	/* ATOM_ENOCDER_MODE_LVDS */
		911	/* ATOM_ENOCDER_MODE_DVI */
		912	/* ATOM_ENOCDER_MODE_HDMI */
		913	/* ATOM_ENOCDER_MODE_SDVO */
		914	/* ATOM_ENCODER_MODE_TV 13 */
		915	/* ATOM_ENCODER_MODE_CV 14 */
		916	/* ATOM_ENCODER_MODE_CRT 15 */
		917
		918	/* ucDVOConfig */
		919	/* #define DVO_ENCODER_CONFIG_RATE_SEL 0x01 */
		920	/* #define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 */
		921	/* #define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 */
		922	/* #define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c */
		923	/* #define DVO_ENCODER_CONFIG_LOW12BIT 0x00 */
		924	/* #define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 */
		925	/* #define DVO_ENCODER_CONFIG_24BIT 0x08 */
		926
		927	/* ucMiscInfo: also changed, see below */
		928	#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01
		929	#define PIXEL_CLOCK_MISC_VGA_MODE 0x02
		930	#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04
		931	#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00
		932	#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04
		933	#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08
		934
		935	typedef struct _PIXEL_CLOCK_PARAMETERS_V3 {
		936	USHORT usPixelClock; /* in 10kHz unit; for bios convenient = (RefClkFB_Div)/(Ref_DivPost_Div) */
		937	/* 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. */
		938	USHORT usRefDiv; /* Reference divider */
		939	USHORT usFbDiv; /* feedback divider */
		940	UCHAR ucPostDiv; /* post divider */
		941	UCHAR ucFracFbDiv; /* fractional feedback divider */
		942	UCHAR ucPpll; /* ATOM_PPLL1 or ATOM_PPL2 */
		943	UCHAR ucTransmitterId; /* graphic encoder id defined in objectId.h */
		944	union {
		945	UCHAR ucEncoderMode; /* encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ */
		946	UCHAR ucDVOConfig; /* when use DVO, need to know SDR/DDR, 12bit or 24bit */
		947	};
		948	UCHAR ucMiscInfo; /* bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel */
		949	/* bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source */
		950	} PIXEL_CLOCK_PARAMETERS_V3;
		951
		952	#define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2
		953	#define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST
		954
		955	/****************************************************************************/
		956	/* Structures used by AdjustDisplayPllTable */
		957	/****************************************************************************/
		958	typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS {
		959	USHORT usPixelClock;
		960	UCHAR ucTransmitterID;
		961	UCHAR ucEncodeMode;
		962	union {
		963	UCHAR ucDVOConfig; /* if DVO, need passing link rate and output 12bitlow or 24bit */
		964	UCHAR ucConfig; /* if none DVO, not defined yet */
		965	};
		966	UCHAR ucReserved[3];
		967	} ADJUST_DISPLAY_PLL_PARAMETERS;
		968
		969	#define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10
		970
		971	#define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS
		972
		973	/****************************************************************************/
		974	/* Structures used by EnableYUVTable */
		975	/****************************************************************************/
		976	typedef struct _ENABLE_YUV_PARAMETERS {
		977	UCHAR ucEnable; /* ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) */
		978	UCHAR ucCRTC; /* Which CRTC needs this YUV or RGB format */
		979	UCHAR ucPadding[2];
		980	} ENABLE_YUV_PARAMETERS;
		981	#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS
		982
		983	/****************************************************************************/
		984	/* Structures used by GetMemoryClockTable */
		985	/****************************************************************************/
		986	typedef struct _GET_MEMORY_CLOCK_PARAMETERS {
		987	ULONG ulReturnMemoryClock; /* current memory speed in 10KHz unit */
		988	} GET_MEMORY_CLOCK_PARAMETERS;
		989	#define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS
		990
		991	/****************************************************************************/
		992	/* Structures used by GetEngineClockTable */
		993	/****************************************************************************/
		994	typedef struct _GET_ENGINE_CLOCK_PARAMETERS {
		995	ULONG ulReturnEngineClock; /* current engine speed in 10KHz unit */
		996	} GET_ENGINE_CLOCK_PARAMETERS;
		997	#define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS
		998
		999	/****************************************************************************/
		1000	/* Following Structures and constant may be obsolete */
		1001	/****************************************************************************/
		1002	/* Maxium 8 bytes,the data read in will be placed in the parameter space. */
		1003	/* Read operaion successeful when the paramter space is non-zero, otherwise read operation failed */
		1004	typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS {
		1005	USHORT usPrescale; /* Ratio between Engine clock and I2C clock */
		1006	USHORT usVRAMAddress; /* Adress in Frame Buffer where to pace raw EDID */
		1007	USHORT usStatus; /* When use output: lower byte EDID checksum, high byte hardware status */
		1008	/* WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte */
		1009	UCHAR ucSlaveAddr; /* Read from which slave */
		1010	UCHAR ucLineNumber; /* Read from which HW assisted line */
		1011	} READ_EDID_FROM_HW_I2C_DATA_PARAMETERS;
		1012	#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
		1013
		1014	#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0
		1015	#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1
		1016	#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2
		1017	#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3
		1018	#define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4
		1019
		1020	typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS {
		1021	USHORT usPrescale; /* Ratio between Engine clock and I2C clock */
		1022	USHORT usByteOffset; /* Write to which byte */
		1023	/* Upper portion of usByteOffset is Format of data */
		1024	/* 1bytePS+offsetPS */
		1025	/* 2bytesPS+offsetPS */
		1026	/* blockID+offsetPS */
		1027	/* blockID+offsetID */
		1028	/* blockID+counterID+offsetID */
		1029	UCHAR ucData; /* PS data1 */
		1030	UCHAR ucStatus; /* Status byte 1=success, 2=failure, Also is used as PS data2 */
		1031	UCHAR ucSlaveAddr; /* Write to which slave */
		1032	UCHAR ucLineNumber; /* Write from which HW assisted line */
		1033	} WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS;
		1034
		1035	#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
		1036
		1037	typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS {
		1038	USHORT usPrescale; /* Ratio between Engine clock and I2C clock */
		1039	UCHAR ucSlaveAddr; /* Write to which slave */
		1040	UCHAR ucLineNumber; /* Write from which HW assisted line */
		1041	} SET_UP_HW_I2C_DATA_PARAMETERS;
		1042
		1043	/**************************************************************************/
		1044	#define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
		1045
		1046	/****************************************************************************/
		1047	/* Structures used by PowerConnectorDetectionTable */
		1048	/****************************************************************************/
		1049	typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS {
		1050	UCHAR ucPowerConnectorStatus; /* Used for return value 0: detected, 1:not detected */
		1051	UCHAR ucPwrBehaviorId;
		1052	USHORT usPwrBudget; /* how much power currently boot to in unit of watt */
		1053	} POWER_CONNECTOR_DETECTION_PARAMETERS;
		1054
		1055	typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION {
		1056	UCHAR ucPowerConnectorStatus; /* Used for return value 0: detected, 1:not detected */
		1057	UCHAR ucReserved;
		1058	USHORT usPwrBudget; /* how much power currently boot to in unit of watt */
		1059	WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
		1060	} POWER_CONNECTOR_DETECTION_PS_ALLOCATION;
		1061
		1062	/**************************LVDS SS Command Table Definitions********************/
		1063
		1064	/****************************************************************************/
		1065	/* Structures used by EnableSpreadSpectrumOnPPLLTable */
		1066	/****************************************************************************/
		1067	typedef struct _ENABLE_LVDS_SS_PARAMETERS {
		1068	USHORT usSpreadSpectrumPercentage;
		1069	UCHAR ucSpreadSpectrumType; /* Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD */
		1070	UCHAR ucSpreadSpectrumStepSize_Delay; /* bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY */
		1071	UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */
		1072	UCHAR ucPadding[3];
		1073	} ENABLE_LVDS_SS_PARAMETERS;
		1074
		1075	/* ucTableFormatRevision=1,ucTableContentRevision=2 */
		1076	typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 {
		1077	USHORT usSpreadSpectrumPercentage;
		1078	UCHAR ucSpreadSpectrumType; /* Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD */
		1079	UCHAR ucSpreadSpectrumStep; /* */
		1080	UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */
		1081	UCHAR ucSpreadSpectrumDelay;
		1082	UCHAR ucSpreadSpectrumRange;
		1083	UCHAR ucPadding;
		1084	} ENABLE_LVDS_SS_PARAMETERS_V2;
		1085
		1086	/* This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. */
		1087	typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL {
		1088	USHORT usSpreadSpectrumPercentage;
		1089	UCHAR ucSpreadSpectrumType; /* Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD */
		1090	UCHAR ucSpreadSpectrumStep; /* */
		1091	UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */
		1092	UCHAR ucSpreadSpectrumDelay;
		1093	UCHAR ucSpreadSpectrumRange;
		1094	UCHAR ucPpll; /* ATOM_PPLL1/ATOM_PPLL2 */
		1095	} ENABLE_SPREAD_SPECTRUM_ON_PPLL;
		1096
		1097	#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL
		1098
		1099	/**************************************************************************/
		1100
		1101	typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION {
		1102	PIXEL_CLOCK_PARAMETERS sPCLKInput;
		1103	ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved; /* Caller doesn't need to init this portion */
		1104	} SET_PIXEL_CLOCK_PS_ALLOCATION;
		1105
		1106	#define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION
		1107
		1108	/****************************************************************************/
		1109	/* Structures used by ### */
		1110	/****************************************************************************/
		1111	typedef struct _MEMORY_TRAINING_PARAMETERS {
		1112	ULONG ulTargetMemoryClock; /* In 10Khz unit */
		1113	} MEMORY_TRAINING_PARAMETERS;
		1114	#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS
		1115
		1116	/**************************LVDS and other encoder command table definitions ********************/
		1117
		1118	/****************************************************************************/
		1119	/* Structures used by LVDSEncoderControlTable (Before DCE30) */
		1120	/* LVTMAEncoderControlTable (Before DCE30) */
		1121	/* TMDSAEncoderControlTable (Before DCE30) */
		1122	/****************************************************************************/
		1123	typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS {
		1124	USHORT usPixelClock; /* in 10KHz; for bios convenient */
		1125	UCHAR ucMisc; /* bit0=0: Enable single link */
		1126	/* =1: Enable dual link */
		1127	/* Bit1=0: 666RGB */
		1128	/* =1: 888RGB */
		1129	UCHAR ucAction; /* 0: turn off encoder */
		1130	/* 1: setup and turn on encoder */
		1131	} LVDS_ENCODER_CONTROL_PARAMETERS;
		1132
		1133	#define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS
		1134
		1135	#define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS
		1136	#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS
		1137
		1138	#define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS
		1139	#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS
		1140
		1141	/* ucTableFormatRevision=1,ucTableContentRevision=2 */
		1142	typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 {
		1143	USHORT usPixelClock; /* in 10KHz; for bios convenient */
		1144	UCHAR ucMisc; /* see PANEL_ENCODER_MISC_xx defintions below */
		1145	UCHAR ucAction; /* 0: turn off encoder */
		1146	/* 1: setup and turn on encoder */
		1147	UCHAR ucTruncate; /* bit0=0: Disable truncate */
		1148	/* =1: Enable truncate */
		1149	/* bit4=0: 666RGB */
		1150	/* =1: 888RGB */
		1151	UCHAR ucSpatial; /* bit0=0: Disable spatial dithering */
		1152	/* =1: Enable spatial dithering */
		1153	/* bit4=0: 666RGB */
		1154	/* =1: 888RGB */
		1155	UCHAR ucTemporal; /* bit0=0: Disable temporal dithering */
		1156	/* =1: Enable temporal dithering */
		1157	/* bit4=0: 666RGB */
		1158	/* =1: 888RGB */
		1159	/* bit5=0: Gray level 2 */
		1160	/* =1: Gray level 4 */
		1161	UCHAR ucFRC; /* bit4=0: 25FRC_SEL pattern E */
		1162	/* =1: 25FRC_SEL pattern F */
		1163	/* bit6:5=0: 50FRC_SEL pattern A */
		1164	/* =1: 50FRC_SEL pattern B */
		1165	/* =2: 50FRC_SEL pattern C */
		1166	/* =3: 50FRC_SEL pattern D */
		1167	/* bit7=0: 75FRC_SEL pattern E */
		1168	/* =1: 75FRC_SEL pattern F */
		1169	} LVDS_ENCODER_CONTROL_PARAMETERS_V2;
		1170
		1171	#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
		1172
		1173	#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
		1174	#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
		1175
		1176	#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
		1177	#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2
		1178
		1179	#define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2
		1180	#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
		1181
		1182	#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
		1183	#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3
		1184
		1185	#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
		1186	#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3
		1187
		1188	/****************************************************************************/
		1189	/* Structures used by ### */
		1190	/****************************************************************************/
		1191	typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS {
		1192	UCHAR ucEnable; /* Enable or Disable External TMDS encoder */
		1193	UCHAR ucMisc; /* Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} */
		1194	UCHAR ucPadding[2];
		1195	} ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS;
		1196
		1197	typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION {
		1198	ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder;
		1199	WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; /* Caller doesn't need to init this portion */
		1200	} ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION;
		1201
		1202	#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
		1203
		1204	typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 {
		1205	ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder;
		1206	WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; /* Caller doesn't need to init this portion */
		1207	} ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2;
		1208
		1209	typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION {
		1210	DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder;
		1211	WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
		1212	} EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION;
		1213
		1214	/****************************************************************************/
		1215	/* Structures used by DVOEncoderControlTable */
		1216	/****************************************************************************/
		1217	/* ucTableFormatRevision=1,ucTableContentRevision=3 */
		1218
		1219	/* ucDVOConfig: */
		1220	#define DVO_ENCODER_CONFIG_RATE_SEL 0x01
		1221	#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00
		1222	#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01
		1223	#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c
		1224	#define DVO_ENCODER_CONFIG_LOW12BIT 0x00
		1225	#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04
		1226	#define DVO_ENCODER_CONFIG_24BIT 0x08
		1227
		1228	typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 {
		1229	USHORT usPixelClock;
		1230	UCHAR ucDVOConfig;
		1231	UCHAR ucAction; /* ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT */
		1232	UCHAR ucReseved[4];
		1233	} DVO_ENCODER_CONTROL_PARAMETERS_V3;
		1234	#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3
		1235
		1236	/* ucTableFormatRevision=1 */
		1237	/* ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for */
		1238	/* bit1=0: non-coherent mode */
		1239	/* =1: coherent mode */
		1240
		1241	/* ========================================================================================== */
		1242	/* Only change is here next time when changing encoder parameter definitions again! */
		1243	#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
		1244	#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST
		1245
		1246	#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
		1247	#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST
		1248
		1249	#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
		1250	#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST
		1251
		1252	#define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS
		1253	#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION
		1254
		1255	/* ========================================================================================== */
		1256	#define PANEL_ENCODER_MISC_DUAL 0x01
		1257	#define PANEL_ENCODER_MISC_COHERENT 0x02
		1258	#define PANEL_ENCODER_MISC_TMDS_LINKB 0x04
		1259	#define PANEL_ENCODER_MISC_HDMI_TYPE 0x08
		1260
		1261	#define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE
		1262	#define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE
		1263	#define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1)
		1264
		1265	#define PANEL_ENCODER_TRUNCATE_EN 0x01
		1266	#define PANEL_ENCODER_TRUNCATE_DEPTH 0x10
		1267	#define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01
		1268	#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10
		1269	#define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01
		1270	#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10
		1271	#define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20
		1272	#define PANEL_ENCODER_25FRC_MASK 0x10
		1273	#define PANEL_ENCODER_25FRC_E 0x00
		1274	#define PANEL_ENCODER_25FRC_F 0x10
		1275	#define PANEL_ENCODER_50FRC_MASK 0x60
		1276	#define PANEL_ENCODER_50FRC_A 0x00
		1277	#define PANEL_ENCODER_50FRC_B 0x20
		1278	#define PANEL_ENCODER_50FRC_C 0x40
		1279	#define PANEL_ENCODER_50FRC_D 0x60
		1280	#define PANEL_ENCODER_75FRC_MASK 0x80
		1281	#define PANEL_ENCODER_75FRC_E 0x00
		1282	#define PANEL_ENCODER_75FRC_F 0x80
		1283
		1284	/****************************************************************************/
		1285	/* Structures used by SetVoltageTable */
		1286	/****************************************************************************/
		1287	#define SET_VOLTAGE_TYPE_ASIC_VDDC 1
		1288	#define SET_VOLTAGE_TYPE_ASIC_MVDDC 2
		1289	#define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3
		1290	#define SET_VOLTAGE_TYPE_ASIC_VDDCI 4
		1291	#define SET_VOLTAGE_INIT_MODE 5
		1292	#define SET_VOLTAGE_GET_MAX_VOLTAGE 6 /* Gets the Max. voltage for the soldered Asic */
		1293
		1294	#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1
		1295	#define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2
		1296	#define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4
		1297
		1298	#define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0
		1299	#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1
		1300	#define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2
		1301
		1302	typedef struct _SET_VOLTAGE_PARAMETERS {
		1303	UCHAR ucVoltageType; /* To tell which voltage to set up, VDDC/MVDDC/MVDDQ */
		1304	UCHAR ucVoltageMode; /* To set all, to set source A or source B or ... */
		1305	UCHAR ucVoltageIndex; /* An index to tell which voltage level */
		1306	UCHAR ucReserved;
		1307	} SET_VOLTAGE_PARAMETERS;
		1308
		1309	typedef struct _SET_VOLTAGE_PARAMETERS_V2 {
		1310	UCHAR ucVoltageType; /* To tell which voltage to set up, VDDC/MVDDC/MVDDQ */
		1311	UCHAR ucVoltageMode; /* Not used, maybe use for state machine for differen power mode */
		1312	USHORT usVoltageLevel; /* real voltage level */
		1313	} SET_VOLTAGE_PARAMETERS_V2;
		1314
		1315	typedef struct _SET_VOLTAGE_PS_ALLOCATION {
		1316	SET_VOLTAGE_PARAMETERS sASICSetVoltage;
		1317	WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
		1318	} SET_VOLTAGE_PS_ALLOCATION;
		1319
		1320	/****************************************************************************/
		1321	/* Structures used by TVEncoderControlTable */
		1322	/****************************************************************************/
		1323	typedef struct _TV_ENCODER_CONTROL_PARAMETERS {
		1324	USHORT usPixelClock; /* in 10KHz; for bios convenient */
		1325	UCHAR ucTvStandard; /* See definition "ATOM_TV_NTSC ..." */
		1326	UCHAR ucAction; /* 0: turn off encoder */
		1327	/* 1: setup and turn on encoder */
		1328	} TV_ENCODER_CONTROL_PARAMETERS;
		1329
		1330	typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION {
		1331	TV_ENCODER_CONTROL_PARAMETERS sTVEncoder;
		1332	WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; /* Don't set this one */
		1333	} TV_ENCODER_CONTROL_PS_ALLOCATION;
		1334
		1335	/* ==============================Data Table Portion==================================== */
		1336
		1337	#ifdef UEFI_BUILD
		1338	#define UTEMP USHORT
		1339	#define USHORT void*
		1340	#endif
		1341
		1342	/****************************************************************************/
		1343	/* Structure used in Data.mtb */
		1344	/****************************************************************************/
		1345	typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES {
		1346	USHORT UtilityPipeLine; /* Offest for the utility to get parser info,Don't change this position! */
		1347	USHORT MultimediaCapabilityInfo; /* Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios */
		1348	USHORT MultimediaConfigInfo; /* Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios */
		1349	USHORT StandardVESA_Timing; /* Only used by Bios */
		1350	USHORT FirmwareInfo; /* Shared by various SW components,latest version 1.4 */
		1351	USHORT DAC_Info; /* Will be obsolete from R600 */
		1352	USHORT LVDS_Info; /* Shared by various SW components,latest version 1.1 */
		1353	USHORT TMDS_Info; /* Will be obsolete from R600 */
		1354	USHORT AnalogTV_Info; /* Shared by various SW components,latest version 1.1 */
		1355	USHORT SupportedDevicesInfo; /* Will be obsolete from R600 */
		1356	USHORT GPIO_I2C_Info; /* Shared by various SW components,latest version 1.2 will be used from R600 */
		1357	USHORT VRAM_UsageByFirmware; /* Shared by various SW components,latest version 1.3 will be used from R600 */
		1358	USHORT GPIO_Pin_LUT; /* Shared by various SW components,latest version 1.1 */
		1359	USHORT VESA_ToInternalModeLUT; /* Only used by Bios */
		1360	USHORT ComponentVideoInfo; /* Shared by various SW components,latest version 2.1 will be used from R600 */
		1361	USHORT PowerPlayInfo; /* Shared by various SW components,latest version 2.1,new design from R600 */
		1362	USHORT CompassionateData; /* Will be obsolete from R600 */
		1363	USHORT SaveRestoreInfo; /* Only used by Bios */
		1364	USHORT PPLL_SS_Info; /* Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info */
		1365	USHORT OemInfo; /* Defined and used by external SW, should be obsolete soon */
		1366	USHORT XTMDS_Info; /* Will be obsolete from R600 */
		1367	USHORT MclkSS_Info; /* Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used */
		1368	USHORT Object_Header; /* Shared by various SW components,latest version 1.1 */
		1369	USHORT IndirectIOAccess; /* Only used by Bios,this table position can't change at all!! */
		1370	USHORT MC_InitParameter; /* Only used by command table */
		1371	USHORT ASIC_VDDC_Info; /* Will be obsolete from R600 */
		1372	USHORT ASIC_InternalSS_Info; /* New tabel name from R600, used to be called "ASIC_MVDDC_Info" */
		1373	USHORT TV_VideoMode; /* Only used by command table */
		1374	USHORT VRAM_Info; /* Only used by command table, latest version 1.3 */
		1375	USHORT MemoryTrainingInfo; /* Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 */
		1376	USHORT IntegratedSystemInfo; /* Shared by various SW components */
		1377	USHORT ASIC_ProfilingInfo; /* New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 */
		1378	USHORT VoltageObjectInfo; /* Shared by various SW components, latest version 1.1 */
		1379	USHORT PowerSourceInfo; /* Shared by various SW components, latest versoin 1.1 */
		1380	} ATOM_MASTER_LIST_OF_DATA_TABLES;
		1381
		1382	#ifdef UEFI_BUILD
		1383	#define USHORT UTEMP
		1384	#endif
		1385
		1386	typedef struct _ATOM_MASTER_DATA_TABLE {
		1387	ATOM_COMMON_TABLE_HEADER sHeader;
		1388	ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables;
		1389	} ATOM_MASTER_DATA_TABLE;
		1390
		1391	/****************************************************************************/
		1392	/* Structure used in MultimediaCapabilityInfoTable */
		1393	/****************************************************************************/
		1394	typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO {
		1395	ATOM_COMMON_TABLE_HEADER sHeader;
		1396	ULONG ulSignature; /* HW info table signature string "$ATI" */
		1397	UCHAR ucI2C_Type; /* I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) */
		1398	UCHAR ucTV_OutInfo; /* Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) */
		1399	UCHAR ucVideoPortInfo; /* Provides the video port capabilities */
		1400	UCHAR ucHostPortInfo; /* Provides host port configuration information */
		1401	} ATOM_MULTIMEDIA_CAPABILITY_INFO;
		1402
		1403	/****************************************************************************/
		1404	/* Structure used in MultimediaConfigInfoTable */
		1405	/****************************************************************************/
		1406	typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO {
		1407	ATOM_COMMON_TABLE_HEADER sHeader;
		1408	ULONG ulSignature; /* MM info table signature sting "$MMT" */
		1409	UCHAR ucTunerInfo; /* Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) */
		1410	UCHAR ucAudioChipInfo; /* List the audio chip type (3:0) product type (4) and OEM revision (7:5) */
		1411	UCHAR ucProductID; /* Defines as OEM ID or ATI board ID dependent on product type setting */
		1412	UCHAR ucMiscInfo1; /* Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) */
		1413	UCHAR ucMiscInfo2; /* I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) */
		1414	UCHAR ucMiscInfo3; /* Video Decoder Type (3:0) Video In Standard/Crystal (7:4) */
		1415	UCHAR ucMiscInfo4; /* Video Decoder Host Config (2:0) reserved (7:3) */
		1416	UCHAR ucVideoInput0Info; /* Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */
		1417	UCHAR ucVideoInput1Info; /* Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */
		1418	UCHAR ucVideoInput2Info; /* Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */
		1419	UCHAR ucVideoInput3Info; /* Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */
		1420	UCHAR ucVideoInput4Info; /* Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */
		1421	} ATOM_MULTIMEDIA_CONFIG_INFO;
		1422
		1423	/****************************************************************************/
		1424	/* Structures used in FirmwareInfoTable */
		1425	/****************************************************************************/
		1426
		1427	/* usBIOSCapability Defintion: */
		1428	/* Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; */
		1429	/* Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; */
		1430	/* Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; */
		1431	/* Others: Reserved */
		1432	#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001
		1433	#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002
		1434	#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004
		1435	#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008
		1436	#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010
		1437	#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020
		1438	#define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040
		1439	#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080
		1440	#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100
		1441	#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00
		1442	#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000
		1443	#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000
		1444
		1445	#ifndef _H2INC
		1446
		1447	/* Please don't add or expand this bitfield structure below, this one will retire soon.! */
		1448	typedef struct _ATOM_FIRMWARE_CAPABILITY {
		1449	#if ATOM_BIG_ENDIAN
		1450	USHORT Reserved:3;
		1451	USHORT HyperMemory_Size:4;
		1452	USHORT HyperMemory_Support:1;
		1453	USHORT PPMode_Assigned:1;
		1454	USHORT WMI_SUPPORT:1;
		1455	USHORT GPUControlsBL:1;
		1456	USHORT EngineClockSS_Support:1;
		1457	USHORT MemoryClockSS_Support:1;
		1458	USHORT ExtendedDesktopSupport:1;
		1459	USHORT DualCRTC_Support:1;
		1460	USHORT FirmwarePosted:1;
		1461	#else
		1462	USHORT FirmwarePosted:1;
		1463	USHORT DualCRTC_Support:1;
		1464	USHORT ExtendedDesktopSupport:1;
		1465	USHORT MemoryClockSS_Support:1;
		1466	USHORT EngineClockSS_Support:1;
		1467	USHORT GPUControlsBL:1;
		1468	USHORT WMI_SUPPORT:1;
		1469	USHORT PPMode_Assigned:1;
		1470	USHORT HyperMemory_Support:1;
		1471	USHORT HyperMemory_Size:4;
		1472	USHORT Reserved:3;
		1473	#endif
		1474	} ATOM_FIRMWARE_CAPABILITY;
		1475
		1476	typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS {
		1477	ATOM_FIRMWARE_CAPABILITY sbfAccess;
		1478	USHORT susAccess;
		1479	} ATOM_FIRMWARE_CAPABILITY_ACCESS;
		1480
		1481	#else
		1482
		1483	typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS {
		1484	USHORT susAccess;
		1485	} ATOM_FIRMWARE_CAPABILITY_ACCESS;
		1486
		1487	#endif
		1488
		1489	typedef struct _ATOM_FIRMWARE_INFO {
		1490	ATOM_COMMON_TABLE_HEADER sHeader;
		1491	ULONG ulFirmwareRevision;
		1492	ULONG ulDefaultEngineClock; /* In 10Khz unit */
		1493	ULONG ulDefaultMemoryClock; /* In 10Khz unit */
		1494	ULONG ulDriverTargetEngineClock; /* In 10Khz unit */
		1495	ULONG ulDriverTargetMemoryClock; /* In 10Khz unit */
		1496	ULONG ulMaxEngineClockPLL_Output; /* In 10Khz unit */
		1497	ULONG ulMaxMemoryClockPLL_Output; /* In 10Khz unit */
		1498	ULONG ulMaxPixelClockPLL_Output; /* In 10Khz unit */
		1499	ULONG ulASICMaxEngineClock; /* In 10Khz unit */
		1500	ULONG ulASICMaxMemoryClock; /* In 10Khz unit */
		1501	UCHAR ucASICMaxTemperature;
		1502	UCHAR ucPadding[3]; /* Don't use them */
		1503	ULONG aulReservedForBIOS[3]; /* Don't use them */
		1504	USHORT usMinEngineClockPLL_Input; /* In 10Khz unit */
		1505	USHORT usMaxEngineClockPLL_Input; /* In 10Khz unit */
		1506	USHORT usMinEngineClockPLL_Output; /* In 10Khz unit */
		1507	USHORT usMinMemoryClockPLL_Input; /* In 10Khz unit */
		1508	USHORT usMaxMemoryClockPLL_Input; /* In 10Khz unit */
		1509	USHORT usMinMemoryClockPLL_Output; /* In 10Khz unit */
		1510	USHORT usMaxPixelClock; /* In 10Khz unit, Max. Pclk */
		1511	USHORT usMinPixelClockPLL_Input; /* In 10Khz unit */
		1512	USHORT usMaxPixelClockPLL_Input; /* In 10Khz unit */
		1513	USHORT usMinPixelClockPLL_Output; /* In 10Khz unit, the definitions above can't change!!! */
		1514	ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
		1515	USHORT usReferenceClock; /* In 10Khz unit */
		1516	USHORT usPM_RTS_Location; /* RTS PM4 starting location in ROM in 1Kb unit */
		1517	UCHAR ucPM_RTS_StreamSize; /* RTS PM4 packets in Kb unit */
		1518	UCHAR ucDesign_ID; /* Indicate what is the board design */
		1519	UCHAR ucMemoryModule_ID; /* Indicate what is the board design */
		1520	} ATOM_FIRMWARE_INFO;
		1521
		1522	typedef struct _ATOM_FIRMWARE_INFO_V1_2 {
		1523	ATOM_COMMON_TABLE_HEADER sHeader;
		1524	ULONG ulFirmwareRevision;
		1525	ULONG ulDefaultEngineClock; /* In 10Khz unit */
		1526	ULONG ulDefaultMemoryClock; /* In 10Khz unit */
		1527	ULONG ulDriverTargetEngineClock; /* In 10Khz unit */
		1528	ULONG ulDriverTargetMemoryClock; /* In 10Khz unit */
		1529	ULONG ulMaxEngineClockPLL_Output; /* In 10Khz unit */
		1530	ULONG ulMaxMemoryClockPLL_Output; /* In 10Khz unit */
		1531	ULONG ulMaxPixelClockPLL_Output; /* In 10Khz unit */
		1532	ULONG ulASICMaxEngineClock; /* In 10Khz unit */
		1533	ULONG ulASICMaxMemoryClock; /* In 10Khz unit */
		1534	UCHAR ucASICMaxTemperature;
		1535	UCHAR ucMinAllowedBL_Level;
		1536	UCHAR ucPadding[2]; /* Don't use them */
		1537	ULONG aulReservedForBIOS[2]; /* Don't use them */
		1538	ULONG ulMinPixelClockPLL_Output; /* In 10Khz unit */
		1539	USHORT usMinEngineClockPLL_Input; /* In 10Khz unit */
		1540	USHORT usMaxEngineClockPLL_Input; /* In 10Khz unit */
		1541	USHORT usMinEngineClockPLL_Output; /* In 10Khz unit */
		1542	USHORT usMinMemoryClockPLL_Input; /* In 10Khz unit */
		1543	USHORT usMaxMemoryClockPLL_Input; /* In 10Khz unit */
		1544	USHORT usMinMemoryClockPLL_Output; /* In 10Khz unit */
		1545	USHORT usMaxPixelClock; /* In 10Khz unit, Max. Pclk */
		1546	USHORT usMinPixelClockPLL_Input; /* In 10Khz unit */
		1547	USHORT usMaxPixelClockPLL_Input; /* In 10Khz unit */
		1548	USHORT usMinPixelClockPLL_Output; /* In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output */
		1549	ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
		1550	USHORT usReferenceClock; /* In 10Khz unit */
		1551	USHORT usPM_RTS_Location; /* RTS PM4 starting location in ROM in 1Kb unit */
		1552	UCHAR ucPM_RTS_StreamSize; /* RTS PM4 packets in Kb unit */
		1553	UCHAR ucDesign_ID; /* Indicate what is the board design */
		1554	UCHAR ucMemoryModule_ID; /* Indicate what is the board design */
		1555	} ATOM_FIRMWARE_INFO_V1_2;
		1556
		1557	typedef struct _ATOM_FIRMWARE_INFO_V1_3 {
		1558	ATOM_COMMON_TABLE_HEADER sHeader;
		1559	ULONG ulFirmwareRevision;
		1560	ULONG ulDefaultEngineClock; /* In 10Khz unit */
		1561	ULONG ulDefaultMemoryClock; /* In 10Khz unit */
		1562	ULONG ulDriverTargetEngineClock; /* In 10Khz unit */
		1563	ULONG ulDriverTargetMemoryClock; /* In 10Khz unit */
		1564	ULONG ulMaxEngineClockPLL_Output; /* In 10Khz unit */
		1565	ULONG ulMaxMemoryClockPLL_Output; /* In 10Khz unit */
		1566	ULONG ulMaxPixelClockPLL_Output; /* In 10Khz unit */
		1567	ULONG ulASICMaxEngineClock; /* In 10Khz unit */
		1568	ULONG ulASICMaxMemoryClock; /* In 10Khz unit */
		1569	UCHAR ucASICMaxTemperature;
		1570	UCHAR ucMinAllowedBL_Level;
		1571	UCHAR ucPadding[2]; /* Don't use them */
		1572	ULONG aulReservedForBIOS; /* Don't use them */
		1573	ULONG ul3DAccelerationEngineClock; /* In 10Khz unit */
		1574	ULONG ulMinPixelClockPLL_Output; /* In 10Khz unit */
		1575	USHORT usMinEngineClockPLL_Input; /* In 10Khz unit */
		1576	USHORT usMaxEngineClockPLL_Input; /* In 10Khz unit */
		1577	USHORT usMinEngineClockPLL_Output; /* In 10Khz unit */
		1578	USHORT usMinMemoryClockPLL_Input; /* In 10Khz unit */
		1579	USHORT usMaxMemoryClockPLL_Input; /* In 10Khz unit */
		1580	USHORT usMinMemoryClockPLL_Output; /* In 10Khz unit */
		1581	USHORT usMaxPixelClock; /* In 10Khz unit, Max. Pclk */
		1582	USHORT usMinPixelClockPLL_Input; /* In 10Khz unit */
		1583	USHORT usMaxPixelClockPLL_Input; /* In 10Khz unit */
		1584	USHORT usMinPixelClockPLL_Output; /* In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output */
		1585	ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
		1586	USHORT usReferenceClock; /* In 10Khz unit */
		1587	USHORT usPM_RTS_Location; /* RTS PM4 starting location in ROM in 1Kb unit */
		1588	UCHAR ucPM_RTS_StreamSize; /* RTS PM4 packets in Kb unit */
		1589	UCHAR ucDesign_ID; /* Indicate what is the board design */
		1590	UCHAR ucMemoryModule_ID; /* Indicate what is the board design */
		1591	} ATOM_FIRMWARE_INFO_V1_3;
		1592
		1593	typedef struct _ATOM_FIRMWARE_INFO_V1_4 {
		1594	ATOM_COMMON_TABLE_HEADER sHeader;
		1595	ULONG ulFirmwareRevision;
		1596	ULONG ulDefaultEngineClock; /* In 10Khz unit */
		1597	ULONG ulDefaultMemoryClock; /* In 10Khz unit */
		1598	ULONG ulDriverTargetEngineClock; /* In 10Khz unit */
		1599	ULONG ulDriverTargetMemoryClock; /* In 10Khz unit */
		1600	ULONG ulMaxEngineClockPLL_Output; /* In 10Khz unit */
		1601	ULONG ulMaxMemoryClockPLL_Output; /* In 10Khz unit */
		1602	ULONG ulMaxPixelClockPLL_Output; /* In 10Khz unit */
		1603	ULONG ulASICMaxEngineClock; /* In 10Khz unit */
		1604	ULONG ulASICMaxMemoryClock; /* In 10Khz unit */
		1605	UCHAR ucASICMaxTemperature;
		1606	UCHAR ucMinAllowedBL_Level;
		1607	USHORT usBootUpVDDCVoltage; /* In MV unit */
		1608	USHORT usLcdMinPixelClockPLL_Output; /* In MHz unit */
		1609	USHORT usLcdMaxPixelClockPLL_Output; /* In MHz unit */
		1610	ULONG ul3DAccelerationEngineClock; /* In 10Khz unit */
		1611	ULONG ulMinPixelClockPLL_Output; /* In 10Khz unit */
		1612	USHORT usMinEngineClockPLL_Input; /* In 10Khz unit */
		1613	USHORT usMaxEngineClockPLL_Input; /* In 10Khz unit */
		1614	USHORT usMinEngineClockPLL_Output; /* In 10Khz unit */
		1615	USHORT usMinMemoryClockPLL_Input; /* In 10Khz unit */
		1616	USHORT usMaxMemoryClockPLL_Input; /* In 10Khz unit */
		1617	USHORT usMinMemoryClockPLL_Output; /* In 10Khz unit */
		1618	USHORT usMaxPixelClock; /* In 10Khz unit, Max. Pclk */
		1619	USHORT usMinPixelClockPLL_Input; /* In 10Khz unit */
		1620	USHORT usMaxPixelClockPLL_Input; /* In 10Khz unit */
		1621	USHORT usMinPixelClockPLL_Output; /* In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output */
		1622	ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
		1623	USHORT usReferenceClock; /* In 10Khz unit */
		1624	USHORT usPM_RTS_Location; /* RTS PM4 starting location in ROM in 1Kb unit */
		1625	UCHAR ucPM_RTS_StreamSize; /* RTS PM4 packets in Kb unit */
		1626	UCHAR ucDesign_ID; /* Indicate what is the board design */
		1627	UCHAR ucMemoryModule_ID; /* Indicate what is the board design */
		1628	} ATOM_FIRMWARE_INFO_V1_4;
		1629
		1630	#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V1_4
		1631
		1632	/****************************************************************************/
		1633	/* Structures used in IntegratedSystemInfoTable */
		1634	/****************************************************************************/
		1635	#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2
		1636	#define IGP_CAP_FLAG_AC_CARD 0x4
		1637	#define IGP_CAP_FLAG_SDVO_CARD 0x8
		1638	#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10
		1639
		1640	typedef struct _ATOM_INTEGRATED_SYSTEM_INFO {
		1641	ATOM_COMMON_TABLE_HEADER sHeader;
		1642	ULONG ulBootUpEngineClock; /* in 10kHz unit */
		1643	ULONG ulBootUpMemoryClock; /* in 10kHz unit */
		1644	ULONG ulMaxSystemMemoryClock; /* in 10kHz unit */
		1645	ULONG ulMinSystemMemoryClock; /* in 10kHz unit */
		1646	UCHAR ucNumberOfCyclesInPeriodHi;
		1647	UCHAR ucLCDTimingSel; /* =0:not valid.!=0 sel this timing descriptor from LCD EDID. */
		1648	USHORT usReserved1;
		1649	USHORT usInterNBVoltageLow; /* An intermidiate PMW value to set the voltage */
		1650	USHORT usInterNBVoltageHigh; /* Another intermidiate PMW value to set the voltage */
		1651	ULONG ulReserved[2];
		1652
		1653	USHORT usFSBClock; /* In MHz unit */
		1654	USHORT usCapabilityFlag; /* Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable */
		1655	/* Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card */
		1656	/* Bit[4]==1: P/2 mode, ==0: P/1 mode */
		1657	USHORT usPCIENBCfgReg7; /* bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal */
		1658	USHORT usK8MemoryClock; /* in MHz unit */
		1659	USHORT usK8SyncStartDelay; /* in 0.01 us unit */
		1660	USHORT usK8DataReturnTime; /* in 0.01 us unit */
		1661	UCHAR ucMaxNBVoltage;
		1662	UCHAR ucMinNBVoltage;
		1663	UCHAR ucMemoryType; /* [7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved */
		1664	UCHAR ucNumberOfCyclesInPeriod; /* CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod */
		1665	UCHAR ucStartingPWM_HighTime; /* CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime */
		1666	UCHAR ucHTLinkWidth; /* 16 bit vs. 8 bit */
		1667	UCHAR ucMaxNBVoltageHigh;
		1668	UCHAR ucMinNBVoltageHigh;
		1669	} ATOM_INTEGRATED_SYSTEM_INFO;
		1670
		1671	/* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO
		1672	ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock
		1673	For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
		1674	ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
		1675	For AMD IGP,for now this can be 0
		1676	ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
		1677	For AMD IGP,for now this can be 0
		1678
		1679	usFSBClock: For Intel IGP,it's FSB Freq
		1680	For AMD IGP,it's HT Link Speed
		1681
		1682	usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200
		1683	usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation
		1684	usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation
		1685
		1686	VC:Voltage Control
		1687	ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
		1688	ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
		1689
		1690	ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value.
		1691	ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0
		1692
		1693	ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
		1694	ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
		1695
		1696	usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
		1697	usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
		1698	*/
		1699
		1700	/*
		1701	The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST;
		1702	Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need.
		1703	The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.
		1704
		1705	SW components can access the IGP system infor structure in the same way as before
		1706	*/
		1707
		1708	typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 {
		1709	ATOM_COMMON_TABLE_HEADER sHeader;
		1710	ULONG ulBootUpEngineClock; /* in 10kHz unit */
		1711	ULONG ulReserved1[2]; /* must be 0x0 for the reserved */
		1712	ULONG ulBootUpUMAClock; /* in 10kHz unit */
		1713	ULONG ulBootUpSidePortClock; /* in 10kHz unit */
		1714	ULONG ulMinSidePortClock; /* in 10kHz unit */
		1715	ULONG ulReserved2[6]; /* must be 0x0 for the reserved */
		1716	ULONG ulSystemConfig; /* see explanation below */
		1717	ULONG ulBootUpReqDisplayVector;
		1718	ULONG ulOtherDisplayMisc;
		1719	ULONG ulDDISlot1Config;
		1720	ULONG ulDDISlot2Config;
		1721	UCHAR ucMemoryType; /* [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved */
		1722	UCHAR ucUMAChannelNumber;
		1723	UCHAR ucDockingPinBit;
		1724	UCHAR ucDockingPinPolarity;
		1725	ULONG ulDockingPinCFGInfo;
		1726	ULONG ulCPUCapInfo;
		1727	USHORT usNumberOfCyclesInPeriod;
		1728	USHORT usMaxNBVoltage;
		1729	USHORT usMinNBVoltage;
		1730	USHORT usBootUpNBVoltage;
		1731	ULONG ulHTLinkFreq; /* in 10Khz */
		1732	USHORT usMinHTLinkWidth;
		1733	USHORT usMaxHTLinkWidth;
		1734	USHORT usUMASyncStartDelay;
		1735	USHORT usUMADataReturnTime;
		1736	USHORT usLinkStatusZeroTime;
		1737	USHORT usReserved;
		1738	ULONG ulHighVoltageHTLinkFreq; /* in 10Khz */
		1739	ULONG ulLowVoltageHTLinkFreq; /* in 10Khz */
		1740	USHORT usMaxUpStreamHTLinkWidth;
		1741	USHORT usMaxDownStreamHTLinkWidth;
		1742	USHORT usMinUpStreamHTLinkWidth;
		1743	USHORT usMinDownStreamHTLinkWidth;
		1744	ULONG ulReserved3[97]; /* must be 0x0 */
		1745	} ATOM_INTEGRATED_SYSTEM_INFO_V2;
		1746
		1747	/*
		1748	ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
		1749	ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
		1750	ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock
		1751
		1752	ulSystemConfig:
		1753	Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
		1754	Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state
		1755	=0: system boots up at driver control state. Power state depends on PowerPlay table.
		1756	Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
		1757	Bit[3]=1: Only one power state(Performance) will be supported.
		1758	=0: Multiple power states supported from PowerPlay table.
		1759	Bit[4]=1: CLMC is supported and enabled on current system.
		1760	=0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface.
		1761	Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement.
		1762	=0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied.
		1763	Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored.
		1764	=0: Voltage settings is determined by powerplay table.
		1765	Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue.
		1766	=0: Enable CLMC as regular mode, CDLD and CILR will be enabled.
		1767
		1768	ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions.
		1769
		1770	ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
		1771	[7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition;
		1772
		1773	ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design).
		1774	[3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
		1775	[7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
		1776	[15:8] - Lane configuration attribute;
		1777	[23:16]- Connector type, possible value:
		1778	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
		1779	CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
		1780	CONNECTOR_OBJECT_ID_HDMI_TYPE_A
		1781	CONNECTOR_OBJECT_ID_DISPLAYPORT
		1782	[31:24]- Reserved
		1783
		1784	ulDDISlot2Config: Same as Slot1.
		1785	ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC.
		1786	For IGP, Hypermemory is the only memory type showed in CCC.
		1787
		1788	ucUMAChannelNumber: how many channels for the UMA;
		1789
		1790	ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin
		1791	ucDockingPinBit: which bit in this register to read the pin status;
		1792	ucDockingPinPolarity:Polarity of the pin when docked;
		1793
		1794	ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, other bits reserved for now and must be 0x0
		1795
		1796	usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
		1797	usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode.
		1798	usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.
		1799	GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0
		1800	PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1
		1801	GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE
		1802	usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
		1803
		1804	ulHTLinkFreq: Bootup HT link Frequency in 10Khz.
		1805	usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth.
		1806	If CDLW enabled, both upstream and downstream width should be the same during bootup.
		1807	usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth.
		1808	If CDLW enabled, both upstream and downstream width should be the same during bootup.
		1809
		1810	usUMASyncStartDelay: Memory access latency, required for watermark calculation
		1811	usUMADataReturnTime: Memory access latency, required for watermark calculation
		1812	usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us
		1813	for Griffin or Greyhound. SBIOS needs to convert to actual time by:
		1814	if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us)
		1815	if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us)
		1816	if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us)
		1817	if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us)
		1818
		1819	ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0.
		1820	This must be less than or equal to ulHTLinkFreq(bootup frequency).
		1821	ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0.
		1822	This must be less than or equal to ulHighVoltageHTLinkFreq.
		1823
		1824	usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now.
		1825	usMaxDownStreamHTLinkWidth: same as above.
		1826	usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now.
		1827	usMinDownStreamHTLinkWidth: same as above.
		1828	*/
		1829
		1830	#define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001
		1831	#define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002
		1832	#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004
		1833	#define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008
		1834	#define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010
		1835	#define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020
		1836	#define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040
		1837	#define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080
		1838
		1839	#define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF
		1840
		1841	#define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F
		1842	#define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0
		1843	#define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01
		1844	#define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02
		1845	#define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04
		1846	#define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08
		1847
		1848	#define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00
		1849	#define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100
		1850	#define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01
		1851
		1852	#define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000
		1853
		1854	#define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000
		1855	#define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001
		1856	#define ATOM_TV_INT_ENCODER1_INDEX 0x00000002
		1857	#define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003
		1858	#define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004
		1859	#define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005
		1860	#define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006
		1861	#define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007
		1862	#define ATOM_CV_INT_ENCODER1_INDEX 0x00000008
		1863	#define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009
		1864	#define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A
		1865	#define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B
		1866	#define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C
		1867	#define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D
		1868
		1869	/* define ASIC internal encoder id ( bit vector ) */
		1870	#define ASIC_INT_DAC1_ENCODER_ID 0x00
		1871	#define ASIC_INT_TV_ENCODER_ID 0x02
		1872	#define ASIC_INT_DIG1_ENCODER_ID 0x03
		1873	#define ASIC_INT_DAC2_ENCODER_ID 0x04
		1874	#define ASIC_EXT_TV_ENCODER_ID 0x06
		1875	#define ASIC_INT_DVO_ENCODER_ID 0x07
		1876	#define ASIC_INT_DIG2_ENCODER_ID 0x09
		1877	#define ASIC_EXT_DIG_ENCODER_ID 0x05
		1878
		1879	/* define Encoder attribute */
		1880	#define ATOM_ANALOG_ENCODER 0
		1881	#define ATOM_DIGITAL_ENCODER 1
		1882
		1883	#define ATOM_DEVICE_CRT1_INDEX 0x00000000
		1884	#define ATOM_DEVICE_LCD1_INDEX 0x00000001
		1885	#define ATOM_DEVICE_TV1_INDEX 0x00000002
		1886	#define ATOM_DEVICE_DFP1_INDEX 0x00000003
		1887	#define ATOM_DEVICE_CRT2_INDEX 0x00000004
		1888	#define ATOM_DEVICE_LCD2_INDEX 0x00000005
		1889	#define ATOM_DEVICE_TV2_INDEX 0x00000006
		1890	#define ATOM_DEVICE_DFP2_INDEX 0x00000007
		1891	#define ATOM_DEVICE_CV_INDEX 0x00000008
		1892	#define ATOM_DEVICE_DFP3_INDEX 0x00000009
		1893	#define ATOM_DEVICE_DFP4_INDEX 0x0000000A
		1894	#define ATOM_DEVICE_DFP5_INDEX 0x0000000B
		1895	#define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C
		1896	#define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D
		1897	#define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E
		1898	#define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F
		1899	#define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1)
		1900	#define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO
		1901	#define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1)
		1902
		1903	#define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1)
		1904
		1905	#define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX)
		1906	#define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX)
		1907	#define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX)
		1908	#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX)
		1909	#define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX)
		1910	#define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX)
		1911	#define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX)
		1912	#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX)
		1913	#define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX)
		1914	#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX)
		1915	#define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX )
		1916	#define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX)
		1917
		1918	#define ATOM_DEVICE_CRT_SUPPORT \
		1919	(ATOM_DEVICE_CRT1_SUPPORT \| ATOM_DEVICE_CRT2_SUPPORT)
		1920	#define ATOM_DEVICE_DFP_SUPPORT \
		1921	(ATOM_DEVICE_DFP1_SUPPORT \| ATOM_DEVICE_DFP2_SUPPORT \| \
		1922	ATOM_DEVICE_DFP3_SUPPORT \| ATOM_DEVICE_DFP4_SUPPORT \| \
		1923	ATOM_DEVICE_DFP5_SUPPORT)
		1924	#define ATOM_DEVICE_TV_SUPPORT \
		1925	(ATOM_DEVICE_TV1_SUPPORT \| ATOM_DEVICE_TV2_SUPPORT)
		1926	#define ATOM_DEVICE_LCD_SUPPORT \
		1927	(ATOM_DEVICE_LCD1_SUPPORT \| ATOM_DEVICE_LCD2_SUPPORT)
		1928
		1929	#define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0
		1930	#define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004
		1931	#define ATOM_DEVICE_CONNECTOR_VGA 0x00000001
		1932	#define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002
		1933	#define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003
		1934	#define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004
		1935	#define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005
		1936	#define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006
		1937	#define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007
		1938	#define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008
		1939	#define ATOM_DEVICE_CONNECTOR_SCART 0x00000009
		1940	#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A
		1941	#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B
		1942	#define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E
		1943	#define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F
		1944
		1945	#define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F
		1946	#define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000
		1947	#define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000
		1948	#define ATOM_DEVICE_DAC_INFO_DACA 0x00000001
		1949	#define ATOM_DEVICE_DAC_INFO_DACB 0x00000002
		1950	#define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003
		1951
		1952	#define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000
		1953
		1954	#define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F
		1955	#define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000
		1956
		1957	#define ATOM_DEVICE_I2C_ID_MASK 0x00000070
		1958	#define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004
		1959	#define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001
		1960	#define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002
		1961	#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 /* For IGP RS600 */
		1962	#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 /* For IGP RS690 */
		1963
		1964	#define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080
		1965	#define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007
		1966	#define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000
		1967	#define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001
		1968
		1969	/* usDeviceSupport: */
		1970	/* Bits0 = 0 - no CRT1 support= 1- CRT1 is supported */
		1971	/* Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported */
		1972	/* Bit 2 = 0 - no TV1 support= 1- TV1 is supported */
		1973	/* Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported */
		1974	/* Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported */
		1975	/* Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported */
		1976	/* Bit 6 = 0 - no TV2 support= 1- TV2 is supported */
		1977	/* Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported */
		1978	/* Bit 8 = 0 - no CV support= 1- CV is supported */
		1979	/* Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported */
		1980	/* Byte1 (Supported Device Info) */
		1981	/* Bit 0 = = 0 - no CV support= 1- CV is supported */
		1982	/* */
		1983	/* */
		1984
		1985	/* ucI2C_ConfigID */
		1986	/* [7:0] - I2C LINE Associate ID */
		1987	/* = 0 - no I2C */
		1988	/* [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) */
		1989	/* = 0, [6:0]=SW assisted I2C ID */
		1990	/* [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use */
		1991	/* = 2, HW engine for Multimedia use */
		1992	/* = 3-7 Reserved for future I2C engines */
		1993	/* [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C */
		1994
		1995	typedef struct _ATOM_I2C_ID_CONFIG {
		1996	#if ATOM_BIG_ENDIAN
		1997	UCHAR bfHW_Capable:1;
		1998	UCHAR bfHW_EngineID:3;
		1999	UCHAR bfI2C_LineMux:4;
		2000	#else
		2001	UCHAR bfI2C_LineMux:4;
		2002	UCHAR bfHW_EngineID:3;
		2003	UCHAR bfHW_Capable:1;
		2004	#endif
		2005	} ATOM_I2C_ID_CONFIG;
		2006
		2007	typedef union _ATOM_I2C_ID_CONFIG_ACCESS {
		2008	ATOM_I2C_ID_CONFIG sbfAccess;
		2009	UCHAR ucAccess;
		2010	} ATOM_I2C_ID_CONFIG_ACCESS;
		2011
		2012	/****************************************************************************/
		2013	/* Structure used in GPIO_I2C_InfoTable */
		2014	/****************************************************************************/
		2015	typedef struct _ATOM_GPIO_I2C_ASSIGMENT {
		2016	USHORT usClkMaskRegisterIndex;
		2017	USHORT usClkEnRegisterIndex;
		2018	USHORT usClkY_RegisterIndex;
		2019	USHORT usClkA_RegisterIndex;
		2020	USHORT usDataMaskRegisterIndex;
		2021	USHORT usDataEnRegisterIndex;
		2022	USHORT usDataY_RegisterIndex;
		2023	USHORT usDataA_RegisterIndex;
		2024	ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
		2025	UCHAR ucClkMaskShift;
		2026	UCHAR ucClkEnShift;
		2027	UCHAR ucClkY_Shift;
		2028	UCHAR ucClkA_Shift;
		2029	UCHAR ucDataMaskShift;
		2030	UCHAR ucDataEnShift;
		2031	UCHAR ucDataY_Shift;
		2032	UCHAR ucDataA_Shift;
		2033	UCHAR ucReserved1;
		2034	UCHAR ucReserved2;
		2035	} ATOM_GPIO_I2C_ASSIGMENT;
		2036
		2037	typedef struct _ATOM_GPIO_I2C_INFO {
		2038	ATOM_COMMON_TABLE_HEADER sHeader;
		2039	ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE];
		2040	} ATOM_GPIO_I2C_INFO;
		2041
		2042	/****************************************************************************/
		2043	/* Common Structure used in other structures */
		2044	/****************************************************************************/
		2045
		2046	#ifndef _H2INC
		2047
		2048	/* Please don't add or expand this bitfield structure below, this one will retire soon.! */
		2049	typedef struct _ATOM_MODE_MISC_INFO {
		2050	#if ATOM_BIG_ENDIAN
		2051	USHORT Reserved:6;
		2052	USHORT RGB888:1;
		2053	USHORT DoubleClock:1;
		2054	USHORT Interlace:1;
		2055	USHORT CompositeSync:1;
		2056	USHORT V_ReplicationBy2:1;
		2057	USHORT H_ReplicationBy2:1;
		2058	USHORT VerticalCutOff:1;
		2059	USHORT VSyncPolarity:1; /* 0=Active High, 1=Active Low */
		2060	USHORT HSyncPolarity:1; /* 0=Active High, 1=Active Low */
		2061	USHORT HorizontalCutOff:1;
		2062	#else
		2063	USHORT HorizontalCutOff:1;
		2064	USHORT HSyncPolarity:1; /* 0=Active High, 1=Active Low */
		2065	USHORT VSyncPolarity:1; /* 0=Active High, 1=Active Low */
		2066	USHORT VerticalCutOff:1;
		2067	USHORT H_ReplicationBy2:1;
		2068	USHORT V_ReplicationBy2:1;
		2069	USHORT CompositeSync:1;
		2070	USHORT Interlace:1;
		2071	USHORT DoubleClock:1;
		2072	USHORT RGB888:1;
		2073	USHORT Reserved:6;
		2074	#endif
		2075	} ATOM_MODE_MISC_INFO;
		2076
		2077	typedef union _ATOM_MODE_MISC_INFO_ACCESS {
		2078	ATOM_MODE_MISC_INFO sbfAccess;
		2079	USHORT usAccess;
		2080	} ATOM_MODE_MISC_INFO_ACCESS;
		2081
		2082	#else
		2083
		2084	typedef union _ATOM_MODE_MISC_INFO_ACCESS {
		2085	USHORT usAccess;
		2086	} ATOM_MODE_MISC_INFO_ACCESS;
		2087
		2088	#endif
		2089
		2090	/* usModeMiscInfo- */
		2091	#define ATOM_H_CUTOFF 0x01
		2092	#define ATOM_HSYNC_POLARITY 0x02 /* 0=Active High, 1=Active Low */
		2093	#define ATOM_VSYNC_POLARITY 0x04 /* 0=Active High, 1=Active Low */
		2094	#define ATOM_V_CUTOFF 0x08
		2095	#define ATOM_H_REPLICATIONBY2 0x10
		2096	#define ATOM_V_REPLICATIONBY2 0x20
		2097	#define ATOM_COMPOSITESYNC 0x40
		2098	#define ATOM_INTERLACE 0x80
		2099	#define ATOM_DOUBLE_CLOCK_MODE 0x100
		2100	#define ATOM_RGB888_MODE 0x200
		2101
		2102	/* usRefreshRate- */
		2103	#define ATOM_REFRESH_43 43
		2104	#define ATOM_REFRESH_47 47
		2105	#define ATOM_REFRESH_56 56
		2106	#define ATOM_REFRESH_60 60
		2107	#define ATOM_REFRESH_65 65
		2108	#define ATOM_REFRESH_70 70
		2109	#define ATOM_REFRESH_72 72
		2110	#define ATOM_REFRESH_75 75
		2111	#define ATOM_REFRESH_85 85
		2112
		2113	/* ATOM_MODE_TIMING data are exactly the same as VESA timing data. */
		2114	/* Translation from EDID to ATOM_MODE_TIMING, use the following formula. */
		2115	/* */
		2116	/* VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK */
		2117	/* = EDID_HA + EDID_HBL */
		2118	/* VESA_HDISP = VESA_ACTIVE = EDID_HA */
		2119	/* VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH */
		2120	/* = EDID_HA + EDID_HSO */
		2121	/* VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW */
		2122	/* VESA_BORDER = EDID_BORDER */
		2123
		2124	/****************************************************************************/
		2125	/* Structure used in SetCRTC_UsingDTDTimingTable */
		2126	/****************************************************************************/
		2127	typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS {
		2128	USHORT usH_Size;
		2129	USHORT usH_Blanking_Time;
		2130	USHORT usV_Size;
		2131	USHORT usV_Blanking_Time;
		2132	USHORT usH_SyncOffset;
		2133	USHORT usH_SyncWidth;
		2134	USHORT usV_SyncOffset;
		2135	USHORT usV_SyncWidth;
		2136	ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
		2137	UCHAR ucH_Border; /* From DFP EDID */
		2138	UCHAR ucV_Border;
		2139	UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */
		2140	UCHAR ucPadding[3];
		2141	} SET_CRTC_USING_DTD_TIMING_PARAMETERS;
		2142
		2143	/****************************************************************************/
		2144	/* Structure used in SetCRTC_TimingTable */
		2145	/****************************************************************************/
		2146	typedef struct _SET_CRTC_TIMING_PARAMETERS {
		2147	USHORT usH_Total; /* horizontal total */
		2148	USHORT usH_Disp; /* horizontal display */
		2149	USHORT usH_SyncStart; /* horozontal Sync start */
		2150	USHORT usH_SyncWidth; /* horizontal Sync width */
		2151	USHORT usV_Total; /* vertical total */
		2152	USHORT usV_Disp; /* vertical display */
		2153	USHORT usV_SyncStart; /* vertical Sync start */
		2154	USHORT usV_SyncWidth; /* vertical Sync width */
		2155	ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
		2156	UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */
		2157	UCHAR ucOverscanRight; /* right */
		2158	UCHAR ucOverscanLeft; /* left */
		2159	UCHAR ucOverscanBottom; /* bottom */
		2160	UCHAR ucOverscanTop; /* top */
		2161	UCHAR ucReserved;
		2162	} SET_CRTC_TIMING_PARAMETERS;
		2163	#define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS
		2164
		2165	/****************************************************************************/
		2166	/* Structure used in StandardVESA_TimingTable */
		2167	/* AnalogTV_InfoTable */
		2168	/* ComponentVideoInfoTable */
		2169	/****************************************************************************/
		2170	typedef struct _ATOM_MODE_TIMING {
		2171	USHORT usCRTC_H_Total;
		2172	USHORT usCRTC_H_Disp;
		2173	USHORT usCRTC_H_SyncStart;
		2174	USHORT usCRTC_H_SyncWidth;
		2175	USHORT usCRTC_V_Total;
		2176	USHORT usCRTC_V_Disp;
		2177	USHORT usCRTC_V_SyncStart;
		2178	USHORT usCRTC_V_SyncWidth;
		2179	USHORT usPixelClock; /* in 10Khz unit */
		2180	ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
		2181	USHORT usCRTC_OverscanRight;
		2182	USHORT usCRTC_OverscanLeft;
		2183	USHORT usCRTC_OverscanBottom;
		2184	USHORT usCRTC_OverscanTop;
		2185	USHORT usReserve;
		2186	UCHAR ucInternalModeNumber;
		2187	UCHAR ucRefreshRate;
		2188	} ATOM_MODE_TIMING;
		2189
		2190	typedef struct _ATOM_DTD_FORMAT {
		2191	USHORT usPixClk;
		2192	USHORT usHActive;
		2193	USHORT usHBlanking_Time;
		2194	USHORT usVActive;
		2195	USHORT usVBlanking_Time;
		2196	USHORT usHSyncOffset;
		2197	USHORT usHSyncWidth;
		2198	USHORT usVSyncOffset;
		2199	USHORT usVSyncWidth;
		2200	USHORT usImageHSize;
		2201	USHORT usImageVSize;
		2202	UCHAR ucHBorder;
		2203	UCHAR ucVBorder;
		2204	ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
		2205	UCHAR ucInternalModeNumber;
		2206	UCHAR ucRefreshRate;
		2207	} ATOM_DTD_FORMAT;
		2208
		2209	/****************************************************************************/
		2210	/* Structure used in LVDS_InfoTable */
		2211	/* * Need a document to describe this table */
		2212	/****************************************************************************/
		2213	#define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
		2214	#define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
		2215	#define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
		2216	#define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
		2217
		2218	/* Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. */
		2219	/* Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL */
		2220	#define LCDPANEL_CAP_READ_EDID 0x1
		2221
		2222	/* ucTableFormatRevision=1 */
		2223	/* ucTableContentRevision=1 */
		2224	typedef struct _ATOM_LVDS_INFO {
		2225	ATOM_COMMON_TABLE_HEADER sHeader;
		2226	ATOM_DTD_FORMAT sLCDTiming;
		2227	USHORT usModePatchTableOffset;
		2228	USHORT usSupportedRefreshRate; /* Refer to panel info table in ATOMBIOS extension Spec. */
		2229	USHORT usOffDelayInMs;
		2230	UCHAR ucPowerSequenceDigOntoDEin10Ms;
		2231	UCHAR ucPowerSequenceDEtoBLOnin10Ms;
		2232	UCHAR ucLVDS_Misc; /* Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} */
		2233	/* Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} */
		2234	/* Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} */
		2235	/* Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} */
		2236	UCHAR ucPanelDefaultRefreshRate;
		2237	UCHAR ucPanelIdentification;
		2238	UCHAR ucSS_Id;
		2239	} ATOM_LVDS_INFO;
		2240
		2241	/* ucTableFormatRevision=1 */
		2242	/* ucTableContentRevision=2 */
		2243	typedef struct _ATOM_LVDS_INFO_V12 {
		2244	ATOM_COMMON_TABLE_HEADER sHeader;
		2245	ATOM_DTD_FORMAT sLCDTiming;
		2246	USHORT usExtInfoTableOffset;
		2247	USHORT usSupportedRefreshRate; /* Refer to panel info table in ATOMBIOS extension Spec. */
		2248	USHORT usOffDelayInMs;
		2249	UCHAR ucPowerSequenceDigOntoDEin10Ms;
		2250	UCHAR ucPowerSequenceDEtoBLOnin10Ms;
		2251	UCHAR ucLVDS_Misc; /* Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} */
		2252	/* Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} */
		2253	/* Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} */
		2254	/* Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} */
		2255	UCHAR ucPanelDefaultRefreshRate;
		2256	UCHAR ucPanelIdentification;
		2257	UCHAR ucSS_Id;
		2258	USHORT usLCDVenderID;
		2259	USHORT usLCDProductID;
		2260	UCHAR ucLCDPanel_SpecialHandlingCap;
		2261	UCHAR ucPanelInfoSize; /* start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable */
		2262	UCHAR ucReserved[2];
		2263	} ATOM_LVDS_INFO_V12;
		2264
		2265	#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12
		2266
		2267	typedef struct _ATOM_PATCH_RECORD_MODE {
		2268	UCHAR ucRecordType;
		2269	USHORT usHDisp;
		2270	USHORT usVDisp;
		2271	} ATOM_PATCH_RECORD_MODE;
		2272
		2273	typedef struct _ATOM_LCD_RTS_RECORD {
		2274	UCHAR ucRecordType;
		2275	UCHAR ucRTSValue;
		2276	} ATOM_LCD_RTS_RECORD;
		2277
		2278	/* !! If the record below exits, it shoud always be the first record for easy use in command table!!! */
		2279	typedef struct _ATOM_LCD_MODE_CONTROL_CAP {
		2280	UCHAR ucRecordType;
		2281	USHORT usLCDCap;
		2282	} ATOM_LCD_MODE_CONTROL_CAP;
		2283
		2284	#define LCD_MODE_CAP_BL_OFF 1
		2285	#define LCD_MODE_CAP_CRTC_OFF 2
		2286	#define LCD_MODE_CAP_PANEL_OFF 4
		2287
		2288	typedef struct _ATOM_FAKE_EDID_PATCH_RECORD {
		2289	UCHAR ucRecordType;
		2290	UCHAR ucFakeEDIDLength;
		2291	UCHAR ucFakeEDIDString[1]; /* This actually has ucFakeEdidLength elements. */
		2292	} ATOM_FAKE_EDID_PATCH_RECORD;
		2293
		2294	typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD {
		2295	UCHAR ucRecordType;
		2296	USHORT usHSize;
		2297	USHORT usVSize;
		2298	} ATOM_PANEL_RESOLUTION_PATCH_RECORD;
		2299
		2300	#define LCD_MODE_PATCH_RECORD_MODE_TYPE 1
		2301	#define LCD_RTS_RECORD_TYPE 2
		2302	#define LCD_CAP_RECORD_TYPE 3
		2303	#define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4
		2304	#define LCD_PANEL_RESOLUTION_RECORD_TYPE 5
		2305	#define ATOM_RECORD_END_TYPE 0xFF
		2306
		2307	/**************************Spread Spectrum Info Table Definitions ********************/
		2308
		2309	/* ucTableFormatRevision=1 */
		2310	/* ucTableContentRevision=2 */
		2311	typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT {
		2312	USHORT usSpreadSpectrumPercentage;
		2313	UCHAR ucSpreadSpectrumType; /* Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD */
		2314	UCHAR ucSS_Step;
		2315	UCHAR ucSS_Delay;
		2316	UCHAR ucSS_Id;
		2317	UCHAR ucRecommandedRef_Div;
		2318	UCHAR ucSS_Range; /* it was reserved for V11 */
		2319	} ATOM_SPREAD_SPECTRUM_ASSIGNMENT;
		2320
		2321	#define ATOM_MAX_SS_ENTRY 16
		2322	#define ATOM_DP_SS_ID1 0x0f1 /* SS modulation freq=30k */
		2323	#define ATOM_DP_SS_ID2 0x0f2 /* SS modulation freq=33k */
		2324
		2325	#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000
		2326	#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000
		2327	#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001
		2328	#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001
		2329	#define ATOM_INTERNAL_SS_MASK 0x00000000
		2330	#define ATOM_EXTERNAL_SS_MASK 0x00000002
		2331	#define EXEC_SS_STEP_SIZE_SHIFT 2
		2332	#define EXEC_SS_DELAY_SHIFT 4
		2333	#define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4
		2334
		2335	typedef struct _ATOM_SPREAD_SPECTRUM_INFO {
		2336	ATOM_COMMON_TABLE_HEADER sHeader;
		2337	ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY];
		2338	} ATOM_SPREAD_SPECTRUM_INFO;
		2339
		2340	/****************************************************************************/
		2341	/* Structure used in AnalogTV_InfoTable (Top level) */
		2342	/****************************************************************************/
		2343	/* ucTVBootUpDefaultStd definiton: */
		2344
		2345	/* ATOM_TV_NTSC 1 */
		2346	/* ATOM_TV_NTSCJ 2 */
		2347	/* ATOM_TV_PAL 3 */
		2348	/* ATOM_TV_PALM 4 */
		2349	/* ATOM_TV_PALCN 5 */
		2350	/* ATOM_TV_PALN 6 */
		2351	/* ATOM_TV_PAL60 7 */
		2352	/* ATOM_TV_SECAM 8 */
		2353
		2354	/* ucTVSuppportedStd definition: */
		2355	#define NTSC_SUPPORT 0x1
		2356	#define NTSCJ_SUPPORT 0x2
		2357
		2358	#define PAL_SUPPORT 0x4
		2359	#define PALM_SUPPORT 0x8
		2360	#define PALCN_SUPPORT 0x10
		2361	#define PALN_SUPPORT 0x20
		2362	#define PAL60_SUPPORT 0x40
		2363	#define SECAM_SUPPORT 0x80
		2364
		2365	#define MAX_SUPPORTED_TV_TIMING 2
		2366
		2367	typedef struct _ATOM_ANALOG_TV_INFO {
		2368	ATOM_COMMON_TABLE_HEADER sHeader;
		2369	UCHAR ucTV_SupportedStandard;
		2370	UCHAR ucTV_BootUpDefaultStandard;
		2371	UCHAR ucExt_TV_ASIC_ID;
		2372	UCHAR ucExt_TV_ASIC_SlaveAddr;
		2373	/ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING]; /
		2374	ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING];
		2375	} ATOM_ANALOG_TV_INFO;
		2376
1179	serge	2377	#define MAX_SUPPORTED_TV_TIMING_V1_2 3
		2378
		2379	typedef struct _ATOM_ANALOG_TV_INFO_V1_2 {
		2380	ATOM_COMMON_TABLE_HEADER sHeader;
		2381	UCHAR ucTV_SupportedStandard;
		2382	UCHAR ucTV_BootUpDefaultStandard;
		2383	UCHAR ucExt_TV_ASIC_ID;
		2384	UCHAR ucExt_TV_ASIC_SlaveAddr;
		2385	ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];
		2386	} ATOM_ANALOG_TV_INFO_V1_2;
		2387
1117	serge	2388	/**************************************************************************/
		2389	/* VRAM usage and their defintions */
		2390
		2391	/* One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. */
		2392	/* Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. */
		2393	/* All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! */
		2394	/* To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR */
		2395	/* To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX */
		2396
		2397	#ifndef VESA_MEMORY_IN_64K_BLOCK
		2398	#define VESA_MEMORY_IN_64K_BLOCK 0x100 /* 25664K=16Mb (Max. VESA memory is 16Mb!) /
		2399	#endif
		2400
		2401	#define ATOM_EDID_RAW_DATASIZE 256 /* In Bytes */
		2402	#define ATOM_HWICON_SURFACE_SIZE 4096 /* In Bytes */
		2403	#define ATOM_HWICON_INFOTABLE_SIZE 32
		2404	#define MAX_DTD_MODE_IN_VRAM 6
		2405	#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM28) / 28= (SIZEOF ATOM_DTD_FORMAT) */
		2406	#define ATOM_STD_MODE_SUPPORT_TBL_SIZE (328) / 32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) */
		2407	#define DFP_ENCODER_TYPE_OFFSET 0x80
		2408	#define DP_ENCODER_LANE_NUM_OFFSET 0x84
		2409	#define DP_ENCODER_LINK_RATE_OFFSET 0x88
		2410
		2411	#define ATOM_HWICON1_SURFACE_ADDR 0
		2412	#define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
		2413	#define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
		2414	#define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE)
		2415	#define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
		2416	#define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
		2417
		2418	#define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
		2419	#define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
		2420	#define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
		2421
		2422	#define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
		2423
		2424	#define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
		2425	#define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
		2426	#define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
		2427
		2428	#define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
		2429	#define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
		2430	#define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
		2431
		2432	#define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
		2433	#define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
		2434	#define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
		2435
		2436	#define ATOM_TV2_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
		2437	#define ATOM_TV2_DTD_MODE_TBL_ADDR (ATOM_TV2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
		2438	#define ATOM_TV2_STD_MODE_TBL_ADDR (ATOM_TV2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
		2439
		2440	#define ATOM_DFP2_EDID_ADDR (ATOM_TV2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
		2441	#define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
		2442	#define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
		2443
		2444	#define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
		2445	#define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
		2446	#define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
		2447
		2448	#define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
		2449	#define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
		2450	#define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
		2451
		2452	#define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
		2453	#define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
		2454	#define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
		2455
		2456	#define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
		2457	#define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
		2458	#define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
		2459
		2460	#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR+ATOM_STD_MODE_SUPPORT_TBL_SIZE)
		2461
		2462	#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 256)
		2463	#define ATOM_STACK_STORAGE_END (ATOM_STACK_STORAGE_START + 512)
		2464
		2465	/* The size below is in Kb! */
		2466	#define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC)
		2467
		2468	#define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L
		2469	#define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30
		2470	#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1
		2471	#define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0
		2472
		2473	/***********************************************************************************/
		2474	/* Structure used in VRAM_UsageByFirmwareTable */
		2475	/* Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm */
		2476	/* at running time. */
		2477	/* note2: From RV770, the memory is more than 32bit addressable, so we will change */
		2478	/* ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains */
		2479	/* exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware */
		2480	/* (in offset to start of memory address) is KB aligned instead of byte aligend. */
		2481	/***********************************************************************************/
		2482	#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1
		2483
		2484	typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO {
		2485	ULONG ulStartAddrUsedByFirmware;
		2486	USHORT usFirmwareUseInKb;
		2487	USHORT usReserved;
		2488	} ATOM_FIRMWARE_VRAM_RESERVE_INFO;
		2489
		2490	typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE {
		2491	ATOM_COMMON_TABLE_HEADER sHeader;
		2492	ATOM_FIRMWARE_VRAM_RESERVE_INFO
		2493	asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
		2494	} ATOM_VRAM_USAGE_BY_FIRMWARE;
		2495
		2496	/****************************************************************************/
		2497	/* Structure used in GPIO_Pin_LUTTable */
		2498	/****************************************************************************/
		2499	typedef struct _ATOM_GPIO_PIN_ASSIGNMENT {
		2500	USHORT usGpioPin_AIndex;
		2501	UCHAR ucGpioPinBitShift;
		2502	UCHAR ucGPIO_ID;
		2503	} ATOM_GPIO_PIN_ASSIGNMENT;
		2504
		2505	typedef struct _ATOM_GPIO_PIN_LUT {
		2506	ATOM_COMMON_TABLE_HEADER sHeader;
		2507	ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1];
		2508	} ATOM_GPIO_PIN_LUT;
		2509
		2510	/****************************************************************************/
		2511	/* Structure used in ComponentVideoInfoTable */
		2512	/****************************************************************************/
		2513	#define GPIO_PIN_ACTIVE_HIGH 0x1
		2514
		2515	#define MAX_SUPPORTED_CV_STANDARDS 5
		2516
		2517	/* definitions for ATOM_D_INFO.ucSettings */
		2518	#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F /* [4:0] */
		2519	#define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 /* [6:5] = must be zeroed out */
		2520	#define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 /* [7] */
		2521
		2522	typedef struct _ATOM_GPIO_INFO {
		2523	USHORT usAOffset;
		2524	UCHAR ucSettings;
		2525	UCHAR ucReserved;
		2526	} ATOM_GPIO_INFO;
		2527
		2528	/* definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) */
		2529	#define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2
		2530
		2531	/* definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i */
		2532	#define ATOM_GPIO_DEFAULT_MODE_EN 0x80 /* [7]; */
		2533	#define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F /* [6:0] */
		2534
		2535	/* definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode */
		2536	/* Line 3 out put 5V. */
		2537	#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 /* represent gpio 3 state for 16:9 */
		2538	#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 /* represent gpio 4 state for 16:9 */
		2539	#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0
		2540
		2541	/* Line 3 out put 2.2V */
		2542	#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 /* represent gpio 3 state for 4:3 Letter box */
		2543	#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 /* represent gpio 4 state for 4:3 Letter box */
		2544	#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2
		2545
		2546	/* Line 3 out put 0V */
		2547	#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 /* represent gpio 3 state for 4:3 */
		2548	#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 /* represent gpio 4 state for 4:3 */
		2549	#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4
		2550
		2551	#define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F /* bit [5:0] */
		2552
		2553	#define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 /* bit 7 */
		2554
		2555	/* GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. */
		2556	#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 /* bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. */
		2557	#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 /* bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. */
		2558
		2559	typedef struct _ATOM_COMPONENT_VIDEO_INFO {
		2560	ATOM_COMMON_TABLE_HEADER sHeader;
		2561	USHORT usMask_PinRegisterIndex;
		2562	USHORT usEN_PinRegisterIndex;
		2563	USHORT usY_PinRegisterIndex;
		2564	USHORT usA_PinRegisterIndex;
		2565	UCHAR ucBitShift;
		2566	UCHAR ucPinActiveState; /* ucPinActiveState: Bit0=1 active high, =0 active low */
		2567	ATOM_DTD_FORMAT sReserved; /* must be zeroed out */
		2568	UCHAR ucMiscInfo;
		2569	UCHAR uc480i;
		2570	UCHAR uc480p;
		2571	UCHAR uc720p;
		2572	UCHAR uc1080i;
		2573	UCHAR ucLetterBoxMode;
		2574	UCHAR ucReserved[3];
		2575	UCHAR ucNumOfWbGpioBlocks; /* For Component video D-Connector support. If zere, NTSC type connector */
		2576	ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
		2577	ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
		2578	} ATOM_COMPONENT_VIDEO_INFO;
		2579
		2580	/* ucTableFormatRevision=2 */
		2581	/* ucTableContentRevision=1 */
		2582	typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 {
		2583	ATOM_COMMON_TABLE_HEADER sHeader;
		2584	UCHAR ucMiscInfo;
		2585	UCHAR uc480i;
		2586	UCHAR uc480p;
		2587	UCHAR uc720p;
		2588	UCHAR uc1080i;
		2589	UCHAR ucReserved;
		2590	UCHAR ucLetterBoxMode;
		2591	UCHAR ucNumOfWbGpioBlocks; /* For Component video D-Connector support. If zere, NTSC type connector */
		2592	ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
		2593	ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
		2594	} ATOM_COMPONENT_VIDEO_INFO_V21;
		2595
		2596	#define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21
		2597
		2598	/****************************************************************************/
		2599	/* Structure used in object_InfoTable */
		2600	/****************************************************************************/
		2601	typedef struct _ATOM_OBJECT_HEADER {
		2602	ATOM_COMMON_TABLE_HEADER sHeader;
		2603	USHORT usDeviceSupport;
		2604	USHORT usConnectorObjectTableOffset;
		2605	USHORT usRouterObjectTableOffset;
		2606	USHORT usEncoderObjectTableOffset;
		2607	USHORT usProtectionObjectTableOffset; /* only available when Protection block is independent. */
		2608	USHORT usDisplayPathTableOffset;
		2609	} ATOM_OBJECT_HEADER;
		2610
		2611	typedef struct _ATOM_DISPLAY_OBJECT_PATH {
		2612	USHORT usDeviceTag; /* supported device */
		2613	USHORT usSize; /* the size of ATOM_DISPLAY_OBJECT_PATH */
		2614	USHORT usConnObjectId; /* Connector Object ID */
		2615	USHORT usGPUObjectId; /* GPU ID */
		2616	USHORT usGraphicObjIds[1]; /* 1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. */
		2617	} ATOM_DISPLAY_OBJECT_PATH;
		2618
		2619	typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE {
		2620	UCHAR ucNumOfDispPath;
		2621	UCHAR ucVersion;
		2622	UCHAR ucPadding[2];
		2623	ATOM_DISPLAY_OBJECT_PATH asDispPath[1];
		2624	} ATOM_DISPLAY_OBJECT_PATH_TABLE;
		2625
		2626	typedef struct _ATOM_OBJECT /* each object has this structure */
		2627	{
		2628	USHORT usObjectID;
		2629	USHORT usSrcDstTableOffset;
		2630	USHORT usRecordOffset; /* this pointing to a bunch of records defined below */
		2631	USHORT usReserved;
		2632	} ATOM_OBJECT;
		2633
		2634	typedef struct _ATOM_OBJECT_TABLE /* Above 4 object table offset pointing to a bunch of objects all have this structure */
		2635	{
		2636	UCHAR ucNumberOfObjects;
		2637	UCHAR ucPadding[3];
		2638	ATOM_OBJECT asObjects[1];
		2639	} ATOM_OBJECT_TABLE;
		2640
		2641	typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT /* usSrcDstTableOffset pointing to this structure */
		2642	{
		2643	UCHAR ucNumberOfSrc;
		2644	USHORT usSrcObjectID[1];
		2645	UCHAR ucNumberOfDst;
		2646	USHORT usDstObjectID[1];
		2647	} ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT;
		2648
		2649	/* Related definitions, all records are differnt but they have a commond header */
		2650	typedef struct _ATOM_COMMON_RECORD_HEADER {
		2651	UCHAR ucRecordType; /* An emun to indicate the record type */
		2652	UCHAR ucRecordSize; /* The size of the whole record in byte */
		2653	} ATOM_COMMON_RECORD_HEADER;
		2654
		2655	#define ATOM_I2C_RECORD_TYPE 1
		2656	#define ATOM_HPD_INT_RECORD_TYPE 2
		2657	#define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3
		2658	#define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4
		2659	#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 /* Obsolete, switch to use GPIO_CNTL_RECORD_TYPE */
		2660	#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 /* Obsolete, switch to use GPIO_CNTL_RECORD_TYPE */
		2661	#define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7
		2662	#define ATOM_JTAG_RECORD_TYPE 8 /* Obsolete, switch to use GPIO_CNTL_RECORD_TYPE */
		2663	#define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9
		2664	#define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10
		2665	#define ATOM_CONNECTOR_CF_RECORD_TYPE 11
		2666	#define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12
		2667	#define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13
		2668	#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14
		2669	#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15
		2670
		2671	/* Must be updated when new record type is added,equal to that record definition! */
		2672	#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_CF_RECORD_TYPE
		2673
		2674	typedef struct _ATOM_I2C_RECORD {
		2675	ATOM_COMMON_RECORD_HEADER sheader;
		2676	ATOM_I2C_ID_CONFIG sucI2cId;
		2677	UCHAR ucI2CAddr; /* The slave address, it's 0 when the record is attached to connector for DDC */
		2678	} ATOM_I2C_RECORD;
		2679
		2680	typedef struct _ATOM_HPD_INT_RECORD {
		2681	ATOM_COMMON_RECORD_HEADER sheader;
		2682	UCHAR ucHPDIntGPIOID; /* Corresponding block in GPIO_PIN_INFO table gives the pin info */
		2683	UCHAR ucPluggged_PinState;
		2684	} ATOM_HPD_INT_RECORD;
		2685
		2686	typedef struct _ATOM_OUTPUT_PROTECTION_RECORD {
		2687	ATOM_COMMON_RECORD_HEADER sheader;
		2688	UCHAR ucProtectionFlag;
		2689	UCHAR ucReserved;
		2690	} ATOM_OUTPUT_PROTECTION_RECORD;
		2691
		2692	typedef struct _ATOM_CONNECTOR_DEVICE_TAG {
		2693	ULONG ulACPIDeviceEnum; /* Reserved for now */
		2694	USHORT usDeviceID; /* This Id is same as "ATOM_DEVICE_XXX_SUPPORT" */
		2695	USHORT usPadding;
		2696	} ATOM_CONNECTOR_DEVICE_TAG;
		2697
		2698	typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD {
		2699	ATOM_COMMON_RECORD_HEADER sheader;
		2700	UCHAR ucNumberOfDevice;
		2701	UCHAR ucReserved;
		2702	ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; /* This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation */
		2703	} ATOM_CONNECTOR_DEVICE_TAG_RECORD;
		2704
		2705	typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD {
		2706	ATOM_COMMON_RECORD_HEADER sheader;
		2707	UCHAR ucConfigGPIOID;
		2708	UCHAR ucConfigGPIOState; /* Set to 1 when it's active high to enable external flow in */
		2709	UCHAR ucFlowinGPIPID;
		2710	UCHAR ucExtInGPIPID;
		2711	} ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD;
		2712
		2713	typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD {
		2714	ATOM_COMMON_RECORD_HEADER sheader;
		2715	UCHAR ucCTL1GPIO_ID;
		2716	UCHAR ucCTL1GPIOState; /* Set to 1 when it's active high */
		2717	UCHAR ucCTL2GPIO_ID;
		2718	UCHAR ucCTL2GPIOState; /* Set to 1 when it's active high */
		2719	UCHAR ucCTL3GPIO_ID;
		2720	UCHAR ucCTL3GPIOState; /* Set to 1 when it's active high */
		2721	UCHAR ucCTLFPGA_IN_ID;
		2722	UCHAR ucPadding[3];
		2723	} ATOM_ENCODER_FPGA_CONTROL_RECORD;
		2724
		2725	typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD {
		2726	ATOM_COMMON_RECORD_HEADER sheader;
		2727	UCHAR ucGPIOID; /* Corresponding block in GPIO_PIN_INFO table gives the pin info */
		2728	UCHAR ucTVActiveState; /* Indicating when the pin==0 or 1 when TV is connected */
		2729	} ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD;
		2730
		2731	typedef struct _ATOM_JTAG_RECORD {
		2732	ATOM_COMMON_RECORD_HEADER sheader;
		2733	UCHAR ucTMSGPIO_ID;
		2734	UCHAR ucTMSGPIOState; /* Set to 1 when it's active high */
		2735	UCHAR ucTCKGPIO_ID;
		2736	UCHAR ucTCKGPIOState; /* Set to 1 when it's active high */
		2737	UCHAR ucTDOGPIO_ID;
		2738	UCHAR ucTDOGPIOState; /* Set to 1 when it's active high */
		2739	UCHAR ucTDIGPIO_ID;
		2740	UCHAR ucTDIGPIOState; /* Set to 1 when it's active high */
		2741	UCHAR ucPadding[2];
		2742	} ATOM_JTAG_RECORD;
		2743
		2744	/* The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually */
		2745	typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR {
		2746	UCHAR ucGPIOID; /* GPIO_ID, find the corresponding ID in GPIO_LUT table */
		2747	UCHAR ucGPIO_PinState; /* Pin state showing how to set-up the pin */
		2748	} ATOM_GPIO_PIN_CONTROL_PAIR;
		2749
		2750	typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD {
		2751	ATOM_COMMON_RECORD_HEADER sheader;
		2752	UCHAR ucFlags; /* Future expnadibility */
		2753	UCHAR ucNumberOfPins; /* Number of GPIO pins used to control the object */
		2754	ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; /* the real gpio pin pair determined by number of pins ucNumberOfPins */
		2755	} ATOM_OBJECT_GPIO_CNTL_RECORD;
		2756
		2757	/* Definitions for GPIO pin state */
		2758	#define GPIO_PIN_TYPE_INPUT 0x00
		2759	#define GPIO_PIN_TYPE_OUTPUT 0x10
		2760	#define GPIO_PIN_TYPE_HW_CONTROL 0x20
		2761
		2762	/* For GPIO_PIN_TYPE_OUTPUT the following is defined */
		2763	#define GPIO_PIN_OUTPUT_STATE_MASK 0x01
		2764	#define GPIO_PIN_OUTPUT_STATE_SHIFT 0
		2765	#define GPIO_PIN_STATE_ACTIVE_LOW 0x0
		2766	#define GPIO_PIN_STATE_ACTIVE_HIGH 0x1
		2767
		2768	typedef struct _ATOM_ENCODER_DVO_CF_RECORD {
		2769	ATOM_COMMON_RECORD_HEADER sheader;
		2770	ULONG ulStrengthControl; /* DVOA strength control for CF */
		2771	UCHAR ucPadding[2];
		2772	} ATOM_ENCODER_DVO_CF_RECORD;
		2773
		2774	/* value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle */
		2775	#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1
		2776	#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2
		2777
		2778	typedef struct _ATOM_CONNECTOR_CF_RECORD {
		2779	ATOM_COMMON_RECORD_HEADER sheader;
		2780	USHORT usMaxPixClk;
		2781	UCHAR ucFlowCntlGpioId;
		2782	UCHAR ucSwapCntlGpioId;
		2783	UCHAR ucConnectedDvoBundle;
		2784	UCHAR ucPadding;
		2785	} ATOM_CONNECTOR_CF_RECORD;
		2786
		2787	typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD {
		2788	ATOM_COMMON_RECORD_HEADER sheader;
		2789	ATOM_DTD_FORMAT asTiming;
		2790	} ATOM_CONNECTOR_HARDCODE_DTD_RECORD;
		2791
		2792	typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD {
		2793	ATOM_COMMON_RECORD_HEADER sheader; /* ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE */
		2794	UCHAR ucSubConnectorType; /* CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D\|X_ID_DUAL_LINK_DVI_D\|HDMI_TYPE_A */
		2795	UCHAR ucReserved;
		2796	} ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD;
		2797
		2798	typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD {
		2799	ATOM_COMMON_RECORD_HEADER sheader;
		2800	UCHAR ucMuxType; /* decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state */
		2801	UCHAR ucMuxControlPin;
		2802	UCHAR ucMuxState[2]; /* for alligment purpose */
		2803	} ATOM_ROUTER_DDC_PATH_SELECT_RECORD;
		2804
		2805	typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD {
		2806	ATOM_COMMON_RECORD_HEADER sheader;
		2807	UCHAR ucMuxType;
		2808	UCHAR ucMuxControlPin;
		2809	UCHAR ucMuxState[2]; /* for alligment purpose */
		2810	} ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD;
		2811
		2812	/* define ucMuxType */
		2813	#define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f
		2814	#define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01
		2815
		2816	/****************************************************************************/
		2817	/* ASIC voltage data table */
		2818	/****************************************************************************/
		2819	typedef struct _ATOM_VOLTAGE_INFO_HEADER {
		2820	USHORT usVDDCBaseLevel; /* In number of 50mv unit */
		2821	USHORT usReserved; /* For possible extension table offset */
		2822	UCHAR ucNumOfVoltageEntries;
		2823	UCHAR ucBytesPerVoltageEntry;
		2824	UCHAR ucVoltageStep; /* Indicating in how many mv increament is one step, 0.5mv unit */
		2825	UCHAR ucDefaultVoltageEntry;
		2826	UCHAR ucVoltageControlI2cLine;
		2827	UCHAR ucVoltageControlAddress;
		2828	UCHAR ucVoltageControlOffset;
		2829	} ATOM_VOLTAGE_INFO_HEADER;
		2830
		2831	typedef struct _ATOM_VOLTAGE_INFO {
		2832	ATOM_COMMON_TABLE_HEADER sHeader;
		2833	ATOM_VOLTAGE_INFO_HEADER viHeader;
		2834	UCHAR ucVoltageEntries[64]; /* 64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntriesucBytesPerVoltageEntry /
		2835	} ATOM_VOLTAGE_INFO;
		2836
		2837	typedef struct _ATOM_VOLTAGE_FORMULA {
		2838	USHORT usVoltageBaseLevel; /* In number of 1mv unit */
		2839	USHORT usVoltageStep; /* Indicating in how many mv increament is one step, 1mv unit */
		2840	UCHAR ucNumOfVoltageEntries; /* Number of Voltage Entry, which indicate max Voltage */
		2841	UCHAR ucFlag; /* bit0=0 :step is 1mv =1 0.5mv */
		2842	UCHAR ucBaseVID; /* if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep */
		2843	UCHAR ucReserved;
		2844	UCHAR ucVIDAdjustEntries[32]; /* 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries */
		2845	} ATOM_VOLTAGE_FORMULA;
		2846
		2847	typedef struct _ATOM_VOLTAGE_CONTROL {
		2848	UCHAR ucVoltageControlId; /* Indicate it is controlled by I2C or GPIO or HW state machine */
		2849	UCHAR ucVoltageControlI2cLine;
		2850	UCHAR ucVoltageControlAddress;
		2851	UCHAR ucVoltageControlOffset;
		2852	USHORT usGpioPin_AIndex; /* GPIO_PAD register index */
		2853	UCHAR ucGpioPinBitShift[9]; /* at most 8 pin support 255 VIDs, termintate with 0xff */
		2854	UCHAR ucReserved;
		2855	} ATOM_VOLTAGE_CONTROL;
		2856
		2857	/* Define ucVoltageControlId */
		2858	#define VOLTAGE_CONTROLLED_BY_HW 0x00
		2859	#define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F
		2860	#define VOLTAGE_CONTROLLED_BY_GPIO 0x80
		2861	#define VOLTAGE_CONTROL_ID_LM64 0x01 /* I2C control, used for R5xx Core Voltage */
		2862	#define VOLTAGE_CONTROL_ID_DAC 0x02 /* I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI */
		2863	#define VOLTAGE_CONTROL_ID_VT116xM 0x03 /* I2C control, used for R6xx Core Voltage */
		2864	#define VOLTAGE_CONTROL_ID_DS4402 0x04
		2865
		2866	typedef struct _ATOM_VOLTAGE_OBJECT {
		2867	UCHAR ucVoltageType; /* Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI */
		2868	UCHAR ucSize; /* Size of Object */
		2869	ATOM_VOLTAGE_CONTROL asControl; /* describ how to control */
		2870	ATOM_VOLTAGE_FORMULA asFormula; /* Indicate How to convert real Voltage to VID */
		2871	} ATOM_VOLTAGE_OBJECT;
		2872
		2873	typedef struct _ATOM_VOLTAGE_OBJECT_INFO {
		2874	ATOM_COMMON_TABLE_HEADER sHeader;
		2875	ATOM_VOLTAGE_OBJECT asVoltageObj[3]; /* Info for Voltage control */
		2876	} ATOM_VOLTAGE_OBJECT_INFO;
		2877
		2878	typedef struct _ATOM_LEAKID_VOLTAGE {
		2879	UCHAR ucLeakageId;
		2880	UCHAR ucReserved;
		2881	USHORT usVoltage;
		2882	} ATOM_LEAKID_VOLTAGE;
		2883
		2884	typedef struct _ATOM_ASIC_PROFILE_VOLTAGE {
		2885	UCHAR ucProfileId;
		2886	UCHAR ucReserved;
		2887	USHORT usSize;
		2888	USHORT usEfuseSpareStartAddr;
		2889	USHORT usFuseIndex[8]; /* from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, */
		2890	ATOM_LEAKID_VOLTAGE asLeakVol[2]; /* Leakid and relatd voltage */
		2891	} ATOM_ASIC_PROFILE_VOLTAGE;
		2892
		2893	/* ucProfileId */
		2894	#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1
		2895	#define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1
		2896	#define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2
		2897
		2898	typedef struct _ATOM_ASIC_PROFILING_INFO {
		2899	ATOM_COMMON_TABLE_HEADER asHeader;
		2900	ATOM_ASIC_PROFILE_VOLTAGE asVoltage;
		2901	} ATOM_ASIC_PROFILING_INFO;
		2902
		2903	typedef struct _ATOM_POWER_SOURCE_OBJECT {
		2904	UCHAR ucPwrSrcId; /* Power source */
		2905	UCHAR ucPwrSensorType; /* GPIO, I2C or none */
		2906	UCHAR ucPwrSensId; /* if GPIO detect, it is GPIO id, if I2C detect, it is I2C id */
		2907	UCHAR ucPwrSensSlaveAddr; /* Slave address if I2C detect */
		2908	UCHAR ucPwrSensRegIndex; /* I2C register Index if I2C detect */
		2909	UCHAR ucPwrSensRegBitMask; /* detect which bit is used if I2C detect */
		2910	UCHAR ucPwrSensActiveState; /* high active or low active */
		2911	UCHAR ucReserve[3]; /* reserve */
		2912	USHORT usSensPwr; /* in unit of watt */
		2913	} ATOM_POWER_SOURCE_OBJECT;
		2914
		2915	typedef struct _ATOM_POWER_SOURCE_INFO {
		2916	ATOM_COMMON_TABLE_HEADER asHeader;
		2917	UCHAR asPwrbehave[16];
		2918	ATOM_POWER_SOURCE_OBJECT asPwrObj[1];
		2919	} ATOM_POWER_SOURCE_INFO;
		2920
		2921	/* Define ucPwrSrcId */
		2922	#define POWERSOURCE_PCIE_ID1 0x00
		2923	#define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01
		2924	#define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02
		2925	#define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04
		2926	#define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08
		2927
		2928	/* define ucPwrSensorId */
		2929	#define POWER_SENSOR_ALWAYS 0x00
		2930	#define POWER_SENSOR_GPIO 0x01
		2931	#define POWER_SENSOR_I2C 0x02
		2932
		2933	/**************************************************************************/
		2934	/* This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design */
		2935	/* Memory SS Info Table */
		2936	/* Define Memory Clock SS chip ID */
		2937	#define ICS91719 1
		2938	#define ICS91720 2
		2939
		2940	/* Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol */
		2941	typedef struct _ATOM_I2C_DATA_RECORD {
		2942	UCHAR ucNunberOfBytes; /* Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" */
		2943	UCHAR ucI2CData[1]; /* I2C data in bytes, should be less than 16 bytes usually */
		2944	} ATOM_I2C_DATA_RECORD;
		2945
		2946	/* Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information */
		2947	typedef struct _ATOM_I2C_DEVICE_SETUP_INFO {
		2948	ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; /* I2C line and HW/SW assisted cap. */
		2949	UCHAR ucSSChipID; /* SS chip being used */
		2950	UCHAR ucSSChipSlaveAddr; /* Slave Address to set up this SS chip */
		2951	UCHAR ucNumOfI2CDataRecords; /* number of data block */
		2952	ATOM_I2C_DATA_RECORD asI2CData[1];
		2953	} ATOM_I2C_DEVICE_SETUP_INFO;
		2954
		2955	/* ========================================================================================== */
		2956	typedef struct _ATOM_ASIC_MVDD_INFO {
		2957	ATOM_COMMON_TABLE_HEADER sHeader;
		2958	ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1];
		2959	} ATOM_ASIC_MVDD_INFO;
		2960
		2961	/* ========================================================================================== */
		2962	#define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO
		2963
		2964	/* ========================================================================================== */
		2965	/**************************************************************************/
		2966
		2967	typedef struct _ATOM_ASIC_SS_ASSIGNMENT {
		2968	ULONG ulTargetClockRange; /* Clock Out frequence (VCO ), in unit of 10Khz */
		2969	USHORT usSpreadSpectrumPercentage; /* in unit of 0.01% */
		2970	USHORT usSpreadRateInKhz; /* in unit of kHz, modulation freq */
		2971	UCHAR ucClockIndication; /* Indicate which clock source needs SS */
		2972	UCHAR ucSpreadSpectrumMode; /* Bit1=0 Down Spread,=1 Center Spread. */
		2973	UCHAR ucReserved[2];
		2974	} ATOM_ASIC_SS_ASSIGNMENT;
		2975
		2976	/* Define ucSpreadSpectrumType */
		2977	#define ASIC_INTERNAL_MEMORY_SS 1
		2978	#define ASIC_INTERNAL_ENGINE_SS 2
		2979	#define ASIC_INTERNAL_UVD_SS 3
		2980
		2981	typedef struct _ATOM_ASIC_INTERNAL_SS_INFO {
		2982	ATOM_COMMON_TABLE_HEADER sHeader;
		2983	ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4];
		2984	} ATOM_ASIC_INTERNAL_SS_INFO;
		2985
		2986	/* ==============================Scratch Pad Definition Portion=============================== */
		2987	#define ATOM_DEVICE_CONNECT_INFO_DEF 0
		2988	#define ATOM_ROM_LOCATION_DEF 1
		2989	#define ATOM_TV_STANDARD_DEF 2
		2990	#define ATOM_ACTIVE_INFO_DEF 3
		2991	#define ATOM_LCD_INFO_DEF 4
		2992	#define ATOM_DOS_REQ_INFO_DEF 5
		2993	#define ATOM_ACC_CHANGE_INFO_DEF 6
		2994	#define ATOM_DOS_MODE_INFO_DEF 7
		2995	#define ATOM_I2C_CHANNEL_STATUS_DEF 8
		2996	#define ATOM_I2C_CHANNEL_STATUS1_DEF 9
		2997
		2998	/* BIOS_0_SCRATCH Definition */
		2999	#define ATOM_S0_CRT1_MONO 0x00000001L
		3000	#define ATOM_S0_CRT1_COLOR 0x00000002L
		3001	#define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR)
		3002
		3003	#define ATOM_S0_TV1_COMPOSITE_A 0x00000004L
		3004	#define ATOM_S0_TV1_SVIDEO_A 0x00000008L
		3005	#define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A)
		3006
		3007	#define ATOM_S0_CV_A 0x00000010L
		3008	#define ATOM_S0_CV_DIN_A 0x00000020L
		3009	#define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A)
		3010
		3011	#define ATOM_S0_CRT2_MONO 0x00000100L
		3012	#define ATOM_S0_CRT2_COLOR 0x00000200L
		3013	#define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR)
		3014
		3015	#define ATOM_S0_TV1_COMPOSITE 0x00000400L
		3016	#define ATOM_S0_TV1_SVIDEO 0x00000800L
		3017	#define ATOM_S0_TV1_SCART 0x00004000L
		3018	#define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART)
		3019
		3020	#define ATOM_S0_CV 0x00001000L
		3021	#define ATOM_S0_CV_DIN 0x00002000L
		3022	#define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN)
		3023
		3024	#define ATOM_S0_DFP1 0x00010000L
		3025	#define ATOM_S0_DFP2 0x00020000L
		3026	#define ATOM_S0_LCD1 0x00040000L
		3027	#define ATOM_S0_LCD2 0x00080000L
		3028	#define ATOM_S0_TV2 0x00100000L
		3029	#define ATOM_S0_DFP3 0x00200000L
		3030	#define ATOM_S0_DFP4 0x00400000L
		3031	#define ATOM_S0_DFP5 0x00800000L
		3032
		3033	#define ATOM_S0_DFP_MASK \
		3034	(ATOM_S0_DFP1 \| ATOM_S0_DFP2 \| ATOM_S0_DFP3 \| ATOM_S0_DFP4 \| ATOM_S0_DFP5)
		3035
		3036	#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L /* If set, indicates we are running a PCIE asic with */
		3037	/* the FAD/HDP reg access bug. Bit is read by DAL */
		3038
		3039	#define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L
		3040	#define ATOM_S0_THERMAL_STATE_SHIFT 26
		3041
		3042	#define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L
		3043	#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29
		3044
		3045	#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1
		3046	#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2
		3047	#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3
		3048
		3049	/* Byte aligned defintion for BIOS usage */
		3050	#define ATOM_S0_CRT1_MONOb0 0x01
		3051	#define ATOM_S0_CRT1_COLORb0 0x02
		3052	#define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0)
		3053
		3054	#define ATOM_S0_TV1_COMPOSITEb0 0x04
		3055	#define ATOM_S0_TV1_SVIDEOb0 0x08
		3056	#define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0)
		3057
		3058	#define ATOM_S0_CVb0 0x10
		3059	#define ATOM_S0_CV_DINb0 0x20
		3060	#define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0)
		3061
		3062	#define ATOM_S0_CRT2_MONOb1 0x01
		3063	#define ATOM_S0_CRT2_COLORb1 0x02
		3064	#define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1)
		3065
		3066	#define ATOM_S0_TV1_COMPOSITEb1 0x04
		3067	#define ATOM_S0_TV1_SVIDEOb1 0x08
		3068	#define ATOM_S0_TV1_SCARTb1 0x40
		3069	#define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1)
		3070
		3071	#define ATOM_S0_CVb1 0x10
		3072	#define ATOM_S0_CV_DINb1 0x20
		3073	#define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1)
		3074
		3075	#define ATOM_S0_DFP1b2 0x01
		3076	#define ATOM_S0_DFP2b2 0x02
		3077	#define ATOM_S0_LCD1b2 0x04
		3078	#define ATOM_S0_LCD2b2 0x08
		3079	#define ATOM_S0_TV2b2 0x10
		3080	#define ATOM_S0_DFP3b2 0x20
		3081
		3082	#define ATOM_S0_THERMAL_STATE_MASKb3 0x1C
		3083	#define ATOM_S0_THERMAL_STATE_SHIFTb3 2
		3084
		3085	#define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0
		3086	#define ATOM_S0_LCD1_SHIFT 18
		3087
		3088	/* BIOS_1_SCRATCH Definition */
		3089	#define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL
		3090	#define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L
		3091
		3092	/* BIOS_2_SCRATCH Definition */
		3093	#define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL
		3094	#define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L
		3095	#define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8
		3096
		3097	#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L
		3098	#define ATOM_S2_LCD1_DPMS_STATE 0x00020000L
		3099	#define ATOM_S2_TV1_DPMS_STATE 0x00040000L
		3100	#define ATOM_S2_DFP1_DPMS_STATE 0x00080000L
		3101	#define ATOM_S2_CRT2_DPMS_STATE 0x00100000L
		3102	#define ATOM_S2_LCD2_DPMS_STATE 0x00200000L
		3103	#define ATOM_S2_TV2_DPMS_STATE 0x00400000L
		3104	#define ATOM_S2_DFP2_DPMS_STATE 0x00800000L
		3105	#define ATOM_S2_CV_DPMS_STATE 0x01000000L
		3106	#define ATOM_S2_DFP3_DPMS_STATE 0x02000000L
		3107	#define ATOM_S2_DFP4_DPMS_STATE 0x04000000L
		3108	#define ATOM_S2_DFP5_DPMS_STATE 0x08000000L
		3109
		3110	#define ATOM_S2_DFP_DPM_STATE \
		3111	(ATOM_S2_DFP1_DPMS_STATE \| ATOM_S2_DFP2_DPMS_STATE \| \
		3112	ATOM_S2_DFP3_DPMS_STATE \| ATOM_S2_DFP4_DPMS_STATE \| \
		3113	ATOM_S2_DFP5_DPMS_STATE)
		3114
		3115	#define ATOM_S2_DEVICE_DPMS_STATE \
		3116	(ATOM_S2_CRT1_DPMS_STATE + ATOM_S2_LCD1_DPMS_STATE + \
		3117	ATOM_S2_TV1_DPMS_STATE + ATOM_S2_DFP_DPMS_STATE + \
		3118	ATOM_S2_CRT2_DPMS_STATE + ATOM_S2_LCD2_DPMS_STATE + \
		3119	ATOM_S2_TV2_DPMS_STATE + ATOM_S2_CV_DPMS_STATE)
		3120
		3121	#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L
		3122	#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26
		3123	#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L
		3124
		3125	#define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L
		3126
		3127	#define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0
		3128	#define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1
		3129	#define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2
		3130	#define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3
		3131	#define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30
		3132	#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L
		3133
		3134	/* Byte aligned defintion for BIOS usage */
		3135	#define ATOM_S2_TV1_STANDARD_MASKb0 0x0F
		3136	#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF
		3137	#define ATOM_S2_CRT1_DPMS_STATEb2 0x01
		3138	#define ATOM_S2_LCD1_DPMS_STATEb2 0x02
		3139	#define ATOM_S2_TV1_DPMS_STATEb2 0x04
		3140	#define ATOM_S2_DFP1_DPMS_STATEb2 0x08
		3141	#define ATOM_S2_CRT2_DPMS_STATEb2 0x10
		3142	#define ATOM_S2_LCD2_DPMS_STATEb2 0x20
		3143	#define ATOM_S2_TV2_DPMS_STATEb2 0x40
		3144	#define ATOM_S2_DFP2_DPMS_STATEb2 0x80
		3145	#define ATOM_S2_CV_DPMS_STATEb3 0x01
		3146	#define ATOM_S2_DFP3_DPMS_STATEb3 0x02
		3147	#define ATOM_S2_DFP4_DPMS_STATEb3 0x04
		3148	#define ATOM_S2_DFP5_DPMS_STATEb3 0x08
		3149
		3150	#define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF
		3151	#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C
		3152	#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3 0x10
		3153	#define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20
		3154	#define ATOM_S2_ROTATION_STATE_MASKb3 0xC0
		3155
		3156	/* BIOS_3_SCRATCH Definition */
		3157	#define ATOM_S3_CRT1_ACTIVE 0x00000001L
		3158	#define ATOM_S3_LCD1_ACTIVE 0x00000002L
		3159	#define ATOM_S3_TV1_ACTIVE 0x00000004L
		3160	#define ATOM_S3_DFP1_ACTIVE 0x00000008L
		3161	#define ATOM_S3_CRT2_ACTIVE 0x00000010L
		3162	#define ATOM_S3_LCD2_ACTIVE 0x00000020L
		3163	#define ATOM_S3_TV2_ACTIVE 0x00000040L
		3164	#define ATOM_S3_DFP2_ACTIVE 0x00000080L
		3165	#define ATOM_S3_CV_ACTIVE 0x00000100L
		3166	#define ATOM_S3_DFP3_ACTIVE 0x00000200L
		3167	#define ATOM_S3_DFP4_ACTIVE 0x00000400L
		3168	#define ATOM_S3_DFP5_ACTIVE 0x00000800L
		3169
		3170	#define ATOM_S3_DEVICE_ACTIVE_MASK 0x000003FFL
		3171
		3172	#define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L
		3173	#define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L
		3174
		3175	#define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L
		3176	#define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L
		3177	#define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L
		3178	#define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L
		3179	#define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L
		3180	#define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L
		3181	#define ATOM_S3_TV2_CRTC_ACTIVE 0x00400000L
		3182	#define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L
		3183	#define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L
		3184	#define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L
		3185	#define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L
		3186	#define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L
		3187
		3188	#define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L
		3189	#define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L
		3190	#define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L
		3191	#define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L
		3192
		3193	/* Byte aligned defintion for BIOS usage */
		3194	#define ATOM_S3_CRT1_ACTIVEb0 0x01
		3195	#define ATOM_S3_LCD1_ACTIVEb0 0x02
		3196	#define ATOM_S3_TV1_ACTIVEb0 0x04
		3197	#define ATOM_S3_DFP1_ACTIVEb0 0x08
		3198	#define ATOM_S3_CRT2_ACTIVEb0 0x10
		3199	#define ATOM_S3_LCD2_ACTIVEb0 0x20
		3200	#define ATOM_S3_TV2_ACTIVEb0 0x40
		3201	#define ATOM_S3_DFP2_ACTIVEb0 0x80
		3202	#define ATOM_S3_CV_ACTIVEb1 0x01
		3203	#define ATOM_S3_DFP3_ACTIVEb1 0x02
		3204	#define ATOM_S3_DFP4_ACTIVEb1 0x04
		3205	#define ATOM_S3_DFP5_ACTIVEb1 0x08
		3206
		3207	#define ATOM_S3_ACTIVE_CRTC1w0 0xFFF
		3208
		3209	#define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01
		3210	#define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02
		3211	#define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04
		3212	#define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08
		3213	#define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10
		3214	#define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20
		3215	#define ATOM_S3_TV2_CRTC_ACTIVEb2 0x40
		3216	#define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80
		3217	#define ATOM_S3_CV_CRTC_ACTIVEb3 0x01
		3218	#define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02
		3219	#define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04
		3220	#define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08
		3221
		3222	#define ATOM_S3_ACTIVE_CRTC2w1 0xFFF
		3223
		3224	#define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20
		3225	#define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40
		3226	#define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80
		3227
		3228	/* BIOS_4_SCRATCH Definition */
		3229	#define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL
		3230	#define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L
		3231	#define ATOM_S4_LCD1_REFRESH_SHIFT 8
		3232
		3233	/* Byte aligned defintion for BIOS usage */
		3234	#define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF
		3235	#define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0
		3236	#define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0
		3237
		3238	/* BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! */
		3239	#define ATOM_S5_DOS_REQ_CRT1b0 0x01
		3240	#define ATOM_S5_DOS_REQ_LCD1b0 0x02
		3241	#define ATOM_S5_DOS_REQ_TV1b0 0x04
		3242	#define ATOM_S5_DOS_REQ_DFP1b0 0x08
		3243	#define ATOM_S5_DOS_REQ_CRT2b0 0x10
		3244	#define ATOM_S5_DOS_REQ_LCD2b0 0x20
		3245	#define ATOM_S5_DOS_REQ_TV2b0 0x40
		3246	#define ATOM_S5_DOS_REQ_DFP2b0 0x80
		3247	#define ATOM_S5_DOS_REQ_CVb1 0x01
		3248	#define ATOM_S5_DOS_REQ_DFP3b1 0x02
		3249	#define ATOM_S5_DOS_REQ_DFP4b1 0x04
		3250	#define ATOM_S5_DOS_REQ_DFP5b1 0x08
		3251
		3252	#define ATOM_S5_DOS_REQ_DEVICEw0 0x03FF
		3253
		3254	#define ATOM_S5_DOS_REQ_CRT1 0x0001
		3255	#define ATOM_S5_DOS_REQ_LCD1 0x0002
		3256	#define ATOM_S5_DOS_REQ_TV1 0x0004
		3257	#define ATOM_S5_DOS_REQ_DFP1 0x0008
		3258	#define ATOM_S5_DOS_REQ_CRT2 0x0010
		3259	#define ATOM_S5_DOS_REQ_LCD2 0x0020
		3260	#define ATOM_S5_DOS_REQ_TV2 0x0040
		3261	#define ATOM_S5_DOS_REQ_DFP2 0x0080
		3262	#define ATOM_S5_DOS_REQ_CV 0x0100
		3263	#define ATOM_S5_DOS_REQ_DFP3 0x0200
		3264	#define ATOM_S5_DOS_REQ_DFP4 0x0400
		3265	#define ATOM_S5_DOS_REQ_DFP5 0x0800
		3266
		3267	#define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0
		3268	#define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0
		3269	#define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0
		3270	#define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1
		3271	#define ATOM_S5_DOS_FORCE_DEVICEw1 \
		3272	(ATOM_S5_DOS_FORCE_CRT1b2 + ATOM_S5_DOS_FORCE_TV1b2 + \
		3273	ATOM_S5_DOS_FORCE_CRT2b2 + (ATOM_S5_DOS_FORCE_CVb3 << 8))
		3274
		3275	/* BIOS_6_SCRATCH Definition */
		3276	#define ATOM_S6_DEVICE_CHANGE 0x00000001L
		3277	#define ATOM_S6_SCALER_CHANGE 0x00000002L
		3278	#define ATOM_S6_LID_CHANGE 0x00000004L
		3279	#define ATOM_S6_DOCKING_CHANGE 0x00000008L
		3280	#define ATOM_S6_ACC_MODE 0x00000010L
		3281	#define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L
		3282	#define ATOM_S6_LID_STATE 0x00000040L
		3283	#define ATOM_S6_DOCK_STATE 0x00000080L
		3284	#define ATOM_S6_CRITICAL_STATE 0x00000100L
		3285	#define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L
		3286	#define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L
		3287	#define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L
		3288	#define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L /* Normal expansion Request bit for LCD */
		3289	#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L /* Aspect ratio expansion Request bit for LCD */
		3290
		3291	#define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L /* This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion */
		3292	#define ATOM_S6_I2C_STATE_CHANGE 0x00008000L /* This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion */
		3293
		3294	#define ATOM_S6_ACC_REQ_CRT1 0x00010000L
		3295	#define ATOM_S6_ACC_REQ_LCD1 0x00020000L
		3296	#define ATOM_S6_ACC_REQ_TV1 0x00040000L
		3297	#define ATOM_S6_ACC_REQ_DFP1 0x00080000L
		3298	#define ATOM_S6_ACC_REQ_CRT2 0x00100000L
		3299	#define ATOM_S6_ACC_REQ_LCD2 0x00200000L
		3300	#define ATOM_S6_ACC_REQ_TV2 0x00400000L
		3301	#define ATOM_S6_ACC_REQ_DFP2 0x00800000L
		3302	#define ATOM_S6_ACC_REQ_CV 0x01000000L
		3303	#define ATOM_S6_ACC_REQ_DFP3 0x02000000L
		3304	#define ATOM_S6_ACC_REQ_DFP4 0x04000000L
		3305	#define ATOM_S6_ACC_REQ_DFP5 0x08000000L
		3306
		3307	#define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L
		3308	#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L
		3309	#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L
		3310	#define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L
		3311	#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L
		3312
		3313	/* Byte aligned defintion for BIOS usage */
		3314	#define ATOM_S6_DEVICE_CHANGEb0 0x01
		3315	#define ATOM_S6_SCALER_CHANGEb0 0x02
		3316	#define ATOM_S6_LID_CHANGEb0 0x04
		3317	#define ATOM_S6_DOCKING_CHANGEb0 0x08
		3318	#define ATOM_S6_ACC_MODEb0 0x10
		3319	#define ATOM_S6_EXT_DESKTOP_MODEb0 0x20
		3320	#define ATOM_S6_LID_STATEb0 0x40
		3321	#define ATOM_S6_DOCK_STATEb0 0x80
		3322	#define ATOM_S6_CRITICAL_STATEb1 0x01
		3323	#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02
		3324	#define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04
		3325	#define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08
		3326	#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10
		3327	#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20
		3328
		3329	#define ATOM_S6_ACC_REQ_CRT1b2 0x01
		3330	#define ATOM_S6_ACC_REQ_LCD1b2 0x02
		3331	#define ATOM_S6_ACC_REQ_TV1b2 0x04
		3332	#define ATOM_S6_ACC_REQ_DFP1b2 0x08
		3333	#define ATOM_S6_ACC_REQ_CRT2b2 0x10
		3334	#define ATOM_S6_ACC_REQ_LCD2b2 0x20
		3335	#define ATOM_S6_ACC_REQ_TV2b2 0x40
		3336	#define ATOM_S6_ACC_REQ_DFP2b2 0x80
		3337	#define ATOM_S6_ACC_REQ_CVb3 0x01
		3338	#define ATOM_S6_ACC_REQ_DFP3b3 0x02
		3339	#define ATOM_S6_ACC_REQ_DFP4b3 0x04
		3340	#define ATOM_S6_ACC_REQ_DFP5b3 0x08
		3341
		3342	#define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0
		3343	#define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10
		3344	#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20
		3345	#define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40
		3346	#define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80
		3347
		3348	#define ATOM_S6_DEVICE_CHANGE_SHIFT 0
		3349	#define ATOM_S6_SCALER_CHANGE_SHIFT 1
		3350	#define ATOM_S6_LID_CHANGE_SHIFT 2
		3351	#define ATOM_S6_DOCKING_CHANGE_SHIFT 3
		3352	#define ATOM_S6_ACC_MODE_SHIFT 4
		3353	#define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5
		3354	#define ATOM_S6_LID_STATE_SHIFT 6
		3355	#define ATOM_S6_DOCK_STATE_SHIFT 7
		3356	#define ATOM_S6_CRITICAL_STATE_SHIFT 8
		3357	#define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9
		3358	#define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10
		3359	#define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11
		3360	#define ATOM_S6_REQ_SCALER_SHIFT 12
		3361	#define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13
		3362	#define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14
		3363	#define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15
		3364	#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28
		3365	#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29
		3366	#define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30
		3367	#define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31
		3368
		3369	/* BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! */
		3370	#define ATOM_S7_DOS_MODE_TYPEb0 0x03
		3371	#define ATOM_S7_DOS_MODE_VGAb0 0x00
		3372	#define ATOM_S7_DOS_MODE_VESAb0 0x01
		3373	#define ATOM_S7_DOS_MODE_EXTb0 0x02
		3374	#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C
		3375	#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0
		3376	#define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01
		3377	#define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF
		3378
		3379	#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8
		3380
		3381	/* BIOS_8_SCRATCH Definition */
		3382	#define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF
		3383	#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000
		3384
		3385	#define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0
		3386	#define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16
		3387
		3388	/* BIOS_9_SCRATCH Definition */
		3389	#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK
		3390	#define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF
		3391	#endif
		3392	#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK
		3393	#define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000
		3394	#endif
		3395	#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT
		3396	#define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0
		3397	#endif
		3398	#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT
		3399	#define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16
		3400	#endif
		3401
		3402	#define ATOM_FLAG_SET 0x20
		3403	#define ATOM_FLAG_CLEAR 0
		3404	#define CLEAR_ATOM_S6_ACC_MODE \
		3405	((ATOM_ACC_CHANGE_INFO_DEF << 8) \| \
		3406	ATOM_S6_ACC_MODE_SHIFT \| ATOM_FLAG_CLEAR)
		3407	#define SET_ATOM_S6_DEVICE_CHANGE \
		3408	((ATOM_ACC_CHANGE_INFO_DEF << 8) \| \
		3409	ATOM_S6_DEVICE_CHANGE_SHIFT \| ATOM_FLAG_SET)
		3410	#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE \
		3411	((ATOM_ACC_CHANGE_INFO_DEF << 8) \| \
		3412	ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT \| ATOM_FLAG_SET)
		3413	#define SET_ATOM_S6_SCALER_CHANGE \
		3414	((ATOM_ACC_CHANGE_INFO_DEF << 8) \| \
		3415	ATOM_S6_SCALER_CHANGE_SHIFT \| ATOM_FLAG_SET)
		3416	#define SET_ATOM_S6_LID_CHANGE \
		3417	((ATOM_ACC_CHANGE_INFO_DEF << 8) \| \
		3418	ATOM_S6_LID_CHANGE_SHIFT \| ATOM_FLAG_SET)
		3419
		3420	#define SET_ATOM_S6_LID_STATE \
		3421	((ATOM_ACC_CHANGE_INFO_DEF << 8) \|\
		3422	ATOM_S6_LID_STATE_SHIFT \| ATOM_FLAG_SET)
		3423	#define CLEAR_ATOM_S6_LID_STATE \
		3424	((ATOM_ACC_CHANGE_INFO_DEF << 8) \| \
		3425	ATOM_S6_LID_STATE_SHIFT \| ATOM_FLAG_CLEAR)
		3426
		3427	#define SET_ATOM_S6_DOCK_CHANGE \
		3428	((ATOM_ACC_CHANGE_INFO_DEF << 8)\| \
		3429	ATOM_S6_DOCKING_CHANGE_SHIFT \| ATOM_FLAG_SET)
		3430	#define SET_ATOM_S6_DOCK_STATE \
		3431	((ATOM_ACC_CHANGE_INFO_DEF << 8) \| \
		3432	ATOM_S6_DOCK_STATE_SHIFT \| ATOM_FLAG_SET)
		3433	#define CLEAR_ATOM_S6_DOCK_STATE \
		3434	((ATOM_ACC_CHANGE_INFO_DEF << 8) \| \
		3435	ATOM_S6_DOCK_STATE_SHIFT \| ATOM_FLAG_CLEAR)
		3436
		3437	#define SET_ATOM_S6_THERMAL_STATE_CHANGE \
		3438	((ATOM_ACC_CHANGE_INFO_DEF << 8) \| \
		3439	ATOM_S6_THERMAL_STATE_CHANGE_SHIFT \| ATOM_FLAG_SET)
		3440	#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE \
		3441	((ATOM_ACC_CHANGE_INFO_DEF << 8) \| \
		3442	ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT \| ATOM_FLAG_SET)
		3443	#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS \
		3444	((ATOM_ACC_CHANGE_INFO_DEF << 8) \| \
		3445	ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT \| ATOM_FLAG_SET)
		3446
		3447	#define SET_ATOM_S6_CRITICAL_STATE \
		3448	((ATOM_ACC_CHANGE_INFO_DEF << 8) \| \
		3449	ATOM_S6_CRITICAL_STATE_SHIFT \| ATOM_FLAG_SET)
		3450	#define CLEAR_ATOM_S6_CRITICAL_STATE \
		3451	((ATOM_ACC_CHANGE_INFO_DEF << 8) \| \
		3452	ATOM_S6_CRITICAL_STATE_SHIFT \| ATOM_FLAG_CLEAR)
		3453
		3454	#define SET_ATOM_S6_REQ_SCALER \
		3455	((ATOM_ACC_CHANGE_INFO_DEF << 8) \| \
		3456	ATOM_S6_REQ_SCALER_SHIFT \| ATOM_FLAG_SET)
		3457	#define CLEAR_ATOM_S6_REQ_SCALER \
		3458	((ATOM_ACC_CHANGE_INFO_DEF << 8) \| \
		3459	ATOM_S6_REQ_SCALER_SHIFT \| ATOM_FLAG_CLEAR )
		3460
		3461	#define SET_ATOM_S6_REQ_SCALER_ARATIO \
		3462	((ATOM_ACC_CHANGE_INFO_DEF << 8) \| \
		3463	ATOM_S6_REQ_SCALER_ARATIO_SHIFT \| ATOM_FLAG_SET )
		3464	#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO \
		3465	((ATOM_ACC_CHANGE_INFO_DEF << 8) \| \
		3466	ATOM_S6_REQ_SCALER_ARATIO_SHIFT \| ATOM_FLAG_CLEAR )
		3467
		3468	#define SET_ATOM_S6_I2C_STATE_CHANGE \
		3469	((ATOM_ACC_CHANGE_INFO_DEF << 8) \| \
		3470	ATOM_S6_I2C_STATE_CHANGE_SHIFT \| ATOM_FLAG_SET )
		3471
		3472	#define SET_ATOM_S6_DISPLAY_STATE_CHANGE \
		3473	((ATOM_ACC_CHANGE_INFO_DEF << 8) \| \
		3474	ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT \| ATOM_FLAG_SET )
		3475
		3476	#define SET_ATOM_S6_DEVICE_RECONFIG \
		3477	((ATOM_ACC_CHANGE_INFO_DEF << 8) \| \
		3478	ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT \| ATOM_FLAG_SET)
		3479	#define CLEAR_ATOM_S0_LCD1 \
		3480	((ATOM_DEVICE_CONNECT_INFO_DEF << 8 ) \| \
		3481	ATOM_S0_LCD1_SHIFT \| ATOM_FLAG_CLEAR )
		3482	#define SET_ATOM_S7_DOS_8BIT_DAC_EN \
		3483	((ATOM_DOS_MODE_INFO_DEF << 8) \| \
		3484	ATOM_S7_DOS_8BIT_DAC_EN_SHIFT \| ATOM_FLAG_SET )
		3485	#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN \
		3486	((ATOM_DOS_MODE_INFO_DEF << 8) \| \
		3487	ATOM_S7_DOS_8BIT_DAC_EN_SHIFT \| ATOM_FLAG_CLEAR )
		3488
		3489	/****************************************************************************/
		3490	/* Portion II: Definitinos only used in Driver */
		3491	/****************************************************************************/
		3492
		3493	/* Macros used by driver */
		3494
		3495	#define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char )(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES )0)->FieldName)-(char *)0)/sizeof(USHORT))
		3496
		3497	#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F)
		3498	#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F)
		3499
		3500	#define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION
		3501	#define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION
		3502
		3503	/****************************************************************************/
		3504	/* Portion III: Definitinos only used in VBIOS */
		3505	/****************************************************************************/
		3506	#define ATOM_DAC_SRC 0x80
		3507	#define ATOM_SRC_DAC1 0
		3508	#define ATOM_SRC_DAC2 0x80
		3509
		3510	#ifdef UEFI_BUILD
		3511	#define USHORT UTEMP
		3512	#endif
		3513
		3514	typedef struct _MEMORY_PLLINIT_PARAMETERS {
		3515	ULONG ulTargetMemoryClock; /* In 10Khz unit */
		3516	UCHAR ucAction; /* not define yet */
		3517	UCHAR ucFbDiv_Hi; /* Fbdiv Hi byte */
		3518	UCHAR ucFbDiv; /* FB value */
		3519	UCHAR ucPostDiv; /* Post div */
		3520	} MEMORY_PLLINIT_PARAMETERS;
		3521
		3522	#define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS
		3523
		3524	#define GPIO_PIN_WRITE 0x01
		3525	#define GPIO_PIN_READ 0x00
		3526
		3527	typedef struct _GPIO_PIN_CONTROL_PARAMETERS {
		3528	UCHAR ucGPIO_ID; /* return value, read from GPIO pins */
		3529	UCHAR ucGPIOBitShift; /* define which bit in uGPIOBitVal need to be update */
		3530	UCHAR ucGPIOBitVal; /* Set/Reset corresponding bit defined in ucGPIOBitMask */
		3531	UCHAR ucAction; /* =GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write */
		3532	} GPIO_PIN_CONTROL_PARAMETERS;
		3533
		3534	typedef struct _ENABLE_SCALER_PARAMETERS {
		3535	UCHAR ucScaler; /* ATOM_SCALER1, ATOM_SCALER2 */
		3536	UCHAR ucEnable; /* ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION */
		3537	UCHAR ucTVStandard; /* */
		3538	UCHAR ucPadding[1];
		3539	} ENABLE_SCALER_PARAMETERS;
		3540	#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS
		3541
		3542	/* ucEnable: */
		3543	#define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0
		3544	#define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1
		3545	#define SCALER_ENABLE_2TAP_ALPHA_MODE 2
		3546	#define SCALER_ENABLE_MULTITAP_MODE 3
		3547
		3548	typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS {
		3549	ULONG usHWIconHorzVertPosn; /* Hardware Icon Vertical position */
		3550	UCHAR ucHWIconVertOffset; /* Hardware Icon Vertical offset */
		3551	UCHAR ucHWIconHorzOffset; /* Hardware Icon Horizontal offset */
		3552	UCHAR ucSelection; /* ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 */
		3553	UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */
		3554	} ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS;
		3555
		3556	typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION {
		3557	ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon;
		3558	ENABLE_CRTC_PARAMETERS sReserved;
		3559	} ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION;
		3560
		3561	typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS {
		3562	USHORT usHight; /* Image Hight */
		3563	USHORT usWidth; /* Image Width */
		3564	UCHAR ucSurface; /* Surface 1 or 2 */
		3565	UCHAR ucPadding[3];
		3566	} ENABLE_GRAPH_SURFACE_PARAMETERS;
		3567
		3568	typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 {
		3569	USHORT usHight; /* Image Hight */
		3570	USHORT usWidth; /* Image Width */
		3571	UCHAR ucSurface; /* Surface 1 or 2 */
		3572	UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */
		3573	UCHAR ucPadding[2];
		3574	} ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2;
		3575
		3576	typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION {
		3577	ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface;
		3578	ENABLE_YUV_PS_ALLOCATION sReserved; /* Don't set this one */
		3579	} ENABLE_GRAPH_SURFACE_PS_ALLOCATION;
		3580
		3581	typedef struct _MEMORY_CLEAN_UP_PARAMETERS {
		3582	USHORT usMemoryStart; /* in 8Kb boundry, offset from memory base address */
		3583	USHORT usMemorySize; /* 8Kb blocks aligned */
		3584	} MEMORY_CLEAN_UP_PARAMETERS;
		3585	#define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS
		3586
		3587	typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS {
		3588	USHORT usX_Size; /* When use as input parameter, usX_Size indicates which CRTC */
		3589	USHORT usY_Size;
		3590	} GET_DISPLAY_SURFACE_SIZE_PARAMETERS;
		3591
		3592	typedef struct _INDIRECT_IO_ACCESS {
		3593	ATOM_COMMON_TABLE_HEADER sHeader;
		3594	UCHAR IOAccessSequence[256];
		3595	} INDIRECT_IO_ACCESS;
		3596
		3597	#define INDIRECT_READ 0x00
		3598	#define INDIRECT_WRITE 0x80
		3599
		3600	#define INDIRECT_IO_MM 0
		3601	#define INDIRECT_IO_PLL 1
		3602	#define INDIRECT_IO_MC 2
		3603	#define INDIRECT_IO_PCIE 3
		3604	#define INDIRECT_IO_PCIEP 4
		3605	#define INDIRECT_IO_NBMISC 5
		3606
		3607	#define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL \| INDIRECT_READ
		3608	#define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL \| INDIRECT_WRITE
		3609	#define INDIRECT_IO_MC_READ INDIRECT_IO_MC \| INDIRECT_READ
		3610	#define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC \| INDIRECT_WRITE
		3611	#define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE \| INDIRECT_READ
		3612	#define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE \| INDIRECT_WRITE
		3613	#define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP \| INDIRECT_READ
		3614	#define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP \| INDIRECT_WRITE
		3615	#define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC \| INDIRECT_READ
		3616	#define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC \| INDIRECT_WRITE
		3617
		3618	typedef struct _ATOM_OEM_INFO {
		3619	ATOM_COMMON_TABLE_HEADER sHeader;
		3620	ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
		3621	} ATOM_OEM_INFO;
		3622
		3623	typedef struct _ATOM_TV_MODE {
		3624	UCHAR ucVMode_Num; /* Video mode number */
		3625	UCHAR ucTV_Mode_Num; /* Internal TV mode number */
		3626	} ATOM_TV_MODE;
		3627
		3628	typedef struct _ATOM_BIOS_INT_TVSTD_MODE {
		3629	ATOM_COMMON_TABLE_HEADER sHeader;
		3630	USHORT usTV_Mode_LUT_Offset; /* Pointer to standard to internal number conversion table */
		3631	USHORT usTV_FIFO_Offset; /* Pointer to FIFO entry table */
		3632	USHORT usNTSC_Tbl_Offset; /* Pointer to SDTV_Mode_NTSC table */
		3633	USHORT usPAL_Tbl_Offset; /* Pointer to SDTV_Mode_PAL table */
		3634	USHORT usCV_Tbl_Offset; /* Pointer to SDTV_Mode_PAL table */
		3635	} ATOM_BIOS_INT_TVSTD_MODE;
		3636
		3637	typedef struct _ATOM_TV_MODE_SCALER_PTR {
		3638	USHORT ucFilter0_Offset; /* Pointer to filter format 0 coefficients */
		3639	USHORT usFilter1_Offset; /* Pointer to filter format 0 coefficients */
		3640	UCHAR ucTV_Mode_Num;
		3641	} ATOM_TV_MODE_SCALER_PTR;
		3642
		3643	typedef struct _ATOM_STANDARD_VESA_TIMING {
		3644	ATOM_COMMON_TABLE_HEADER sHeader;
		3645	ATOM_DTD_FORMAT aModeTimings[16]; /* 16 is not the real array number, just for initial allocation */
		3646	} ATOM_STANDARD_VESA_TIMING;
		3647
		3648	typedef struct _ATOM_STD_FORMAT {
		3649	USHORT usSTD_HDisp;
		3650	USHORT usSTD_VDisp;
		3651	USHORT usSTD_RefreshRate;
		3652	USHORT usReserved;
		3653	} ATOM_STD_FORMAT;
		3654
		3655	typedef struct _ATOM_VESA_TO_EXTENDED_MODE {
		3656	USHORT usVESA_ModeNumber;
		3657	USHORT usExtendedModeNumber;
		3658	} ATOM_VESA_TO_EXTENDED_MODE;
		3659
		3660	typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT {
		3661	ATOM_COMMON_TABLE_HEADER sHeader;
		3662	ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76];
		3663	} ATOM_VESA_TO_INTENAL_MODE_LUT;
		3664
		3665	/************* ATOM Memory Related Data Structure *********************/
		3666	typedef struct _ATOM_MEMORY_VENDOR_BLOCK {
		3667	UCHAR ucMemoryType;
		3668	UCHAR ucMemoryVendor;
		3669	UCHAR ucAdjMCId;
		3670	UCHAR ucDynClkId;
		3671	ULONG ulDllResetClkRange;
		3672	} ATOM_MEMORY_VENDOR_BLOCK;
		3673
		3674	typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG {
		3675	#if ATOM_BIG_ENDIAN
		3676	ULONG ucMemBlkId:8;
		3677	ULONG ulMemClockRange:24;
		3678	#else
		3679	ULONG ulMemClockRange:24;
		3680	ULONG ucMemBlkId:8;
		3681	#endif
		3682	} ATOM_MEMORY_SETTING_ID_CONFIG;
		3683
		3684	typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS {
		3685	ATOM_MEMORY_SETTING_ID_CONFIG slAccess;
		3686	ULONG ulAccess;
		3687	} ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS;
		3688
		3689	typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK {
		3690	ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID;
		3691	ULONG aulMemData[1];
		3692	} ATOM_MEMORY_SETTING_DATA_BLOCK;
		3693
		3694	typedef struct _ATOM_INIT_REG_INDEX_FORMAT {
		3695	USHORT usRegIndex; /* MC register index */
		3696	UCHAR ucPreRegDataLength; /* offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf */
		3697	} ATOM_INIT_REG_INDEX_FORMAT;
		3698
		3699	typedef struct _ATOM_INIT_REG_BLOCK {
		3700	USHORT usRegIndexTblSize; /* size of asRegIndexBuf */
		3701	USHORT usRegDataBlkSize; /* size of ATOM_MEMORY_SETTING_DATA_BLOCK */
		3702	ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1];
		3703	ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1];
		3704	} ATOM_INIT_REG_BLOCK;
		3705
		3706	#define END_OF_REG_INDEX_BLOCK 0x0ffff
		3707	#define END_OF_REG_DATA_BLOCK 0x00000000
		3708	#define ATOM_INIT_REG_MASK_FLAG 0x80
		3709	#define CLOCK_RANGE_HIGHEST 0x00ffffff
		3710
		3711	#define VALUE_DWORD SIZEOF ULONG
		3712	#define VALUE_SAME_AS_ABOVE 0
		3713	#define VALUE_MASK_DWORD 0x84
		3714
		3715	#define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1)
		3716	#define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1)
		3717	#define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1)
		3718
		3719	typedef struct _ATOM_MC_INIT_PARAM_TABLE {
		3720	ATOM_COMMON_TABLE_HEADER sHeader;
		3721	USHORT usAdjustARB_SEQDataOffset;
		3722	USHORT usMCInitMemTypeTblOffset;
		3723	USHORT usMCInitCommonTblOffset;
		3724	USHORT usMCInitPowerDownTblOffset;
		3725	ULONG ulARB_SEQDataBuf[32];
		3726	ATOM_INIT_REG_BLOCK asMCInitMemType;
		3727	ATOM_INIT_REG_BLOCK asMCInitCommon;
		3728	} ATOM_MC_INIT_PARAM_TABLE;
		3729
		3730	#define _4Mx16 0x2
		3731	#define _4Mx32 0x3
		3732	#define _8Mx16 0x12
		3733	#define _8Mx32 0x13
		3734	#define _16Mx16 0x22
		3735	#define _16Mx32 0x23
		3736	#define _32Mx16 0x32
		3737	#define _32Mx32 0x33
		3738	#define _64Mx8 0x41
		3739	#define _64Mx16 0x42
		3740
		3741	#define SAMSUNG 0x1
		3742	#define INFINEON 0x2
		3743	#define ELPIDA 0x3
		3744	#define ETRON 0x4
		3745	#define NANYA 0x5
		3746	#define HYNIX 0x6
		3747	#define MOSEL 0x7
		3748	#define WINBOND 0x8
		3749	#define ESMT 0x9
		3750	#define MICRON 0xF
		3751
		3752	#define QIMONDA INFINEON
		3753	#define PROMOS MOSEL
		3754
		3755	/* ///////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// */
		3756
		3757	#define UCODE_ROM_START_ADDRESS 0x1c000
		3758	#define UCODE_SIGNATURE 0x4375434d /* 'MCuC' - MC uCode */
		3759
		3760	/* uCode block header for reference */
		3761
		3762	typedef struct _MCuCodeHeader {
		3763	ULONG ulSignature;
		3764	UCHAR ucRevision;
		3765	UCHAR ucChecksum;
		3766	UCHAR ucReserved1;
		3767	UCHAR ucReserved2;
		3768	USHORT usParametersLength;
		3769	USHORT usUCodeLength;
		3770	USHORT usReserved1;
		3771	USHORT usReserved2;
		3772	} MCuCodeHeader;
		3773
		3774	/* //////////////////////////////////////////////////////////////////////////////// */
		3775
		3776	#define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16
		3777
		3778	#define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF
		3779	typedef struct _ATOM_VRAM_MODULE_V1 {
		3780	ULONG ulReserved;
		3781	USHORT usEMRSValue;
		3782	USHORT usMRSValue;
		3783	USHORT usReserved;
		3784	UCHAR ucExtMemoryID; /* An external indicator (by hardcode, callback or pin) to tell what is the current memory module */
		3785	UCHAR ucMemoryType; /* [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; */
		3786	UCHAR ucMemoryVenderID; /* Predefined,never change across designs or memory type/vender */
		3787	UCHAR ucMemoryDeviceCfg; /* [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... */
		3788	UCHAR ucRow; /* Number of Row,in power of 2; */
		3789	UCHAR ucColumn; /* Number of Column,in power of 2; */
		3790	UCHAR ucBank; /* Nunber of Bank; */
		3791	UCHAR ucRank; /* Number of Rank, in power of 2 */
		3792	UCHAR ucChannelNum; /* Number of channel; */
		3793	UCHAR ucChannelConfig; /* [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 */
		3794	UCHAR ucDefaultMVDDQ_ID; /* Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; */
		3795	UCHAR ucDefaultMVDDC_ID; /* Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; */
		3796	UCHAR ucReserved[2];
		3797	} ATOM_VRAM_MODULE_V1;
		3798
		3799	typedef struct _ATOM_VRAM_MODULE_V2 {
		3800	ULONG ulReserved;
		3801	ULONG ulFlags; /* To enable/disable functionalities based on memory type */
		3802	ULONG ulEngineClock; /* Override of default engine clock for particular memory type */
		3803	ULONG ulMemoryClock; /* Override of default memory clock for particular memory type */
		3804	USHORT usEMRS2Value; /* EMRS2 Value is used for GDDR2 and GDDR4 memory type */
		3805	USHORT usEMRS3Value; /* EMRS3 Value is used for GDDR2 and GDDR4 memory type */
		3806	USHORT usEMRSValue;
		3807	USHORT usMRSValue;
		3808	USHORT usReserved;
		3809	UCHAR ucExtMemoryID; /* An external indicator (by hardcode, callback or pin) to tell what is the current memory module */
		3810	UCHAR ucMemoryType; /* [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; */
		3811	UCHAR ucMemoryVenderID; /* Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed */
		3812	UCHAR ucMemoryDeviceCfg; /* [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... */
		3813	UCHAR ucRow; /* Number of Row,in power of 2; */
		3814	UCHAR ucColumn; /* Number of Column,in power of 2; */
		3815	UCHAR ucBank; /* Nunber of Bank; */
		3816	UCHAR ucRank; /* Number of Rank, in power of 2 */
		3817	UCHAR ucChannelNum; /* Number of channel; */
		3818	UCHAR ucChannelConfig; /* [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 */
		3819	UCHAR ucDefaultMVDDQ_ID; /* Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; */
		3820	UCHAR ucDefaultMVDDC_ID; /* Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; */
		3821	UCHAR ucRefreshRateFactor;
		3822	UCHAR ucReserved[3];
		3823	} ATOM_VRAM_MODULE_V2;
		3824
		3825	typedef struct _ATOM_MEMORY_TIMING_FORMAT {
		3826	ULONG ulClkRange; /* memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing */
		3827	union {
		3828	USHORT usMRS; /* mode register */
		3829	USHORT usDDR3_MR0;
		3830	};
		3831	union {
		3832	USHORT usEMRS; /* extended mode register */
		3833	USHORT usDDR3_MR1;
		3834	};
		3835	UCHAR ucCL; /* CAS latency */
		3836	UCHAR ucWL; /* WRITE Latency */
		3837	UCHAR uctRAS; /* tRAS */
		3838	UCHAR uctRC; /* tRC */
		3839	UCHAR uctRFC; /* tRFC */
		3840	UCHAR uctRCDR; /* tRCDR */
		3841	UCHAR uctRCDW; /* tRCDW */
		3842	UCHAR uctRP; /* tRP */
		3843	UCHAR uctRRD; /* tRRD */
		3844	UCHAR uctWR; /* tWR */
		3845	UCHAR uctWTR; /* tWTR */
		3846	UCHAR uctPDIX; /* tPDIX */
		3847	UCHAR uctFAW; /* tFAW */
		3848	UCHAR uctAOND; /* tAOND */
		3849	union {
		3850	struct {
		3851	UCHAR ucflag; /* flag to control memory timing calculation. bit0= control EMRS2 Infineon */
		3852	UCHAR ucReserved;
		3853	};
		3854	USHORT usDDR3_MR2;
		3855	};
		3856	} ATOM_MEMORY_TIMING_FORMAT;
		3857
		3858	typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 {
		3859	ULONG ulClkRange; /* memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing */
		3860	USHORT usMRS; /* mode register */
		3861	USHORT usEMRS; /* extended mode register */
		3862	UCHAR ucCL; /* CAS latency */
		3863	UCHAR ucWL; /* WRITE Latency */
		3864	UCHAR uctRAS; /* tRAS */
		3865	UCHAR uctRC; /* tRC */
		3866	UCHAR uctRFC; /* tRFC */
		3867	UCHAR uctRCDR; /* tRCDR */
		3868	UCHAR uctRCDW; /* tRCDW */
		3869	UCHAR uctRP; /* tRP */
		3870	UCHAR uctRRD; /* tRRD */
		3871	UCHAR uctWR; /* tWR */
		3872	UCHAR uctWTR; /* tWTR */
		3873	UCHAR uctPDIX; /* tPDIX */
		3874	UCHAR uctFAW; /* tFAW */
		3875	UCHAR uctAOND; /* tAOND */
		3876	UCHAR ucflag; /* flag to control memory timing calculation. bit0= control EMRS2 Infineon */
		3877	/* ///////////////////////GDDR parameters/////////////////////////////////// */
		3878	UCHAR uctCCDL; /* */
		3879	UCHAR uctCRCRL; /* */
		3880	UCHAR uctCRCWL; /* */
		3881	UCHAR uctCKE; /* */
		3882	UCHAR uctCKRSE; /* */
		3883	UCHAR uctCKRSX; /* */
		3884	UCHAR uctFAW32; /* */
		3885	UCHAR ucReserved1; /* */
		3886	UCHAR ucReserved2; /* */
		3887	UCHAR ucTerminator;
		3888	} ATOM_MEMORY_TIMING_FORMAT_V1;
		3889
		3890	typedef struct _ATOM_MEMORY_FORMAT {
		3891	ULONG ulDllDisClock; /* memory DLL will be disable when target memory clock is below this clock */
		3892	union {
		3893	USHORT usEMRS2Value; /* EMRS2 Value is used for GDDR2 and GDDR4 memory type */
		3894	USHORT usDDR3_Reserved; /* Not used for DDR3 memory */
		3895	};
		3896	union {
		3897	USHORT usEMRS3Value; /* EMRS3 Value is used for GDDR2 and GDDR4 memory type */
		3898	USHORT usDDR3_MR3; /* Used for DDR3 memory */
		3899	};
		3900	UCHAR ucMemoryType; /* [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; */
		3901	UCHAR ucMemoryVenderID; /* Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed */
		3902	UCHAR ucRow; /* Number of Row,in power of 2; */
		3903	UCHAR ucColumn; /* Number of Column,in power of 2; */
		3904	UCHAR ucBank; /* Nunber of Bank; */
		3905	UCHAR ucRank; /* Number of Rank, in power of 2 */
		3906	UCHAR ucBurstSize; /* burst size, 0= burst size=4 1= burst size=8 */
		3907	UCHAR ucDllDisBit; /* position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) */
		3908	UCHAR ucRefreshRateFactor; /* memory refresh rate in unit of ms */
		3909	UCHAR ucDensity; /* _8Mx32, _16Mx32, _16Mx16, _32Mx16 */
		3910	UCHAR ucPreamble; /* [7:4] Write Preamble, [3:0] Read Preamble */
		3911	UCHAR ucMemAttrib; /* Memory Device Addribute, like RDBI/WDBI etc */
		3912	ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; /* Memory Timing block sort from lower clock to higher clock */
		3913	} ATOM_MEMORY_FORMAT;
		3914
		3915	typedef struct _ATOM_VRAM_MODULE_V3 {
		3916	ULONG ulChannelMapCfg; /* board dependent paramenter:Channel combination */
		3917	USHORT usSize; /* size of ATOM_VRAM_MODULE_V3 */
		3918	USHORT usDefaultMVDDQ; /* board dependent parameter:Default Memory Core Voltage */
		3919	USHORT usDefaultMVDDC; /* board dependent parameter:Default Memory IO Voltage */
		3920	UCHAR ucExtMemoryID; /* An external indicator (by hardcode, callback or pin) to tell what is the current memory module */
		3921	UCHAR ucChannelNum; /* board dependent parameter:Number of channel; */
		3922	UCHAR ucChannelSize; /* board dependent parameter:32bit or 64bit */
		3923	UCHAR ucVREFI; /* board dependnt parameter: EXT or INT +160mv to -140mv */
		3924	UCHAR ucNPL_RT; /* board dependent parameter:NPL round trip delay, used for calculate memory timing parameters */
		3925	UCHAR ucFlag; /* To enable/disable functionalities based on memory type */
		3926	ATOM_MEMORY_FORMAT asMemory; /* describ all of video memory parameters from memory spec */
		3927	} ATOM_VRAM_MODULE_V3;
		3928
		3929	/* ATOM_VRAM_MODULE_V3.ucNPL_RT */
		3930	#define NPL_RT_MASK 0x0f
		3931	#define BATTERY_ODT_MASK 0xc0
		3932
		3933	#define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3
		3934
		3935	typedef struct _ATOM_VRAM_MODULE_V4 {
		3936	ULONG ulChannelMapCfg; /* board dependent parameter: Channel combination */
		3937	USHORT usModuleSize; /* size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE */
		3938	USHORT usPrivateReserved; /* BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! */
		3939	/* MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) */
		3940	USHORT usReserved;
		3941	UCHAR ucExtMemoryID; /* An external indicator (by hardcode, callback or pin) to tell what is the current memory module */
		3942	UCHAR ucMemoryType; /* [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; */
		3943	UCHAR ucChannelNum; /* Number of channels present in this module config */
		3944	UCHAR ucChannelWidth; /* 0 - 32 bits; 1 - 64 bits */
		3945	UCHAR ucDensity; /* _8Mx32, _16Mx32, _16Mx16, _32Mx16 */
		3946	UCHAR ucFlag; /* To enable/disable functionalities based on memory type */
		3947	UCHAR ucMisc; /* bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 */
		3948	UCHAR ucVREFI; /* board dependent parameter */
		3949	UCHAR ucNPL_RT; /* board dependent parameter:NPL round trip delay, used for calculate memory timing parameters */
		3950	UCHAR ucPreamble; /* [7:4] Write Preamble, [3:0] Read Preamble */
		3951	UCHAR ucMemorySize; /* BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! */
		3952	/* Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros */
		3953	UCHAR ucReserved[3];
		3954
		3955	/* compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level */
		3956	union {
		3957	USHORT usEMRS2Value; /* EMRS2 Value is used for GDDR2 and GDDR4 memory type */
		3958	USHORT usDDR3_Reserved;
		3959	};
		3960	union {
		3961	USHORT usEMRS3Value; /* EMRS3 Value is used for GDDR2 and GDDR4 memory type */
		3962	USHORT usDDR3_MR3; /* Used for DDR3 memory */
		3963	};
		3964	UCHAR ucMemoryVenderID; /* Predefined, If not predefined, vendor detection table gets executed */
		3965	UCHAR ucRefreshRateFactor; /* [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) */
		3966	UCHAR ucReserved2[2];
		3967	ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; /* Memory Timing block sort from lower clock to higher clock */
		3968	} ATOM_VRAM_MODULE_V4;
		3969
		3970	#define VRAM_MODULE_V4_MISC_RANK_MASK 0x3
		3971	#define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1
		3972	#define VRAM_MODULE_V4_MISC_BL_MASK 0x4
		3973	#define VRAM_MODULE_V4_MISC_BL8 0x4
		3974	#define VRAM_MODULE_V4_MISC_DUAL_CS 0x10
		3975
		3976	typedef struct _ATOM_VRAM_MODULE_V5 {
		3977	ULONG ulChannelMapCfg; /* board dependent parameter: Channel combination */
		3978	USHORT usModuleSize; /* size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE */
		3979	USHORT usPrivateReserved; /* BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! */
		3980	/* MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) */
		3981	USHORT usReserved;
		3982	UCHAR ucExtMemoryID; /* An external indicator (by hardcode, callback or pin) to tell what is the current memory module */
		3983	UCHAR ucMemoryType; /* [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; */
		3984	UCHAR ucChannelNum; /* Number of channels present in this module config */
		3985	UCHAR ucChannelWidth; /* 0 - 32 bits; 1 - 64 bits */
		3986	UCHAR ucDensity; /* _8Mx32, _16Mx32, _16Mx16, _32Mx16 */
		3987	UCHAR ucFlag; /* To enable/disable functionalities based on memory type */
		3988	UCHAR ucMisc; /* bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 */
		3989	UCHAR ucVREFI; /* board dependent parameter */
		3990	UCHAR ucNPL_RT; /* board dependent parameter:NPL round trip delay, used for calculate memory timing parameters */
		3991	UCHAR ucPreamble; /* [7:4] Write Preamble, [3:0] Read Preamble */
		3992	UCHAR ucMemorySize; /* BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! */
		3993	/* Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros */
		3994	UCHAR ucReserved[3];
		3995
		3996	/* compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level */
		3997	USHORT usEMRS2Value; /* EMRS2 Value is used for GDDR2 and GDDR4 memory type */
		3998	USHORT usEMRS3Value; /* EMRS3 Value is used for GDDR2 and GDDR4 memory type */
		3999	UCHAR ucMemoryVenderID; /* Predefined, If not predefined, vendor detection table gets executed */
		4000	UCHAR ucRefreshRateFactor; /* [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) */
		4001	UCHAR ucFIFODepth; /* FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth */
		4002	UCHAR ucCDR_Bandwidth; /* [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth */
		4003	ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5]; /* Memory Timing block sort from lower clock to higher clock */
		4004	} ATOM_VRAM_MODULE_V5;
		4005
		4006	typedef struct _ATOM_VRAM_INFO_V2 {
		4007	ATOM_COMMON_TABLE_HEADER sHeader;
		4008	UCHAR ucNumOfVRAMModule;
		4009	ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; /* just for allocation, real number of blocks is in ucNumOfVRAMModule; */
		4010	} ATOM_VRAM_INFO_V2;
		4011
		4012	typedef struct _ATOM_VRAM_INFO_V3 {
		4013	ATOM_COMMON_TABLE_HEADER sHeader;
		4014	USHORT usMemAdjustTblOffset; /* offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting */
		4015	USHORT usMemClkPatchTblOffset; /* offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting */
		4016	USHORT usRerseved;
		4017	UCHAR aVID_PinsShift[9]; /* 8 bit strap maximum+terminator */
		4018	UCHAR ucNumOfVRAMModule;
		4019	ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; /* just for allocation, real number of blocks is in ucNumOfVRAMModule; */
		4020	ATOM_INIT_REG_BLOCK asMemPatch; /* for allocation */
		4021	/* ATOM_INIT_REG_BLOCK aMemAdjust; */
		4022	} ATOM_VRAM_INFO_V3;
		4023
		4024	#define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3
		4025
		4026	typedef struct _ATOM_VRAM_INFO_V4 {
		4027	ATOM_COMMON_TABLE_HEADER sHeader;
		4028	USHORT usMemAdjustTblOffset; /* offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting */
		4029	USHORT usMemClkPatchTblOffset; /* offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting */
		4030	USHORT usRerseved;
		4031	UCHAR ucMemDQ7_0ByteRemap; /* DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 */
		4032	ULONG ulMemDQ7_0BitRemap; /* each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] */
		4033	UCHAR ucReservde[4];
		4034	UCHAR ucNumOfVRAMModule;
		4035	ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; /* just for allocation, real number of blocks is in ucNumOfVRAMModule; */
		4036	ATOM_INIT_REG_BLOCK asMemPatch; /* for allocation */
		4037	/* ATOM_INIT_REG_BLOCK aMemAdjust; */
		4038	} ATOM_VRAM_INFO_V4;
		4039
		4040	typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO {
		4041	ATOM_COMMON_TABLE_HEADER sHeader;
		4042	UCHAR aVID_PinsShift[9]; /* 8 bit strap maximum+terminator */
		4043	} ATOM_VRAM_GPIO_DETECTION_INFO;
		4044
		4045	typedef struct _ATOM_MEMORY_TRAINING_INFO {
		4046	ATOM_COMMON_TABLE_HEADER sHeader;
		4047	UCHAR ucTrainingLoop;
		4048	UCHAR ucReserved[3];
		4049	ATOM_INIT_REG_BLOCK asMemTrainingSetting;
		4050	} ATOM_MEMORY_TRAINING_INFO;
		4051
		4052	typedef struct SW_I2C_CNTL_DATA_PARAMETERS {
		4053	UCHAR ucControl;
		4054	UCHAR ucData;
		4055	UCHAR ucSatus;
		4056	UCHAR ucTemp;
		4057	} SW_I2C_CNTL_DATA_PARAMETERS;
		4058
		4059	#define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS
		4060
		4061	typedef struct _SW_I2C_IO_DATA_PARAMETERS {
		4062	USHORT GPIO_Info;
		4063	UCHAR ucAct;
		4064	UCHAR ucData;
		4065	} SW_I2C_IO_DATA_PARAMETERS;
		4066
		4067	#define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS
		4068
		4069	/**************************SW I2C CNTL DEFINITIONS********************/
		4070	#define SW_I2C_IO_RESET 0
		4071	#define SW_I2C_IO_GET 1
		4072	#define SW_I2C_IO_DRIVE 2
		4073	#define SW_I2C_IO_SET 3
		4074	#define SW_I2C_IO_START 4
		4075
		4076	#define SW_I2C_IO_CLOCK 0
		4077	#define SW_I2C_IO_DATA 0x80
		4078
		4079	#define SW_I2C_IO_ZERO 0
		4080	#define SW_I2C_IO_ONE 0x100
		4081
		4082	#define SW_I2C_CNTL_READ 0
		4083	#define SW_I2C_CNTL_WRITE 1
		4084	#define SW_I2C_CNTL_START 2
		4085	#define SW_I2C_CNTL_STOP 3
		4086	#define SW_I2C_CNTL_OPEN 4
		4087	#define SW_I2C_CNTL_CLOSE 5
		4088	#define SW_I2C_CNTL_WRITE1BIT 6
		4089
		4090	/* ==============================VESA definition Portion=============================== */
		4091	#define VESA_OEM_PRODUCT_REV '01.00'
		4092	#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB /* refer to VBE spec p.32, no TTY support */
		4093	#define VESA_MODE_WIN_ATTRIBUTE 7
		4094	#define VESA_WIN_SIZE 64
		4095
		4096	typedef struct _PTR_32_BIT_STRUCTURE {
		4097	USHORT Offset16;
		4098	USHORT Segment16;
		4099	} PTR_32_BIT_STRUCTURE;
		4100
		4101	typedef union _PTR_32_BIT_UNION {
		4102	PTR_32_BIT_STRUCTURE SegmentOffset;
		4103	ULONG Ptr32_Bit;
		4104	} PTR_32_BIT_UNION;
		4105
		4106	typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE {
		4107	UCHAR VbeSignature[4];
		4108	USHORT VbeVersion;
		4109	PTR_32_BIT_UNION OemStringPtr;
		4110	UCHAR Capabilities[4];
		4111	PTR_32_BIT_UNION VideoModePtr;
		4112	USHORT TotalMemory;
		4113	} VBE_1_2_INFO_BLOCK_UPDATABLE;
		4114
		4115	typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE {
		4116	VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock;
		4117	USHORT OemSoftRev;
		4118	PTR_32_BIT_UNION OemVendorNamePtr;
		4119	PTR_32_BIT_UNION OemProductNamePtr;
		4120	PTR_32_BIT_UNION OemProductRevPtr;
		4121	} VBE_2_0_INFO_BLOCK_UPDATABLE;
		4122
		4123	typedef union _VBE_VERSION_UNION {
		4124	VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock;
		4125	VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock;
		4126	} VBE_VERSION_UNION;
		4127
		4128	typedef struct _VBE_INFO_BLOCK {
		4129	VBE_VERSION_UNION UpdatableVBE_Info;
		4130	UCHAR Reserved[222];
		4131	UCHAR OemData[256];
		4132	} VBE_INFO_BLOCK;
		4133
		4134	typedef struct _VBE_FP_INFO {
		4135	USHORT HSize;
		4136	USHORT VSize;
		4137	USHORT FPType;
		4138	UCHAR RedBPP;
		4139	UCHAR GreenBPP;
		4140	UCHAR BlueBPP;
		4141	UCHAR ReservedBPP;
		4142	ULONG RsvdOffScrnMemSize;
		4143	ULONG RsvdOffScrnMEmPtr;
		4144	UCHAR Reserved[14];
		4145	} VBE_FP_INFO;
		4146
		4147	typedef struct _VESA_MODE_INFO_BLOCK {
		4148	/* Mandatory information for all VBE revisions */
		4149	USHORT ModeAttributes; /* dw ? ; mode attributes */
		4150	UCHAR WinAAttributes; /* db ? ; window A attributes */
		4151	UCHAR WinBAttributes; /* db ? ; window B attributes */
		4152	USHORT WinGranularity; /* dw ? ; window granularity */
		4153	USHORT WinSize; /* dw ? ; window size */
		4154	USHORT WinASegment; /* dw ? ; window A start segment */
		4155	USHORT WinBSegment; /* dw ? ; window B start segment */
		4156	ULONG WinFuncPtr; /* dd ? ; real mode pointer to window function */
		4157	USHORT BytesPerScanLine; /* dw ? ; bytes per scan line */
		4158
		4159	/* ; Mandatory information for VBE 1.2 and above */
		4160	USHORT XResolution; /* dw ? ; horizontal resolution in pixels or characters */
		4161	USHORT YResolution; /* dw ? ; vertical resolution in pixels or characters */
		4162	UCHAR XCharSize; /* db ? ; character cell width in pixels */
		4163	UCHAR YCharSize; /* db ? ; character cell height in pixels */
		4164	UCHAR NumberOfPlanes; /* db ? ; number of memory planes */
		4165	UCHAR BitsPerPixel; /* db ? ; bits per pixel */
		4166	UCHAR NumberOfBanks; /* db ? ; number of banks */
		4167	UCHAR MemoryModel; /* db ? ; memory model type */
		4168	UCHAR BankSize; /* db ? ; bank size in KB */
		4169	UCHAR NumberOfImagePages; /* db ? ; number of images */
		4170	UCHAR ReservedForPageFunction; /* db 1 ; reserved for page function */
		4171
		4172	/* ; Direct Color fields(required for direct/6 and YUV/7 memory models) */
		4173	UCHAR RedMaskSize; /* db ? ; size of direct color red mask in bits */
		4174	UCHAR RedFieldPosition; /* db ? ; bit position of lsb of red mask */
		4175	UCHAR GreenMaskSize; /* db ? ; size of direct color green mask in bits */
		4176	UCHAR GreenFieldPosition; /* db ? ; bit position of lsb of green mask */
		4177	UCHAR BlueMaskSize; /* db ? ; size of direct color blue mask in bits */
		4178	UCHAR BlueFieldPosition; /* db ? ; bit position of lsb of blue mask */
		4179	UCHAR RsvdMaskSize; /* db ? ; size of direct color reserved mask in bits */
		4180	UCHAR RsvdFieldPosition; /* db ? ; bit position of lsb of reserved mask */
		4181	UCHAR DirectColorModeInfo; /* db ? ; direct color mode attributes */
		4182
		4183	/* ; Mandatory information for VBE 2.0 and above */
		4184	ULONG PhysBasePtr; /* dd ? ; physical address for flat memory frame buffer */
		4185	ULONG Reserved_1; /* dd 0 ; reserved - always set to 0 */
		4186	USHORT Reserved_2; /* dw 0 ; reserved - always set to 0 */
		4187
		4188	/* ; Mandatory information for VBE 3.0 and above */
		4189	USHORT LinBytesPerScanLine; /* dw ? ; bytes per scan line for linear modes */
		4190	UCHAR BnkNumberOfImagePages; /* db ? ; number of images for banked modes */
		4191	UCHAR LinNumberOfImagPages; /* db ? ; number of images for linear modes */
		4192	UCHAR LinRedMaskSize; /* db ? ; size of direct color red mask(linear modes) */
		4193	UCHAR LinRedFieldPosition; /* db ? ; bit position of lsb of red mask(linear modes) */
		4194	UCHAR LinGreenMaskSize; /* db ? ; size of direct color green mask(linear modes) */
		4195	UCHAR LinGreenFieldPosition; /* db ? ; bit position of lsb of green mask(linear modes) */
		4196	UCHAR LinBlueMaskSize; /* db ? ; size of direct color blue mask(linear modes) */
		4197	UCHAR LinBlueFieldPosition; /* db ? ; bit position of lsb of blue mask(linear modes) */
		4198	UCHAR LinRsvdMaskSize; /* db ? ; size of direct color reserved mask(linear modes) */
		4199	UCHAR LinRsvdFieldPosition; /* db ? ; bit position of lsb of reserved mask(linear modes) */
		4200	ULONG MaxPixelClock; /* dd ? ; maximum pixel clock(in Hz) for graphics mode */
		4201	UCHAR Reserved; /* db 190 dup (0) */
		4202	} VESA_MODE_INFO_BLOCK;
		4203
		4204	/* BIOS function CALLS */
		4205	#define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 /* ATI Extended Function code */
		4206	#define ATOM_BIOS_FUNCTION_COP_MODE 0x00
		4207	#define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04
		4208	#define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05
		4209	#define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06
		4210	#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B
		4211	#define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E
		4212	#define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F
		4213	#define ATOM_BIOS_FUNCTION_STV_STD 0x16
		4214	#define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17
		4215	#define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18
		4216
		4217	#define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82
		4218	#define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83
		4219	#define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84
		4220	#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A
		4221	#define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B
		4222	#define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 /* Sub function 80 */
		4223	#define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 /* Sub function 80 */
		4224
		4225	#define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D
		4226	#define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E
		4227	#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F
		4228	#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 /* Sub function 03 */
		4229	#define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 /* Sub function 7 */
		4230	#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 /* Notify caller the current thermal state */
		4231	#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 /* Notify caller the current critical state */
		4232	#define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 /* Sub function 85 */
		4233	#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900 /* Sub function 89 */
		4234	#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 /* Notify caller that ADC is supported */
		4235
		4236	#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 /* Set DPMS */
		4237	#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 /* BL: Sub function 01 */
		4238	#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 /* BL: Sub function 02 */
		4239	#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 /* BH Parameter for DPMS ON. */
		4240	#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 /* BH Parameter for DPMS STANDBY */
		4241	#define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 /* BH Parameter for DPMS SUSPEND */
		4242	#define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 /* BH Parameter for DPMS OFF */
		4243	#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 /* BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) */
		4244
		4245	#define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L
		4246	#define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L
		4247	#define ATOM_BIOS_REG_LOW_MASK 0x000000FFL
		4248
		4249	/* structure used for VBIOS only */
		4250
		4251	/* DispOutInfoTable */
		4252	typedef struct _ASIC_TRANSMITTER_INFO {
		4253	USHORT usTransmitterObjId;
		4254	USHORT usSupportDevice;
		4255	UCHAR ucTransmitterCmdTblId;
		4256	UCHAR ucConfig;
		4257	UCHAR ucEncoderID; /* available 1st encoder ( default ) */
		4258	UCHAR ucOptionEncoderID; /* available 2nd encoder ( optional ) */
		4259	UCHAR uc2ndEncoderID;
		4260	UCHAR ucReserved;
		4261	} ASIC_TRANSMITTER_INFO;
		4262
		4263	typedef struct _ASIC_ENCODER_INFO {
		4264	UCHAR ucEncoderID;
		4265	UCHAR ucEncoderConfig;
		4266	USHORT usEncoderCmdTblId;
		4267	} ASIC_ENCODER_INFO;
		4268
		4269	typedef struct _ATOM_DISP_OUT_INFO {
		4270	ATOM_COMMON_TABLE_HEADER sHeader;
		4271	USHORT ptrTransmitterInfo;
		4272	USHORT ptrEncoderInfo;
		4273	ASIC_TRANSMITTER_INFO asTransmitterInfo[1];
		4274	ASIC_ENCODER_INFO asEncoderInfo[1];
		4275	} ATOM_DISP_OUT_INFO;
		4276
		4277	/* DispDevicePriorityInfo */
		4278	typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO {
		4279	ATOM_COMMON_TABLE_HEADER sHeader;
		4280	USHORT asDevicePriority[16];
		4281	} ATOM_DISPLAY_DEVICE_PRIORITY_INFO;
		4282
		4283	/* ProcessAuxChannelTransactionTable */
		4284	typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS {
		4285	USHORT lpAuxRequest;
		4286	USHORT lpDataOut;
		4287	UCHAR ucChannelID;
		4288	union {
		4289	UCHAR ucReplyStatus;
		4290	UCHAR ucDelay;
		4291	};
		4292	UCHAR ucDataOutLen;
		4293	UCHAR ucReserved;
		4294	} PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS;
		4295
		4296	#define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
		4297
		4298	/* GetSinkType */
		4299
		4300	typedef struct _DP_ENCODER_SERVICE_PARAMETERS {
		4301	USHORT ucLinkClock;
		4302	union {
		4303	UCHAR ucConfig; /* for DP training command */
		4304	UCHAR ucI2cId; /* use for GET_SINK_TYPE command */
		4305	};
		4306	UCHAR ucAction;
		4307	UCHAR ucStatus;
		4308	UCHAR ucLaneNum;
		4309	UCHAR ucReserved[2];
		4310	} DP_ENCODER_SERVICE_PARAMETERS;
		4311
		4312	/* ucAction */
		4313	#define ATOM_DP_ACTION_GET_SINK_TYPE 0x01
		4314	#define ATOM_DP_ACTION_TRAINING_START 0x02
		4315	#define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03
		4316	#define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04
		4317	#define ATOM_DP_ACTION_SET_VSWING_PREEMP 0x05
		4318	#define ATOM_DP_ACTION_GET_VSWING_PREEMP 0x06
		4319	#define ATOM_DP_ACTION_BLANKING 0x07
		4320
		4321	/* ucConfig */
		4322	#define ATOM_DP_CONFIG_ENCODER_SEL_MASK 0x03
		4323	#define ATOM_DP_CONFIG_DIG1_ENCODER 0x00
		4324	#define ATOM_DP_CONFIG_DIG2_ENCODER 0x01
		4325	#define ATOM_DP_CONFIG_EXTERNAL_ENCODER 0x02
		4326	#define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04
		4327	#define ATOM_DP_CONFIG_LINK_A 0x00
		4328	#define ATOM_DP_CONFIG_LINK_B 0x04
		4329
		4330	#define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
		4331
		4332	/* DP_TRAINING_TABLE */
		4333	#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR
		4334	#define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 )
		4335	#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16)
		4336	#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24)
		4337	#define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32)
		4338	#define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40)
		4339	#define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48)
		4340	#define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60)
		4341	#define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64)
		4342	#define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72)
		4343	#define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76)
		4344	#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80)
		4345
		4346	typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS {
		4347	UCHAR ucI2CSpeed;
		4348	union {
		4349	UCHAR ucRegIndex;
		4350	UCHAR ucStatus;
		4351	};
		4352	USHORT lpI2CDataOut;
		4353	UCHAR ucFlag;
		4354	UCHAR ucTransBytes;
		4355	UCHAR ucSlaveAddr;
		4356	UCHAR ucLineNumber;
		4357	} PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS;
		4358
		4359	#define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
		4360
		4361	/* ucFlag */
		4362	#define HW_I2C_WRITE 1
		4363	#define HW_I2C_READ 0
		4364
		4365	/****************************************************************************/
		4366	/* Portion VI: Definitinos being oboselete */
		4367	/****************************************************************************/
		4368
		4369	/* ========================================================================================== */
		4370	/* Remove the definitions below when driver is ready! */
		4371	typedef struct _ATOM_DAC_INFO {
		4372	ATOM_COMMON_TABLE_HEADER sHeader;
		4373	USHORT usMaxFrequency; /* in 10kHz unit */
		4374	USHORT usReserved;
		4375	} ATOM_DAC_INFO;
		4376
		4377	typedef struct _COMPASSIONATE_DATA {
		4378	ATOM_COMMON_TABLE_HEADER sHeader;
		4379
		4380	/* ============================== DAC1 portion */
		4381	UCHAR ucDAC1_BG_Adjustment;
		4382	UCHAR ucDAC1_DAC_Adjustment;
		4383	USHORT usDAC1_FORCE_Data;
		4384	/* ============================== DAC2 portion */
		4385	UCHAR ucDAC2_CRT2_BG_Adjustment;
		4386	UCHAR ucDAC2_CRT2_DAC_Adjustment;
		4387	USHORT usDAC2_CRT2_FORCE_Data;
		4388	USHORT usDAC2_CRT2_MUX_RegisterIndex;
		4389	UCHAR ucDAC2_CRT2_MUX_RegisterInfo; /* Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low */
		4390	UCHAR ucDAC2_NTSC_BG_Adjustment;
		4391	UCHAR ucDAC2_NTSC_DAC_Adjustment;
		4392	USHORT usDAC2_TV1_FORCE_Data;
		4393	USHORT usDAC2_TV1_MUX_RegisterIndex;
		4394	UCHAR ucDAC2_TV1_MUX_RegisterInfo; /* Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low */
		4395	UCHAR ucDAC2_CV_BG_Adjustment;
		4396	UCHAR ucDAC2_CV_DAC_Adjustment;
		4397	USHORT usDAC2_CV_FORCE_Data;
		4398	USHORT usDAC2_CV_MUX_RegisterIndex;
		4399	UCHAR ucDAC2_CV_MUX_RegisterInfo; /* Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low */
		4400	UCHAR ucDAC2_PAL_BG_Adjustment;
		4401	UCHAR ucDAC2_PAL_DAC_Adjustment;
		4402	USHORT usDAC2_TV2_FORCE_Data;
		4403	} COMPASSIONATE_DATA;
		4404
		4405	/**************************Supported Device Info Table Definitions********************/
		4406	/* ucConnectInfo: */
		4407	/* [7:4] - connector type */
		4408	/* = 1 - VGA connector */
		4409	/* = 2 - DVI-I */
		4410	/* = 3 - DVI-D */
		4411	/* = 4 - DVI-A */
		4412	/* = 5 - SVIDEO */
		4413	/* = 6 - COMPOSITE */
		4414	/* = 7 - LVDS */
		4415	/* = 8 - DIGITAL LINK */
		4416	/* = 9 - SCART */
		4417	/* = 0xA - HDMI_type A */
		4418	/* = 0xB - HDMI_type B */
		4419	/* = 0xE - Special case1 (DVI+DIN) */
		4420	/* Others=TBD */
		4421	/* [3:0] - DAC Associated */
		4422	/* = 0 - no DAC */
		4423	/* = 1 - DACA */
		4424	/* = 2 - DACB */
		4425	/* = 3 - External DAC */
		4426	/* Others=TBD */
		4427	/* */
		4428
		4429	typedef struct _ATOM_CONNECTOR_INFO {
		4430	#if ATOM_BIG_ENDIAN
		4431	UCHAR bfConnectorType:4;
		4432	UCHAR bfAssociatedDAC:4;
		4433	#else
		4434	UCHAR bfAssociatedDAC:4;
		4435	UCHAR bfConnectorType:4;
		4436	#endif
		4437	} ATOM_CONNECTOR_INFO;
		4438
		4439	typedef union _ATOM_CONNECTOR_INFO_ACCESS {
		4440	ATOM_CONNECTOR_INFO sbfAccess;
		4441	UCHAR ucAccess;
		4442	} ATOM_CONNECTOR_INFO_ACCESS;
		4443
		4444	typedef struct _ATOM_CONNECTOR_INFO_I2C {
		4445	ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo;
		4446	ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
		4447	} ATOM_CONNECTOR_INFO_I2C;
		4448
		4449	typedef struct _ATOM_SUPPORTED_DEVICES_INFO {
		4450	ATOM_COMMON_TABLE_HEADER sHeader;
		4451	USHORT usDeviceSupport;
		4452	ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO];
		4453	} ATOM_SUPPORTED_DEVICES_INFO;
		4454
		4455	#define NO_INT_SRC_MAPPED 0xFF
		4456
		4457	typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP {
		4458	UCHAR ucIntSrcBitmap;
		4459	} ATOM_CONNECTOR_INC_SRC_BITMAP;
		4460
		4461	typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 {
		4462	ATOM_COMMON_TABLE_HEADER sHeader;
		4463	USHORT usDeviceSupport;
		4464	ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
		4465	ATOM_CONNECTOR_INC_SRC_BITMAP
		4466	asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
		4467	} ATOM_SUPPORTED_DEVICES_INFO_2;
		4468
		4469	typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 {
		4470	ATOM_COMMON_TABLE_HEADER sHeader;
		4471	USHORT usDeviceSupport;
		4472	ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE];
		4473	ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE];
		4474	} ATOM_SUPPORTED_DEVICES_INFO_2d1;
		4475
		4476	#define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1
		4477
		4478	typedef struct _ATOM_MISC_CONTROL_INFO {
		4479	USHORT usFrequency;
		4480	UCHAR ucPLL_ChargePump; /* PLL charge-pump gain control */
		4481	UCHAR ucPLL_DutyCycle; /* PLL duty cycle control */
		4482	UCHAR ucPLL_VCO_Gain; /* PLL VCO gain control */
		4483	UCHAR ucPLL_VoltageSwing; /* PLL driver voltage swing control */
		4484	} ATOM_MISC_CONTROL_INFO;
		4485
		4486	#define ATOM_MAX_MISC_INFO 4
		4487
		4488	typedef struct _ATOM_TMDS_INFO {
		4489	ATOM_COMMON_TABLE_HEADER sHeader;
		4490	USHORT usMaxFrequency; /* in 10Khz */
		4491	ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO];
		4492	} ATOM_TMDS_INFO;
		4493
		4494	typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE {
		4495	UCHAR ucTVStandard; /* Same as TV standards defined above, */
		4496	UCHAR ucPadding[1];
		4497	} ATOM_ENCODER_ANALOG_ATTRIBUTE;
		4498
		4499	typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE {
		4500	UCHAR ucAttribute; /* Same as other digital encoder attributes defined above */
		4501	UCHAR ucPadding[1];
		4502	} ATOM_ENCODER_DIGITAL_ATTRIBUTE;
		4503
		4504	typedef union _ATOM_ENCODER_ATTRIBUTE {
		4505	ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib;
		4506	ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib;
		4507	} ATOM_ENCODER_ATTRIBUTE;
		4508
		4509	typedef struct _DVO_ENCODER_CONTROL_PARAMETERS {
		4510	USHORT usPixelClock;
		4511	USHORT usEncoderID;
		4512	UCHAR ucDeviceType; /* Use ATOM_DEVICE_xxx1_Index to indicate device type only. */
		4513	UCHAR ucAction; /* ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT */
		4514	ATOM_ENCODER_ATTRIBUTE usDevAttr;
		4515	} DVO_ENCODER_CONTROL_PARAMETERS;
		4516
		4517	typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION {
		4518	DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder;
		4519	WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; /* Caller doesn't need to init this portion */
		4520	} DVO_ENCODER_CONTROL_PS_ALLOCATION;
		4521
		4522	#define ATOM_XTMDS_ASIC_SI164_ID 1
		4523	#define ATOM_XTMDS_ASIC_SI178_ID 2
		4524	#define ATOM_XTMDS_ASIC_TFP513_ID 3
		4525	#define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001
		4526	#define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002
		4527	#define ATOM_XTMDS_MVPU_FPGA 0x00000004
		4528
		4529	typedef struct _ATOM_XTMDS_INFO {
		4530	ATOM_COMMON_TABLE_HEADER sHeader;
		4531	USHORT usSingleLinkMaxFrequency;
		4532	ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; /* Point the ID on which I2C is used to control external chip */
		4533	UCHAR ucXtransimitterID;
		4534	UCHAR ucSupportedLink; /* Bit field, bit0=1, single link supported;bit1=1,dual link supported */
		4535	UCHAR ucSequnceAlterID; /* Even with the same external TMDS asic, it's possible that the program seqence alters */
		4536	/* due to design. This ID is used to alert driver that the sequence is not "standard"! */
		4537	UCHAR ucMasterAddress; /* Address to control Master xTMDS Chip */
		4538	UCHAR ucSlaveAddress; /* Address to control Slave xTMDS Chip */
		4539	} ATOM_XTMDS_INFO;
		4540
		4541	typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS {
		4542	UCHAR ucEnable; /* ATOM_ENABLE=On or ATOM_DISABLE=Off */
		4543	UCHAR ucDevice; /* ATOM_DEVICE_DFP1_INDEX.... */
		4544	UCHAR ucPadding[2];
		4545	} DFP_DPMS_STATUS_CHANGE_PARAMETERS;
		4546
		4547	/**************************Legacy Power Play Table Definitions ********************/
		4548
		4549	/* Definitions for ulPowerPlayMiscInfo */
		4550	#define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L
		4551	#define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L
		4552	#define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L
		4553
		4554	#define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L
		4555	#define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L
		4556
		4557	#define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L
		4558
		4559	#define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L
		4560	#define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L
		4561	#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L /* When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program */
		4562
		4563	#define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L
		4564	#define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L
		4565	#define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L
		4566	#define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L
		4567	#define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L
		4568	#define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L
		4569	#define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L
		4570
		4571	#define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L
		4572	#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L
		4573	#define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L
		4574	#define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L
		4575	#define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L
		4576
		4577	#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L /* 0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved */
		4578	#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20
		4579
		4580	#define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L
		4581	#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L
		4582	#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L
		4583	#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L /* When set, Dynamic */
		4584	#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L /* When set, Dynamic */
		4585	#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L /* When set, This mode is for acceleated 3D mode */
		4586
		4587	#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L /* 1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) */
		4588	#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28
		4589	#define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L
		4590
		4591	#define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L
		4592	#define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L
		4593	#define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L
		4594	#define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L
		4595	#define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L
		4596	#define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L
		4597	#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L /* If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. */
		4598	/* If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback */
		4599	#define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L
		4600	#define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L
		4601	#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L
		4602
		4603	/* ucTableFormatRevision=1 */
		4604	/* ucTableContentRevision=1 */
		4605	typedef struct _ATOM_POWERMODE_INFO {
		4606	ULONG ulMiscInfo; /* The power level should be arranged in ascending order */
		4607	ULONG ulReserved1; /* must set to 0 */
		4608	ULONG ulReserved2; /* must set to 0 */
		4609	USHORT usEngineClock;
		4610	USHORT usMemoryClock;
		4611	UCHAR ucVoltageDropIndex; /* index to GPIO table */
		4612	UCHAR ucSelectedPanel_RefreshRate; /* panel refresh rate */
		4613	UCHAR ucMinTemperature;
		4614	UCHAR ucMaxTemperature;
		4615	UCHAR ucNumPciELanes; /* number of PCIE lanes */
		4616	} ATOM_POWERMODE_INFO;
		4617
		4618	/* ucTableFormatRevision=2 */
		4619	/* ucTableContentRevision=1 */
		4620	typedef struct _ATOM_POWERMODE_INFO_V2 {
		4621	ULONG ulMiscInfo; /* The power level should be arranged in ascending order */
		4622	ULONG ulMiscInfo2;
		4623	ULONG ulEngineClock;
		4624	ULONG ulMemoryClock;
		4625	UCHAR ucVoltageDropIndex; /* index to GPIO table */
		4626	UCHAR ucSelectedPanel_RefreshRate; /* panel refresh rate */
		4627	UCHAR ucMinTemperature;
		4628	UCHAR ucMaxTemperature;
		4629	UCHAR ucNumPciELanes; /* number of PCIE lanes */
		4630	} ATOM_POWERMODE_INFO_V2;
		4631
		4632	/* ucTableFormatRevision=2 */
		4633	/* ucTableContentRevision=2 */
		4634	typedef struct _ATOM_POWERMODE_INFO_V3 {
		4635	ULONG ulMiscInfo; /* The power level should be arranged in ascending order */
		4636	ULONG ulMiscInfo2;
		4637	ULONG ulEngineClock;
		4638	ULONG ulMemoryClock;
		4639	UCHAR ucVoltageDropIndex; /* index to Core (VDDC) votage table */
		4640	UCHAR ucSelectedPanel_RefreshRate; /* panel refresh rate */
		4641	UCHAR ucMinTemperature;
		4642	UCHAR ucMaxTemperature;
		4643	UCHAR ucNumPciELanes; /* number of PCIE lanes */
		4644	UCHAR ucVDDCI_VoltageDropIndex; /* index to VDDCI votage table */
		4645	} ATOM_POWERMODE_INFO_V3;
		4646
		4647	#define ATOM_MAX_NUMBEROF_POWER_BLOCK 8
		4648
		4649	#define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01
		4650	#define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02
		4651
		4652	#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01
		4653	#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02
		4654	#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03
		4655	#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04
		4656	#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05
		4657	#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06
		4658	#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 /* Andigilog */
		4659
		4660	typedef struct _ATOM_POWERPLAY_INFO {
		4661	ATOM_COMMON_TABLE_HEADER sHeader;
		4662	UCHAR ucOverdriveThermalController;
		4663	UCHAR ucOverdriveI2cLine;
		4664	UCHAR ucOverdriveIntBitmap;
		4665	UCHAR ucOverdriveControllerAddress;
		4666	UCHAR ucSizeOfPowerModeEntry;
		4667	UCHAR ucNumOfPowerModeEntries;
		4668	ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
		4669	} ATOM_POWERPLAY_INFO;
		4670
		4671	typedef struct _ATOM_POWERPLAY_INFO_V2 {
		4672	ATOM_COMMON_TABLE_HEADER sHeader;
		4673	UCHAR ucOverdriveThermalController;
		4674	UCHAR ucOverdriveI2cLine;
		4675	UCHAR ucOverdriveIntBitmap;
		4676	UCHAR ucOverdriveControllerAddress;
		4677	UCHAR ucSizeOfPowerModeEntry;
		4678	UCHAR ucNumOfPowerModeEntries;
		4679	ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
		4680	} ATOM_POWERPLAY_INFO_V2;
		4681
		4682	typedef struct _ATOM_POWERPLAY_INFO_V3 {
		4683	ATOM_COMMON_TABLE_HEADER sHeader;
		4684	UCHAR ucOverdriveThermalController;
		4685	UCHAR ucOverdriveI2cLine;
		4686	UCHAR ucOverdriveIntBitmap;
		4687	UCHAR ucOverdriveControllerAddress;
		4688	UCHAR ucSizeOfPowerModeEntry;
		4689	UCHAR ucNumOfPowerModeEntries;
		4690	ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
		4691	} ATOM_POWERPLAY_INFO_V3;
		4692
		4693	/**************************************************************************/
		4694
		4695	/* Following definitions are for compatiblity issue in different SW components. */
		4696	#define ATOM_MASTER_DATA_TABLE_REVISION 0x01
		4697	#define Object_Info Object_Header
		4698	#define AdjustARB_SEQ MC_InitParameter
		4699	#define VRAM_GPIO_DetectionInfo VoltageObjectInfo
		4700	#define ASIC_VDDCI_Info ASIC_ProfilingInfo
		4701	#define ASIC_MVDDQ_Info MemoryTrainingInfo
		4702	#define SS_Info PPLL_SS_Info
		4703	#define ASIC_MVDDC_Info ASIC_InternalSS_Info
		4704	#define DispDevicePriorityInfo SaveRestoreInfo
		4705	#define DispOutInfo TV_VideoMode
		4706
		4707	#define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE
		4708	#define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE
		4709
		4710	/* New device naming, remove them when both DAL/VBIOS is ready */
		4711	#define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS
		4712	#define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS
		4713
		4714	#define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS
		4715	#define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS
		4716
		4717	#define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS
		4718	#define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION
		4719
		4720	#define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT
		4721	#define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT
		4722
		4723	#define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX
		4724	#define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX
		4725
		4726	#define ATOM_DEVICE_DFP2I_INDEX 0x00000009
		4727	#define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX)
		4728
		4729	#define ATOM_S0_DFP1I ATOM_S0_DFP1
		4730	#define ATOM_S0_DFP1X ATOM_S0_DFP2
		4731
		4732	#define ATOM_S0_DFP2I 0x00200000L
		4733	#define ATOM_S0_DFP2Ib2 0x20
		4734
		4735	#define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE
		4736	#define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE
		4737
		4738	#define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L
		4739	#define ATOM_S2_DFP2I_DPMS_STATEb3 0x02
		4740
		4741	#define ATOM_S3_DFP2I_ACTIVEb1 0x02
		4742
		4743	#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE
		4744	#define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE
		4745
		4746	#define ATOM_S3_DFP2I_ACTIVE 0x00000200L
		4747
		4748	#define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE
		4749	#define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE
		4750	#define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L
		4751
		4752	#define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02
		4753	#define ATOM_S5_DOS_REQ_DFP2Ib1 0x02
		4754
		4755	#define ATOM_S5_DOS_REQ_DFP2I 0x0200
		4756	#define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1
		4757	#define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2
		4758
		4759	#define ATOM_S6_ACC_REQ_DFP2Ib3 0x02
		4760	#define ATOM_S6_ACC_REQ_DFP2I 0x02000000L
		4761
		4762	#define TMDS1XEncoderControl DVOEncoderControl
		4763	#define DFP1XOutputControl DVOOutputControl
		4764
		4765	#define ExternalDFPOutputControl DFP1XOutputControl
		4766	#define EnableExternalTMDS_Encoder TMDS1XEncoderControl
		4767
		4768	#define DFP1IOutputControl TMDSAOutputControl
		4769	#define DFP2IOutputControl LVTMAOutputControl
		4770
		4771	#define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS
		4772	#define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
		4773
		4774	#define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS
		4775	#define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
		4776
		4777	#define ucDac1Standard ucDacStandard
		4778	#define ucDac2Standard ucDacStandard
		4779
		4780	#define TMDS1EncoderControl TMDSAEncoderControl
		4781	#define TMDS2EncoderControl LVTMAEncoderControl
		4782
		4783	#define DFP1OutputControl TMDSAOutputControl
		4784	#define DFP2OutputControl LVTMAOutputControl
		4785	#define CRT1OutputControl DAC1OutputControl
		4786	#define CRT2OutputControl DAC2OutputControl
		4787
		4788	/* These two lines will be removed for sure in a few days, will follow up with Michael V. */
		4789	#define EnableLVDS_SS EnableSpreadSpectrumOnPPLL
		4790	#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL
		4791
		4792	/*********************************************************************************/
		4793
		4794	#pragma pack() /* BIOS data must use byte aligment */
		4795
		4796	#endif /* _ATOMBIOS_H */

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(root)/drivers/video/drm/radeon/atombios.h – Rev 1179