WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/main.c

Rev	Author	Line No.	Line
6084	serge	1	#include
		2
3031	serge	3	#include
		4	#include
2338	Serge	5	#include "i915_drv.h"
		6
2325	Serge	7	#include
		8	#include
		9	#include
		10	#include
6660	serge	11	#include
		12	#include "../drm_internal.h"
2325	Serge	13
6088	serge	14	#include "getopt.h"
		15
2342	Serge	16	#include "bitmap.h"
6088	serge	17	#include "i915_kos32.h"
2340	Serge	18
7144	serge	19	#define DRV_NAME "i915 v4.6.7"
6084	serge	20
5060	serge	21	#define I915_DEV_CLOSE 0
		22	#define I915_DEV_INIT 1
		23	#define I915_DEV_READY 2
		24
6937	serge	25	int printf ( const char * format, ... );
		26
6088	serge	27	static int my_atoi(char **cmd);
		28	static char* parse_mode(char p, videomode_t mode);
5354	serge	29	void cpu_detect1();
		30	int kmap_init();
6660	serge	31	int fake_framebuffer_create();
		32	int i915_init(void);
		33	int init_display_kms(struct drm_device dev, videomode_t usermode);
		34	int get_videomodes(videomode_t mode, int count);
		35	int set_user_mode(videomode_t *mode);
		36	int i915_fbinfo(struct drm_i915_fb_info *fb);
		37	int i915_mask_update_ex(struct drm_device dev, void data,
		38	struct drm_file *file);
2344	Serge	39
6660	serge	40
		41
5060	serge	42	unsigned long volatile jiffies;
6088	serge	43	int oops_in_progress;
		44	int x86_clflush_size;
		45	unsigned int tsc_khz;
3482	Serge	46	struct workqueue_struct *system_wq;
6937	serge	47	volatile int driver_wq_state;
6088	serge	48	struct drm_device *main_device;
		49	struct drm_file *drm_file_handlers[256];
		50	videomode_t usermode;
		51	extern int __getopt_initialized;
3482	Serge	52
4126	Serge	53	void i915_driver_thread()
		54	{
5060	serge	55	struct drm_i915_private *dev_priv = NULL;
		56	struct workqueue_struct *cwq = NULL;
4126	Serge	57	static int dpms = 1;
		58	static int dpms_lock = 0;
		59	oskey_t key;
		60	unsigned long irqflags;
		61	int tmp;
		62
5060	serge	63	while(driver_wq_state == I915_DEV_INIT)
		64	{
6084	serge	65	jiffies = GetClockNs() / 10000000;
5060	serge	66	delay(1);
		67	};
		68
6084	serge	69	if( driver_wq_state == I915_DEV_CLOSE)
		70	asm volatile ("int $0x40"::"a"(-1));
		71
5060	serge	72	dev_priv = main_device->dev_private;
		73
4126	Serge	74	asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(1),"c"(1));
		75	asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0x46),"d"(0x330));
		76	asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0xC6),"d"(0x330));
		77
5060	serge	78	while(driver_wq_state != I915_DEV_CLOSE)
4126	Serge	79	{
6084	serge	80	jiffies = GetClockNs() / 10000000;
5060	serge	81
4126	Serge	82	key = get_key();
		83
		84	if( (key.val != 1) && (key.state == 0x02))
		85	{
		86	if(key.code == 0x46 && dpms_lock == 0)
		87	{
		88	dpms_lock = 1;
		89	if(dpms == 1)
		90	{
		91	i915_dpms(main_device, DRM_MODE_DPMS_OFF);
		92	printf("dpms off\n");
		93	}
		94	else
		95	{
		96	i915_dpms(main_device, DRM_MODE_DPMS_ON);
		97	printf("dpms on\n");
		98	};
		99	dpms ^= 1;
		100	}
		101	else if(key.code == 0xC6)
		102	dpms_lock = 0;
		103	};
6296	serge	104	cwq = dev_priv->wq;
4126	Serge	105
		106	spin_lock_irqsave(&cwq->lock, irqflags);
6296	serge	107	while (!list_empty(&cwq->worklist))
		108	{
		109	struct work_struct *work = list_entry(cwq->worklist.next,
		110	struct work_struct, entry);
		111	work_func_t f = work->func;
		112	list_del_init(cwq->worklist.next);
4126	Serge	113
6296	serge	114	spin_unlock_irqrestore(&cwq->lock, irqflags);
		115	f(work);
		116	spin_lock_irqsave(&cwq->lock, irqflags);
		117	}
		118	spin_unlock_irqrestore(&cwq->lock, irqflags);
		119
		120	cwq = dev_priv->hotplug.dp_wq;
		121
		122	spin_lock_irqsave(&cwq->lock, irqflags);
4126	Serge	123	while (!list_empty(&cwq->worklist))
		124	{
		125	struct work_struct *work = list_entry(cwq->worklist.next,
		126	struct work_struct, entry);
		127	work_func_t f = work->func;
		128	list_del_init(cwq->worklist.next);
		129
		130	spin_unlock_irqrestore(&cwq->lock, irqflags);
		131	f(work);
		132	spin_lock_irqsave(&cwq->lock, irqflags);
		133	}
		134	spin_unlock_irqrestore(&cwq->lock, irqflags);
		135
		136	delay(1);
		137	};
		138
		139	asm volatile ("int $0x40"::"a"(-1));
		140	}
		141
5354	serge	142	u32 __attribute__((externally_visible)) drvEntry(int action, char *cmdline)
2325	Serge	143	{
5060	serge	144	static pci_dev_t device;
		145	const struct pci_device_id *ent;
6088	serge	146	char *safecmdline;
4104	Serge	147	int err = 0;
2325	Serge	148
		149	if(action != 1)
3764	Serge	150	{
5060	serge	151	driver_wq_state = I915_DEV_CLOSE;
2325	Serge	152	return 0;
3764	Serge	153	};
2325	Serge	154
		155	if( GetService("DISPLAY") != 0 )
		156	return 0;
		157
6283	serge	158	printf("\n%s build %s %s\nusage: i915 [options]\n",
6084	serge	159	DRV_NAME, __DATE__, __TIME__);
		160
6088	serge	161	printf("--rc6 <-1,0-7> Enable power-saving render C-state 6.\n"
		162	" Different stages can be selected via bitmask values\n"
		163	" (0 = disable; 1 = enable rc6; 2 = enable deep rc6;\n"
		164	" 4 = enable deepest rc6).\n"
		165	" For example, 3 would enable rc6 and deep rc6,\n"
		166	" and 7 would enable everything.\n"
		167	" default: -1 (use per-chip default)\n");
		168	printf("--fbc <-1,0,1> Enable frame buffer compression for power savings\n"
		169	" (default: -1 (use per-chip default))\n");
		170	printf("-l\n"
		171	"--log path to log file\n");
		172	printf("-m\n"
		173	"--mode set videomode\n");
		174	printf("-v\n"
		175	"--video :x[M][R][-][@][i][m][eDd]\n"
		176	" set videomode for CONNECTOR\n");
6084	serge	177
2340	Serge	178	if( cmdline && *cmdline )
6088	serge	179	{
		180	int argc, i, c;
		181	char **argv;
2325	Serge	182
6088	serge	183	safecmdline = __builtin_strdup(cmdline);
		184	printf("cmdline %s\n", safecmdline);
		185
		186	argc = split_cmdline(safecmdline, NULL);
		187	argv = __builtin_malloc((argc+1)sizeof(char));
		188	split_cmdline(safecmdline, argv);
		189	argv[argc] = NULL;
		190
		191	while(1)
		192	{
		193	static struct option long_options[] =
		194	{
		195	{"log", required_argument, 0, 'l'},
		196	{"mode", required_argument, 0, 'm'},
		197	{"video", required_argument, 0, 'v'},
		198	{"rc6", required_argument, 0, OPTION_RC6},
		199	{"fbc", required_argument, 0, OPTION_FBC},
		200	{0, 0, 0, 0}
		201	};
		202
		203	int option_index = 0;
		204
6283	serge	205	c = getopt_long (argc, argv, "l:m:v:",
6088	serge	206	long_options, &option_index);
		207
		208	if (c == -1)
		209	break;
		210
		211	switch(c)
		212	{
		213	case OPTION_RC6:
		214	i915.enable_rc6 = my_atoi(&optarg);
		215	printf("i915.rc6 = %d\n",i915.enable_rc6);
		216	break;
		217
		218	case OPTION_FBC:
		219	i915.enable_fbc = my_atoi(&optarg);
		220	printf("i915.fbc = %d\n",i915.enable_fbc);
		221	break;
		222
		223	case 'l':
		224	i915.log_file = optarg;
		225	break;
		226
		227	case 'm':
		228	parse_mode(optarg, &usermode);
		229	break;
		230
		231	case 'v':
		232	i915.cmdline_mode = optarg;
		233	printf("i915.cmdline_mode =%s\n",i915.cmdline_mode);
		234	break;
		235	}
		236	}
		237	};
		238
		239	if( i915.log_file && !dbg_open(i915.log_file))
6084	serge	240	{
6088	serge	241	printf("Can't open %s\nExit\n", i915.log_file);
6084	serge	242	return 0;
2325	Serge	243	}
6084	serge	244	else
		245	{
		246	dbgprintf("\nLOG: %s build %s %s\n",DRV_NAME,__DATE__, __TIME__);
		247	}
2325	Serge	248
5354	serge	249	cpu_detect1();
2351	Serge	250
5060	serge	251	err = enum_pci_devices();
		252	if( unlikely(err != 0) )
		253	{
		254	dbgprintf("Device enumeration failed\n");
		255	return 0;
		256	}
2325	Serge	257
5354	serge	258	err = kmap_init();
		259	if( unlikely(err != 0) )
		260	{
		261	dbgprintf("kmap initialization failed\n");
		262	return 0;
		263	}
		264
5097	serge	265	dmi_scan_machine();
		266
6320	serge	267	err = fake_framebuffer_create();
		268	if( unlikely(err != 0))
		269	return 0;
		270
5060	serge	271	driver_wq_state = I915_DEV_INIT;
		272	CreateKernelThread(i915_driver_thread);
		273
2325	Serge	274	err = i915_init();
5060	serge	275	if(unlikely(err!= 0))
2338	Serge	276	{
5060	serge	277	driver_wq_state = I915_DEV_CLOSE;
3298	Serge	278	dbgprintf("Epic Fail :(\n");
6084	serge	279	delay(100);
3298	Serge	280	return 0;
2338	Serge	281	};
2325	Serge	282
5060	serge	283	driver_wq_state = I915_DEV_READY;
		284
4280	Serge	285	init_display_kms(main_device, &usermode);
		286
2338	Serge	287	err = RegService("DISPLAY", display_handler);
2325	Serge	288
2338	Serge	289	if( err != 0)
		290	dbgprintf("Set DISPLAY handler\n");
		291
2325	Serge	292	return err;
		293	};
		294
6088	serge	295	int do_command_line(const char* usercmd)
		296	{
		297	char *cmdline;
		298	int argc, i, c;
		299	char **argv;
6103	serge	300	int retval = 0;
3480	Serge	301
6088	serge	302	if( (usercmd == NULL) \|\| (*usercmd == 0) )
		303	return 1;
		304
		305	cmdline = __builtin_strdup(usercmd);
		306	printf("cmdline %s\n", cmdline);
		307
		308	argc = split_cmdline(cmdline, NULL);
		309	argv = __builtin_malloc((argc+1)sizeof(char));
		310	split_cmdline(cmdline, argv);
		311	argv[argc] = NULL;
		312
		313	__getopt_initialized = 0;
		314
		315	while(1)
		316	{
		317	static struct option long_options[] =
		318	{
6103	serge	319	{"list-connectors", no_argument, 0, OPTION_CONNECTORS},
		320	{"list-connector-modes", required_argument, 0, OPTION_CONN_MODES},
		321	{"video", required_argument, 0, 'v'},
6088	serge	322	{0, 0, 0, 0}
		323	};
		324
		325	int option_index = 0;
		326
		327	c = getopt_long (argc, argv, "v:",
		328	long_options, &option_index);
		329
		330	if (c == -1)
		331	break;
		332
		333	switch(c)
		334	{
		335	case 'v':
		336	printf("cmdline_mode %s\n",optarg);
6103	serge	337	retval = set_cmdline_mode_ext(main_device, optarg);
6088	serge	338	break;
6103	serge	339
		340	case OPTION_CONNECTORS:
		341	list_connectors(main_device);
		342	break;
		343
		344	case OPTION_CONN_MODES:
		345	retval = list_connector_modes(main_device, optarg);
		346	break;
6088	serge	347	}
		348	}
		349	__builtin_free(argv);
		350	__builtin_free(cmdline);
		351
6103	serge	352	return retval;
6088	serge	353	};
		354
2344	Serge	355	#define CURRENT_API 0x0200 /* 2.00 */
		356	#define COMPATIBLE_API 0x0100 /* 1.00 */
2338	Serge	357
2344	Serge	358	#define API_VERSION (COMPATIBLE_API << 16) \| CURRENT_API
2351	Serge	359	#define DISPLAY_VERSION API_VERSION
2338	Serge	360
		361
6084	serge	362	#define SRV_GETVERSION 0
		363	#define SRV_ENUM_MODES 1
		364	#define SRV_SET_MODE 2
		365	#define SRV_GET_CAPS 3
6088	serge	366	#define SRV_CMDLINE 4
2342	Serge	367
6084	serge	368	#define SRV_GET_PCI_INFO 20
4246	Serge	369	#define SRV_I915_GET_PARAM 21
6084	serge	370	#define SRV_I915_GEM_CREATE 22
		371	#define SRV_DRM_GEM_CLOSE 23
4246	Serge	372	#define SRV_DRM_GEM_FLINK 24
		373	#define SRV_DRM_GEM_OPEN 25
		374	#define SRV_I915_GEM_PIN 26
		375	#define SRV_I915_GEM_UNPIN 27
5367	serge	376	#define SRV_I915_GEM_GET_CACHING 28
		377	#define SRV_I915_GEM_SET_CACHING 29
		378	#define SRV_I915_GEM_PWRITE 30
		379	#define SRV_I915_GEM_BUSY 31
		380	#define SRV_I915_GEM_SET_DOMAIN 32
		381	#define SRV_I915_GEM_MMAP 33
		382	#define SRV_I915_GEM_SET_TILING 34
		383	#define SRV_I915_GEM_GET_TILING 35
		384	#define SRV_I915_GEM_GET_APERTURE 36
		385	#define SRV_I915_GEM_MMAP_GTT 37
		386	#define SRV_I915_GEM_THROTTLE 38
		387	#define SRV_I915_GEM_EXECBUFFER2 39
		388	#define SRV_I915_GEM_WAIT 40
		389	#define SRV_I915_GEM_CONTEXT_CREATE 41
		390	#define SRV_I915_GEM_CONTEXT_DESTROY 42
		391	#define SRV_I915_REG_READ 43
3260	Serge	392
5367	serge	393	#define SRV_FBINFO 44
		394	#define SRV_MASK_UPDATE 45
		395	#define SRV_MASK_UPDATE_EX 46
3263	Serge	396
6131	serge	397	#define SRV_I915_GEM_PREAD 47
		398
2338	Serge	399	#define check_input(size) \
		400	if( unlikely((inp==NULL)\|\|(io->inp_size != (size))) ) \
		401	break;
		402
		403	#define check_output(size) \
		404	if( unlikely((outp==NULL)\|\|(io->out_size != (size))) ) \
		405	break;
		406
		407	int _stdcall display_handler(ioctl_t *io)
		408	{
3255	Serge	409	struct drm_file *file;
		410
6084	serge	411	int retval = -1;
5354	serge	412	u32 *inp;
		413	u32 *outp;
2338	Serge	414
		415	inp = io->input;
		416	outp = io->output;
		417
3255	Serge	418	file = drm_file_handlers[0];
		419
2338	Serge	420	switch(io->io_code)
		421	{
		422	case SRV_GETVERSION:
		423	check_output(4);
2344	Serge	424	*outp = DISPLAY_VERSION;
2338	Serge	425	retval = 0;
		426	break;
		427
		428	case SRV_ENUM_MODES:
3031	serge	429	// dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",
		430	// inp, io->inp_size, io->out_size );
2340	Serge	431	check_output(4);
2338	Serge	432	// check_input(outp sizeof(videomode_t));
6088	serge	433	retval = get_videomodes((videomode_t*)inp, outp);
2338	Serge	434	break;
		435
		436	case SRV_SET_MODE:
3031	serge	437	// dbgprintf("SRV_SET_MODE inp %x inp_size %x\n",
		438	// inp, io->inp_size);
2338	Serge	439	check_input(sizeof(videomode_t));
6088	serge	440	retval = set_user_mode((videomode_t*)inp);
2338	Serge	441	break;
3033	serge	442
2351	Serge	443	case SRV_GET_CAPS:
		444	retval = get_driver_caps((hwcaps_t*)inp);
		445	break;
		446
6088	serge	447	case SRV_CMDLINE:
		448	retval = do_command_line((char*)inp);
		449	break;
		450
3260	Serge	451	case SRV_GET_PCI_INFO:
3255	Serge	452	get_pci_info((struct pci_device *)inp);
2338	Serge	453	retval = 0;
		454	break;
3031	serge	455
4246	Serge	456	case SRV_I915_GET_PARAM:
		457	retval = i915_getparam(main_device, inp, file);
3255	Serge	458	break;
		459
		460	case SRV_I915_GEM_CREATE:
		461	retval = i915_gem_create_ioctl(main_device, inp, file);
		462	break;
		463
		464	case SRV_DRM_GEM_CLOSE:
		465	retval = drm_gem_close_ioctl(main_device, inp, file);
		466	break;
		467
4246	Serge	468	case SRV_DRM_GEM_FLINK:
		469	retval = drm_gem_flink_ioctl(main_device, inp, file);
		470	break;
		471
		472	case SRV_DRM_GEM_OPEN:
		473	retval = drm_gem_open_ioctl(main_device, inp, file);
		474	break;
		475
5367	serge	476	case SRV_I915_GEM_GET_CACHING:
		477	retval = i915_gem_get_caching_ioctl(main_device, inp, file);
		478	break;
		479
4246	Serge	480	case SRV_I915_GEM_SET_CACHING:
		481	retval = i915_gem_set_caching_ioctl(main_device, inp, file);
3260	Serge	482	break;
		483
6131	serge	484	case SRV_I915_GEM_PREAD:
		485	retval = i915_gem_pread_ioctl(main_device, inp, file);
		486	break;
		487
3260	Serge	488	case SRV_I915_GEM_PWRITE:
		489	retval = i915_gem_pwrite_ioctl(main_device, inp, file);
		490	break;
		491
		492	case SRV_I915_GEM_BUSY:
		493	retval = i915_gem_busy_ioctl(main_device, inp, file);
		494	break;
		495
		496	case SRV_I915_GEM_SET_DOMAIN:
		497	retval = i915_gem_set_domain_ioctl(main_device, inp, file);
		498	break;
		499
3263	Serge	500	case SRV_I915_GEM_MMAP:
		501	retval = i915_gem_mmap_ioctl(main_device, inp, file);
		502	break;
		503
4246	Serge	504	case SRV_I915_GEM_SET_TILING:
		505	retval = i915_gem_set_tiling(main_device, inp, file);
		506	break;
		507
		508	case SRV_I915_GEM_GET_TILING:
		509	retval = i915_gem_get_tiling(main_device, inp, file);
		510	break;
		511
		512	case SRV_I915_GEM_GET_APERTURE:
		513	// printf("SRV_I915_GEM_GET_APERTURE ");
		514	retval = i915_gem_get_aperture_ioctl(main_device, inp, file);
		515	// printf(" retval=%d\n", retval);
		516	break;
		517
3480	Serge	518	case SRV_I915_GEM_MMAP_GTT:
		519	retval = i915_gem_mmap_gtt_ioctl(main_device, inp, file);
		520	break;
		521
4246	Serge	522	case SRV_I915_GEM_THROTTLE:
		523	retval = i915_gem_throttle_ioctl(main_device, inp, file);
3263	Serge	524	break;
		525
		526	case SRV_I915_GEM_EXECBUFFER2:
		527	retval = i915_gem_execbuffer2(main_device, inp, file);
		528	break;
		529
4246	Serge	530	case SRV_I915_GEM_WAIT:
		531	retval = i915_gem_wait_ioctl(main_device, inp, file);
		532	break;
		533
		534	case SRV_I915_GEM_CONTEXT_CREATE:
		535	retval = i915_gem_context_create_ioctl(main_device, inp, file);
		536	break;
		537
		538	case SRV_I915_GEM_CONTEXT_DESTROY:
		539	retval = i915_gem_context_destroy_ioctl(main_device, inp, file);
		540	break;
		541
		542	case SRV_I915_REG_READ:
		543	retval = i915_reg_read_ioctl(main_device, inp, file);
		544	break;
		545
		546	case SRV_FBINFO:
6660	serge	547	retval = i915_fbinfo((struct drm_i915_fb_info*)inp);
4246	Serge	548	break;
		549
3290	Serge	550	case SRV_MASK_UPDATE:
		551	retval = i915_mask_update(main_device, inp, file);
		552	break;
4539	Serge	553
		554	case SRV_MASK_UPDATE_EX:
		555	retval = i915_mask_update_ex(main_device, inp, file);
		556	break;
2338	Serge	557	};
		558
		559	return retval;
		560	}
		561
		562
2325	Serge	563	#define PCI_CLASS_REVISION 0x08
		564	#define PCI_CLASS_DISPLAY_VGA 0x0300
		565	#define PCI_CLASS_BRIDGE_HOST 0x0600
2326	Serge	566	#define PCI_CLASS_BRIDGE_ISA 0x0601
2325	Serge	567
5354	serge	568	int pci_scan_filter(u32 id, u32 busnr, u32 devfn)
2325	Serge	569	{
5354	serge	570	u16 vendor, device;
		571	u32 class;
2325	Serge	572	int ret = 0;
		573
		574	vendor = id & 0xffff;
		575	device = (id >> 16) & 0xffff;
		576
		577	if(vendor == 0x8086)
		578	{
		579	class = PciRead32(busnr, devfn, PCI_CLASS_REVISION);
		580	class >>= 16;
		581
		582	if( (class == PCI_CLASS_DISPLAY_VGA) \|\|
2326	Serge	583	(class == PCI_CLASS_BRIDGE_HOST) \|\|
		584	(class == PCI_CLASS_BRIDGE_ISA))
2325	Serge	585	ret = 1;
		586	}
		587	return ret;
		588	};
2340	Serge	589
		590
5060	serge	591	struct mtrr
		592	{
5354	serge	593	u64 base;
		594	u64 mask;
5060	serge	595	};
		596
		597	struct cpuinfo
		598	{
5354	serge	599	u64 caps;
		600	u64 def_mtrr;
		601	u64 mtrr_cap;
5060	serge	602	int var_mtrr_count;
		603	int fix_mtrr_count;
		604	struct mtrr var_mtrr[9];
		605	char model_name[64];
		606	};
		607
		608	#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
		609	#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
		610
		611	#define MSR_MTRRdefType 0x000002ff
		612
		613	#define IA32_MTRRCAP 0xFE
		614	#define IA32_CR_PAT_MSR 0x277
		615
		616	#define PAT_TYPE_UC 0
		617	#define PAT_TYPE_WC 1
		618	#define PAT_TYPE_WB 6
		619	#define PAT_TYPE_UCM 7
		620
		621
		622	#define MTRR_UC 0
		623	#define MTRR_WC 1
		624	#define MTRR_WB 6
		625
5354	serge	626	static inline u64 read_msr(u32 msr)
5060	serge	627	{
		628	union {
5354	serge	629	u64 val;
5060	serge	630	struct {
5354	serge	631	u32 low;
		632	u32 high;
5060	serge	633	};
		634	}tmp;
		635
		636	asm volatile (
		637	"rdmsr"
		638	: "=a" (tmp.low), "=d" (tmp.high)
		639	: "c" (msr));
		640	return tmp.val;
		641	}
		642
5354	serge	643	static inline void write_msr(u32 msr, u64 val)
5060	serge	644	{
		645	union {
5354	serge	646	u64 val;
5060	serge	647	struct {
5354	serge	648	u32 low;
		649	u32 high;
5060	serge	650	};
		651	}tmp;
		652
		653	tmp.val = val;
		654
		655	asm volatile (
		656	"wrmsr"
		657	:: "a" (tmp.low), "d" (tmp.high), "c" (msr));
		658	}
		659
		660	#define SIZE_OR_MASK_BITS(n) (~((1ULL << ((n) - PAGE_SHIFT)) - 1))
		661
		662	static void set_mtrr(unsigned int reg, unsigned long base,
		663	unsigned long size, int type)
		664	{
		665	unsigned int base_lo, base_hi, mask_lo, mask_hi;
		666	u64 size_or_mask, size_and_mask;
		667
		668	size_or_mask = SIZE_OR_MASK_BITS(36);
		669	size_and_mask = 0x00f00000;
		670
		671	if (size == 0) {
		672	/*
		673	* The invalid bit is kept in the mask, so we simply
		674	* clear the relevant mask register to disable a range.
		675	*/
		676	native_write_msr(MTRRphysMask_MSR(reg), 0, 0);
		677	}
		678	else {
		679	base_lo = base << PAGE_SHIFT \| type;
		680	base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT);
		681	mask_lo = -size << PAGE_SHIFT \| 0x800;
		682	mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT);
		683
		684	native_write_msr(MTRRphysBase_MSR(reg), base_lo, base_hi);
		685	native_write_msr(MTRRphysMask_MSR(reg), mask_lo, mask_hi);
		686	};
		687	}
		688
		689
		690	static u32 deftype_lo, deftype_hi;
		691
5354	serge	692	void cpu_detect1()
2344	Serge	693	{
5060	serge	694	struct cpuinfo cpuinfo;
		695
2344	Serge	696	u32 junk, tfms, cap0, misc;
5060	serge	697	int i;
5354	serge	698
2344	Serge	699	cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
		700
		701	if (cap0 & (1<<19))
		702	{
		703	x86_clflush_size = ((misc >> 8) & 0xff) * 8;
		704	}
3482	Serge	705
5354	serge	706	#if 0
5060	serge	707	cpuid(0x80000002, (unsigned int)&cpuinfo.model_name[0], (unsigned int)&cpuinfo.model_name[4],
		708	(unsigned int)&cpuinfo.model_name[8], (unsigned int)&cpuinfo.model_name[12]);
		709	cpuid(0x80000003, (unsigned int)&cpuinfo.model_name[16], (unsigned int)&cpuinfo.model_name[20],
		710	(unsigned int)&cpuinfo.model_name[24], (unsigned int)&cpuinfo.model_name[28]);
		711	cpuid(0x80000004, (unsigned int)&cpuinfo.model_name[32], (unsigned int)&cpuinfo.model_name[36],
		712	(unsigned int)&cpuinfo.model_name[40], (unsigned int)&cpuinfo.model_name[44]);
		713
		714	printf("\n%s\n\n",cpuinfo.model_name);
		715
		716	cpuinfo.def_mtrr = read_msr(MSR_MTRRdefType);
		717	cpuinfo.mtrr_cap = read_msr(IA32_MTRRCAP);
		718
		719	printf("MSR_MTRRdefType %016llx\n\n", cpuinfo.def_mtrr);
		720
		721	cpuinfo.var_mtrr_count = (u8_t)cpuinfo.mtrr_cap;
		722
		723	for(i = 0; i < cpuinfo.var_mtrr_count; i++)
		724	{
		725	u64_t mtrr_base;
		726	u64_t mtrr_mask;
		727
		728	cpuinfo.var_mtrr[i].base = read_msr(MTRRphysBase_MSR(i));
		729	cpuinfo.var_mtrr[i].mask = read_msr(MTRRphysMask_MSR(i));
		730
		731	printf("MTRR_%d base: %016llx mask: %016llx\n", i,
		732	cpuinfo.var_mtrr[i].base,
		733	cpuinfo.var_mtrr[i].mask);
		734	};
		735
		736	unsigned int cr0, cr3, cr4, eflags;
		737
		738	eflags = safe_cli();
		739
		740	/* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */
		741	cr0 = read_cr0() \| (1<<30);
		742	write_cr0(cr0);
		743	wbinvd();
		744
		745	cr4 = read_cr4();
		746	write_cr4(cr4 & ~(1<<7));
		747
		748	cr3 = read_cr3();
		749	write_cr3(cr3);
		750
		751	/* Save MTRR state */
		752	rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
		753
		754	/* Disable MTRRs, and set the default type to uncached */
		755	native_write_msr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi);
		756	wbinvd();
		757
		758	i = 0;
		759	set_mtrr(i++,0,0x80000000>>12,MTRR_WB);
		760	set_mtrr(i++,0x80000000>>12,0x40000000>>12,MTRR_WB);
		761	set_mtrr(i++,0xC0000000>>12,0x20000000>>12,MTRR_WB);
		762	set_mtrr(i++,0xdb800000>>12,0x00800000>>12,MTRR_UC);
		763	set_mtrr(i++,0xdc000000>>12,0x04000000>>12,MTRR_UC);
		764	set_mtrr(i++,0xE0000000>>12,0x10000000>>12,MTRR_WC);
		765
		766	for(; i < cpuinfo.var_mtrr_count; i++)
		767	set_mtrr(i,0,0,0);
		768
		769	write_cr3(cr3);
		770
		771	/* Intel (P6) standard MTRRs */
		772	native_write_msr(MSR_MTRRdefType, deftype_lo, deftype_hi);
		773
		774	/* Enable caches */
		775	write_cr0(read_cr0() & ~(1<<30));
		776
		777	/* Restore value of CR4 */
		778	write_cr4(cr4);
		779
		780	safe_sti(eflags);
		781
		782	printf("\nnew MTRR map\n\n");
		783
		784	for(i = 0; i < cpuinfo.var_mtrr_count; i++)
		785	{
		786	u64_t mtrr_base;
		787	u64_t mtrr_mask;
		788
		789	cpuinfo.var_mtrr[i].base = read_msr(MTRRphysBase_MSR(i));
		790	cpuinfo.var_mtrr[i].mask = read_msr(MTRRphysMask_MSR(i));
		791
		792	printf("MTRR_%d base: %016llx mask: %016llx\n", i,
		793	cpuinfo.var_mtrr[i].base,
		794	cpuinfo.var_mtrr[i].mask);
		795	};
		796	#endif
		797
3482	Serge	798	tsc_khz = (unsigned int)(GetCpuFreq()/1000);
2344	Serge	799	}
		800
3243	Serge	801
		802	int get_driver_caps(hwcaps_t *caps)
		803	{
		804	int ret = 0;
		805
		806	switch(caps->idx)
		807	{
		808	case 0:
		809	caps->opt[0] = 0;
		810	caps->opt[1] = 0;
		811	break;
		812
		813	case 1:
		814	caps->cap1.max_tex_width = 4096;
		815	caps->cap1.max_tex_height = 4096;
		816	break;
		817	default:
		818	ret = 1;
		819	};
		820	caps->idx = 1;
		821	return ret;
		822	}
		823
3255	Serge	824
		825	void get_pci_info(struct pci_device *dev)
		826	{
		827	struct pci_dev *pdev = main_device->pdev;
		828
		829	memset(dev, sizeof(*dev), 0);
		830
		831	dev->domain = 0;
		832	dev->bus = pdev->busnr;
		833	dev->dev = pdev->devfn >> 3;
		834	dev->func = pdev->devfn & 7;
		835	dev->vendor_id = pdev->vendor;
		836	dev->device_id = pdev->device;
		837	dev->revision = pdev->revision;
		838	};
4246	Serge	839
		840
		841
4280	Serge	842	char strstr(const char cs, const char *ct);
		843
		844	static int my_atoi(char **cmd)
		845	{
		846	char* p = *cmd;
		847	int val = 0;
		848	int sign = 1;
		849
		850	if(*p == '-')
		851	{
		852	sign = -1;
		853	p++;
		854	};
		855
		856	for (;; *p++) {
		857	switch (*p) {
		858	case '0' ... '9':
		859	val = 10val+(p-'0');
		860	break;
		861	default:
		862	*cmd = p;
		863	return val*sign;
		864	}
		865	}
		866	}
		867
6088	serge	868	static char* parse_mode(char p, videomode_t mode)
4280	Serge	869	{
		870	char c;
		871
		872	while( (c = *p++) == ' ');
		873
		874	if( c )
		875	{
		876	p--;
		877
		878	mode->width = my_atoi(&p);
		879	if(*p == 'x') p++;
		880
		881	mode->height = my_atoi(&p);
		882	if(*p == 'x') p++;
		883
		884	mode->bpp = 32;
		885
		886	mode->freq = my_atoi(&p);
		887
		888	if( mode->freq == 0 )
		889	mode->freq = 60;
		890	}
		891
		892	return p;
		893	};
		894

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(root)/drivers/video/drm/i915/main.c – Rev 7144