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Rev | Author | Line No. | Line |
---|---|---|---|
6084 | serge | 1 | #include |
2 | |||
3031 | serge | 3 | #include |
4 | #include |
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2338 | Serge | 5 | #include "i915_drv.h" |
6 | |||
2325 | Serge | 7 | #include |
8 | #include |
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9 | #include |
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10 | #include |
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11 | |||
6088 | serge | 12 | #include "getopt.h" |
13 | |||
2342 | Serge | 14 | #include "bitmap.h" |
6088 | serge | 15 | #include "i915_kos32.h" |
2340 | Serge | 16 | |
6296 | serge | 17 | #define DRV_NAME "i915 v4.4.3" |
6084 | serge | 18 | |
5060 | serge | 19 | #define I915_DEV_CLOSE 0 |
20 | #define I915_DEV_INIT 1 |
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21 | #define I915_DEV_READY 2 |
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22 | |||
6088 | serge | 23 | static int my_atoi(char **cmd); |
24 | static char* parse_mode(char *p, videomode_t *mode); |
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5354 | serge | 25 | void cpu_detect1(); |
26 | int kmap_init(); |
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2344 | Serge | 27 | |
5060 | serge | 28 | unsigned long volatile jiffies; |
6088 | serge | 29 | int oops_in_progress; |
30 | int x86_clflush_size; |
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31 | unsigned int tsc_khz; |
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3482 | Serge | 32 | struct workqueue_struct *system_wq; |
3764 | Serge | 33 | int driver_wq_state; |
6088 | serge | 34 | struct drm_device *main_device; |
35 | struct drm_file *drm_file_handlers[256]; |
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36 | videomode_t usermode; |
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37 | extern int __getopt_initialized; |
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3482 | Serge | 38 | |
4126 | Serge | 39 | void i915_driver_thread() |
40 | { |
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5060 | serge | 41 | struct drm_i915_private *dev_priv = NULL; |
42 | struct workqueue_struct *cwq = NULL; |
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4126 | Serge | 43 | static int dpms = 1; |
44 | static int dpms_lock = 0; |
||
45 | oskey_t key; |
||
46 | unsigned long irqflags; |
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47 | int tmp; |
||
48 | |||
49 | printf("%s\n",__FUNCTION__); |
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50 | |||
5060 | serge | 51 | while(driver_wq_state == I915_DEV_INIT) |
52 | { |
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6084 | serge | 53 | jiffies = GetClockNs() / 10000000; |
5060 | serge | 54 | delay(1); |
55 | }; |
||
56 | |||
6084 | serge | 57 | if( driver_wq_state == I915_DEV_CLOSE) |
58 | { |
||
59 | asm volatile ("int $0x40"::"a"(-1)); |
||
60 | }; |
||
61 | |||
5060 | serge | 62 | dev_priv = main_device->dev_private; |
63 | |||
4126 | Serge | 64 | asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(1),"c"(1)); |
65 | asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0x46),"d"(0x330)); |
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66 | asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0xC6),"d"(0x330)); |
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67 | |||
5060 | serge | 68 | while(driver_wq_state != I915_DEV_CLOSE) |
4126 | Serge | 69 | { |
6084 | serge | 70 | jiffies = GetClockNs() / 10000000; |
5060 | serge | 71 | |
4126 | Serge | 72 | key = get_key(); |
73 | |||
74 | if( (key.val != 1) && (key.state == 0x02)) |
||
75 | { |
||
76 | if(key.code == 0x46 && dpms_lock == 0) |
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77 | { |
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78 | dpms_lock = 1; |
||
79 | if(dpms == 1) |
||
80 | { |
||
81 | i915_dpms(main_device, DRM_MODE_DPMS_OFF); |
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82 | printf("dpms off\n"); |
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83 | } |
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84 | else |
||
85 | { |
||
86 | i915_dpms(main_device, DRM_MODE_DPMS_ON); |
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87 | printf("dpms on\n"); |
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88 | }; |
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89 | dpms ^= 1; |
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90 | } |
||
91 | else if(key.code == 0xC6) |
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92 | dpms_lock = 0; |
||
93 | }; |
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6296 | serge | 94 | cwq = dev_priv->wq; |
4126 | Serge | 95 | |
96 | spin_lock_irqsave(&cwq->lock, irqflags); |
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6296 | serge | 97 | while (!list_empty(&cwq->worklist)) |
98 | { |
||
99 | struct work_struct *work = list_entry(cwq->worklist.next, |
||
100 | struct work_struct, entry); |
||
101 | work_func_t f = work->func; |
||
102 | list_del_init(cwq->worklist.next); |
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4126 | Serge | 103 | |
6296 | serge | 104 | spin_unlock_irqrestore(&cwq->lock, irqflags); |
105 | f(work); |
||
106 | spin_lock_irqsave(&cwq->lock, irqflags); |
||
107 | } |
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108 | spin_unlock_irqrestore(&cwq->lock, irqflags); |
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109 | |||
110 | cwq = dev_priv->hotplug.dp_wq; |
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111 | |||
112 | spin_lock_irqsave(&cwq->lock, irqflags); |
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4126 | Serge | 113 | while (!list_empty(&cwq->worklist)) |
114 | { |
||
115 | struct work_struct *work = list_entry(cwq->worklist.next, |
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116 | struct work_struct, entry); |
||
117 | work_func_t f = work->func; |
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118 | list_del_init(cwq->worklist.next); |
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119 | |||
120 | spin_unlock_irqrestore(&cwq->lock, irqflags); |
||
121 | f(work); |
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122 | spin_lock_irqsave(&cwq->lock, irqflags); |
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123 | } |
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124 | spin_unlock_irqrestore(&cwq->lock, irqflags); |
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125 | |||
126 | delay(1); |
||
127 | }; |
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128 | |||
129 | asm volatile ("int $0x40"::"a"(-1)); |
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130 | } |
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131 | |||
5354 | serge | 132 | u32 __attribute__((externally_visible)) drvEntry(int action, char *cmdline) |
2325 | Serge | 133 | { |
5060 | serge | 134 | static pci_dev_t device; |
135 | const struct pci_device_id *ent; |
||
6088 | serge | 136 | char *safecmdline; |
4104 | Serge | 137 | int err = 0; |
2325 | Serge | 138 | |
139 | if(action != 1) |
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3764 | Serge | 140 | { |
5060 | serge | 141 | driver_wq_state = I915_DEV_CLOSE; |
2325 | Serge | 142 | return 0; |
3764 | Serge | 143 | }; |
2325 | Serge | 144 | |
145 | if( GetService("DISPLAY") != 0 ) |
||
146 | return 0; |
||
147 | |||
6283 | serge | 148 | printf("\n%s build %s %s\nusage: i915 [options]\n", |
6084 | serge | 149 | DRV_NAME, __DATE__, __TIME__); |
150 | |||
6088 | serge | 151 | printf("--rc6 <-1,0-7> Enable power-saving render C-state 6.\n" |
152 | " Different stages can be selected via bitmask values\n" |
||
153 | " (0 = disable; 1 = enable rc6; 2 = enable deep rc6;\n" |
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154 | " 4 = enable deepest rc6).\n" |
||
155 | " For example, 3 would enable rc6 and deep rc6,\n" |
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156 | " and 7 would enable everything.\n" |
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157 | " default: -1 (use per-chip default)\n"); |
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158 | printf("--fbc <-1,0,1> Enable frame buffer compression for power savings\n" |
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159 | " (default: -1 (use per-chip default))\n"); |
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160 | printf("-l\n" |
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161 | "--log |
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162 | printf("-m\n" |
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163 | "--mode |
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164 | printf("-v\n" |
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165 | "--video |
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166 | " set videomode for CONNECTOR\n"); |
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6084 | serge | 167 | |
2340 | Serge | 168 | if( cmdline && *cmdline ) |
6088 | serge | 169 | { |
170 | int argc, i, c; |
||
171 | char **argv; |
||
2325 | Serge | 172 | |
6088 | serge | 173 | safecmdline = __builtin_strdup(cmdline); |
174 | printf("cmdline %s\n", safecmdline); |
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175 | |||
176 | argc = split_cmdline(safecmdline, NULL); |
||
177 | argv = __builtin_malloc((argc+1)*sizeof(char*)); |
||
178 | split_cmdline(safecmdline, argv); |
||
179 | argv[argc] = NULL; |
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180 | |||
181 | while(1) |
||
182 | { |
||
183 | static struct option long_options[] = |
||
184 | { |
||
185 | {"log", required_argument, 0, 'l'}, |
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186 | {"mode", required_argument, 0, 'm'}, |
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187 | {"video", required_argument, 0, 'v'}, |
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188 | {"rc6", required_argument, 0, OPTION_RC6}, |
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189 | {"fbc", required_argument, 0, OPTION_FBC}, |
||
190 | {0, 0, 0, 0} |
||
191 | }; |
||
192 | |||
193 | int option_index = 0; |
||
194 | |||
6283 | serge | 195 | c = getopt_long (argc, argv, "l:m:v:", |
6088 | serge | 196 | long_options, &option_index); |
197 | |||
198 | if (c == -1) |
||
199 | break; |
||
200 | |||
201 | switch(c) |
||
202 | { |
||
203 | case OPTION_RC6: |
||
204 | i915.enable_rc6 = my_atoi(&optarg); |
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205 | printf("i915.rc6 = %d\n",i915.enable_rc6); |
||
206 | break; |
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207 | |||
208 | case OPTION_FBC: |
||
209 | i915.enable_fbc = my_atoi(&optarg); |
||
210 | printf("i915.fbc = %d\n",i915.enable_fbc); |
||
211 | break; |
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212 | |||
213 | case 'l': |
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214 | i915.log_file = optarg; |
||
215 | break; |
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216 | |||
217 | case 'm': |
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218 | parse_mode(optarg, &usermode); |
||
219 | break; |
||
220 | |||
221 | case 'v': |
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222 | i915.cmdline_mode = optarg; |
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223 | printf("i915.cmdline_mode =%s\n",i915.cmdline_mode); |
||
224 | break; |
||
225 | } |
||
226 | } |
||
227 | }; |
||
228 | |||
229 | if( i915.log_file && !dbg_open(i915.log_file)) |
||
6084 | serge | 230 | { |
6088 | serge | 231 | printf("Can't open %s\nExit\n", i915.log_file); |
6084 | serge | 232 | return 0; |
2325 | Serge | 233 | } |
6084 | serge | 234 | else |
235 | { |
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236 | dbgprintf("\nLOG: %s build %s %s\n",DRV_NAME,__DATE__, __TIME__); |
||
237 | } |
||
2325 | Serge | 238 | |
5354 | serge | 239 | cpu_detect1(); |
2351 | Serge | 240 | |
5060 | serge | 241 | err = enum_pci_devices(); |
242 | if( unlikely(err != 0) ) |
||
243 | { |
||
244 | dbgprintf("Device enumeration failed\n"); |
||
245 | return 0; |
||
246 | } |
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2325 | Serge | 247 | |
5354 | serge | 248 | err = kmap_init(); |
249 | if( unlikely(err != 0) ) |
||
250 | { |
||
251 | dbgprintf("kmap initialization failed\n"); |
||
252 | return 0; |
||
253 | } |
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254 | |||
5097 | serge | 255 | dmi_scan_machine(); |
256 | |||
5060 | serge | 257 | driver_wq_state = I915_DEV_INIT; |
258 | CreateKernelThread(i915_driver_thread); |
||
259 | |||
2325 | Serge | 260 | err = i915_init(); |
5060 | serge | 261 | if(unlikely(err!= 0)) |
2338 | Serge | 262 | { |
5060 | serge | 263 | driver_wq_state = I915_DEV_CLOSE; |
3298 | Serge | 264 | dbgprintf("Epic Fail :(\n"); |
6084 | serge | 265 | delay(100); |
3298 | Serge | 266 | return 0; |
2338 | Serge | 267 | }; |
2325 | Serge | 268 | |
5060 | serge | 269 | driver_wq_state = I915_DEV_READY; |
270 | |||
4280 | Serge | 271 | init_display_kms(main_device, &usermode); |
272 | |||
2338 | Serge | 273 | err = RegService("DISPLAY", display_handler); |
2325 | Serge | 274 | |
2338 | Serge | 275 | if( err != 0) |
276 | dbgprintf("Set DISPLAY handler\n"); |
||
277 | |||
2325 | Serge | 278 | return err; |
279 | }; |
||
280 | |||
6088 | serge | 281 | int do_command_line(const char* usercmd) |
282 | { |
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283 | char *cmdline; |
||
284 | int argc, i, c; |
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285 | char **argv; |
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6103 | serge | 286 | int retval = 0; |
3480 | Serge | 287 | |
6088 | serge | 288 | if( (usercmd == NULL) || (*usercmd == 0) ) |
289 | return 1; |
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290 | |||
291 | cmdline = __builtin_strdup(usercmd); |
||
292 | printf("cmdline %s\n", cmdline); |
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293 | |||
294 | argc = split_cmdline(cmdline, NULL); |
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295 | argv = __builtin_malloc((argc+1)*sizeof(char*)); |
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296 | split_cmdline(cmdline, argv); |
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297 | argv[argc] = NULL; |
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298 | |||
299 | __getopt_initialized = 0; |
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300 | |||
301 | while(1) |
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302 | { |
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303 | static struct option long_options[] = |
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304 | { |
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6103 | serge | 305 | {"list-connectors", no_argument, 0, OPTION_CONNECTORS}, |
306 | {"list-connector-modes", required_argument, 0, OPTION_CONN_MODES}, |
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307 | {"video", required_argument, 0, 'v'}, |
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6088 | serge | 308 | {0, 0, 0, 0} |
309 | }; |
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310 | |||
311 | int option_index = 0; |
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312 | |||
313 | c = getopt_long (argc, argv, "v:", |
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314 | long_options, &option_index); |
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315 | |||
316 | if (c == -1) |
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317 | break; |
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318 | |||
319 | switch(c) |
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320 | { |
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321 | case 'v': |
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322 | printf("cmdline_mode %s\n",optarg); |
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6103 | serge | 323 | retval = set_cmdline_mode_ext(main_device, optarg); |
6088 | serge | 324 | break; |
6103 | serge | 325 | |
326 | case OPTION_CONNECTORS: |
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327 | list_connectors(main_device); |
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328 | break; |
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329 | |||
330 | case OPTION_CONN_MODES: |
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331 | retval = list_connector_modes(main_device, optarg); |
||
332 | break; |
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6088 | serge | 333 | } |
334 | } |
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335 | __builtin_free(argv); |
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336 | __builtin_free(cmdline); |
||
337 | |||
6103 | serge | 338 | return retval; |
6088 | serge | 339 | }; |
340 | |||
2344 | Serge | 341 | #define CURRENT_API 0x0200 /* 2.00 */ |
342 | #define COMPATIBLE_API 0x0100 /* 1.00 */ |
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2338 | Serge | 343 | |
2344 | Serge | 344 | #define API_VERSION (COMPATIBLE_API << 16) | CURRENT_API |
2351 | Serge | 345 | #define DISPLAY_VERSION API_VERSION |
2338 | Serge | 346 | |
347 | |||
6084 | serge | 348 | #define SRV_GETVERSION 0 |
349 | #define SRV_ENUM_MODES 1 |
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350 | #define SRV_SET_MODE 2 |
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351 | #define SRV_GET_CAPS 3 |
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6088 | serge | 352 | #define SRV_CMDLINE 4 |
2342 | Serge | 353 | |
6084 | serge | 354 | #define SRV_GET_PCI_INFO 20 |
4246 | Serge | 355 | #define SRV_I915_GET_PARAM 21 |
6084 | serge | 356 | #define SRV_I915_GEM_CREATE 22 |
357 | #define SRV_DRM_GEM_CLOSE 23 |
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4246 | Serge | 358 | #define SRV_DRM_GEM_FLINK 24 |
359 | #define SRV_DRM_GEM_OPEN 25 |
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360 | #define SRV_I915_GEM_PIN 26 |
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361 | #define SRV_I915_GEM_UNPIN 27 |
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5367 | serge | 362 | #define SRV_I915_GEM_GET_CACHING 28 |
363 | #define SRV_I915_GEM_SET_CACHING 29 |
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364 | #define SRV_I915_GEM_PWRITE 30 |
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365 | #define SRV_I915_GEM_BUSY 31 |
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366 | #define SRV_I915_GEM_SET_DOMAIN 32 |
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367 | #define SRV_I915_GEM_MMAP 33 |
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368 | #define SRV_I915_GEM_SET_TILING 34 |
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369 | #define SRV_I915_GEM_GET_TILING 35 |
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370 | #define SRV_I915_GEM_GET_APERTURE 36 |
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371 | #define SRV_I915_GEM_MMAP_GTT 37 |
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372 | #define SRV_I915_GEM_THROTTLE 38 |
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373 | #define SRV_I915_GEM_EXECBUFFER2 39 |
||
374 | #define SRV_I915_GEM_WAIT 40 |
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375 | #define SRV_I915_GEM_CONTEXT_CREATE 41 |
||
376 | #define SRV_I915_GEM_CONTEXT_DESTROY 42 |
||
377 | #define SRV_I915_REG_READ 43 |
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3260 | Serge | 378 | |
5367 | serge | 379 | #define SRV_FBINFO 44 |
380 | #define SRV_MASK_UPDATE 45 |
||
381 | #define SRV_MASK_UPDATE_EX 46 |
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3263 | Serge | 382 | |
6131 | serge | 383 | #define SRV_I915_GEM_PREAD 47 |
384 | |||
2338 | Serge | 385 | #define check_input(size) \ |
386 | if( unlikely((inp==NULL)||(io->inp_size != (size))) ) \ |
||
387 | break; |
||
388 | |||
389 | #define check_output(size) \ |
||
390 | if( unlikely((outp==NULL)||(io->out_size != (size))) ) \ |
||
391 | break; |
||
392 | |||
393 | int _stdcall display_handler(ioctl_t *io) |
||
394 | { |
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3255 | Serge | 395 | struct drm_file *file; |
396 | |||
6084 | serge | 397 | int retval = -1; |
5354 | serge | 398 | u32 *inp; |
399 | u32 *outp; |
||
2338 | Serge | 400 | |
401 | inp = io->input; |
||
402 | outp = io->output; |
||
403 | |||
3255 | Serge | 404 | file = drm_file_handlers[0]; |
405 | |||
2338 | Serge | 406 | switch(io->io_code) |
407 | { |
||
408 | case SRV_GETVERSION: |
||
409 | check_output(4); |
||
2344 | Serge | 410 | *outp = DISPLAY_VERSION; |
2338 | Serge | 411 | retval = 0; |
412 | break; |
||
413 | |||
414 | case SRV_ENUM_MODES: |
||
3031 | serge | 415 | // dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n", |
416 | // inp, io->inp_size, io->out_size ); |
||
2340 | Serge | 417 | check_output(4); |
2338 | Serge | 418 | // check_input(*outp * sizeof(videomode_t)); |
6088 | serge | 419 | retval = get_videomodes((videomode_t*)inp, outp); |
2338 | Serge | 420 | break; |
421 | |||
422 | case SRV_SET_MODE: |
||
3031 | serge | 423 | // dbgprintf("SRV_SET_MODE inp %x inp_size %x\n", |
424 | // inp, io->inp_size); |
||
2338 | Serge | 425 | check_input(sizeof(videomode_t)); |
6088 | serge | 426 | retval = set_user_mode((videomode_t*)inp); |
2338 | Serge | 427 | break; |
3033 | serge | 428 | |
2351 | Serge | 429 | case SRV_GET_CAPS: |
430 | retval = get_driver_caps((hwcaps_t*)inp); |
||
431 | break; |
||
432 | |||
6088 | serge | 433 | case SRV_CMDLINE: |
434 | retval = do_command_line((char*)inp); |
||
435 | break; |
||
436 | |||
3260 | Serge | 437 | case SRV_GET_PCI_INFO: |
3255 | Serge | 438 | get_pci_info((struct pci_device *)inp); |
2338 | Serge | 439 | retval = 0; |
440 | break; |
||
3031 | serge | 441 | |
4246 | Serge | 442 | case SRV_I915_GET_PARAM: |
443 | retval = i915_getparam(main_device, inp, file); |
||
3255 | Serge | 444 | break; |
445 | |||
446 | case SRV_I915_GEM_CREATE: |
||
447 | retval = i915_gem_create_ioctl(main_device, inp, file); |
||
448 | break; |
||
449 | |||
450 | case SRV_DRM_GEM_CLOSE: |
||
451 | retval = drm_gem_close_ioctl(main_device, inp, file); |
||
452 | break; |
||
453 | |||
4246 | Serge | 454 | case SRV_DRM_GEM_FLINK: |
455 | retval = drm_gem_flink_ioctl(main_device, inp, file); |
||
456 | break; |
||
457 | |||
458 | case SRV_DRM_GEM_OPEN: |
||
459 | retval = drm_gem_open_ioctl(main_device, inp, file); |
||
460 | break; |
||
461 | |||
5367 | serge | 462 | case SRV_I915_GEM_GET_CACHING: |
463 | retval = i915_gem_get_caching_ioctl(main_device, inp, file); |
||
464 | break; |
||
465 | |||
4246 | Serge | 466 | case SRV_I915_GEM_SET_CACHING: |
467 | retval = i915_gem_set_caching_ioctl(main_device, inp, file); |
||
3260 | Serge | 468 | break; |
469 | |||
6131 | serge | 470 | case SRV_I915_GEM_PREAD: |
471 | retval = i915_gem_pread_ioctl(main_device, inp, file); |
||
472 | break; |
||
473 | |||
3260 | Serge | 474 | case SRV_I915_GEM_PWRITE: |
475 | retval = i915_gem_pwrite_ioctl(main_device, inp, file); |
||
476 | break; |
||
477 | |||
478 | case SRV_I915_GEM_BUSY: |
||
479 | retval = i915_gem_busy_ioctl(main_device, inp, file); |
||
480 | break; |
||
481 | |||
482 | case SRV_I915_GEM_SET_DOMAIN: |
||
483 | retval = i915_gem_set_domain_ioctl(main_device, inp, file); |
||
484 | break; |
||
485 | |||
3263 | Serge | 486 | case SRV_I915_GEM_MMAP: |
487 | retval = i915_gem_mmap_ioctl(main_device, inp, file); |
||
488 | break; |
||
489 | |||
4246 | Serge | 490 | case SRV_I915_GEM_SET_TILING: |
491 | retval = i915_gem_set_tiling(main_device, inp, file); |
||
492 | break; |
||
493 | |||
494 | case SRV_I915_GEM_GET_TILING: |
||
495 | retval = i915_gem_get_tiling(main_device, inp, file); |
||
496 | break; |
||
497 | |||
498 | case SRV_I915_GEM_GET_APERTURE: |
||
499 | // printf("SRV_I915_GEM_GET_APERTURE "); |
||
500 | retval = i915_gem_get_aperture_ioctl(main_device, inp, file); |
||
501 | // printf(" retval=%d\n", retval); |
||
502 | break; |
||
503 | |||
3480 | Serge | 504 | case SRV_I915_GEM_MMAP_GTT: |
505 | retval = i915_gem_mmap_gtt_ioctl(main_device, inp, file); |
||
506 | break; |
||
507 | |||
4246 | Serge | 508 | case SRV_I915_GEM_THROTTLE: |
509 | retval = i915_gem_throttle_ioctl(main_device, inp, file); |
||
3263 | Serge | 510 | break; |
511 | |||
512 | case SRV_I915_GEM_EXECBUFFER2: |
||
513 | retval = i915_gem_execbuffer2(main_device, inp, file); |
||
514 | break; |
||
515 | |||
4246 | Serge | 516 | case SRV_I915_GEM_WAIT: |
517 | retval = i915_gem_wait_ioctl(main_device, inp, file); |
||
518 | break; |
||
519 | |||
520 | case SRV_I915_GEM_CONTEXT_CREATE: |
||
521 | retval = i915_gem_context_create_ioctl(main_device, inp, file); |
||
522 | break; |
||
523 | |||
524 | case SRV_I915_GEM_CONTEXT_DESTROY: |
||
525 | retval = i915_gem_context_destroy_ioctl(main_device, inp, file); |
||
526 | break; |
||
527 | |||
528 | case SRV_I915_REG_READ: |
||
529 | retval = i915_reg_read_ioctl(main_device, inp, file); |
||
530 | break; |
||
531 | |||
532 | case SRV_FBINFO: |
||
533 | retval = i915_fbinfo(inp); |
||
534 | break; |
||
535 | |||
3290 | Serge | 536 | case SRV_MASK_UPDATE: |
537 | retval = i915_mask_update(main_device, inp, file); |
||
538 | break; |
||
4539 | Serge | 539 | |
540 | case SRV_MASK_UPDATE_EX: |
||
541 | retval = i915_mask_update_ex(main_device, inp, file); |
||
542 | break; |
||
2338 | Serge | 543 | }; |
544 | |||
545 | return retval; |
||
546 | } |
||
547 | |||
548 | |||
2325 | Serge | 549 | #define PCI_CLASS_REVISION 0x08 |
550 | #define PCI_CLASS_DISPLAY_VGA 0x0300 |
||
551 | #define PCI_CLASS_BRIDGE_HOST 0x0600 |
||
2326 | Serge | 552 | #define PCI_CLASS_BRIDGE_ISA 0x0601 |
2325 | Serge | 553 | |
5354 | serge | 554 | int pci_scan_filter(u32 id, u32 busnr, u32 devfn) |
2325 | Serge | 555 | { |
5354 | serge | 556 | u16 vendor, device; |
557 | u32 class; |
||
2325 | Serge | 558 | int ret = 0; |
559 | |||
560 | vendor = id & 0xffff; |
||
561 | device = (id >> 16) & 0xffff; |
||
562 | |||
563 | if(vendor == 0x8086) |
||
564 | { |
||
565 | class = PciRead32(busnr, devfn, PCI_CLASS_REVISION); |
||
566 | class >>= 16; |
||
567 | |||
568 | if( (class == PCI_CLASS_DISPLAY_VGA) || |
||
2326 | Serge | 569 | (class == PCI_CLASS_BRIDGE_HOST) || |
570 | (class == PCI_CLASS_BRIDGE_ISA)) |
||
2325 | Serge | 571 | ret = 1; |
572 | } |
||
573 | return ret; |
||
574 | }; |
||
2340 | Serge | 575 | |
576 | |||
5060 | serge | 577 | struct mtrr |
578 | { |
||
5354 | serge | 579 | u64 base; |
580 | u64 mask; |
||
5060 | serge | 581 | }; |
582 | |||
583 | struct cpuinfo |
||
584 | { |
||
5354 | serge | 585 | u64 caps; |
586 | u64 def_mtrr; |
||
587 | u64 mtrr_cap; |
||
5060 | serge | 588 | int var_mtrr_count; |
589 | int fix_mtrr_count; |
||
590 | struct mtrr var_mtrr[9]; |
||
591 | char model_name[64]; |
||
592 | }; |
||
593 | |||
594 | #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) |
||
595 | #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) |
||
596 | |||
597 | #define MSR_MTRRdefType 0x000002ff |
||
598 | |||
599 | #define IA32_MTRRCAP 0xFE |
||
600 | #define IA32_CR_PAT_MSR 0x277 |
||
601 | |||
602 | #define PAT_TYPE_UC 0 |
||
603 | #define PAT_TYPE_WC 1 |
||
604 | #define PAT_TYPE_WB 6 |
||
605 | #define PAT_TYPE_UCM 7 |
||
606 | |||
607 | |||
608 | #define MTRR_UC 0 |
||
609 | #define MTRR_WC 1 |
||
610 | #define MTRR_WB 6 |
||
611 | |||
5354 | serge | 612 | static inline u64 read_msr(u32 msr) |
5060 | serge | 613 | { |
614 | union { |
||
5354 | serge | 615 | u64 val; |
5060 | serge | 616 | struct { |
5354 | serge | 617 | u32 low; |
618 | u32 high; |
||
5060 | serge | 619 | }; |
620 | }tmp; |
||
621 | |||
622 | asm volatile ( |
||
623 | "rdmsr" |
||
624 | : "=a" (tmp.low), "=d" (tmp.high) |
||
625 | : "c" (msr)); |
||
626 | return tmp.val; |
||
627 | } |
||
628 | |||
5354 | serge | 629 | static inline void write_msr(u32 msr, u64 val) |
5060 | serge | 630 | { |
631 | union { |
||
5354 | serge | 632 | u64 val; |
5060 | serge | 633 | struct { |
5354 | serge | 634 | u32 low; |
635 | u32 high; |
||
5060 | serge | 636 | }; |
637 | }tmp; |
||
638 | |||
639 | tmp.val = val; |
||
640 | |||
641 | asm volatile ( |
||
642 | "wrmsr" |
||
643 | :: "a" (tmp.low), "d" (tmp.high), "c" (msr)); |
||
644 | } |
||
645 | |||
646 | #define SIZE_OR_MASK_BITS(n) (~((1ULL << ((n) - PAGE_SHIFT)) - 1)) |
||
647 | |||
648 | static void set_mtrr(unsigned int reg, unsigned long base, |
||
649 | unsigned long size, int type) |
||
650 | { |
||
651 | unsigned int base_lo, base_hi, mask_lo, mask_hi; |
||
652 | u64 size_or_mask, size_and_mask; |
||
653 | |||
654 | size_or_mask = SIZE_OR_MASK_BITS(36); |
||
655 | size_and_mask = 0x00f00000; |
||
656 | |||
657 | if (size == 0) { |
||
658 | /* |
||
659 | * The invalid bit is kept in the mask, so we simply |
||
660 | * clear the relevant mask register to disable a range. |
||
661 | */ |
||
662 | native_write_msr(MTRRphysMask_MSR(reg), 0, 0); |
||
663 | } |
||
664 | else { |
||
665 | base_lo = base << PAGE_SHIFT | type; |
||
666 | base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT); |
||
667 | mask_lo = -size << PAGE_SHIFT | 0x800; |
||
668 | mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT); |
||
669 | |||
670 | native_write_msr(MTRRphysBase_MSR(reg), base_lo, base_hi); |
||
671 | native_write_msr(MTRRphysMask_MSR(reg), mask_lo, mask_hi); |
||
672 | }; |
||
673 | } |
||
674 | |||
675 | |||
676 | static u32 deftype_lo, deftype_hi; |
||
677 | |||
5354 | serge | 678 | void cpu_detect1() |
2344 | Serge | 679 | { |
5060 | serge | 680 | struct cpuinfo cpuinfo; |
681 | |||
2344 | Serge | 682 | u32 junk, tfms, cap0, misc; |
5060 | serge | 683 | int i; |
5354 | serge | 684 | |
2344 | Serge | 685 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
686 | |||
687 | if (cap0 & (1<<19)) |
||
688 | { |
||
689 | x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
||
690 | } |
||
3482 | Serge | 691 | |
5354 | serge | 692 | #if 0 |
5060 | serge | 693 | cpuid(0x80000002, (unsigned int*)&cpuinfo.model_name[0], (unsigned int*)&cpuinfo.model_name[4], |
694 | (unsigned int*)&cpuinfo.model_name[8], (unsigned int*)&cpuinfo.model_name[12]); |
||
695 | cpuid(0x80000003, (unsigned int*)&cpuinfo.model_name[16], (unsigned int*)&cpuinfo.model_name[20], |
||
696 | (unsigned int*)&cpuinfo.model_name[24], (unsigned int*)&cpuinfo.model_name[28]); |
||
697 | cpuid(0x80000004, (unsigned int*)&cpuinfo.model_name[32], (unsigned int*)&cpuinfo.model_name[36], |
||
698 | (unsigned int*)&cpuinfo.model_name[40], (unsigned int*)&cpuinfo.model_name[44]); |
||
699 | |||
700 | printf("\n%s\n\n",cpuinfo.model_name); |
||
701 | |||
702 | cpuinfo.def_mtrr = read_msr(MSR_MTRRdefType); |
||
703 | cpuinfo.mtrr_cap = read_msr(IA32_MTRRCAP); |
||
704 | |||
705 | printf("MSR_MTRRdefType %016llx\n\n", cpuinfo.def_mtrr); |
||
706 | |||
707 | cpuinfo.var_mtrr_count = (u8_t)cpuinfo.mtrr_cap; |
||
708 | |||
709 | for(i = 0; i < cpuinfo.var_mtrr_count; i++) |
||
710 | { |
||
711 | u64_t mtrr_base; |
||
712 | u64_t mtrr_mask; |
||
713 | |||
714 | cpuinfo.var_mtrr[i].base = read_msr(MTRRphysBase_MSR(i)); |
||
715 | cpuinfo.var_mtrr[i].mask = read_msr(MTRRphysMask_MSR(i)); |
||
716 | |||
717 | printf("MTRR_%d base: %016llx mask: %016llx\n", i, |
||
718 | cpuinfo.var_mtrr[i].base, |
||
719 | cpuinfo.var_mtrr[i].mask); |
||
720 | }; |
||
721 | |||
722 | unsigned int cr0, cr3, cr4, eflags; |
||
723 | |||
724 | eflags = safe_cli(); |
||
725 | |||
726 | /* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */ |
||
727 | cr0 = read_cr0() | (1<<30); |
||
728 | write_cr0(cr0); |
||
729 | wbinvd(); |
||
730 | |||
731 | cr4 = read_cr4(); |
||
732 | write_cr4(cr4 & ~(1<<7)); |
||
733 | |||
734 | cr3 = read_cr3(); |
||
735 | write_cr3(cr3); |
||
736 | |||
737 | /* Save MTRR state */ |
||
738 | rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); |
||
739 | |||
740 | /* Disable MTRRs, and set the default type to uncached */ |
||
741 | native_write_msr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi); |
||
742 | wbinvd(); |
||
743 | |||
744 | i = 0; |
||
745 | set_mtrr(i++,0,0x80000000>>12,MTRR_WB); |
||
746 | set_mtrr(i++,0x80000000>>12,0x40000000>>12,MTRR_WB); |
||
747 | set_mtrr(i++,0xC0000000>>12,0x20000000>>12,MTRR_WB); |
||
748 | set_mtrr(i++,0xdb800000>>12,0x00800000>>12,MTRR_UC); |
||
749 | set_mtrr(i++,0xdc000000>>12,0x04000000>>12,MTRR_UC); |
||
750 | set_mtrr(i++,0xE0000000>>12,0x10000000>>12,MTRR_WC); |
||
751 | |||
752 | for(; i < cpuinfo.var_mtrr_count; i++) |
||
753 | set_mtrr(i,0,0,0); |
||
754 | |||
755 | write_cr3(cr3); |
||
756 | |||
757 | /* Intel (P6) standard MTRRs */ |
||
758 | native_write_msr(MSR_MTRRdefType, deftype_lo, deftype_hi); |
||
759 | |||
760 | /* Enable caches */ |
||
761 | write_cr0(read_cr0() & ~(1<<30)); |
||
762 | |||
763 | /* Restore value of CR4 */ |
||
764 | write_cr4(cr4); |
||
765 | |||
766 | safe_sti(eflags); |
||
767 | |||
768 | printf("\nnew MTRR map\n\n"); |
||
769 | |||
770 | for(i = 0; i < cpuinfo.var_mtrr_count; i++) |
||
771 | { |
||
772 | u64_t mtrr_base; |
||
773 | u64_t mtrr_mask; |
||
774 | |||
775 | cpuinfo.var_mtrr[i].base = read_msr(MTRRphysBase_MSR(i)); |
||
776 | cpuinfo.var_mtrr[i].mask = read_msr(MTRRphysMask_MSR(i)); |
||
777 | |||
778 | printf("MTRR_%d base: %016llx mask: %016llx\n", i, |
||
779 | cpuinfo.var_mtrr[i].base, |
||
780 | cpuinfo.var_mtrr[i].mask); |
||
781 | }; |
||
782 | #endif |
||
783 | |||
3482 | Serge | 784 | tsc_khz = (unsigned int)(GetCpuFreq()/1000); |
2344 | Serge | 785 | } |
786 | |||
3243 | Serge | 787 | |
788 | int get_driver_caps(hwcaps_t *caps) |
||
789 | { |
||
790 | int ret = 0; |
||
791 | |||
792 | switch(caps->idx) |
||
793 | { |
||
794 | case 0: |
||
795 | caps->opt[0] = 0; |
||
796 | caps->opt[1] = 0; |
||
797 | break; |
||
798 | |||
799 | case 1: |
||
800 | caps->cap1.max_tex_width = 4096; |
||
801 | caps->cap1.max_tex_height = 4096; |
||
802 | break; |
||
803 | default: |
||
804 | ret = 1; |
||
805 | }; |
||
806 | caps->idx = 1; |
||
807 | return ret; |
||
808 | } |
||
809 | |||
3255 | Serge | 810 | |
811 | void get_pci_info(struct pci_device *dev) |
||
812 | { |
||
813 | struct pci_dev *pdev = main_device->pdev; |
||
814 | |||
815 | memset(dev, sizeof(*dev), 0); |
||
816 | |||
817 | dev->domain = 0; |
||
818 | dev->bus = pdev->busnr; |
||
819 | dev->dev = pdev->devfn >> 3; |
||
820 | dev->func = pdev->devfn & 7; |
||
821 | dev->vendor_id = pdev->vendor; |
||
822 | dev->device_id = pdev->device; |
||
823 | dev->revision = pdev->revision; |
||
824 | }; |
||
4246 | Serge | 825 | |
826 | |||
827 | |||
4280 | Serge | 828 | char *strstr(const char *cs, const char *ct); |
829 | |||
830 | static int my_atoi(char **cmd) |
||
831 | { |
||
832 | char* p = *cmd; |
||
833 | int val = 0; |
||
834 | int sign = 1; |
||
835 | |||
836 | if(*p == '-') |
||
837 | { |
||
838 | sign = -1; |
||
839 | p++; |
||
840 | }; |
||
841 | |||
842 | for (;; *p++) { |
||
843 | switch (*p) { |
||
844 | case '0' ... '9': |
||
845 | val = 10*val+(*p-'0'); |
||
846 | break; |
||
847 | default: |
||
848 | *cmd = p; |
||
849 | return val*sign; |
||
850 | } |
||
851 | } |
||
852 | } |
||
853 | |||
6088 | serge | 854 | static char* parse_mode(char *p, videomode_t *mode) |
4280 | Serge | 855 | { |
856 | char c; |
||
857 | |||
858 | while( (c = *p++) == ' '); |
||
859 | |||
860 | if( c ) |
||
861 | { |
||
862 | p--; |
||
863 | |||
864 | mode->width = my_atoi(&p); |
||
865 | if(*p == 'x') p++; |
||
866 | |||
867 | mode->height = my_atoi(&p); |
||
868 | if(*p == 'x') p++; |
||
869 | |||
870 | mode->bpp = 32; |
||
871 | |||
872 | mode->freq = my_atoi(&p); |
||
873 | |||
874 | if( mode->freq == 0 ) |
||
875 | mode->freq = 60; |
||
876 | } |
||
877 | |||
878 | return p; |
||
879 | };>30)); |
||
880 |