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Rev Author Line No. Line
6084 serge 1
#include 
2
 
3031 serge 3
#include 
4
#include 
2338 Serge 5
#include "i915_drv.h"
6
 
2325 Serge 7
#include 
8
#include 
9
#include 
10
#include 
11
 
6088 serge 12
#include "getopt.h"
13
 
2342 Serge 14
#include "bitmap.h"
6088 serge 15
#include "i915_kos32.h"
2340 Serge 16
 
6283 serge 17
#define DRV_NAME "i915 v4.4.2-dbg2"
6084 serge 18
 
5060 serge 19
#define I915_DEV_CLOSE 0
20
#define I915_DEV_INIT  1
21
#define I915_DEV_READY 2
22
 
6088 serge 23
static int my_atoi(char **cmd);
24
static char* parse_mode(char *p, videomode_t *mode);
5354 serge 25
void cpu_detect1();
26
int kmap_init();
2344 Serge 27
 
5060 serge 28
unsigned long volatile jiffies;
6088 serge 29
int oops_in_progress;
30
int x86_clflush_size;
31
unsigned int tsc_khz;
3482 Serge 32
struct workqueue_struct *system_wq;
3764 Serge 33
int driver_wq_state;
6088 serge 34
struct drm_device *main_device;
35
struct drm_file   *drm_file_handlers[256];
36
videomode_t usermode;
37
extern int __getopt_initialized;
3482 Serge 38
 
4126 Serge 39
void i915_driver_thread()
40
{
5060 serge 41
    struct drm_i915_private *dev_priv = NULL;
42
    struct workqueue_struct *cwq = NULL;
4126 Serge 43
    static int dpms = 1;
44
    static int dpms_lock = 0;
45
    oskey_t   key;
46
    unsigned long irqflags;
47
    int tmp;
48
 
49
    printf("%s\n",__FUNCTION__);
50
 
5060 serge 51
    while(driver_wq_state == I915_DEV_INIT)
52
    {
6084 serge 53
        jiffies = GetClockNs() / 10000000;
5060 serge 54
        delay(1);
55
    };
56
 
6084 serge 57
    if( driver_wq_state == I915_DEV_CLOSE)
58
    {
59
        asm volatile ("int $0x40"::"a"(-1));
60
    };
61
 
5060 serge 62
    dev_priv = main_device->dev_private;
63
    cwq = dev_priv->wq;
64
 
4126 Serge 65
    asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(1),"c"(1));
66
    asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0x46),"d"(0x330));
67
    asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0xC6),"d"(0x330));
68
 
5060 serge 69
    while(driver_wq_state != I915_DEV_CLOSE)
4126 Serge 70
    {
6084 serge 71
        jiffies = GetClockNs() / 10000000;
5060 serge 72
 
4126 Serge 73
        key = get_key();
74
 
75
        if( (key.val != 1) && (key.state == 0x02))
76
        {
77
            if(key.code == 0x46 && dpms_lock == 0)
78
            {
79
                dpms_lock = 1;
80
                if(dpms == 1)
81
                {
82
                    i915_dpms(main_device, DRM_MODE_DPMS_OFF);
83
                    printf("dpms off\n");
84
                }
85
                else
86
                {
87
                    i915_dpms(main_device, DRM_MODE_DPMS_ON);
88
                    printf("dpms on\n");
89
                };
90
                dpms ^= 1;
91
                }
92
            else if(key.code == 0xC6)
93
                dpms_lock = 0;
94
        };
95
 
96
        spin_lock_irqsave(&cwq->lock, irqflags);
97
 
98
        while (!list_empty(&cwq->worklist))
99
        {
100
            struct work_struct *work = list_entry(cwq->worklist.next,
101
                                        struct work_struct, entry);
102
            work_func_t f = work->func;
103
            list_del_init(cwq->worklist.next);
104
 
105
            spin_unlock_irqrestore(&cwq->lock, irqflags);
106
            f(work);
107
            spin_lock_irqsave(&cwq->lock, irqflags);
108
        }
109
 
110
        spin_unlock_irqrestore(&cwq->lock, irqflags);
111
 
112
        delay(1);
113
    };
114
 
115
    asm volatile ("int $0x40"::"a"(-1));
116
}
117
 
5354 serge 118
u32  __attribute__((externally_visible)) drvEntry(int action, char *cmdline)
2325 Serge 119
{
5060 serge 120
    static pci_dev_t device;
121
    const struct pci_device_id  *ent;
6088 serge 122
    char *safecmdline;
4104 Serge 123
    int err = 0;
2325 Serge 124
 
125
    if(action != 1)
3764 Serge 126
    {
5060 serge 127
        driver_wq_state = I915_DEV_CLOSE;
2325 Serge 128
        return 0;
3764 Serge 129
    };
2325 Serge 130
 
131
    if( GetService("DISPLAY") != 0 )
132
        return 0;
133
 
6283 serge 134
    printf("\n%s build %s %s\nusage: i915 [options]\n",
6084 serge 135
           DRV_NAME, __DATE__, __TIME__);
136
 
6088 serge 137
    printf("--rc6 <-1,0-7>  Enable power-saving render C-state 6.\n"
138
           "                Different stages can be selected via bitmask values\n"
139
           "                (0 = disable; 1 = enable rc6; 2 = enable deep rc6;\n"
140
           "                4 = enable deepest rc6).\n"
141
           "                For example, 3 would enable rc6 and deep rc6,\n"
142
           "                and 7 would enable everything.\n"
143
           "                default: -1 (use per-chip default)\n");
144
    printf("--fbc <-1,0,1>  Enable frame buffer compression for power savings\n"
145
           "                (default: -1 (use per-chip default))\n");
146
    printf("-l\n"
147
           "--log     path to log file\n");
148
    printf("-m\n"
149
           "--mode  set videomode\n");
150
    printf("-v\n"
151
           "--video :x[M][R][-][@][i][m][eDd]\n"
152
           "                set videomode for CONNECTOR\n");
6084 serge 153
 
2340 Serge 154
    if( cmdline && *cmdline )
6088 serge 155
    {
156
        int argc, i, c;
157
        char **argv;
2325 Serge 158
 
6088 serge 159
        safecmdline = __builtin_strdup(cmdline);
160
        printf("cmdline %s\n", safecmdline);
161
 
162
        argc = split_cmdline(safecmdline, NULL);
163
        argv = __builtin_malloc((argc+1)*sizeof(char*));
164
        split_cmdline(safecmdline, argv);
165
        argv[argc] = NULL;
166
 
167
        while(1)
168
        {
169
            static struct option long_options[] =
170
            {
171
                {"log",   required_argument, 0, 'l'},
172
                {"mode",  required_argument, 0, 'm'},
173
                {"video", required_argument, 0, 'v'},
174
                {"rc6", required_argument, 0, OPTION_RC6},
175
                {"fbc", required_argument, 0, OPTION_FBC},
176
                {0, 0, 0, 0}
177
            };
178
 
179
            int option_index = 0;
180
 
6283 serge 181
            c = getopt_long (argc, argv, "l:m:v:",
6088 serge 182
                            long_options, &option_index);
183
 
184
            if (c == -1)
185
                break;
186
 
187
            switch(c)
188
            {
189
                case OPTION_RC6:
190
                    i915.enable_rc6 = my_atoi(&optarg);
191
                    printf("i915.rc6 = %d\n",i915.enable_rc6);
192
                    break;
193
 
194
                case OPTION_FBC:
195
                    i915.enable_fbc = my_atoi(&optarg);
196
                    printf("i915.fbc = %d\n",i915.enable_fbc);
197
                    break;
198
 
199
                case 'l':
200
                    i915.log_file = optarg;
201
                    break;
202
 
203
                case 'm':
204
                    parse_mode(optarg, &usermode);
205
                    break;
206
 
207
                case 'v':
208
                    i915.cmdline_mode = optarg;
209
                    printf("i915.cmdline_mode =%s\n",i915.cmdline_mode);
210
                    break;
211
            }
212
        }
213
    };
214
 
215
    if( i915.log_file && !dbg_open(i915.log_file))
6084 serge 216
    {
6088 serge 217
        printf("Can't open %s\nExit\n", i915.log_file);
6084 serge 218
        return 0;
2325 Serge 219
    }
6084 serge 220
    else
221
    {
222
        dbgprintf("\nLOG: %s build %s %s\n",DRV_NAME,__DATE__, __TIME__);
223
    }
2325 Serge 224
 
5354 serge 225
    cpu_detect1();
2351 Serge 226
 
5060 serge 227
    err = enum_pci_devices();
228
    if( unlikely(err != 0) )
229
    {
230
        dbgprintf("Device enumeration failed\n");
231
        return 0;
232
    }
2325 Serge 233
 
5354 serge 234
    err = kmap_init();
235
    if( unlikely(err != 0) )
236
    {
237
        dbgprintf("kmap initialization failed\n");
238
        return 0;
239
    }
240
 
5097 serge 241
    dmi_scan_machine();
242
 
5060 serge 243
    driver_wq_state = I915_DEV_INIT;
244
    CreateKernelThread(i915_driver_thread);
245
 
2325 Serge 246
    err = i915_init();
5060 serge 247
    if(unlikely(err!= 0))
2338 Serge 248
    {
5060 serge 249
        driver_wq_state = I915_DEV_CLOSE;
3298 Serge 250
        dbgprintf("Epic Fail :(\n");
6084 serge 251
        delay(100);
3298 Serge 252
        return 0;
2338 Serge 253
    };
2325 Serge 254
 
5060 serge 255
    driver_wq_state = I915_DEV_READY;
256
 
4280 Serge 257
    init_display_kms(main_device, &usermode);
258
 
2338 Serge 259
    err = RegService("DISPLAY", display_handler);
2325 Serge 260
 
2338 Serge 261
    if( err != 0)
262
        dbgprintf("Set DISPLAY handler\n");
263
 
2325 Serge 264
    return err;
265
};
266
 
6088 serge 267
int do_command_line(const char* usercmd)
268
{
269
    char *cmdline;
270
    int argc, i, c;
271
    char **argv;
6103 serge 272
    int retval = 0;
3480 Serge 273
 
6088 serge 274
    if( (usercmd == NULL) || (*usercmd == 0) )
275
        return 1;
276
 
277
    cmdline = __builtin_strdup(usercmd);
278
    printf("cmdline %s\n", cmdline);
279
 
280
    argc = split_cmdline(cmdline, NULL);
281
    argv = __builtin_malloc((argc+1)*sizeof(char*));
282
    split_cmdline(cmdline, argv);
283
    argv[argc] = NULL;
284
 
285
    __getopt_initialized = 0;
286
 
287
    while(1)
288
    {
289
        static struct option long_options[] =
290
        {
6103 serge 291
            {"list-connectors",      no_argument,       0, OPTION_CONNECTORS},
292
            {"list-connector-modes", required_argument, 0, OPTION_CONN_MODES},
293
            {"video",                required_argument, 0, 'v'},
6088 serge 294
            {0, 0, 0, 0}
295
        };
296
 
297
        int option_index = 0;
298
 
299
        c = getopt_long (argc, argv, "v:",
300
                        long_options, &option_index);
301
 
302
        if (c == -1)
303
            break;
304
 
305
        switch(c)
306
        {
307
            case 'v':
308
                printf("cmdline_mode %s\n",optarg);
6103 serge 309
                retval = set_cmdline_mode_ext(main_device, optarg);
6088 serge 310
                break;
6103 serge 311
 
312
            case OPTION_CONNECTORS:
313
                list_connectors(main_device);
314
                break;
315
 
316
            case OPTION_CONN_MODES:
317
                retval = list_connector_modes(main_device, optarg);
318
                break;
6088 serge 319
        }
320
    }
321
    __builtin_free(argv);
322
    __builtin_free(cmdline);
323
 
6103 serge 324
    return retval;
6088 serge 325
};
326
 
2344 Serge 327
#define CURRENT_API     0x0200      /*      2.00     */
328
#define COMPATIBLE_API  0x0100      /*      1.00     */
2338 Serge 329
 
2344 Serge 330
#define API_VERSION     (COMPATIBLE_API << 16) | CURRENT_API
2351 Serge 331
#define DISPLAY_VERSION  API_VERSION
2338 Serge 332
 
333
 
6084 serge 334
#define SRV_GETVERSION              0
335
#define SRV_ENUM_MODES              1
336
#define SRV_SET_MODE                2
337
#define SRV_GET_CAPS                3
6088 serge 338
#define SRV_CMDLINE                 4
2342 Serge 339
 
6084 serge 340
#define SRV_GET_PCI_INFO                20
4246 Serge 341
#define SRV_I915_GET_PARAM              21
6084 serge 342
#define SRV_I915_GEM_CREATE             22
343
#define SRV_DRM_GEM_CLOSE               23
4246 Serge 344
#define SRV_DRM_GEM_FLINK               24
345
#define SRV_DRM_GEM_OPEN                25
346
#define SRV_I915_GEM_PIN                26
347
#define SRV_I915_GEM_UNPIN              27
5367 serge 348
#define SRV_I915_GEM_GET_CACHING        28
349
#define SRV_I915_GEM_SET_CACHING        29
350
#define SRV_I915_GEM_PWRITE             30
351
#define SRV_I915_GEM_BUSY               31
352
#define SRV_I915_GEM_SET_DOMAIN         32
353
#define SRV_I915_GEM_MMAP               33
354
#define SRV_I915_GEM_SET_TILING         34
355
#define SRV_I915_GEM_GET_TILING         35
356
#define SRV_I915_GEM_GET_APERTURE       36
357
#define SRV_I915_GEM_MMAP_GTT           37
358
#define SRV_I915_GEM_THROTTLE           38
359
#define SRV_I915_GEM_EXECBUFFER2        39
360
#define SRV_I915_GEM_WAIT               40
361
#define SRV_I915_GEM_CONTEXT_CREATE     41
362
#define SRV_I915_GEM_CONTEXT_DESTROY    42
363
#define SRV_I915_REG_READ               43
3260 Serge 364
 
5367 serge 365
#define SRV_FBINFO                      44
366
#define SRV_MASK_UPDATE                 45
367
#define SRV_MASK_UPDATE_EX              46
3263 Serge 368
 
6131 serge 369
#define SRV_I915_GEM_PREAD              47
370
 
2338 Serge 371
#define check_input(size) \
372
    if( unlikely((inp==NULL)||(io->inp_size != (size))) )   \
373
        break;
374
 
375
#define check_output(size) \
376
    if( unlikely((outp==NULL)||(io->out_size != (size))) )   \
377
        break;
378
 
379
int _stdcall display_handler(ioctl_t *io)
380
{
3255 Serge 381
    struct drm_file *file;
382
 
6084 serge 383
    int  retval = -1;
5354 serge 384
    u32 *inp;
385
    u32 *outp;
2338 Serge 386
 
387
    inp = io->input;
388
    outp = io->output;
389
 
3255 Serge 390
    file = drm_file_handlers[0];
391
 
2338 Serge 392
    switch(io->io_code)
393
    {
394
        case SRV_GETVERSION:
395
            check_output(4);
2344 Serge 396
            *outp  = DISPLAY_VERSION;
2338 Serge 397
            retval = 0;
398
            break;
399
 
400
        case SRV_ENUM_MODES:
3031 serge 401
//            dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",
402
//                       inp, io->inp_size, io->out_size );
2340 Serge 403
            check_output(4);
2338 Serge 404
//            check_input(*outp * sizeof(videomode_t));
6088 serge 405
            retval = get_videomodes((videomode_t*)inp, outp);
2338 Serge 406
            break;
407
 
408
        case SRV_SET_MODE:
3031 serge 409
//            dbgprintf("SRV_SET_MODE inp %x inp_size %x\n",
410
//                       inp, io->inp_size);
2338 Serge 411
            check_input(sizeof(videomode_t));
6088 serge 412
            retval = set_user_mode((videomode_t*)inp);
2338 Serge 413
            break;
3033 serge 414
 
2351 Serge 415
        case SRV_GET_CAPS:
416
            retval = get_driver_caps((hwcaps_t*)inp);
417
            break;
418
 
6088 serge 419
        case SRV_CMDLINE:
420
            retval = do_command_line((char*)inp);
421
            break;
422
 
3260 Serge 423
        case SRV_GET_PCI_INFO:
3255 Serge 424
            get_pci_info((struct pci_device *)inp);
2338 Serge 425
            retval = 0;
426
            break;
3031 serge 427
 
4246 Serge 428
        case SRV_I915_GET_PARAM:
429
            retval = i915_getparam(main_device, inp, file);
3255 Serge 430
            break;
431
 
432
        case SRV_I915_GEM_CREATE:
433
            retval = i915_gem_create_ioctl(main_device, inp, file);
434
            break;
435
 
436
        case SRV_DRM_GEM_CLOSE:
437
            retval = drm_gem_close_ioctl(main_device, inp, file);
438
            break;
439
 
4246 Serge 440
        case SRV_DRM_GEM_FLINK:
441
            retval = drm_gem_flink_ioctl(main_device, inp, file);
442
            break;
443
 
444
        case SRV_DRM_GEM_OPEN:
445
            retval = drm_gem_open_ioctl(main_device, inp, file);
446
            break;
447
 
5367 serge 448
        case SRV_I915_GEM_GET_CACHING:
449
            retval = i915_gem_get_caching_ioctl(main_device, inp, file);
450
            break;
451
 
4246 Serge 452
        case SRV_I915_GEM_SET_CACHING:
453
            retval = i915_gem_set_caching_ioctl(main_device, inp, file);
3260 Serge 454
            break;
455
 
6131 serge 456
        case SRV_I915_GEM_PREAD:
457
            retval = i915_gem_pread_ioctl(main_device, inp, file);
458
            break;
459
 
3260 Serge 460
        case SRV_I915_GEM_PWRITE:
461
            retval = i915_gem_pwrite_ioctl(main_device, inp, file);
462
            break;
463
 
464
        case SRV_I915_GEM_BUSY:
465
            retval = i915_gem_busy_ioctl(main_device, inp, file);
466
            break;
467
 
468
        case SRV_I915_GEM_SET_DOMAIN:
469
            retval = i915_gem_set_domain_ioctl(main_device, inp, file);
470
            break;
471
 
3263 Serge 472
        case SRV_I915_GEM_MMAP:
473
            retval = i915_gem_mmap_ioctl(main_device, inp, file);
474
            break;
475
 
4246 Serge 476
        case SRV_I915_GEM_SET_TILING:
477
            retval = i915_gem_set_tiling(main_device, inp, file);
478
            break;
479
 
480
        case SRV_I915_GEM_GET_TILING:
481
            retval = i915_gem_get_tiling(main_device, inp, file);
482
            break;
483
 
484
        case SRV_I915_GEM_GET_APERTURE:
485
//            printf("SRV_I915_GEM_GET_APERTURE ");
486
            retval = i915_gem_get_aperture_ioctl(main_device, inp, file);
487
//            printf(" retval=%d\n", retval);
488
            break;
489
 
3480 Serge 490
        case SRV_I915_GEM_MMAP_GTT:
491
            retval = i915_gem_mmap_gtt_ioctl(main_device, inp, file);
492
            break;
493
 
4246 Serge 494
        case SRV_I915_GEM_THROTTLE:
495
            retval = i915_gem_throttle_ioctl(main_device, inp, file);
3263 Serge 496
            break;
497
 
498
        case SRV_I915_GEM_EXECBUFFER2:
499
            retval = i915_gem_execbuffer2(main_device, inp, file);
500
            break;
501
 
4246 Serge 502
        case SRV_I915_GEM_WAIT:
503
            retval = i915_gem_wait_ioctl(main_device, inp, file);
504
            break;
505
 
506
        case SRV_I915_GEM_CONTEXT_CREATE:
507
            retval = i915_gem_context_create_ioctl(main_device, inp, file);
508
            break;
509
 
510
        case SRV_I915_GEM_CONTEXT_DESTROY:
511
            retval = i915_gem_context_destroy_ioctl(main_device, inp, file);
512
            break;
513
 
514
        case SRV_I915_REG_READ:
515
            retval = i915_reg_read_ioctl(main_device, inp, file);
516
            break;
517
 
518
        case SRV_FBINFO:
519
            retval = i915_fbinfo(inp);
520
            break;
521
 
3290 Serge 522
        case SRV_MASK_UPDATE:
523
            retval = i915_mask_update(main_device, inp, file);
524
            break;
4539 Serge 525
 
526
        case SRV_MASK_UPDATE_EX:
527
            retval = i915_mask_update_ex(main_device, inp, file);
528
            break;
2338 Serge 529
    };
530
 
531
    return retval;
532
}
533
 
534
 
2325 Serge 535
#define PCI_CLASS_REVISION      0x08
536
#define PCI_CLASS_DISPLAY_VGA   0x0300
537
#define PCI_CLASS_BRIDGE_HOST   0x0600
2326 Serge 538
#define PCI_CLASS_BRIDGE_ISA    0x0601
2325 Serge 539
 
5354 serge 540
int pci_scan_filter(u32 id, u32 busnr, u32 devfn)
2325 Serge 541
{
5354 serge 542
    u16 vendor, device;
543
    u32 class;
2325 Serge 544
    int   ret = 0;
545
 
546
    vendor   = id & 0xffff;
547
    device   = (id >> 16) & 0xffff;
548
 
549
    if(vendor == 0x8086)
550
    {
551
        class = PciRead32(busnr, devfn, PCI_CLASS_REVISION);
552
        class >>= 16;
553
 
554
        if( (class == PCI_CLASS_DISPLAY_VGA) ||
2326 Serge 555
            (class == PCI_CLASS_BRIDGE_HOST) ||
556
            (class == PCI_CLASS_BRIDGE_ISA))
2325 Serge 557
            ret = 1;
558
    }
559
    return ret;
560
};
2340 Serge 561
 
562
 
5060 serge 563
struct mtrr
564
{
5354 serge 565
    u64  base;
566
    u64  mask;
5060 serge 567
};
568
 
569
struct cpuinfo
570
{
5354 serge 571
    u64  caps;
572
    u64  def_mtrr;
573
    u64  mtrr_cap;
5060 serge 574
    int    var_mtrr_count;
575
    int    fix_mtrr_count;
576
    struct mtrr var_mtrr[9];
577
    char   model_name[64];
578
};
579
 
580
#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
581
#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
582
 
583
#define MSR_MTRRdefType                 0x000002ff
584
 
585
#define IA32_MTRRCAP            0xFE
586
#define IA32_CR_PAT_MSR         0x277
587
 
588
#define PAT_TYPE_UC             0
589
#define PAT_TYPE_WC             1
590
#define PAT_TYPE_WB             6
591
#define PAT_TYPE_UCM            7
592
 
593
 
594
#define MTRR_UC                 0
595
#define MTRR_WC                 1
596
#define MTRR_WB                 6
597
 
5354 serge 598
static inline u64 read_msr(u32 msr)
5060 serge 599
{
600
    union {
5354 serge 601
        u64  val;
5060 serge 602
        struct {
5354 serge 603
            u32 low;
604
            u32 high;
5060 serge 605
        };
606
    }tmp;
607
 
608
    asm volatile (
609
    "rdmsr"
610
    : "=a" (tmp.low), "=d" (tmp.high)
611
    : "c" (msr));
612
    return tmp.val;
613
}
614
 
5354 serge 615
static inline void write_msr(u32 msr, u64 val)
5060 serge 616
{
617
    union {
5354 serge 618
        u64  val;
5060 serge 619
        struct {
5354 serge 620
            u32 low;
621
            u32 high;
5060 serge 622
        };
623
    }tmp;
624
 
625
    tmp.val = val;
626
 
627
    asm volatile (
628
    "wrmsr"
629
    :: "a" (tmp.low), "d" (tmp.high), "c" (msr));
630
}
631
 
632
#define SIZE_OR_MASK_BITS(n)  (~((1ULL << ((n) - PAGE_SHIFT)) - 1))
633
 
634
static void set_mtrr(unsigned int reg, unsigned long base,
635
                 unsigned long size, int type)
636
{
637
    unsigned int base_lo, base_hi, mask_lo, mask_hi;
638
    u64 size_or_mask, size_and_mask;
639
 
640
    size_or_mask = SIZE_OR_MASK_BITS(36);
641
    size_and_mask = 0x00f00000;
642
 
643
    if (size == 0) {
644
        /*
645
         * The invalid bit is kept in the mask, so we simply
646
         * clear the relevant mask register to disable a range.
647
         */
648
        native_write_msr(MTRRphysMask_MSR(reg), 0, 0);
649
    }
650
    else {
651
        base_lo = base << PAGE_SHIFT | type;
652
        base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT);
653
        mask_lo = -size << PAGE_SHIFT | 0x800;
654
        mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT);
655
 
656
        native_write_msr(MTRRphysBase_MSR(reg), base_lo, base_hi);
657
        native_write_msr(MTRRphysMask_MSR(reg), mask_lo, mask_hi);
658
    };
659
}
660
 
661
 
662
static u32 deftype_lo, deftype_hi;
663
 
5354 serge 664
void cpu_detect1()
2344 Serge 665
{
5060 serge 666
    struct cpuinfo cpuinfo;
667
 
2344 Serge 668
    u32 junk, tfms, cap0, misc;
5060 serge 669
    int i;
5354 serge 670
 
2344 Serge 671
    cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
672
 
673
    if (cap0 & (1<<19))
674
    {
675
        x86_clflush_size = ((misc >> 8) & 0xff) * 8;
676
    }
3482 Serge 677
 
5354 serge 678
#if 0
5060 serge 679
    cpuid(0x80000002, (unsigned int*)&cpuinfo.model_name[0], (unsigned int*)&cpuinfo.model_name[4],
680
          (unsigned int*)&cpuinfo.model_name[8], (unsigned int*)&cpuinfo.model_name[12]);
681
    cpuid(0x80000003, (unsigned int*)&cpuinfo.model_name[16], (unsigned int*)&cpuinfo.model_name[20],
682
          (unsigned int*)&cpuinfo.model_name[24], (unsigned int*)&cpuinfo.model_name[28]);
683
    cpuid(0x80000004, (unsigned int*)&cpuinfo.model_name[32], (unsigned int*)&cpuinfo.model_name[36],
684
          (unsigned int*)&cpuinfo.model_name[40], (unsigned int*)&cpuinfo.model_name[44]);
685
 
686
    printf("\n%s\n\n",cpuinfo.model_name);
687
 
688
    cpuinfo.def_mtrr = read_msr(MSR_MTRRdefType);
689
    cpuinfo.mtrr_cap = read_msr(IA32_MTRRCAP);
690
 
691
    printf("MSR_MTRRdefType %016llx\n\n", cpuinfo.def_mtrr);
692
 
693
    cpuinfo.var_mtrr_count = (u8_t)cpuinfo.mtrr_cap;
694
 
695
    for(i = 0; i < cpuinfo.var_mtrr_count; i++)
696
    {
697
        u64_t mtrr_base;
698
        u64_t mtrr_mask;
699
 
700
        cpuinfo.var_mtrr[i].base = read_msr(MTRRphysBase_MSR(i));
701
        cpuinfo.var_mtrr[i].mask = read_msr(MTRRphysMask_MSR(i));
702
 
703
        printf("MTRR_%d base: %016llx mask: %016llx\n", i,
704
               cpuinfo.var_mtrr[i].base,
705
               cpuinfo.var_mtrr[i].mask);
706
    };
707
 
708
    unsigned int cr0, cr3, cr4, eflags;
709
 
710
    eflags = safe_cli();
711
 
712
    /* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */
713
    cr0 = read_cr0() | (1<<30);
714
    write_cr0(cr0);
715
    wbinvd();
716
 
717
    cr4 = read_cr4();
718
    write_cr4(cr4 & ~(1<<7));
719
 
720
    cr3 = read_cr3();
721
    write_cr3(cr3);
722
 
723
    /* Save MTRR state */
724
    rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
725
 
726
    /* Disable MTRRs, and set the default type to uncached */
727
    native_write_msr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi);
728
    wbinvd();
729
 
730
    i = 0;
731
    set_mtrr(i++,0,0x80000000>>12,MTRR_WB);
732
    set_mtrr(i++,0x80000000>>12,0x40000000>>12,MTRR_WB);
733
    set_mtrr(i++,0xC0000000>>12,0x20000000>>12,MTRR_WB);
734
    set_mtrr(i++,0xdb800000>>12,0x00800000>>12,MTRR_UC);
735
    set_mtrr(i++,0xdc000000>>12,0x04000000>>12,MTRR_UC);
736
    set_mtrr(i++,0xE0000000>>12,0x10000000>>12,MTRR_WC);
737
 
738
    for(; i < cpuinfo.var_mtrr_count; i++)
739
        set_mtrr(i,0,0,0);
740
 
741
    write_cr3(cr3);
742
 
743
    /* Intel (P6) standard MTRRs */
744
    native_write_msr(MSR_MTRRdefType, deftype_lo, deftype_hi);
745
 
746
    /* Enable caches */
747
    write_cr0(read_cr0() & ~(1<<30));
748
 
749
    /* Restore value of CR4 */
750
    write_cr4(cr4);
751
 
752
    safe_sti(eflags);
753
 
754
    printf("\nnew MTRR map\n\n");
755
 
756
    for(i = 0; i < cpuinfo.var_mtrr_count; i++)
757
    {
758
        u64_t mtrr_base;
759
        u64_t mtrr_mask;
760
 
761
        cpuinfo.var_mtrr[i].base = read_msr(MTRRphysBase_MSR(i));
762
        cpuinfo.var_mtrr[i].mask = read_msr(MTRRphysMask_MSR(i));
763
 
764
        printf("MTRR_%d base: %016llx mask: %016llx\n", i,
765
               cpuinfo.var_mtrr[i].base,
766
               cpuinfo.var_mtrr[i].mask);
767
    };
768
#endif
769
 
3482 Serge 770
    tsc_khz = (unsigned int)(GetCpuFreq()/1000);
2344 Serge 771
}
772
 
3243 Serge 773
 
774
int get_driver_caps(hwcaps_t *caps)
775
{
776
    int ret = 0;
777
 
778
    switch(caps->idx)
779
    {
780
        case 0:
781
            caps->opt[0] = 0;
782
            caps->opt[1] = 0;
783
            break;
784
 
785
        case 1:
786
            caps->cap1.max_tex_width  = 4096;
787
            caps->cap1.max_tex_height = 4096;
788
            break;
789
        default:
790
            ret = 1;
791
    };
792
    caps->idx = 1;
793
    return ret;
794
}
795
 
3255 Serge 796
 
797
void get_pci_info(struct pci_device *dev)
798
{
799
    struct pci_dev *pdev = main_device->pdev;
800
 
801
    memset(dev, sizeof(*dev), 0);
802
 
803
    dev->domain     = 0;
804
    dev->bus        = pdev->busnr;
805
    dev->dev        = pdev->devfn >> 3;
806
    dev->func       = pdev->devfn & 7;
807
    dev->vendor_id  = pdev->vendor;
808
    dev->device_id  = pdev->device;
809
    dev->revision   = pdev->revision;
810
};
4246 Serge 811
 
812
 
813
 
4280 Serge 814
char *strstr(const char *cs, const char *ct);
815
 
816
static int my_atoi(char **cmd)
817
{
818
    char* p = *cmd;
819
    int val = 0;
820
    int sign = 1;
821
 
822
    if(*p == '-')
823
    {
824
        sign = -1;
825
        p++;
826
    };
827
 
828
    for (;; *p++) {
829
        switch (*p) {
830
        case '0' ... '9':
831
            val = 10*val+(*p-'0');
832
            break;
833
        default:
834
            *cmd = p;
835
            return val*sign;
836
        }
837
    }
838
}
839
 
6088 serge 840
static char* parse_mode(char *p, videomode_t *mode)
4280 Serge 841
{
842
    char c;
843
 
844
    while( (c = *p++) == ' ');
845
 
846
    if( c )
847
    {
848
        p--;
849
 
850
        mode->width = my_atoi(&p);
851
        if(*p == 'x') p++;
852
 
853
        mode->height = my_atoi(&p);
854
        if(*p == 'x') p++;
855
 
856
        mode->bpp = 32;
857
 
858
        mode->freq = my_atoi(&p);
859
 
860
        if( mode->freq == 0 )
861
            mode->freq = 60;
862
    }
863
 
864
    return p;
865
};
866