WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/main.c

Rev	Author	Line No.	Line
6084	serge	1	#include
		2
3031	serge	3	#include
		4	#include
2338	Serge	5	#include "i915_drv.h"
		6
2325	Serge	7	#include
		8	#include
		9	#include
		10	#include
		11
6088	serge	12	#include "getopt.h"
		13
2342	Serge	14	#include "bitmap.h"
6088	serge	15	#include "i915_kos32.h"
2340	Serge	16
6084	serge	17	#define DRV_NAME "i915 v4.4"
		18
5060	serge	19	#define I915_DEV_CLOSE 0
		20	#define I915_DEV_INIT 1
		21	#define I915_DEV_READY 2
		22
6088	serge	23	static int my_atoi(char **cmd);
		24	static char* parse_mode(char p, videomode_t mode);
5354	serge	25	void cpu_detect1();
		26	int kmap_init();
2344	Serge	27
5060	serge	28	unsigned long volatile jiffies;
6088	serge	29	int oops_in_progress;
		30	int x86_clflush_size;
		31	unsigned int tsc_khz;
3482	Serge	32	struct workqueue_struct *system_wq;
3764	Serge	33	int driver_wq_state;
6088	serge	34	struct drm_device *main_device;
		35	struct drm_file *drm_file_handlers[256];
		36	videomode_t usermode;
		37	extern int __getopt_initialized;
3482	Serge	38
4126	Serge	39	void i915_driver_thread()
		40	{
5060	serge	41	struct drm_i915_private *dev_priv = NULL;
		42	struct workqueue_struct *cwq = NULL;
4126	Serge	43	static int dpms = 1;
		44	static int dpms_lock = 0;
		45	oskey_t key;
		46	unsigned long irqflags;
		47	int tmp;
		48
		49	printf("%s\n",__FUNCTION__);
		50
5060	serge	51	while(driver_wq_state == I915_DEV_INIT)
		52	{
6084	serge	53	jiffies = GetClockNs() / 10000000;
5060	serge	54	delay(1);
		55	};
		56
6084	serge	57	if( driver_wq_state == I915_DEV_CLOSE)
		58	{
		59	asm volatile ("int $0x40"::"a"(-1));
		60	};
		61
5060	serge	62	dev_priv = main_device->dev_private;
		63	cwq = dev_priv->wq;
		64
4126	Serge	65	asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(1),"c"(1));
		66	asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0x46),"d"(0x330));
		67	asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0xC6),"d"(0x330));
		68
5060	serge	69	while(driver_wq_state != I915_DEV_CLOSE)
4126	Serge	70	{
6084	serge	71	jiffies = GetClockNs() / 10000000;
5060	serge	72
4126	Serge	73	key = get_key();
		74
		75	if( (key.val != 1) && (key.state == 0x02))
		76	{
		77	if(key.code == 0x46 && dpms_lock == 0)
		78	{
		79	dpms_lock = 1;
		80	if(dpms == 1)
		81	{
		82	i915_dpms(main_device, DRM_MODE_DPMS_OFF);
		83	printf("dpms off\n");
		84	}
		85	else
		86	{
		87	i915_dpms(main_device, DRM_MODE_DPMS_ON);
		88	printf("dpms on\n");
		89	};
		90	dpms ^= 1;
		91	}
		92	else if(key.code == 0xC6)
		93	dpms_lock = 0;
		94	};
		95
		96	spin_lock_irqsave(&cwq->lock, irqflags);
		97
		98	while (!list_empty(&cwq->worklist))
		99	{
		100	struct work_struct *work = list_entry(cwq->worklist.next,
		101	struct work_struct, entry);
		102	work_func_t f = work->func;
		103	list_del_init(cwq->worklist.next);
		104
		105	spin_unlock_irqrestore(&cwq->lock, irqflags);
		106	f(work);
		107	spin_lock_irqsave(&cwq->lock, irqflags);
		108	}
		109
		110	spin_unlock_irqrestore(&cwq->lock, irqflags);
		111
		112	delay(1);
		113	};
		114
		115	asm volatile ("int $0x40"::"a"(-1));
		116	}
		117
5354	serge	118	u32 __attribute__((externally_visible)) drvEntry(int action, char *cmdline)
2325	Serge	119	{
5060	serge	120	static pci_dev_t device;
		121	const struct pci_device_id *ent;
6088	serge	122	char *safecmdline;
4104	Serge	123	int err = 0;
2325	Serge	124
		125	if(action != 1)
3764	Serge	126	{
5060	serge	127	driver_wq_state = I915_DEV_CLOSE;
2325	Serge	128	return 0;
3764	Serge	129	};
2325	Serge	130
		131	if( GetService("DISPLAY") != 0 )
		132	return 0;
		133
6084	serge	134	printf("\n%s build %s %s\nusage: i915 [options]\n"
6088	serge	135	"-f\n"
		136	"--fbsize <0-9> Set framebuffer size in megabytes (default: 16)\n",
6084	serge	137	DRV_NAME, __DATE__, __TIME__);
		138
6088	serge	139	printf("--rc6 <-1,0-7> Enable power-saving render C-state 6.\n"
		140	" Different stages can be selected via bitmask values\n"
		141	" (0 = disable; 1 = enable rc6; 2 = enable deep rc6;\n"
		142	" 4 = enable deepest rc6).\n"
		143	" For example, 3 would enable rc6 and deep rc6,\n"
		144	" and 7 would enable everything.\n"
		145	" default: -1 (use per-chip default)\n");
		146	printf("--fbc <-1,0,1> Enable frame buffer compression for power savings\n"
		147	" (default: -1 (use per-chip default))\n");
		148	printf("-l\n"
		149	"--log path to log file\n");
		150	printf("-m\n"
		151	"--mode set videomode\n");
		152	printf("-v\n"
		153	"--video :x[M][R][-][@][i][m][eDd]\n"
		154	" set videomode for CONNECTOR\n");
6084	serge	155
2340	Serge	156	if( cmdline && *cmdline )
6088	serge	157	{
		158	int argc, i, c;
		159	char **argv;
2325	Serge	160
6088	serge	161	safecmdline = __builtin_strdup(cmdline);
		162	printf("cmdline %s\n", safecmdline);
		163
		164	argc = split_cmdline(safecmdline, NULL);
		165	argv = __builtin_malloc((argc+1)sizeof(char));
		166	split_cmdline(safecmdline, argv);
		167	argv[argc] = NULL;
		168
		169	while(1)
		170	{
		171	static struct option long_options[] =
		172	{
		173	{"log", required_argument, 0, 'l'},
		174	{"mode", required_argument, 0, 'm'},
		175	{"fbsize",required_argument, 0, 'f'},
		176	{"video", required_argument, 0, 'v'},
		177	{"rc6", required_argument, 0, OPTION_RC6},
		178	{"fbc", required_argument, 0, OPTION_FBC},
		179	{0, 0, 0, 0}
		180	};
		181
		182	int option_index = 0;
		183
		184	c = getopt_long (argc, argv, "f:l:m:v:",
		185	long_options, &option_index);
		186
		187	if (c == -1)
		188	break;
		189
		190	switch(c)
		191	{
		192	case OPTION_RC6:
		193	i915.enable_rc6 = my_atoi(&optarg);
		194	printf("i915.rc6 = %d\n",i915.enable_rc6);
		195	break;
		196
		197	case OPTION_FBC:
		198	i915.enable_fbc = my_atoi(&optarg);
		199	printf("i915.fbc = %d\n",i915.enable_fbc);
		200	break;
		201
		202	case 'f':
		203	i915.fbsize = my_atoi(&optarg);
		204	printf("i915.fbsize =%d\n",i915.fbsize);
		205	break;
		206
		207	case 'l':
		208	i915.log_file = optarg;
		209	break;
		210
		211	case 'm':
		212	parse_mode(optarg, &usermode);
		213	break;
		214
		215	case 'v':
		216	i915.cmdline_mode = optarg;
		217	printf("i915.cmdline_mode =%s\n",i915.cmdline_mode);
		218	break;
		219	}
		220	}
		221	};
		222
		223	if( i915.log_file && !dbg_open(i915.log_file))
6084	serge	224	{
6088	serge	225	printf("Can't open %s\nExit\n", i915.log_file);
6084	serge	226	return 0;
2325	Serge	227	}
6084	serge	228	else
		229	{
		230	dbgprintf("\nLOG: %s build %s %s\n",DRV_NAME,__DATE__, __TIME__);
		231	}
2325	Serge	232
5354	serge	233	cpu_detect1();
2351	Serge	234
5060	serge	235	err = enum_pci_devices();
		236	if( unlikely(err != 0) )
		237	{
		238	dbgprintf("Device enumeration failed\n");
		239	return 0;
		240	}
2325	Serge	241
5354	serge	242	err = kmap_init();
		243	if( unlikely(err != 0) )
		244	{
		245	dbgprintf("kmap initialization failed\n");
		246	return 0;
		247	}
		248
5097	serge	249	dmi_scan_machine();
		250
5060	serge	251	driver_wq_state = I915_DEV_INIT;
		252	CreateKernelThread(i915_driver_thread);
		253
2325	Serge	254	err = i915_init();
5060	serge	255	if(unlikely(err!= 0))
2338	Serge	256	{
5060	serge	257	driver_wq_state = I915_DEV_CLOSE;
3298	Serge	258	dbgprintf("Epic Fail :(\n");
6084	serge	259	delay(100);
3298	Serge	260	return 0;
2338	Serge	261	};
2325	Serge	262
5060	serge	263	driver_wq_state = I915_DEV_READY;
		264
4280	Serge	265	init_display_kms(main_device, &usermode);
		266
2338	Serge	267	err = RegService("DISPLAY", display_handler);
2325	Serge	268
2338	Serge	269	if( err != 0)
		270	dbgprintf("Set DISPLAY handler\n");
		271
2325	Serge	272	return err;
		273	};
		274
6088	serge	275	int do_command_line(const char* usercmd)
		276	{
		277	char *cmdline;
		278	int argc, i, c;
		279	char **argv;
3480	Serge	280
6088	serge	281	if( (usercmd == NULL) \|\| (*usercmd == 0) )
		282	return 1;
		283
		284	cmdline = __builtin_strdup(usercmd);
		285	printf("cmdline %s\n", cmdline);
		286
		287	argc = split_cmdline(cmdline, NULL);
		288	argv = __builtin_malloc((argc+1)sizeof(char));
		289	split_cmdline(cmdline, argv);
		290	argv[argc] = NULL;
		291
		292	__getopt_initialized = 0;
		293
		294	while(1)
		295	{
		296	static struct option long_options[] =
		297	{
		298	{"video", required_argument, 0, 'v'},
		299	{0, 0, 0, 0}
		300	};
		301
		302	int option_index = 0;
		303
		304	c = getopt_long (argc, argv, "v:",
		305	long_options, &option_index);
		306
		307	if (c == -1)
		308	break;
		309
		310	switch(c)
		311	{
		312	case 'v':
		313	printf("cmdline_mode %s\n",optarg);
		314	set_cmdline_mode_ext(main_device, optarg);
		315	break;
		316	}
		317	}
		318	__builtin_free(argv);
		319	__builtin_free(cmdline);
		320
		321	return 0;
		322	};
		323
2344	Serge	324	#define CURRENT_API 0x0200 /* 2.00 */
		325	#define COMPATIBLE_API 0x0100 /* 1.00 */
2338	Serge	326
2344	Serge	327	#define API_VERSION (COMPATIBLE_API << 16) \| CURRENT_API
2351	Serge	328	#define DISPLAY_VERSION API_VERSION
2338	Serge	329
		330
6084	serge	331	#define SRV_GETVERSION 0
		332	#define SRV_ENUM_MODES 1
		333	#define SRV_SET_MODE 2
		334	#define SRV_GET_CAPS 3
6088	serge	335	#define SRV_CMDLINE 4
2342	Serge	336
6084	serge	337	#define SRV_GET_PCI_INFO 20
4246	Serge	338	#define SRV_I915_GET_PARAM 21
6084	serge	339	#define SRV_I915_GEM_CREATE 22
		340	#define SRV_DRM_GEM_CLOSE 23
4246	Serge	341	#define SRV_DRM_GEM_FLINK 24
		342	#define SRV_DRM_GEM_OPEN 25
		343	#define SRV_I915_GEM_PIN 26
		344	#define SRV_I915_GEM_UNPIN 27
5367	serge	345	#define SRV_I915_GEM_GET_CACHING 28
		346	#define SRV_I915_GEM_SET_CACHING 29
		347	#define SRV_I915_GEM_PWRITE 30
		348	#define SRV_I915_GEM_BUSY 31
		349	#define SRV_I915_GEM_SET_DOMAIN 32
		350	#define SRV_I915_GEM_MMAP 33
		351	#define SRV_I915_GEM_SET_TILING 34
		352	#define SRV_I915_GEM_GET_TILING 35
		353	#define SRV_I915_GEM_GET_APERTURE 36
		354	#define SRV_I915_GEM_MMAP_GTT 37
		355	#define SRV_I915_GEM_THROTTLE 38
		356	#define SRV_I915_GEM_EXECBUFFER2 39
		357	#define SRV_I915_GEM_WAIT 40
		358	#define SRV_I915_GEM_CONTEXT_CREATE 41
		359	#define SRV_I915_GEM_CONTEXT_DESTROY 42
		360	#define SRV_I915_REG_READ 43
3260	Serge	361
5367	serge	362	#define SRV_FBINFO 44
		363	#define SRV_MASK_UPDATE 45
		364	#define SRV_MASK_UPDATE_EX 46
3263	Serge	365
2338	Serge	366	#define check_input(size) \
		367	if( unlikely((inp==NULL)\|\|(io->inp_size != (size))) ) \
		368	break;
		369
		370	#define check_output(size) \
		371	if( unlikely((outp==NULL)\|\|(io->out_size != (size))) ) \
		372	break;
		373
		374	int _stdcall display_handler(ioctl_t *io)
		375	{
3255	Serge	376	struct drm_file *file;
		377
6084	serge	378	int retval = -1;
5354	serge	379	u32 *inp;
		380	u32 *outp;
2338	Serge	381
		382	inp = io->input;
		383	outp = io->output;
		384
3255	Serge	385	file = drm_file_handlers[0];
		386
2338	Serge	387	switch(io->io_code)
		388	{
		389	case SRV_GETVERSION:
		390	check_output(4);
2344	Serge	391	*outp = DISPLAY_VERSION;
2338	Serge	392	retval = 0;
		393	break;
		394
		395	case SRV_ENUM_MODES:
3031	serge	396	// dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",
		397	// inp, io->inp_size, io->out_size );
2340	Serge	398	check_output(4);
2338	Serge	399	// check_input(outp sizeof(videomode_t));
6088	serge	400	retval = get_videomodes((videomode_t*)inp, outp);
2338	Serge	401	break;
		402
		403	case SRV_SET_MODE:
3031	serge	404	// dbgprintf("SRV_SET_MODE inp %x inp_size %x\n",
		405	// inp, io->inp_size);
2338	Serge	406	check_input(sizeof(videomode_t));
6088	serge	407	retval = set_user_mode((videomode_t*)inp);
2338	Serge	408	break;
3033	serge	409
2351	Serge	410	case SRV_GET_CAPS:
		411	retval = get_driver_caps((hwcaps_t*)inp);
		412	break;
		413
6088	serge	414	case SRV_CMDLINE:
		415	retval = do_command_line((char*)inp);
		416	break;
		417
3260	Serge	418	case SRV_GET_PCI_INFO:
3255	Serge	419	get_pci_info((struct pci_device *)inp);
2338	Serge	420	retval = 0;
		421	break;
3031	serge	422
4246	Serge	423	case SRV_I915_GET_PARAM:
		424	retval = i915_getparam(main_device, inp, file);
3255	Serge	425	break;
		426
		427	case SRV_I915_GEM_CREATE:
		428	retval = i915_gem_create_ioctl(main_device, inp, file);
		429	break;
		430
		431	case SRV_DRM_GEM_CLOSE:
		432	retval = drm_gem_close_ioctl(main_device, inp, file);
		433	break;
		434
4246	Serge	435	case SRV_DRM_GEM_FLINK:
		436	retval = drm_gem_flink_ioctl(main_device, inp, file);
		437	break;
		438
		439	case SRV_DRM_GEM_OPEN:
		440	retval = drm_gem_open_ioctl(main_device, inp, file);
		441	break;
		442
5367	serge	443	case SRV_I915_GEM_GET_CACHING:
		444	retval = i915_gem_get_caching_ioctl(main_device, inp, file);
		445	break;
		446
4246	Serge	447	case SRV_I915_GEM_SET_CACHING:
		448	retval = i915_gem_set_caching_ioctl(main_device, inp, file);
3260	Serge	449	break;
		450
		451	case SRV_I915_GEM_PWRITE:
		452	retval = i915_gem_pwrite_ioctl(main_device, inp, file);
		453	break;
		454
		455	case SRV_I915_GEM_BUSY:
		456	retval = i915_gem_busy_ioctl(main_device, inp, file);
		457	break;
		458
		459	case SRV_I915_GEM_SET_DOMAIN:
		460	retval = i915_gem_set_domain_ioctl(main_device, inp, file);
		461	break;
		462
3263	Serge	463	case SRV_I915_GEM_MMAP:
		464	retval = i915_gem_mmap_ioctl(main_device, inp, file);
		465	break;
		466
4246	Serge	467	case SRV_I915_GEM_SET_TILING:
		468	retval = i915_gem_set_tiling(main_device, inp, file);
		469	break;
		470
		471	case SRV_I915_GEM_GET_TILING:
		472	retval = i915_gem_get_tiling(main_device, inp, file);
		473	break;
		474
		475	case SRV_I915_GEM_GET_APERTURE:
		476	// printf("SRV_I915_GEM_GET_APERTURE ");
		477	retval = i915_gem_get_aperture_ioctl(main_device, inp, file);
		478	// printf(" retval=%d\n", retval);
		479	break;
		480
3480	Serge	481	case SRV_I915_GEM_MMAP_GTT:
		482	retval = i915_gem_mmap_gtt_ioctl(main_device, inp, file);
		483	break;
		484
4246	Serge	485	case SRV_I915_GEM_THROTTLE:
		486	retval = i915_gem_throttle_ioctl(main_device, inp, file);
3263	Serge	487	break;
		488
		489	case SRV_I915_GEM_EXECBUFFER2:
4246	Serge	490	// printf("SRV_I915_GEM_EXECBUFFER2\n");
3263	Serge	491	retval = i915_gem_execbuffer2(main_device, inp, file);
		492	break;
		493
4246	Serge	494	case SRV_I915_GEM_WAIT:
		495	retval = i915_gem_wait_ioctl(main_device, inp, file);
		496	break;
		497
		498	case SRV_I915_GEM_CONTEXT_CREATE:
		499	retval = i915_gem_context_create_ioctl(main_device, inp, file);
		500	break;
		501
		502	case SRV_I915_GEM_CONTEXT_DESTROY:
		503	retval = i915_gem_context_destroy_ioctl(main_device, inp, file);
		504	break;
		505
		506	case SRV_I915_REG_READ:
		507	retval = i915_reg_read_ioctl(main_device, inp, file);
		508	break;
		509
		510	case SRV_FBINFO:
		511	retval = i915_fbinfo(inp);
		512	break;
		513
3290	Serge	514	case SRV_MASK_UPDATE:
		515	retval = i915_mask_update(main_device, inp, file);
		516	break;
4539	Serge	517
		518	case SRV_MASK_UPDATE_EX:
		519	retval = i915_mask_update_ex(main_device, inp, file);
		520	break;
2338	Serge	521	};
		522
		523	return retval;
		524	}
		525
		526
2325	Serge	527	#define PCI_CLASS_REVISION 0x08
		528	#define PCI_CLASS_DISPLAY_VGA 0x0300
		529	#define PCI_CLASS_BRIDGE_HOST 0x0600
2326	Serge	530	#define PCI_CLASS_BRIDGE_ISA 0x0601
2325	Serge	531
5354	serge	532	int pci_scan_filter(u32 id, u32 busnr, u32 devfn)
2325	Serge	533	{
5354	serge	534	u16 vendor, device;
		535	u32 class;
2325	Serge	536	int ret = 0;
		537
		538	vendor = id & 0xffff;
		539	device = (id >> 16) & 0xffff;
		540
		541	if(vendor == 0x8086)
		542	{
		543	class = PciRead32(busnr, devfn, PCI_CLASS_REVISION);
		544	class >>= 16;
		545
		546	if( (class == PCI_CLASS_DISPLAY_VGA) \|\|
2326	Serge	547	(class == PCI_CLASS_BRIDGE_HOST) \|\|
		548	(class == PCI_CLASS_BRIDGE_ISA))
2325	Serge	549	ret = 1;
		550	}
		551	return ret;
		552	};
2340	Serge	553
		554
5060	serge	555	struct mtrr
		556	{
5354	serge	557	u64 base;
		558	u64 mask;
5060	serge	559	};
		560
		561	struct cpuinfo
		562	{
5354	serge	563	u64 caps;
		564	u64 def_mtrr;
		565	u64 mtrr_cap;
5060	serge	566	int var_mtrr_count;
		567	int fix_mtrr_count;
		568	struct mtrr var_mtrr[9];
		569	char model_name[64];
		570	};
		571
		572	#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
		573	#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
		574
		575	#define MSR_MTRRdefType 0x000002ff
		576
		577	#define IA32_MTRRCAP 0xFE
		578	#define IA32_CR_PAT_MSR 0x277
		579
		580	#define PAT_TYPE_UC 0
		581	#define PAT_TYPE_WC 1
		582	#define PAT_TYPE_WB 6
		583	#define PAT_TYPE_UCM 7
		584
		585
		586	#define MTRR_UC 0
		587	#define MTRR_WC 1
		588	#define MTRR_WB 6
		589
5354	serge	590	static inline u64 read_msr(u32 msr)
5060	serge	591	{
		592	union {
5354	serge	593	u64 val;
5060	serge	594	struct {
5354	serge	595	u32 low;
		596	u32 high;
5060	serge	597	};
		598	}tmp;
		599
		600	asm volatile (
		601	"rdmsr"
		602	: "=a" (tmp.low), "=d" (tmp.high)
		603	: "c" (msr));
		604	return tmp.val;
		605	}
		606
5354	serge	607	static inline void write_msr(u32 msr, u64 val)
5060	serge	608	{
		609	union {
5354	serge	610	u64 val;
5060	serge	611	struct {
5354	serge	612	u32 low;
		613	u32 high;
5060	serge	614	};
		615	}tmp;
		616
		617	tmp.val = val;
		618
		619	asm volatile (
		620	"wrmsr"
		621	:: "a" (tmp.low), "d" (tmp.high), "c" (msr));
		622	}
		623
		624	#define SIZE_OR_MASK_BITS(n) (~((1ULL << ((n) - PAGE_SHIFT)) - 1))
		625
		626	static void set_mtrr(unsigned int reg, unsigned long base,
		627	unsigned long size, int type)
		628	{
		629	unsigned int base_lo, base_hi, mask_lo, mask_hi;
		630	u64 size_or_mask, size_and_mask;
		631
		632	size_or_mask = SIZE_OR_MASK_BITS(36);
		633	size_and_mask = 0x00f00000;
		634
		635	if (size == 0) {
		636	/*
		637	* The invalid bit is kept in the mask, so we simply
		638	* clear the relevant mask register to disable a range.
		639	*/
		640	native_write_msr(MTRRphysMask_MSR(reg), 0, 0);
		641	}
		642	else {
		643	base_lo = base << PAGE_SHIFT \| type;
		644	base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT);
		645	mask_lo = -size << PAGE_SHIFT \| 0x800;
		646	mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT);
		647
		648	native_write_msr(MTRRphysBase_MSR(reg), base_lo, base_hi);
		649	native_write_msr(MTRRphysMask_MSR(reg), mask_lo, mask_hi);
		650	};
		651	}
		652
		653
		654	static u32 deftype_lo, deftype_hi;
		655
5354	serge	656	void cpu_detect1()
2344	Serge	657	{
5060	serge	658	struct cpuinfo cpuinfo;
		659
2344	Serge	660	u32 junk, tfms, cap0, misc;
5060	serge	661	int i;
5354	serge	662
2344	Serge	663	cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
		664
		665	if (cap0 & (1<<19))
		666	{
		667	x86_clflush_size = ((misc >> 8) & 0xff) * 8;
		668	}
3482	Serge	669
5354	serge	670	#if 0
5060	serge	671	cpuid(0x80000002, (unsigned int)&cpuinfo.model_name[0], (unsigned int)&cpuinfo.model_name[4],
		672	(unsigned int)&cpuinfo.model_name[8], (unsigned int)&cpuinfo.model_name[12]);
		673	cpuid(0x80000003, (unsigned int)&cpuinfo.model_name[16], (unsigned int)&cpuinfo.model_name[20],
		674	(unsigned int)&cpuinfo.model_name[24], (unsigned int)&cpuinfo.model_name[28]);
		675	cpuid(0x80000004, (unsigned int)&cpuinfo.model_name[32], (unsigned int)&cpuinfo.model_name[36],
		676	(unsigned int)&cpuinfo.model_name[40], (unsigned int)&cpuinfo.model_name[44]);
		677
		678	printf("\n%s\n\n",cpuinfo.model_name);
		679
		680	cpuinfo.def_mtrr = read_msr(MSR_MTRRdefType);
		681	cpuinfo.mtrr_cap = read_msr(IA32_MTRRCAP);
		682
		683	printf("MSR_MTRRdefType %016llx\n\n", cpuinfo.def_mtrr);
		684
		685	cpuinfo.var_mtrr_count = (u8_t)cpuinfo.mtrr_cap;
		686
		687	for(i = 0; i < cpuinfo.var_mtrr_count; i++)
		688	{
		689	u64_t mtrr_base;
		690	u64_t mtrr_mask;
		691
		692	cpuinfo.var_mtrr[i].base = read_msr(MTRRphysBase_MSR(i));
		693	cpuinfo.var_mtrr[i].mask = read_msr(MTRRphysMask_MSR(i));
		694
		695	printf("MTRR_%d base: %016llx mask: %016llx\n", i,
		696	cpuinfo.var_mtrr[i].base,
		697	cpuinfo.var_mtrr[i].mask);
		698	};
		699
		700	unsigned int cr0, cr3, cr4, eflags;
		701
		702	eflags = safe_cli();
		703
		704	/* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */
		705	cr0 = read_cr0() \| (1<<30);
		706	write_cr0(cr0);
		707	wbinvd();
		708
		709	cr4 = read_cr4();
		710	write_cr4(cr4 & ~(1<<7));
		711
		712	cr3 = read_cr3();
		713	write_cr3(cr3);
		714
		715	/* Save MTRR state */
		716	rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
		717
		718	/* Disable MTRRs, and set the default type to uncached */
		719	native_write_msr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi);
		720	wbinvd();
		721
		722	i = 0;
		723	set_mtrr(i++,0,0x80000000>>12,MTRR_WB);
		724	set_mtrr(i++,0x80000000>>12,0x40000000>>12,MTRR_WB);
		725	set_mtrr(i++,0xC0000000>>12,0x20000000>>12,MTRR_WB);
		726	set_mtrr(i++,0xdb800000>>12,0x00800000>>12,MTRR_UC);
		727	set_mtrr(i++,0xdc000000>>12,0x04000000>>12,MTRR_UC);
		728	set_mtrr(i++,0xE0000000>>12,0x10000000>>12,MTRR_WC);
		729
		730	for(; i < cpuinfo.var_mtrr_count; i++)
		731	set_mtrr(i,0,0,0);
		732
		733	write_cr3(cr3);
		734
		735	/* Intel (P6) standard MTRRs */
		736	native_write_msr(MSR_MTRRdefType, deftype_lo, deftype_hi);
		737
		738	/* Enable caches */
		739	write_cr0(read_cr0() & ~(1<<30));
		740
		741	/* Restore value of CR4 */
		742	write_cr4(cr4);
		743
		744	safe_sti(eflags);
		745
		746	printf("\nnew MTRR map\n\n");
		747
		748	for(i = 0; i < cpuinfo.var_mtrr_count; i++)
		749	{
		750	u64_t mtrr_base;
		751	u64_t mtrr_mask;
		752
		753	cpuinfo.var_mtrr[i].base = read_msr(MTRRphysBase_MSR(i));
		754	cpuinfo.var_mtrr[i].mask = read_msr(MTRRphysMask_MSR(i));
		755
		756	printf("MTRR_%d base: %016llx mask: %016llx\n", i,
		757	cpuinfo.var_mtrr[i].base,
		758	cpuinfo.var_mtrr[i].mask);
		759	};
		760	#endif
		761
3482	Serge	762	tsc_khz = (unsigned int)(GetCpuFreq()/1000);
2344	Serge	763	}
		764
3243	Serge	765
		766	int get_driver_caps(hwcaps_t *caps)
		767	{
		768	int ret = 0;
		769
		770	switch(caps->idx)
		771	{
		772	case 0:
		773	caps->opt[0] = 0;
		774	caps->opt[1] = 0;
		775	break;
		776
		777	case 1:
		778	caps->cap1.max_tex_width = 4096;
		779	caps->cap1.max_tex_height = 4096;
		780	break;
		781	default:
		782	ret = 1;
		783	};
		784	caps->idx = 1;
		785	return ret;
		786	}
		787
3255	Serge	788
		789	void get_pci_info(struct pci_device *dev)
		790	{
		791	struct pci_dev *pdev = main_device->pdev;
		792
		793	memset(dev, sizeof(*dev), 0);
		794
		795	dev->domain = 0;
		796	dev->bus = pdev->busnr;
		797	dev->dev = pdev->devfn >> 3;
		798	dev->func = pdev->devfn & 7;
		799	dev->vendor_id = pdev->vendor;
		800	dev->device_id = pdev->device;
		801	dev->revision = pdev->revision;
		802	};
4246	Serge	803
		804
		805
4280	Serge	806	char strstr(const char cs, const char *ct);
		807
		808	static int my_atoi(char **cmd)
		809	{
		810	char* p = *cmd;
		811	int val = 0;
		812	int sign = 1;
		813
		814	if(*p == '-')
		815	{
		816	sign = -1;
		817	p++;
		818	};
		819
		820	for (;; *p++) {
		821	switch (*p) {
		822	case '0' ... '9':
		823	val = 10val+(p-'0');
		824	break;
		825	default:
		826	*cmd = p;
		827	return val*sign;
		828	}
		829	}
		830	}
		831
6088	serge	832	static char* parse_mode(char p, videomode_t mode)
4280	Serge	833	{
		834	char c;
		835
		836	while( (c = *p++) == ' ');
		837
		838	if( c )
		839	{
		840	p--;
		841
		842	mode->width = my_atoi(&p);
		843	if(*p == 'x') p++;
		844
		845	mode->height = my_atoi(&p);
		846	if(*p == 'x') p++;
		847
		848	mode->bpp = 32;
		849
		850	mode->freq = my_atoi(&p);
		851
		852	if( mode->freq == 0 )
		853	mode->freq = 60;
		854	}
		855
		856	return p;
		857	};
		858
6084	serge	859	#include
		860
		861	u64 long_div(u64 dividend, u64 divisor)
		862	{
		863	#if 1
		864	u32 high = divisor >> 32;
		865	u64 quot;
		866
		867	if (high == 0) {
		868	quot = div_u64(dividend, divisor);
		869	} else {
		870	int n = 1 + fls(high);
		871	quot = div_u64(dividend >> n, divisor >> n);
		872
		873	if (quot != 0)
		874	quot--;
		875	if ((dividend - quot * divisor) >= divisor)
		876	quot++;
		877	}
		878
		879	return quot;
		880	#endif
		881	// return dividend / divisor;
		882	};
		883
		884
		885
		886

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