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Rev | Author | Line No. | Line |
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6084 | serge | 1 | #include |
2 | |||
3031 | serge | 3 | #include |
4 | #include |
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2338 | Serge | 5 | #include "i915_drv.h" |
6 | |||
2325 | Serge | 7 | #include |
8 | #include |
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9 | #include |
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10 | #include |
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11 | |||
2342 | Serge | 12 | #include "bitmap.h" |
2340 | Serge | 13 | |
6084 | serge | 14 | #define DRV_NAME "i915 v4.4" |
15 | |||
5060 | serge | 16 | #define I915_DEV_CLOSE 0 |
17 | #define I915_DEV_INIT 1 |
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18 | #define I915_DEV_READY 2 |
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19 | |||
20 | |||
3255 | Serge | 21 | struct pci_device { |
22 | uint16_t domain; |
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23 | uint8_t bus; |
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24 | uint8_t dev; |
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25 | uint8_t func; |
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26 | uint16_t vendor_id; |
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27 | uint16_t device_id; |
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28 | uint16_t subvendor_id; |
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29 | uint16_t subdevice_id; |
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30 | uint32_t device_class; |
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31 | uint8_t revision; |
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32 | }; |
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33 | |||
6084 | serge | 34 | struct cmdtable |
35 | { |
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36 | char *key; |
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37 | int size; |
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38 | int *val; |
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39 | }; |
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40 | |||
41 | #define CMDENTRY(key, val) {(key), (sizeof(key)-1), &val} |
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42 | void parse_cmdline(char *cmdline, struct cmdtable *table, char *log, videomode_t *mode); |
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43 | |||
44 | |||
45 | int oops_in_progress; |
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46 | int i915_fbsize = 16; |
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4104 | Serge | 47 | struct drm_device *main_device; |
48 | struct drm_file *drm_file_handlers[256]; |
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4280 | Serge | 49 | videomode_t usermode; |
3033 | serge | 50 | |
5354 | serge | 51 | void cpu_detect1(); |
52 | int kmap_init(); |
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2344 | Serge | 53 | |
2338 | Serge | 54 | int _stdcall display_handler(ioctl_t *io); |
2325 | Serge | 55 | int init_agp(void); |
56 | |||
3255 | Serge | 57 | void get_pci_info(struct pci_device *dev); |
4246 | Serge | 58 | int i915_getparam(struct drm_device *dev, void *data, |
59 | struct drm_file *file_priv); |
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3255 | Serge | 60 | |
3277 | Serge | 61 | int i915_mask_update(struct drm_device *dev, void *data, |
62 | struct drm_file *file); |
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3255 | Serge | 63 | |
4280 | Serge | 64 | struct cmdtable cmdtable[]= { |
6084 | serge | 65 | CMDENTRY("-FB=", i915_fbsize), |
66 | /* CMDENTRY("-pm=", i915.powersave), */ |
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67 | CMDENTRY("-rc6=", i915.enable_rc6), |
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68 | CMDENTRY("-fbc=", i915.enable_fbc), |
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69 | CMDENTRY("-ppgt=", i915.enable_ppgtt), |
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4280 | Serge | 70 | {NULL, 0} |
71 | }; |
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3277 | Serge | 72 | |
4280 | Serge | 73 | |
2325 | Serge | 74 | static char log[256]; |
75 | |||
5060 | serge | 76 | unsigned long volatile jiffies; |
77 | |||
3482 | Serge | 78 | struct workqueue_struct *system_wq; |
3764 | Serge | 79 | int driver_wq_state; |
3482 | Serge | 80 | |
2344 | Serge | 81 | int x86_clflush_size; |
3482 | Serge | 82 | unsigned int tsc_khz; |
2344 | Serge | 83 | |
2338 | Serge | 84 | int i915_modeset = 1; |
85 | |||
4126 | Serge | 86 | typedef union __attribute__((packed)) |
87 | { |
||
88 | uint32_t val; |
||
89 | struct |
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90 | { |
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91 | uint8_t state; |
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92 | uint8_t code; |
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93 | uint16_t ctrl_key; |
||
94 | }; |
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95 | }oskey_t; |
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96 | |||
97 | static inline oskey_t get_key(void) |
||
98 | { |
||
99 | oskey_t val; |
||
100 | asm volatile("int $0x40":"=a"(val):"a"(2)); |
||
101 | return val; |
||
102 | }; |
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103 | |||
104 | void i915_dpms(struct drm_device *dev, int mode); |
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105 | |||
106 | void i915_driver_thread() |
||
107 | { |
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5060 | serge | 108 | struct drm_i915_private *dev_priv = NULL; |
109 | struct workqueue_struct *cwq = NULL; |
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4126 | Serge | 110 | static int dpms = 1; |
111 | static int dpms_lock = 0; |
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112 | oskey_t key; |
||
113 | unsigned long irqflags; |
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114 | int tmp; |
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115 | |||
116 | printf("%s\n",__FUNCTION__); |
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117 | |||
5060 | serge | 118 | while(driver_wq_state == I915_DEV_INIT) |
119 | { |
||
6084 | serge | 120 | jiffies = GetClockNs() / 10000000; |
5060 | serge | 121 | delay(1); |
122 | }; |
||
123 | |||
6084 | serge | 124 | if( driver_wq_state == I915_DEV_CLOSE) |
125 | { |
||
126 | asm volatile ("int $0x40"::"a"(-1)); |
||
127 | }; |
||
128 | |||
5060 | serge | 129 | dev_priv = main_device->dev_private; |
130 | cwq = dev_priv->wq; |
||
131 | |||
4126 | Serge | 132 | asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(1),"c"(1)); |
133 | asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0x46),"d"(0x330)); |
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134 | asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0xC6),"d"(0x330)); |
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135 | |||
5060 | serge | 136 | while(driver_wq_state != I915_DEV_CLOSE) |
4126 | Serge | 137 | { |
6084 | serge | 138 | jiffies = GetClockNs() / 10000000; |
5060 | serge | 139 | |
4126 | Serge | 140 | key = get_key(); |
141 | |||
142 | if( (key.val != 1) && (key.state == 0x02)) |
||
143 | { |
||
144 | if(key.code == 0x46 && dpms_lock == 0) |
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145 | { |
||
146 | dpms_lock = 1; |
||
147 | if(dpms == 1) |
||
148 | { |
||
149 | i915_dpms(main_device, DRM_MODE_DPMS_OFF); |
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150 | printf("dpms off\n"); |
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151 | } |
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152 | else |
||
153 | { |
||
154 | i915_dpms(main_device, DRM_MODE_DPMS_ON); |
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155 | printf("dpms on\n"); |
||
156 | }; |
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157 | dpms ^= 1; |
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158 | } |
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159 | else if(key.code == 0xC6) |
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160 | dpms_lock = 0; |
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161 | }; |
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162 | |||
163 | spin_lock_irqsave(&cwq->lock, irqflags); |
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164 | |||
165 | while (!list_empty(&cwq->worklist)) |
||
166 | { |
||
167 | struct work_struct *work = list_entry(cwq->worklist.next, |
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168 | struct work_struct, entry); |
||
169 | work_func_t f = work->func; |
||
170 | list_del_init(cwq->worklist.next); |
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171 | |||
172 | spin_unlock_irqrestore(&cwq->lock, irqflags); |
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173 | f(work); |
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174 | spin_lock_irqsave(&cwq->lock, irqflags); |
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175 | } |
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176 | |||
177 | spin_unlock_irqrestore(&cwq->lock, irqflags); |
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178 | |||
179 | delay(1); |
||
180 | }; |
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181 | |||
182 | asm volatile ("int $0x40"::"a"(-1)); |
||
183 | } |
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184 | |||
5354 | serge | 185 | u32 __attribute__((externally_visible)) drvEntry(int action, char *cmdline) |
2325 | Serge | 186 | { |
5060 | serge | 187 | static pci_dev_t device; |
188 | const struct pci_device_id *ent; |
||
189 | |||
4104 | Serge | 190 | int err = 0; |
2325 | Serge | 191 | |
192 | if(action != 1) |
||
3764 | Serge | 193 | { |
5060 | serge | 194 | driver_wq_state = I915_DEV_CLOSE; |
2325 | Serge | 195 | return 0; |
3764 | Serge | 196 | }; |
2325 | Serge | 197 | |
198 | if( GetService("DISPLAY") != 0 ) |
||
199 | return 0; |
||
200 | |||
6084 | serge | 201 | printf("\n%s build %s %s\nusage: i915 [options]\n" |
202 | "-FB=<0-9> Set framebuffer size in megabytes (default: 16)\n", |
||
4560 | Serge | 203 | "-pm=<0,1> Enable powersavings, fbc, downclocking, etc. (default: 1 - true)\n", |
6084 | serge | 204 | DRV_NAME, __DATE__, __TIME__); |
205 | |||
4280 | Serge | 206 | printf("-rc6=<-1,0-7> Enable power-saving render C-state 6.\n" |
207 | " Different stages can be selected via bitmask values\n" |
||
208 | " (0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6).\n" |
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209 | " For example, 3 would enable rc6 and deep rc6, and 7 would enable everything.\n" |
||
210 | " default: -1 (use per-chip default)\n"); |
||
211 | printf("-fbc=<-1,0,1> Enable frame buffer compression for power savings\n" |
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4560 | Serge | 212 | " (default: -1 (use per-chip default))\n"); |
213 | printf("-ppgt=<0,1> Enable PPGTT (default: true)\n"); |
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6084 | serge | 214 | |
4280 | Serge | 215 | printf("-l |
216 | printf("-m |
||
217 | |||
6084 | serge | 218 | printf("cmdline %s\n", cmdline); |
2340 | Serge | 219 | if( cmdline && *cmdline ) |
4280 | Serge | 220 | parse_cmdline(cmdline, cmdtable, log, &usermode); |
2325 | Serge | 221 | |
4293 | Serge | 222 | if( *log && !dbg_open(log)) |
6084 | serge | 223 | { |
224 | printf("Can't open %s\nExit\n", log); |
||
225 | return 0; |
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2325 | Serge | 226 | } |
6084 | serge | 227 | else |
228 | { |
||
229 | dbgprintf("\nLOG: %s build %s %s\n",DRV_NAME,__DATE__, __TIME__); |
||
230 | } |
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2325 | Serge | 231 | |
5354 | serge | 232 | cpu_detect1(); |
3480 | Serge | 233 | // dbgprintf("\ncache line size %d\n", x86_clflush_size); |
2351 | Serge | 234 | |
5060 | serge | 235 | err = enum_pci_devices(); |
236 | if( unlikely(err != 0) ) |
||
237 | { |
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238 | dbgprintf("Device enumeration failed\n"); |
||
239 | return 0; |
||
240 | } |
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2325 | Serge | 241 | |
5354 | serge | 242 | err = kmap_init(); |
243 | if( unlikely(err != 0) ) |
||
244 | { |
||
245 | dbgprintf("kmap initialization failed\n"); |
||
246 | return 0; |
||
247 | } |
||
248 | |||
5097 | serge | 249 | dmi_scan_machine(); |
250 | |||
5060 | serge | 251 | driver_wq_state = I915_DEV_INIT; |
252 | CreateKernelThread(i915_driver_thread); |
||
253 | |||
2325 | Serge | 254 | err = i915_init(); |
5060 | serge | 255 | if(unlikely(err!= 0)) |
2338 | Serge | 256 | { |
5060 | serge | 257 | driver_wq_state = I915_DEV_CLOSE; |
3298 | Serge | 258 | dbgprintf("Epic Fail :(\n"); |
6084 | serge | 259 | delay(100); |
3298 | Serge | 260 | return 0; |
2338 | Serge | 261 | }; |
2325 | Serge | 262 | |
5060 | serge | 263 | driver_wq_state = I915_DEV_READY; |
264 | |||
4280 | Serge | 265 | init_display_kms(main_device, &usermode); |
266 | |||
2338 | Serge | 267 | err = RegService("DISPLAY", display_handler); |
2325 | Serge | 268 | |
2338 | Serge | 269 | if( err != 0) |
270 | dbgprintf("Set DISPLAY handler\n"); |
||
271 | |||
2325 | Serge | 272 | return err; |
273 | }; |
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274 | |||
3480 | Serge | 275 | |
2344 | Serge | 276 | #define CURRENT_API 0x0200 /* 2.00 */ |
277 | #define COMPATIBLE_API 0x0100 /* 1.00 */ |
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2338 | Serge | 278 | |
2344 | Serge | 279 | #define API_VERSION (COMPATIBLE_API << 16) | CURRENT_API |
2351 | Serge | 280 | #define DISPLAY_VERSION API_VERSION |
2338 | Serge | 281 | |
282 | |||
6084 | serge | 283 | #define SRV_GETVERSION 0 |
284 | #define SRV_ENUM_MODES 1 |
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285 | #define SRV_SET_MODE 2 |
||
286 | #define SRV_GET_CAPS 3 |
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2342 | Serge | 287 | |
2344 | Serge | 288 | |
6084 | serge | 289 | #define SRV_GET_PCI_INFO 20 |
4246 | Serge | 290 | #define SRV_I915_GET_PARAM 21 |
6084 | serge | 291 | #define SRV_I915_GEM_CREATE 22 |
292 | #define SRV_DRM_GEM_CLOSE 23 |
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4246 | Serge | 293 | #define SRV_DRM_GEM_FLINK 24 |
294 | #define SRV_DRM_GEM_OPEN 25 |
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295 | #define SRV_I915_GEM_PIN 26 |
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296 | #define SRV_I915_GEM_UNPIN 27 |
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5367 | serge | 297 | #define SRV_I915_GEM_GET_CACHING 28 |
298 | #define SRV_I915_GEM_SET_CACHING 29 |
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299 | #define SRV_I915_GEM_PWRITE 30 |
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300 | #define SRV_I915_GEM_BUSY 31 |
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301 | #define SRV_I915_GEM_SET_DOMAIN 32 |
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302 | #define SRV_I915_GEM_MMAP 33 |
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303 | #define SRV_I915_GEM_SET_TILING 34 |
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304 | #define SRV_I915_GEM_GET_TILING 35 |
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305 | #define SRV_I915_GEM_GET_APERTURE 36 |
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306 | #define SRV_I915_GEM_MMAP_GTT 37 |
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307 | #define SRV_I915_GEM_THROTTLE 38 |
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308 | #define SRV_I915_GEM_EXECBUFFER2 39 |
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309 | #define SRV_I915_GEM_WAIT 40 |
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310 | #define SRV_I915_GEM_CONTEXT_CREATE 41 |
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311 | #define SRV_I915_GEM_CONTEXT_DESTROY 42 |
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312 | #define SRV_I915_REG_READ 43 |
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3260 | Serge | 313 | |
5367 | serge | 314 | #define SRV_FBINFO 44 |
315 | #define SRV_MASK_UPDATE 45 |
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316 | #define SRV_MASK_UPDATE_EX 46 |
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3263 | Serge | 317 | |
2338 | Serge | 318 | #define check_input(size) \ |
319 | if( unlikely((inp==NULL)||(io->inp_size != (size))) ) \ |
||
320 | break; |
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321 | |||
322 | #define check_output(size) \ |
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323 | if( unlikely((outp==NULL)||(io->out_size != (size))) ) \ |
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324 | break; |
||
325 | |||
326 | int _stdcall display_handler(ioctl_t *io) |
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327 | { |
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3255 | Serge | 328 | struct drm_file *file; |
329 | |||
6084 | serge | 330 | int retval = -1; |
5354 | serge | 331 | u32 *inp; |
332 | u32 *outp; |
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2338 | Serge | 333 | |
334 | inp = io->input; |
||
335 | outp = io->output; |
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336 | |||
3255 | Serge | 337 | file = drm_file_handlers[0]; |
338 | |||
2338 | Serge | 339 | switch(io->io_code) |
340 | { |
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341 | case SRV_GETVERSION: |
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342 | check_output(4); |
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2344 | Serge | 343 | *outp = DISPLAY_VERSION; |
2338 | Serge | 344 | retval = 0; |
345 | break; |
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346 | |||
347 | case SRV_ENUM_MODES: |
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3031 | serge | 348 | // dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n", |
349 | // inp, io->inp_size, io->out_size ); |
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2340 | Serge | 350 | check_output(4); |
2338 | Serge | 351 | // check_input(*outp * sizeof(videomode_t)); |
352 | if( i915_modeset) |
||
353 | retval = get_videomodes((videomode_t*)inp, outp); |
||
354 | break; |
||
355 | |||
356 | case SRV_SET_MODE: |
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3031 | serge | 357 | // dbgprintf("SRV_SET_MODE inp %x inp_size %x\n", |
358 | // inp, io->inp_size); |
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2338 | Serge | 359 | check_input(sizeof(videomode_t)); |
360 | if( i915_modeset ) |
||
361 | retval = set_user_mode((videomode_t*)inp); |
||
362 | break; |
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3033 | serge | 363 | |
2351 | Serge | 364 | case SRV_GET_CAPS: |
365 | retval = get_driver_caps((hwcaps_t*)inp); |
||
366 | break; |
||
367 | |||
3260 | Serge | 368 | case SRV_GET_PCI_INFO: |
3255 | Serge | 369 | get_pci_info((struct pci_device *)inp); |
2338 | Serge | 370 | retval = 0; |
371 | break; |
||
3031 | serge | 372 | |
4246 | Serge | 373 | case SRV_I915_GET_PARAM: |
374 | retval = i915_getparam(main_device, inp, file); |
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3255 | Serge | 375 | break; |
376 | |||
377 | case SRV_I915_GEM_CREATE: |
||
378 | retval = i915_gem_create_ioctl(main_device, inp, file); |
||
379 | break; |
||
380 | |||
381 | case SRV_DRM_GEM_CLOSE: |
||
382 | retval = drm_gem_close_ioctl(main_device, inp, file); |
||
383 | break; |
||
384 | |||
4246 | Serge | 385 | case SRV_DRM_GEM_FLINK: |
386 | retval = drm_gem_flink_ioctl(main_device, inp, file); |
||
387 | break; |
||
388 | |||
389 | case SRV_DRM_GEM_OPEN: |
||
390 | retval = drm_gem_open_ioctl(main_device, inp, file); |
||
391 | break; |
||
392 | |||
5367 | serge | 393 | case SRV_I915_GEM_GET_CACHING: |
394 | retval = i915_gem_get_caching_ioctl(main_device, inp, file); |
||
395 | break; |
||
396 | |||
4246 | Serge | 397 | case SRV_I915_GEM_SET_CACHING: |
398 | retval = i915_gem_set_caching_ioctl(main_device, inp, file); |
||
3260 | Serge | 399 | break; |
400 | |||
401 | case SRV_I915_GEM_PWRITE: |
||
402 | retval = i915_gem_pwrite_ioctl(main_device, inp, file); |
||
403 | break; |
||
404 | |||
405 | case SRV_I915_GEM_BUSY: |
||
406 | retval = i915_gem_busy_ioctl(main_device, inp, file); |
||
407 | break; |
||
408 | |||
409 | case SRV_I915_GEM_SET_DOMAIN: |
||
410 | retval = i915_gem_set_domain_ioctl(main_device, inp, file); |
||
411 | break; |
||
412 | |||
3263 | Serge | 413 | case SRV_I915_GEM_MMAP: |
414 | retval = i915_gem_mmap_ioctl(main_device, inp, file); |
||
415 | break; |
||
416 | |||
4246 | Serge | 417 | case SRV_I915_GEM_SET_TILING: |
418 | retval = i915_gem_set_tiling(main_device, inp, file); |
||
419 | break; |
||
420 | |||
421 | case SRV_I915_GEM_GET_TILING: |
||
422 | retval = i915_gem_get_tiling(main_device, inp, file); |
||
423 | break; |
||
424 | |||
425 | case SRV_I915_GEM_GET_APERTURE: |
||
426 | // printf("SRV_I915_GEM_GET_APERTURE "); |
||
427 | retval = i915_gem_get_aperture_ioctl(main_device, inp, file); |
||
428 | // printf(" retval=%d\n", retval); |
||
429 | break; |
||
430 | |||
3480 | Serge | 431 | case SRV_I915_GEM_MMAP_GTT: |
432 | retval = i915_gem_mmap_gtt_ioctl(main_device, inp, file); |
||
433 | break; |
||
434 | |||
4246 | Serge | 435 | case SRV_I915_GEM_THROTTLE: |
436 | retval = i915_gem_throttle_ioctl(main_device, inp, file); |
||
3263 | Serge | 437 | break; |
438 | |||
439 | case SRV_I915_GEM_EXECBUFFER2: |
||
4246 | Serge | 440 | // printf("SRV_I915_GEM_EXECBUFFER2\n"); |
3263 | Serge | 441 | retval = i915_gem_execbuffer2(main_device, inp, file); |
442 | break; |
||
443 | |||
4246 | Serge | 444 | case SRV_I915_GEM_WAIT: |
445 | retval = i915_gem_wait_ioctl(main_device, inp, file); |
||
446 | break; |
||
447 | |||
448 | case SRV_I915_GEM_CONTEXT_CREATE: |
||
449 | retval = i915_gem_context_create_ioctl(main_device, inp, file); |
||
450 | break; |
||
451 | |||
452 | case SRV_I915_GEM_CONTEXT_DESTROY: |
||
453 | retval = i915_gem_context_destroy_ioctl(main_device, inp, file); |
||
454 | break; |
||
455 | |||
456 | case SRV_I915_REG_READ: |
||
457 | retval = i915_reg_read_ioctl(main_device, inp, file); |
||
458 | break; |
||
459 | |||
460 | case SRV_FBINFO: |
||
461 | retval = i915_fbinfo(inp); |
||
462 | break; |
||
463 | |||
3290 | Serge | 464 | case SRV_MASK_UPDATE: |
465 | retval = i915_mask_update(main_device, inp, file); |
||
466 | break; |
||
4539 | Serge | 467 | |
468 | case SRV_MASK_UPDATE_EX: |
||
469 | retval = i915_mask_update_ex(main_device, inp, file); |
||
470 | break; |
||
2338 | Serge | 471 | }; |
472 | |||
473 | return retval; |
||
474 | } |
||
475 | |||
476 | |||
2325 | Serge | 477 | #define PCI_CLASS_REVISION 0x08 |
478 | #define PCI_CLASS_DISPLAY_VGA 0x0300 |
||
479 | #define PCI_CLASS_BRIDGE_HOST 0x0600 |
||
2326 | Serge | 480 | #define PCI_CLASS_BRIDGE_ISA 0x0601 |
2325 | Serge | 481 | |
5354 | serge | 482 | int pci_scan_filter(u32 id, u32 busnr, u32 devfn) |
2325 | Serge | 483 | { |
5354 | serge | 484 | u16 vendor, device; |
485 | u32 class; |
||
2325 | Serge | 486 | int ret = 0; |
487 | |||
488 | vendor = id & 0xffff; |
||
489 | device = (id >> 16) & 0xffff; |
||
490 | |||
491 | if(vendor == 0x8086) |
||
492 | { |
||
493 | class = PciRead32(busnr, devfn, PCI_CLASS_REVISION); |
||
494 | class >>= 16; |
||
495 | |||
496 | if( (class == PCI_CLASS_DISPLAY_VGA) || |
||
2326 | Serge | 497 | (class == PCI_CLASS_BRIDGE_HOST) || |
498 | (class == PCI_CLASS_BRIDGE_ISA)) |
||
2325 | Serge | 499 | ret = 1; |
500 | } |
||
501 | return ret; |
||
502 | }; |
||
2340 | Serge | 503 | |
504 | |||
5060 | serge | 505 | struct mtrr |
506 | { |
||
5354 | serge | 507 | u64 base; |
508 | u64 mask; |
||
5060 | serge | 509 | }; |
510 | |||
511 | struct cpuinfo |
||
512 | { |
||
5354 | serge | 513 | u64 caps; |
514 | u64 def_mtrr; |
||
515 | u64 mtrr_cap; |
||
5060 | serge | 516 | int var_mtrr_count; |
517 | int fix_mtrr_count; |
||
518 | struct mtrr var_mtrr[9]; |
||
519 | char model_name[64]; |
||
520 | }; |
||
521 | |||
522 | #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) |
||
523 | #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) |
||
524 | |||
525 | #define MSR_MTRRdefType 0x000002ff |
||
526 | |||
527 | #define IA32_MTRRCAP 0xFE |
||
528 | #define IA32_CR_PAT_MSR 0x277 |
||
529 | |||
530 | #define PAT_TYPE_UC 0 |
||
531 | #define PAT_TYPE_WC 1 |
||
532 | #define PAT_TYPE_WB 6 |
||
533 | #define PAT_TYPE_UCM 7 |
||
534 | |||
535 | |||
536 | #define MTRR_UC 0 |
||
537 | #define MTRR_WC 1 |
||
538 | #define MTRR_WB 6 |
||
539 | |||
5354 | serge | 540 | static inline u64 read_msr(u32 msr) |
5060 | serge | 541 | { |
542 | union { |
||
5354 | serge | 543 | u64 val; |
5060 | serge | 544 | struct { |
5354 | serge | 545 | u32 low; |
546 | u32 high; |
||
5060 | serge | 547 | }; |
548 | }tmp; |
||
549 | |||
550 | asm volatile ( |
||
551 | "rdmsr" |
||
552 | : "=a" (tmp.low), "=d" (tmp.high) |
||
553 | : "c" (msr)); |
||
554 | return tmp.val; |
||
555 | } |
||
556 | |||
5354 | serge | 557 | static inline void write_msr(u32 msr, u64 val) |
5060 | serge | 558 | { |
559 | union { |
||
5354 | serge | 560 | u64 val; |
5060 | serge | 561 | struct { |
5354 | serge | 562 | u32 low; |
563 | u32 high; |
||
5060 | serge | 564 | }; |
565 | }tmp; |
||
566 | |||
567 | tmp.val = val; |
||
568 | |||
569 | asm volatile ( |
||
570 | "wrmsr" |
||
571 | :: "a" (tmp.low), "d" (tmp.high), "c" (msr)); |
||
572 | } |
||
573 | |||
574 | #define SIZE_OR_MASK_BITS(n) (~((1ULL << ((n) - PAGE_SHIFT)) - 1)) |
||
575 | |||
576 | static void set_mtrr(unsigned int reg, unsigned long base, |
||
577 | unsigned long size, int type) |
||
578 | { |
||
579 | unsigned int base_lo, base_hi, mask_lo, mask_hi; |
||
580 | u64 size_or_mask, size_and_mask; |
||
581 | |||
582 | size_or_mask = SIZE_OR_MASK_BITS(36); |
||
583 | size_and_mask = 0x00f00000; |
||
584 | |||
585 | if (size == 0) { |
||
586 | /* |
||
587 | * The invalid bit is kept in the mask, so we simply |
||
588 | * clear the relevant mask register to disable a range. |
||
589 | */ |
||
590 | native_write_msr(MTRRphysMask_MSR(reg), 0, 0); |
||
591 | } |
||
592 | else { |
||
593 | base_lo = base << PAGE_SHIFT | type; |
||
594 | base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT); |
||
595 | mask_lo = -size << PAGE_SHIFT | 0x800; |
||
596 | mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT); |
||
597 | |||
598 | native_write_msr(MTRRphysBase_MSR(reg), base_lo, base_hi); |
||
599 | native_write_msr(MTRRphysMask_MSR(reg), mask_lo, mask_hi); |
||
600 | }; |
||
601 | } |
||
602 | |||
603 | |||
604 | static u32 deftype_lo, deftype_hi; |
||
605 | |||
5354 | serge | 606 | void cpu_detect1() |
2344 | Serge | 607 | { |
5060 | serge | 608 | struct cpuinfo cpuinfo; |
609 | |||
2344 | Serge | 610 | u32 junk, tfms, cap0, misc; |
5060 | serge | 611 | int i; |
5354 | serge | 612 | |
2344 | Serge | 613 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
614 | |||
615 | if (cap0 & (1<<19)) |
||
616 | { |
||
617 | x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
||
618 | } |
||
3482 | Serge | 619 | |
5354 | serge | 620 | #if 0 |
5060 | serge | 621 | cpuid(0x80000002, (unsigned int*)&cpuinfo.model_name[0], (unsigned int*)&cpuinfo.model_name[4], |
622 | (unsigned int*)&cpuinfo.model_name[8], (unsigned int*)&cpuinfo.model_name[12]); |
||
623 | cpuid(0x80000003, (unsigned int*)&cpuinfo.model_name[16], (unsigned int*)&cpuinfo.model_name[20], |
||
624 | (unsigned int*)&cpuinfo.model_name[24], (unsigned int*)&cpuinfo.model_name[28]); |
||
625 | cpuid(0x80000004, (unsigned int*)&cpuinfo.model_name[32], (unsigned int*)&cpuinfo.model_name[36], |
||
626 | (unsigned int*)&cpuinfo.model_name[40], (unsigned int*)&cpuinfo.model_name[44]); |
||
627 | |||
628 | printf("\n%s\n\n",cpuinfo.model_name); |
||
629 | |||
630 | cpuinfo.def_mtrr = read_msr(MSR_MTRRdefType); |
||
631 | cpuinfo.mtrr_cap = read_msr(IA32_MTRRCAP); |
||
632 | |||
633 | printf("MSR_MTRRdefType %016llx\n\n", cpuinfo.def_mtrr); |
||
634 | |||
635 | cpuinfo.var_mtrr_count = (u8_t)cpuinfo.mtrr_cap; |
||
636 | |||
637 | for(i = 0; i < cpuinfo.var_mtrr_count; i++) |
||
638 | { |
||
639 | u64_t mtrr_base; |
||
640 | u64_t mtrr_mask; |
||
641 | |||
642 | cpuinfo.var_mtrr[i].base = read_msr(MTRRphysBase_MSR(i)); |
||
643 | cpuinfo.var_mtrr[i].mask = read_msr(MTRRphysMask_MSR(i)); |
||
644 | |||
645 | printf("MTRR_%d base: %016llx mask: %016llx\n", i, |
||
646 | cpuinfo.var_mtrr[i].base, |
||
647 | cpuinfo.var_mtrr[i].mask); |
||
648 | }; |
||
649 | |||
650 | unsigned int cr0, cr3, cr4, eflags; |
||
651 | |||
652 | eflags = safe_cli(); |
||
653 | |||
654 | /* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */ |
||
655 | cr0 = read_cr0() | (1<<30); |
||
656 | write_cr0(cr0); |
||
657 | wbinvd(); |
||
658 | |||
659 | cr4 = read_cr4(); |
||
660 | write_cr4(cr4 & ~(1<<7)); |
||
661 | |||
662 | cr3 = read_cr3(); |
||
663 | write_cr3(cr3); |
||
664 | |||
665 | /* Save MTRR state */ |
||
666 | rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); |
||
667 | |||
668 | /* Disable MTRRs, and set the default type to uncached */ |
||
669 | native_write_msr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi); |
||
670 | wbinvd(); |
||
671 | |||
672 | i = 0; |
||
673 | set_mtrr(i++,0,0x80000000>>12,MTRR_WB); |
||
674 | set_mtrr(i++,0x80000000>>12,0x40000000>>12,MTRR_WB); |
||
675 | set_mtrr(i++,0xC0000000>>12,0x20000000>>12,MTRR_WB); |
||
676 | set_mtrr(i++,0xdb800000>>12,0x00800000>>12,MTRR_UC); |
||
677 | set_mtrr(i++,0xdc000000>>12,0x04000000>>12,MTRR_UC); |
||
678 | set_mtrr(i++,0xE0000000>>12,0x10000000>>12,MTRR_WC); |
||
679 | |||
680 | for(; i < cpuinfo.var_mtrr_count; i++) |
||
681 | set_mtrr(i,0,0,0); |
||
682 | |||
683 | write_cr3(cr3); |
||
684 | |||
685 | /* Intel (P6) standard MTRRs */ |
||
686 | native_write_msr(MSR_MTRRdefType, deftype_lo, deftype_hi); |
||
687 | |||
688 | /* Enable caches */ |
||
689 | write_cr0(read_cr0() & ~(1<<30)); |
||
690 | |||
691 | /* Restore value of CR4 */ |
||
692 | write_cr4(cr4); |
||
693 | |||
694 | safe_sti(eflags); |
||
695 | |||
696 | printf("\nnew MTRR map\n\n"); |
||
697 | |||
698 | for(i = 0; i < cpuinfo.var_mtrr_count; i++) |
||
699 | { |
||
700 | u64_t mtrr_base; |
||
701 | u64_t mtrr_mask; |
||
702 | |||
703 | cpuinfo.var_mtrr[i].base = read_msr(MTRRphysBase_MSR(i)); |
||
704 | cpuinfo.var_mtrr[i].mask = read_msr(MTRRphysMask_MSR(i)); |
||
705 | |||
706 | printf("MTRR_%d base: %016llx mask: %016llx\n", i, |
||
707 | cpuinfo.var_mtrr[i].base, |
||
708 | cpuinfo.var_mtrr[i].mask); |
||
709 | }; |
||
710 | #endif |
||
711 | |||
3482 | Serge | 712 | tsc_khz = (unsigned int)(GetCpuFreq()/1000); |
2344 | Serge | 713 | } |
714 | |||
3243 | Serge | 715 | |
716 | int get_driver_caps(hwcaps_t *caps) |
||
717 | { |
||
718 | int ret = 0; |
||
719 | |||
720 | switch(caps->idx) |
||
721 | { |
||
722 | case 0: |
||
723 | caps->opt[0] = 0; |
||
724 | caps->opt[1] = 0; |
||
725 | break; |
||
726 | |||
727 | case 1: |
||
728 | caps->cap1.max_tex_width = 4096; |
||
729 | caps->cap1.max_tex_height = 4096; |
||
730 | break; |
||
731 | default: |
||
732 | ret = 1; |
||
733 | }; |
||
734 | caps->idx = 1; |
||
735 | return ret; |
||
736 | } |
||
737 | |||
3255 | Serge | 738 | |
739 | void get_pci_info(struct pci_device *dev) |
||
740 | { |
||
741 | struct pci_dev *pdev = main_device->pdev; |
||
742 | |||
743 | memset(dev, sizeof(*dev), 0); |
||
744 | |||
745 | dev->domain = 0; |
||
746 | dev->bus = pdev->busnr; |
||
747 | dev->dev = pdev->devfn >> 3; |
||
748 | dev->func = pdev->devfn & 7; |
||
749 | dev->vendor_id = pdev->vendor; |
||
750 | dev->device_id = pdev->device; |
||
751 | dev->revision = pdev->revision; |
||
752 | }; |
||
4246 | Serge | 753 | |
754 | |||
755 | |||
4280 | Serge | 756 | char *strstr(const char *cs, const char *ct); |
757 | |||
758 | static int my_atoi(char **cmd) |
||
759 | { |
||
760 | char* p = *cmd; |
||
761 | int val = 0; |
||
762 | int sign = 1; |
||
763 | |||
764 | if(*p == '-') |
||
765 | { |
||
766 | sign = -1; |
||
767 | p++; |
||
768 | }; |
||
769 | |||
770 | for (;; *p++) { |
||
771 | switch (*p) { |
||
772 | case '0' ... '9': |
||
773 | val = 10*val+(*p-'0'); |
||
774 | break; |
||
775 | default: |
||
776 | *cmd = p; |
||
777 | return val*sign; |
||
778 | } |
||
779 | } |
||
780 | } |
||
781 | |||
782 | char* parse_mode(char *p, videomode_t *mode) |
||
783 | { |
||
784 | char c; |
||
785 | |||
786 | while( (c = *p++) == ' '); |
||
787 | |||
788 | if( c ) |
||
789 | { |
||
790 | p--; |
||
791 | |||
792 | mode->width = my_atoi(&p); |
||
793 | if(*p == 'x') p++; |
||
794 | |||
795 | mode->height = my_atoi(&p); |
||
796 | if(*p == 'x') p++; |
||
797 | |||
798 | mode->bpp = 32; |
||
799 | |||
800 | mode->freq = my_atoi(&p); |
||
801 | |||
802 | if( mode->freq == 0 ) |
||
803 | mode->freq = 60; |
||
804 | } |
||
805 | |||
806 | return p; |
||
807 | }; |
||
808 | |||
809 | |||
810 | static char* parse_path(char *p, char *log) |
||
811 | { |
||
812 | char c; |
||
813 | |||
814 | while( (c = *p++) == ' '); |
||
815 | p--; |
||
4293 | Serge | 816 | while((c = *p++) && (c != ' ')) |
817 | *log++ = c; |
||
818 | |||
4280 | Serge | 819 | *log = 0; |
820 | |||
821 | return p; |
||
822 | }; |
||
823 | |||
824 | void parse_cmdline(char *cmdline, struct cmdtable *table, char *log, videomode_t *mode) |
||
825 | { |
||
826 | char *p = cmdline; |
||
827 | char *p1; |
||
828 | int val; |
||
829 | char c = *p++; |
||
830 | |||
831 | if( table ) |
||
832 | { |
||
833 | while(table->key) |
||
834 | { |
||
835 | if(p1 = strstr(cmdline, table->key)) |
||
836 | { |
||
837 | p1+= table->size; |
||
838 | *table->val = my_atoi(&p1); |
||
839 | } |
||
840 | table++; |
||
841 | } |
||
842 | } |
||
843 | |||
844 | while( c ) |
||
845 | { |
||
846 | if( c == '-') |
||
847 | { |
||
848 | switch(*p++) |
||
849 | { |
||
850 | case 'l': |
||
851 | p = parse_path(p, log); |
||
852 | break; |
||
853 | |||
854 | case 'm': |
||
855 | p = parse_mode(p, mode); |
||
856 | break; |
||
857 | }; |
||
858 | }; |
||
859 | c = *p++; |
||
860 | }; |
||
861 | }; |
||
862 | |||
863 | char *strstr(const char *cs, const char *ct) |
||
864 | { |
||
865 | int d0, d1; |
||
866 | register char *__res; |
||
867 | __asm__ __volatile__( |
||
868 | "movl %6,%%edi\n\t" |
||
869 | "repne\n\t" |
||
870 | "scasb\n\t" |
||
871 | "notl %%ecx\n\t" |
||
872 | "decl %%ecx\n\t" /* NOTE! This also sets Z if searchstring='' */ |
||
873 | "movl %%ecx,%%edx\n" |
||
874 | "1:\tmovl %6,%%edi\n\t" |
||
875 | "movl %%esi,%%eax\n\t" |
||
876 | "movl %%edx,%%ecx\n\t" |
||
877 | "repe\n\t" |
||
878 | "cmpsb\n\t" |
||
879 | "je 2f\n\t" /* also works for empty string, see above */ |
||
880 | "xchgl %%eax,%%esi\n\t" |
||
881 | "incl %%esi\n\t" |
||
882 | "cmpb $0,-1(%%eax)\n\t" |
||
883 | "jne 1b\n\t" |
||
884 | "xorl %%eax,%%eax\n\t" |
||
885 | "2:" |
||
886 | : "=a" (__res), "=&c" (d0), "=&S" (d1) |
||
887 | : "0" (0), "1" (0xffffffff), "2" (cs), "g" (ct) |
||
888 | : "dx", "di"); |
||
889 | return __res; |
||
890 | } |
||
4293 | Serge | 891 | |
6084 | serge | 892 | #include |
893 | |||
894 | u64 long_div(u64 dividend, u64 divisor) |
||
895 | { |
||
896 | #if 1 |
||
897 | u32 high = divisor >> 32; |
||
898 | u64 quot; |
||
899 | |||
900 | if (high == 0) { |
||
901 | quot = div_u64(dividend, divisor); |
||
902 | } else { |
||
903 | int n = 1 + fls(high); |
||
904 | quot = div_u64(dividend >> n, divisor >> n); |
||
905 | |||
906 | if (quot != 0) |
||
907 | quot--; |
||
908 | if ((dividend - quot * divisor) >= divisor) |
||
909 | quot++; |
||
910 | } |
||
911 | |||
912 | return quot; |
||
913 | #endif |
||
914 | // return dividend / divisor; |
||
915 | };>30)); |
||
916 | |||
917 | |||
918 | |||
919 |