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2340 Serge 1
 
2
3
 
2338 Serge 4
#include "drm.h"
5
#include "i915_drm.h"
6
#include "i915_drv.h"
7
#include "intel_drv.h"
8
9
 
10
#include 
11
#include 
12
#include 
13
#include 
14
15
 
16
17
 
3033 serge 18
#include "bitmap.h"
2340 Serge 19
2338 Serge 20
 
2351 Serge 21
2338 Serge 22
 
2351 Serge 23
 
2338 Serge 24
{
25
    kobj_t     header;
26
27
 
28
    uint32_t   hot_x;
29
    uint32_t   hot_y;
30
31
 
32
    struct drm_i915_gem_object  *cobj;
33
}cursor_t;
34
35
 
36
#define CURSOR_HEIGHT 64
37
38
 
39
 
40
{
41
    int  x;
42
    int  y;
43
    int  width;
44
    int  height;
45
    int  bpp;
46
    int  vrefresh;
47
    int  pitch;
48
    int  lfb;
49
50
 
51
    struct drm_device    *ddev;
52
    struct drm_connector *connector;
53
    struct drm_crtc      *crtc;
54
55
 
56
57
 
58
    int       (*init_cursor)(cursor_t*);
59
    cursor_t* (__stdcall *select_cursor)(cursor_t*);
60
    void      (*show_cursor)(int show);
61
    void      (__stdcall *move_cursor)(cursor_t *cursor, int x, int y);
62
    void      (__stdcall *restore_cursor)(int x, int y);
63
    void      (*disable_mouse)(void);
64
    u32  mask_seqno;
2361 Serge 65
    u32  check_mouse;
3031 serge 66
    u32  check_m_pixel;
67
68
 
2338 Serge 69
70
 
71
 
72
73
 
2340 Serge 74
u32_t cmd_offset;
75
76
 
2351 Serge 77
int  sna_init();
78
79
 
2338 Serge 80
static cursor_t*  __stdcall select_cursor_kms(cursor_t *cursor);
81
static void       __stdcall move_cursor_kms(cursor_t *cursor, int x, int y);
82
83
 
84
{};
85
86
 
87
{};
88
89
 
3031 serge 90
{
91
    static char name[4];
92
93
 
94
    name[1] = ((x[0] & 0x03) << 3) + ((x[1] & 0xE0) >> 5) + '@';
95
    name[2] = (x[1] & 0x1F) + '@';
96
    name[3] = 0;
97
98
 
99
}
100
101
 
102
              videomode_t *reqmode, bool strict)
103
{
104
    drm_i915_private_t      *dev_priv   = dev->dev_private;
105
    struct drm_fb_helper    *fb_helper  = &dev_priv->fbdev->helper;
106
107
 
108
    struct drm_display_mode *mode       = NULL, *tmpmode;
109
    struct drm_framebuffer  *fb         = NULL;
110
    struct drm_crtc         *crtc;
111
    struct drm_encoder      *encoder;
112
    struct drm_mode_set     set;
113
    char *con_name;
114
    char *enc_name;
115
    unsigned hdisplay, vdisplay;
116
    int ret;
117
118
 
119
120
 
121
    {
122
        if( (drm_mode_width(tmpmode)    == reqmode->width)  &&
123
            (drm_mode_height(tmpmode)   == reqmode->height) &&
124
            (drm_mode_vrefresh(tmpmode) == reqmode->freq) )
125
        {
126
            mode = tmpmode;
127
            goto do_set;
128
        }
129
    };
130
131
 
132
    {
133
        list_for_each_entry(tmpmode, &connector->modes, head)
134
        {
135
            if( (drm_mode_width(tmpmode)  == reqmode->width)  &&
136
                (drm_mode_height(tmpmode) == reqmode->height) )
137
            {
138
                mode = tmpmode;
139
                goto do_set;
140
            }
141
        };
142
    };
143
144
 
3037 serge 145
3031 serge 146
 
147
148
 
149
150
 
151
 
152
    crtc = encoder->crtc;
153
154
 
155
    enc_name = drm_get_encoder_name(encoder);
156
157
 
158
              reqmode->width, reqmode->height, crtc->base.id,
159
              con_name, enc_name);
160
161
 
162
163
 
164
    vdisplay = mode->vdisplay;
165
166
 
167
        swap(hdisplay, vdisplay);
168
169
 
170
171
 
172
    fb->height = reqmode->height;
173
    fb->pitches[0]  = ALIGN(reqmode->width * 4, 64);
174
    fb->pitches[1]  = ALIGN(reqmode->width * 4, 64);
175
    fb->pitches[2]  = ALIGN(reqmode->width * 4, 64);
176
    fb->pitches[3]  = ALIGN(reqmode->width * 4, 64);
177
178
 
179
    fb->depth = 24;
180
181
 
182
    crtc->enabled = true;
183
    os_display->crtc = crtc;
184
185
 
186
    set.x = 0;
187
    set.y = 0;
188
    set.mode = mode;
189
    set.connectors = &connector;
190
    set.num_connectors = 1;
191
    set.fb = fb;
192
    ret = crtc->funcs->set_config(&set);
193
    mutex_unlock(&dev->mode_config.mutex);
194
195
 
196
    {
197
        os_display->width    = fb->width;
198
        os_display->height   = fb->height;
199
        os_display->pitch    = fb->pitches[0];
200
        os_display->vrefresh = drm_mode_vrefresh(mode);
201
202
 
203
204
 
3037 serge 205
                       fb->width, fb->height, fb->pitches[0]);
3031 serge 206
    }
207
    else
208
        DRM_ERROR("failed to set mode %d_%d on crtc %p\n",
209
                   fb->width, fb->height, crtc);
210
211
 
212
 
213
}
214
215
 
2338 Serge 216
{
217
    struct drm_display_mode  *mode;
218
    int count = 0;
219
220
 
221
    {
222
        count++;
223
    };
224
    return count;
225
};
226
227
 
3031 serge 228
{
229
    struct drm_connector  *connector;
230
    struct drm_connector_helper_funcs *connector_funcs;
231
232
 
233
234
 
235
    {
236
        struct drm_encoder  *encoder;
237
        struct drm_crtc     *crtc;
238
239
 
240
            continue;
241
242
 
243
        encoder = connector_funcs->best_encoder(connector);
244
        if( encoder == NULL)
245
            continue;
246
247
 
248
249
 
250
251
 
3037 serge 252
                   connector, connector->base.id,
3031 serge 253
                   connector->status, connector->encoder,
254
                   crtc);
255
256
 
257
//            continue;
258
259
 
260
261
 
262
    };
263
264
 
265
};
266
267
 
268
 
2338 Serge 269
{
270
    struct drm_connector    *connector;
271
    struct drm_connector_helper_funcs *connector_funcs;
272
    struct drm_encoder      *encoder;
273
    struct drm_crtc         *crtc = NULL;
274
    struct drm_framebuffer  *fb;
275
276
 
277
    u32_t      ifl;
278
    int        err;
3033 serge 279
2338 Serge 280
 
281
    {
282
        if( connector->status != connector_status_connected)
283
            continue;
284
285
 
286
        encoder = connector_funcs->best_encoder(connector);
287
        if( encoder == NULL)
288
        {
289
            DRM_DEBUG_KMS("CONNECTOR %x ID: %d no active encoders\n",
3037 serge 290
                      connector, connector->base.id);
2338 Serge 291
            continue;
292
        }
293
        connector->encoder = encoder;
294
        crtc = encoder->crtc;
3031 serge 295
2338 Serge 296
 
3037 serge 297
               connector, connector->base.id,
2338 Serge 298
               connector->status, connector->encoder,
299
               crtc, crtc->base.id );
3031 serge 300
2338 Serge 301
 
302
    };
303
304
 
305
    {
306
        DRM_ERROR("No active connectors!\n");
3037 serge 307
        return -1;
2338 Serge 308
    };
309
310
 
311
    {
312
        struct drm_crtc *tmp_crtc;
313
        int crtc_mask = 1;
314
315
 
316
        {
317
            if (encoder->possible_crtcs & crtc_mask)
318
            {
319
                crtc = tmp_crtc;
320
                encoder->crtc = crtc;
321
                break;
322
            };
323
            crtc_mask <<= 1;
324
        };
325
    };
326
327
 
328
    {
329
        DRM_ERROR("No CRTC for encoder %d\n", encoder->base.id);
3037 serge 330
        return -1;
2338 Serge 331
    };
332
333
 
334
 
335
336
 
337
    os_display->ddev = dev;
338
    os_display->connector = connector;
339
    os_display->crtc = crtc;
340
341
 
342
343
 
344
 
345
    {
346
        struct intel_crtc *intel_crtc = to_intel_crtc(os_display->crtc);
347
348
 
349
        {
350
            init_cursor(cursor);
351
        };
352
353
 
354
        os_display->init_cursor    = init_cursor;
355
        os_display->select_cursor  = select_cursor_kms;
356
        os_display->show_cursor    = NULL;
357
        os_display->move_cursor    = move_cursor_kms;
358
        os_display->restore_cursor = restore_cursor;
359
        os_display->disable_mouse  = disable_mouse;
360
361
 
362
        intel_crtc->cursor_y = os_display->height/2;
363
364
 
365
    };
366
    safe_sti(ifl);
367
368
 
2351 Serge 369
370
 
3243 Serge 371
    err = init_bitmaps();
2342 Serge 372
#endif
3243 Serge 373
2340 Serge 374
 
2338 Serge 375
};
376
377
 
378
 
379
{
380
    int err = -1;
381
382
 
3031 serge 383
2338 Serge 384
 
385
    {
386
        *count = os_display->supported_modes;
387
        err = 0;
388
    }
389
    else if( mode != NULL )
390
    {
391
        struct drm_display_mode  *drmmode;
392
        int i = 0;
393
394
 
395
            *count = os_display->supported_modes;
396
397
 
398
        {
399
            if( i < *count)
400
            {
401
                mode->width  = drm_mode_width(drmmode);
402
                mode->height = drm_mode_height(drmmode);
403
                mode->bpp    = 32;
404
                mode->freq   = drm_mode_vrefresh(drmmode);
405
                i++;
406
                mode++;
407
            }
408
            else break;
409
        };
410
        *count = i;
411
        err = 0;
412
    };
413
    return err;
414
};
415
416
 
417
{
418
    int err = -1;
419
420
 
3031 serge 421
//               mode->width, mode->height, mode->freq);
422
2338 Serge 423
 
424
        (mode->height != 0)  &&
425
        (mode->freq   != 0 ) &&
426
        ( (mode->width   != os_display->width)  ||
427
          (mode->height  != os_display->height) ||
428
          (mode->freq    != os_display->vrefresh) ) )
429
    {
430
        if( set_mode(os_display->ddev, os_display->connector, mode, true) )
431
            err = 0;
432
    };
433
434
 
435
};
436
437
 
438
{
439
    list_del(&cursor->list);
3037 serge 440
2342 Serge 441
 
3037 serge 442
443
 
444
    drm_gem_object_unreference(&cursor->cobj->base);
445
    mutex_unlock(&main_device->struct_mutex);
446
447
 
2338 Serge 448
};
449
450
 
451
{
452
    struct drm_i915_private *dev_priv = os_display->ddev->dev_private;
453
    struct drm_i915_gem_object *obj;
454
    uint32_t *bits;
455
    uint32_t *src;
456
    void     *mapped;
3037 serge 457
2338 Serge 458
 
459
    int       ret;
460
461
 
462
    {
463
        bits = (uint32_t*)KernelAlloc(CURSOR_WIDTH*CURSOR_HEIGHT*4);
464
        if (unlikely(bits == NULL))
465
            return ENOMEM;
466
        cursor->cobj = (struct drm_i915_gem_object *)GetPgAddr(bits);
467
    }
468
    else
469
    {
470
        obj = i915_gem_alloc_object(os_display->ddev, CURSOR_WIDTH*CURSOR_HEIGHT*4);
471
        if (unlikely(obj == NULL))
472
            return -ENOMEM;
473
474
 
3031 serge 475
        if (ret) {
2338 Serge 476
            drm_gem_object_unreference(&obj->base);
2344 Serge 477
            return ret;
2338 Serge 478
        }
479
480
 
481
 * GTT space is continuous. I guarantee it.                           */
482
483
 
3037 serge 484
                    CURSOR_WIDTH*CURSOR_HEIGHT*4, PG_SW);
2338 Serge 485
486
 
487
        {
488
            i915_gem_object_unpin(obj);
2344 Serge 489
            drm_gem_object_unreference(&obj->base);
490
            return -ENOMEM;
2338 Serge 491
        };
492
        cursor->cobj = obj;
493
    };
494
495
 
496
497
 
498
    {
499
        for(j = 0; j < 32; j++)
500
            *bits++ = *src++;
501
        for(j = 32; j < CURSOR_WIDTH; j++)
502
            *bits++ = 0;
503
    }
504
    for(i = 0; i < CURSOR_WIDTH*(CURSOR_HEIGHT-32); i++)
505
        *bits++ = 0;
506
507
 
3037 serge 508
509
 
2338 Serge 510
511
 
2340 Serge 512
2338 Serge 513
 
514
515
 
516
517
 
518
}
519
520
 
521
 
522
{
523
    struct drm_device *dev = crtc->dev;
524
    struct drm_i915_private *dev_priv = dev->dev_private;
525
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
526
    int pipe = intel_crtc->pipe;
527
    bool visible = base != 0;
528
529
 
530
        uint32_t cntl = I915_READ(CURCNTR(pipe));
531
        if (base) {
532
            cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
533
            cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
534
            cntl |= pipe << 28; /* Connect to correct pipe */
535
        } else {
536
            cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
537
            cntl |= CURSOR_MODE_DISABLE;
538
        }
539
        I915_WRITE(CURCNTR(pipe), cntl);
540
541
 
542
    }
543
    /* and commit changes on next vblank */
544
    I915_WRITE(CURBASE(pipe), base);
545
}
546
547
 
548
{
549
    struct drm_i915_private *dev_priv = os_display->ddev->dev_private;
550
    struct intel_crtc *intel_crtc = to_intel_crtc(os_display->crtc);
551
    u32 base, pos;
552
    bool visible;
553
554
 
555
556
 
557
    intel_crtc->cursor_y = y;
558
559
 
560
    y = y - cursor->hot_y;
561
562
 
563
 
564
565
 
566
    if (x >= os_display->width)
567
        base = 0;
568
569
 
570
        base = 0;
571
572
 
573
    {
574
        if (x + intel_crtc->cursor_width < 0)
575
            base = 0;
576
577
 
578
        x = -x;
579
    }
580
    pos |= x << CURSOR_X_SHIFT;
581
582
 
583
    {
584
        if (y + intel_crtc->cursor_height < 0)
585
            base = 0;
586
587
 
588
        y = -y;
589
    }
590
    pos |= y << CURSOR_Y_SHIFT;
591
592
 
593
    if (!visible && !intel_crtc->cursor_visible)
594
        return;
595
596
 
597
//    if (IS_845G(dev) || IS_I865G(dev))
598
//        i845_update_cursor(crtc, base);
599
//    else
600
        i9xx_update_cursor(os_display->crtc, base);
601
602
 
603
604
 
605
 
606
{
607
    struct drm_i915_private *dev_priv = os_display->ddev->dev_private;
608
    struct intel_crtc *intel_crtc = to_intel_crtc(os_display->crtc);
609
    cursor_t *old;
610
611
 
612
    os_display->cursor = cursor;
613
614
 
615
       intel_crtc->cursor_addr = cursor->cobj->gtt_offset;
616
    else
617
        intel_crtc->cursor_addr = (addr_t)cursor->cobj;
2352 Serge 618
2338 Serge 619
 
620
    intel_crtc->cursor_height = 32;
621
622
 
623
    return old;
624
};
625
626
 
3263 Serge 627
{
628
    uint32_t  width;
629
    uint32_t  height;
630
    uint32_t  pitch;
631
    uint32_t  tiling;
632
};
633
2340 Serge 634
 
3263 Serge 635
{
636
    fb->width  = os_display->width;
637
    fb->height = os_display->height;
638
    fb->pitch  = os_display->pitch;
639
    fb->tiling = 0;
640
2340 Serge 641
 
3263 Serge 642
};
643
644
 
3277 Serge 645
{
646
    int left;
647
    int top;
648
    int right;
649
    int bottom;
650
}rect_t;
651
3263 Serge 652
 
3277 Serge 653
    __u32 handle;
654
    __u32 width;
3290 Serge 655
    __u32 height;
656
    __u32 bo_size;
3277 Serge 657
    __u32 bo_pitch;
658
    __u32 bo_map;
659
};
660
661
 
662
663
 
664
{
665
    u32_t   addr;
666
667
 
668
    addr+= sizeof(display_t);            /*  shoot me  */
669
    return *(u32_t*)addr;
670
}
671
672
 
673
674
 
675
            struct drm_file *file)
676
{
677
    struct drm_i915_mask *mask = data;
678
    struct drm_gem_object *obj;
679
    static unsigned int mask_seqno[256];
680
    rect_t winrc;
681
    u32    slot;
682
    int    ret;
683
684
 
685
    if (obj == NULL)
686
        return -ENOENT;
687
688
 
689
        drm_gem_object_unreference_unlocked(obj);
690
        return -EINVAL;
691
    }
692
693
 
694
    {
695
        static warn_count;
696
697
 
3290 Serge 698
        mask->height   = winrc.bottom - winrc.top + 1;
699
        mask->bo_pitch = (mask->width+15) & ~15;
700
701
 
3277 Serge 702
        {
703
            printf("left %d top %d right %d bottom %d\n",
704
                    winrc.left, winrc.top, winrc.right, winrc.bottom);
705
            printf("mask pitch %d data %p\n", mask->bo_pitch, mask->bo_size);
706
            warn_count++;
707
        };
708
    };
709
710
 
3290 Serge 711
 
3277 Serge 712
713
 
714
    {
715
        u8* src_offset;
716
        u8* dst_offset;
717
        u32 ifl;
718
719
 
720
        if (ret)
721
            return ret;
722
723
 
724
        if(ret !=0 )
725
        {
726
            dbgprintf("%s fail\n", __FUNCTION__);
727
            return ret;
728
        };
729
730
 
731
732
 
733
734
 
735
 
736
        src_offset+= get_display_map();
737
        dst_offset = (u8*)mask->bo_map;
738
739
 
3290 Serge 740
3277 Serge 741
 
742
        {
743
            mask_seqno[slot] = os_display->mask_seqno;
744
745
 
746
747
 
748
                "movd       %[slot],   %%xmm6    \n"
749
            "punpckldq  %%xmm6, %%xmm6            \n"
750
            "punpcklqdq %%xmm6, %%xmm6            \n"
751
            :: [slot]  "m" (slot)
752
            :"xmm6");
753
754
 
755
            {
756
                int tmp_w = mask->bo_pitch;
757
758
 
759
                u8* tmp_dst = dst_offset;
760
761
 
762
                dst_offset+= mask->bo_pitch;
763
764
 
765
                {
766
                    __asm__ __volatile__ (
767
                    "movdqu     (%0),   %%xmm0            \n"
768
                    "movdqu   16(%0),   %%xmm1            \n"
769
                    "movdqu   32(%0),   %%xmm2            \n"
770
                    "movdqu   48(%0),   %%xmm3            \n"
771
                    "pcmpeqb    %%xmm6, %%xmm0            \n"
772
                    "pcmpeqb    %%xmm6, %%xmm1            \n"
773
                    "pcmpeqb    %%xmm6, %%xmm2            \n"
774
                    "pcmpeqb    %%xmm6, %%xmm3            \n"
775
                    "movdqa     %%xmm0,   (%%edi)         \n"
776
                    "movdqa     %%xmm1, 16(%%edi)         \n"
777
                    "movdqa     %%xmm2, 32(%%edi)         \n"
778
                    "movdqa     %%xmm3, 48(%%edi)         \n"
779
780
 
781
                    :"xmm0","xmm1","xmm2","xmm3");
782
                    tmp_w -= 64;
783
                    tmp_src += 64;
784
                    tmp_dst += 64;
785
                }
786
787
 
788
                {
789
                    __asm__ __volatile__ (
790
                    "movdqu     (%0),   %%xmm0            \n"
791
                    "movdqu   16(%0),   %%xmm1            \n"
792
                    "pcmpeqb    %%xmm6, %%xmm0            \n"
793
                    "pcmpeqb    %%xmm6, %%xmm1            \n"
794
                    "movdqa     %%xmm0,   (%%edi)         \n"
795
                    "movdqa     %%xmm1, 16(%%edi)         \n"
796
797
 
798
                    :"xmm0","xmm1");
799
                    tmp_w -= 32;
800
                    tmp_src += 32;
801
                    tmp_dst += 32;
802
                }
803
804
 
805
                {
806
                    __asm__ __volatile__ (
807
                    "movdqu     (%0),   %%xmm0            \n"
808
                    "pcmpeqb    %%xmm6, %%xmm0            \n"
809
                    "movdqa     %%xmm0,   (%%edi)         \n"
810
                    :: "r" (tmp_src), "D" (tmp_dst)
811
                    :"xmm0");
812
                    tmp_w -= 16;
813
                    tmp_src += 16;
814
                    tmp_dst += 16;
815
                }
816
            };
817
        };
818
        safe_sti(ifl);
819
    }
820
821
 
822
823
 
824
825
 
826
}
827
828
 
829
 
830
 
3243 Serge 831
2342 Serge 832
 
3033 serge 833
834
 
835
 
2342 Serge 836
{
2338 Serge 837
    int left;
2342 Serge 838
    int top;
839
    int right;
840
    int bottom;
841
}rect_t;
842
2338 Serge 843
 
2342 Serge 844
 
845
846
 
847
848
 
849
850
 
851
{
852
    u32_t   addr;
853
854
 
855
    addr+= sizeof(display_t);            /*  shoot me  */
856
    return *(u32_t*)addr;
857
}
858
859
 
3033 serge 860
#define XY_SRC_COPY_BLT_CMD         ((2<<29)|(0x53<<22)|6)
861
#define XY_SRC_COPY_CHROMA_CMD      ((2<<29)|(0x73<<22)|8)
3243 Serge 862
#define ROP_COPY_SRC                0xCC
863
#define FORMAT8888                  3
864
2342 Serge 865
 
3033 serge 866
#define BLT_WRITE_RGB               (1<<20)
867
868
 
869
 
870
 
2342 Serge 871
872
 
873
 
3037 serge 874
 
3033 serge 875
i915_gem_execbuffer_retire_commands(struct drm_device *dev,
876
                    struct drm_file *file,
3037 serge 877
                    struct intel_ring_buffer *ring)
3033 serge 878
{
879
    /* Unconditionally force add_request to emit a full flush. */
3037 serge 880
    ring->gpu_caches_dirty = true;
881
3033 serge 882
 
883
    (void)i915_add_request(ring, file, NULL);
3037 serge 884
}
3033 serge 885
886
 
3120 serge 887
               int src_x, int src_y, u32 w, u32 h)
2342 Serge 888
{
889
    drm_i915_private_t *dev_priv = main_device->dev_private;
2340 Serge 890
    struct intel_ring_buffer *ring;
891
    struct context *context;
3033 serge 892
2338 Serge 893
 
2342 Serge 894
    rect_t     winrc;
895
    clip_t     dst_clip;
896
    clip_t     src_clip;
897
    u32_t      width;
898
    u32_t      height;
899
2338 Serge 900
 
2342 Serge 901
    u32_t      offset;
902
    u8         slot;
903
    int        n=0;
3243 Serge 904
    int        ret;
3037 serge 905
2338 Serge 906
 
2342 Serge 907
        return -1;
908
2338 Serge 909
 
3033 serge 910
2338 Serge 911
 
2342 Serge 912
        return -1;
913
2338 Serge 914
 
3033 serge 915
    if(unlikely(context == NULL))
916
        return -1;
917
2338 Serge 918
 
2342 Serge 919
    {
3120 serge 920
        static warn_count;
921
2338 Serge 922
 
3120 serge 923
        {
924
            printf("left %d top %d right %d bottom %d\n",
925
                    winrc.left, winrc.top, winrc.right, winrc.bottom);
926
            printf("bitmap width %d height %d\n", w, h);
927
            warn_count++;
928
        };
929
    };
930
931
 
932
 
2342 Serge 933
    dst_clip.ymin   = 0;
934
    dst_clip.xmax   = winrc.right-winrc.left;
3039 serge 935
    dst_clip.ymax   = winrc.bottom -winrc.top;
936
2338 Serge 937
 
2342 Serge 938
    src_clip.ymin   = 0;
939
    src_clip.xmax   = bitmap->width  - 1;
940
    src_clip.ymax   = bitmap->height - 1;
941
2338 Serge 942
 
2342 Serge 943
    height = h;
944
2338 Serge 945
 
2342 Serge 946
                  &src_clip, &src_x, &src_y,
947
                  &width, &height) )
948
        return 0;
949
2340 Serge 950
 
2342 Serge 951
    dst_y+= winrc.top;
952
2340 Serge 953
 
2342 Serge 954
2340 Serge 955
 
2342 Serge 956
2340 Serge 957
 
2342 Serge 958
#if 0
959
        static v4si write_mask = {0xFF000000, 0xFF000000,
960
                                  0xFF000000, 0xFF000000};
961
2340 Serge 962
 
2342 Serge 963
        u8* dst_offset;
964
2340 Serge 965
 
2342 Serge 966
        src_offset += (u32)bitmap->uaddr;
967
2340 Serge 968
 
2342 Serge 969
        dst_offset+= get_display_map();
970
2340 Serge 971
 
2342 Serge 972
2340 Serge 973
 
2342 Serge 974
        "movdqa     %[write_mask],  %%xmm7    \n"
975
        "movd       %[slot_mask],   %%xmm6    \n"
976
        "punpckldq  %%xmm6, %%xmm6            \n"
977
        "punpcklqdq %%xmm6, %%xmm6            \n"
978
        :: [write_mask] "m" (write_mask),
979
           [slot_mask]  "g" (slot_mask)
980
        :"xmm7", "xmm6");
981
2340 Serge 982
 
2342 Serge 983
        {
984
            u32_t tmp_w = width;
985
2340 Serge 986
 
2342 Serge 987
            u8* tmp_dst = dst_offset;
988
2340 Serge 989
 
2342 Serge 990
            dst_offset+= os_display->width;
991
2340 Serge 992
 
2342 Serge 993
            {
994
                __asm__ __volatile__ (
995
                "movq       (%0),   %%xmm0            \n"
996
                "punpcklbw  %%xmm0, %%xmm0            \n"
997
                "movdqa     %%xmm0, %%xmm1            \n"
998
                "punpcklwd  %%xmm0, %%xmm0            \n"
999
                "punpckhwd  %%xmm1, %%xmm1            \n"
1000
                "pcmpeqb    %%xmm6, %%xmm0            \n"
1001
                "pcmpeqb    %%xmm6, %%xmm1            \n"
1002
                "maskmovdqu %%xmm7, %%xmm0            \n"
1003
                "addl       $16, %%edi                \n"
1004
                "maskmovdqu %%xmm7, %%xmm1            \n"
1005
                :: "r" (tmp_dst), "D" (tmp_src)
1006
                :"xmm0", "xmm1");
1007
                __asm__ __volatile__ ("":::"edi");
1008
                tmp_w -= 8;
1009
                tmp_src += 32;
1010
                tmp_dst += 8;
1011
            };
1012
2340 Serge 1013
 
2342 Serge 1014
            {
1015
                __asm__ __volatile__ (
1016
                "movd       (%0),   %%xmm0            \n"
1017
                "punpcklbw  %%xmm0, %%xmm0            \n"
1018
                "punpcklwd  %%xmm0, %%xmm0            \n"
1019
                "pcmpeqb    %%xmm6, %%xmm0            \n"
1020
                "maskmovdqu %%xmm7, %%xmm0            \n"
1021
                :: "r" (tmp_dst), "D" (tmp_src)
1022
                :"xmm0");
1023
                tmp_w -= 4;
1024
                tmp_src += 16;
1025
                tmp_dst += 4;
1026
            };
1027
2340 Serge 1028
 
2342 Serge 1029
            {
1030
                *(tmp_src+3) = (*tmp_dst==slot)?0xFF:0x00;
1031
                tmp_src+=4;
1032
                tmp_dst++;
1033
            };
1034
        };
1035
#else
1036
        u8* src_offset;
1037
        u8* dst_offset;
1038
        u32 ifl;
2351 Serge 1039
2340 Serge 1040
 
2342 Serge 1041
        src_offset += (u32)bitmap->uaddr;
1042
2340 Serge 1043
 
2342 Serge 1044
        dst_offset+= get_display_map();
1045
1046
 
1047
1048
 
2351 Serge 1049
        while( tmp_h--)
2342 Serge 1050
        {
1051
            u32_t tmp_w = width;
1052
1053
 
1054
            u8* tmp_dst = dst_offset;
1055
1056
 
1057
            dst_offset+= os_display->width;
1058
1059
 
1060
            {
1061
                *(tmp_src+3) = (*tmp_dst==slot)?0xFF:0x00;
1062
                tmp_src+=4;
1063
                tmp_dst++;
1064
            };
1065
        };
1066
      safe_sti(ifl);
2351 Serge 1067
    }
2342 Serge 1068
#endif
1069
1070
 
3120 serge 1071
        static warn_count;
1072
1073
 
1074
        {
1075
            printf("blit width %d height %d\n",
1076
                    width, height);
1077
            warn_count++;
1078
        };
1079
    };
1080
1081
 
1082
 
3033 serge 1083
        context->cmd_buffer&= 0xFFFFF000;
1084
2342 Serge 1085
 
3033 serge 1086
2342 Serge 1087
 
3033 serge 1088
2342 Serge 1089
 
1090
    cmd |= 3 << 17;
1091
1092
 
2340 Serge 1093
    br13|= ROP_COPY_SRC << 16;
2342 Serge 1094
    br13|= FORMAT8888   << 24;
1095
2340 Serge 1096
 
1097
    b[n++] = br13;
1098
    b[n++] = (dst_y << 16) | dst_x;                   // left, top
2342 Serge 1099
    b[n++] = ((dst_y+height)<< 16)|(dst_x+width); // bottom, right
3039 serge 1100
    b[n++] = 0;                          // destination
2342 Serge 1101
    b[n++] = (src_y << 16) | src_x;      // source left & top
1102
    b[n++] = bitmap->pitch;              // source pitch
1103
    b[n++] = bitmap->gaddr;              // source
1104
2340 Serge 1105
 
2342 Serge 1106
    b[n++] = 0x00FFFFFF;                 // Transparency Color High
1107
2340 Serge 1108
 
1109
    if( n & 1)
1110
        b[n++] = MI_NOOP;
1111
1112
 
3033 serge 1113
2340 Serge 1114
 
3037 serge 1115
3033 serge 1116
 
3037 serge 1117
 
1118
1119
 
1120
1121
 
2342 Serge 1122
    {
2351 Serge 1123
        u32 seqno;
3037 serge 1124
        int i;
1125
2351 Serge 1126
 
2342 Serge 1127
//        printf("dispatch...  ");
3033 serge 1128
3037 serge 1129
 
1130
        intel_ring_invalidate_all_caches(ring);
1131
1132
 
1133
//        printf("seqno = %d\n", seqno);
1134
1135
 
1136
            if (seqno < ring->sync_seqno[i]) {
1137
            /* The GPU can not handle its semaphore value wrapping,
1138
             * so every billion or so execbuffers, we need to stall
1139
             * the GPU in order to reset the counters.
1140
             */
1141
                DRM_DEBUG("wrap seqno\n");
1142
1143
 
1144
                if (ret)
1145
                    goto fail;
1146
                i915_gem_retire_requests(main_device);
1147
1148
 
1149
            }
1150
        }
1151
1152
 
1153
        if (ret)
1154
            goto fail;
1155
//        printf("done\n");
3033 serge 1156
2351 Serge 1157
 
3037 serge 1158
        bitmap->obj->base.write_domain = bitmap->obj->base.pending_write_domain;
1159
        bitmap->obj->fenced_gpu_access = bitmap->obj->pending_fenced_gpu_access;
1160
1161
 
1162
1163
 
1164
//        printf("retire\n");
3033 serge 1165
    }
2351 Serge 1166
    else
2342 Serge 1167
    {
2351 Serge 1168
        ring = &dev_priv->ring[RCS];
2342 Serge 1169
        ring->dispatch_execbuffer(ring, offset, n*4);
3033 serge 1170
        ring->flush(ring, 0, I915_GEM_DOMAIN_RENDER);
2351 Serge 1171
    };
1172
2342 Serge 1173
 
3037 serge 1174
//    bitmap->obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1175
2340 Serge 1176
 
3037 serge 1177
fail:
2351 Serge 1178
    return ret;
3037 serge 1179
};
2351 Serge 1180
2340 Serge 1181
 
2344 Serge 1182
 
3033 serge 1183
1184
 
1185
/* For display hotplug interrupt */
2351 Serge 1186
static void
1187
ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
1188
{
1189
    if ((dev_priv->irq_mask & mask) != 0) {
1190
        dev_priv->irq_mask &= ~mask;
1191
        I915_WRITE(DEIMR, dev_priv->irq_mask);
1192
        POSTING_READ(DEIMR);
1193
    }
1194
}
1195
2340 Serge 1196
 
2351 Serge 1197
{
1198
    drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1199
    unsigned long irqflags;
1200
1201
 
1202
//        return -EINVAL;
1203
1204
 
1205
    ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1206
                    DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1207
    spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1208
1209
 
2340 Serge 1210
}
2351 Serge 1211
1212
 
1213
 
1214
 
1215
{
1216
    drm_i915_private_t *dev_priv = dev->dev_private;
1217
    int ret, i, pipe;
1218
1219
 
1220
        dbgprintf("Interrupt enable:    %08x\n",
1221
               I915_READ(IER));
1222
        dbgprintf("Interrupt identity:  %08x\n",
1223
               I915_READ(IIR));
1224
        dbgprintf("Interrupt mask:      %08x\n",
1225
               I915_READ(IMR));
1226
        for_each_pipe(pipe)
1227
            dbgprintf("Pipe %c stat:         %08x\n",
1228
                   pipe_name(pipe),
1229
                   I915_READ(PIPESTAT(pipe)));
1230
    } else {
1231
        dbgprintf("North Display Interrupt enable:      %08x\n",
1232
           I915_READ(DEIER));
1233
        dbgprintf("North Display Interrupt identity:    %08x\n",
1234
           I915_READ(DEIIR));
1235
        dbgprintf("North Display Interrupt mask:        %08x\n",
1236
           I915_READ(DEIMR));
1237
        dbgprintf("South Display Interrupt enable:      %08x\n",
1238
           I915_READ(SDEIER));
1239
        dbgprintf("South Display Interrupt identity:    %08x\n",
1240
           I915_READ(SDEIIR));
1241
        dbgprintf("South Display Interrupt mask:        %08x\n",
1242
           I915_READ(SDEIMR));
1243
        dbgprintf("Graphics Interrupt enable:           %08x\n",
1244
           I915_READ(GTIER));
1245
        dbgprintf("Graphics Interrupt identity:         %08x\n",
1246
           I915_READ(GTIIR));
1247
        dbgprintf("Graphics Interrupt mask:             %08x\n",
1248
               I915_READ(GTIMR));
1249
    }
1250
    dbgprintf("Interrupts received: %d\n",
1251
           atomic_read(&dev_priv->irq_received));
1252
    for (i = 0; i < I915_NUM_RINGS; i++) {
1253
        if (IS_GEN6(dev) || IS_GEN7(dev)) {
1254
            printf("Graphics Interrupt mask (%s):       %08x\n",
1255
                   dev_priv->ring[i].name,
1256
                   I915_READ_IMR(&dev_priv->ring[i]));
1257
        }
1258
//        i915_ring_seqno_info(m, &dev_priv->ring[i]);
1259
    }
1260
1261
 
1262
}
1263
1264
 
1265
                     int size)
1266
{
1267
    struct intel_ring_buffer *ring;
1268
    drm_i915_private_t *dev_priv = main_device->dev_private;
1269
    u32 invalidate;
1270
    u32 seqno = 2;
1271
1272
 
1273
//    dbgprintf("execute %x size %d\n", offset, size);
1274
1275
 
1276
//    "mfence \n"
1277
//    "wbinvd \n"
1278
//    "mfence  \n"
1279
//    :::"memory");
1280
1281
 
1282
    ring->dispatch_execbuffer(ring, offset, size);
1283
1284
 
1285
    if (INTEL_INFO(main_device)->gen >= 4)
1286
        invalidate |= I915_GEM_DOMAIN_SAMPLER;
1287
    if (ring->flush(ring, invalidate, 0))
1288
        i915_gem_next_request_seqno(ring);
1289
1290
 
1291
1292
 
1293
1294
 
1295
1296
 
2340 Serge 1297
2351 Serge 1298
 
1299
 
1300
               int src_x, int src_y, u32 w, u32 h)
1301
{
1302
    drm_i915_private_t *dev_priv = main_device->dev_private;
1303
1304
 
1305
    bitmap_t   screen;
1306
1307
 
1308
1309
 
1310
//              hbitmap, dst_x, dst_y, src_x, src_y, w, h);
1311
1312
 
1313
        return -1;
1314
1315
 
1316
//    dbgprintf("bitmap %x\n", src_bitmap);
1317
1318
 
1319
        return -1;
1320
1321
 
1322
1323
 
1324
    screen.gaddr  = 0;
1325
    screen.width  = os_display->width;
1326
    screen.height = os_display->height;
1327
    screen.obj    = (void*)-1;
1328
1329
 
1330
1331
 
1332
    dst_y+= winrc.top;
1333
1334
 
1335
1336
 
1337
1338
 
2361 Serge 1339
                  int w, int h, bitmap_t *src_bitmap, int src_x, int src_y,
1340
                  bitmap_t *mask_bitmap);
1341
2360 Serge 1342
 
2361 Serge 1343
 
1344
             int src_x, int src_y, u32 w, u32 h)
1345
{
1346
    drm_i915_private_t *dev_priv = main_device->dev_private;
1347
    struct context *ctx;
1348
1349
 
1350
    bitmap_t   screen;
1351
    int        ret;
1352
1353
 
1354
    rect_t     winrc;
1355
1356
 
1357
//              hbitmap, dst_x, dst_y, src_x, src_y, w, h);
1358
1359
 
1360
        return -1;
1361
1362
 
1363
//    dbgprintf("bitmap %x\n", src_bitmap);
1364
1365
 
1366
        return -1;
1367
1368
 
1369
    if(unlikely(ctx==NULL))
1370
    {
1371
        ret = create_context();
1372
        if(ret!=0)
1373
            return -1;
1374
1375
 
1376
    };
1377
1378
 
1379
1380
 
1381
    dst_x+= winrc.left;
1382
    dst_y+= winrc.top;
1383
1384
 
1385
 
1386
    {
1387
        u8* src_offset;
1388
        u8* dst_offset;
1389
        u32 slot;
3031 serge 1390
        u32 ifl;
2361 Serge 1391
1392
 
1393
        if(ret !=0 )
1394
        {
1395
            dbgprintf("%s fail\n", __FUNCTION__);
1396
            return ret;
1397
        };
1398
1399
 
3031 serge 1400
2361 Serge 1401
 
1402
        mask_bitmap->height = winrc.bottom;
1403
        mask_bitmap->pitch =  ALIGN(w,64);
1404
1405
 
3031 serge 1406
//        slot = 0x01;
1407
1408
 
2361 Serge 1409
1410
 
1411
 
1412
        "movd       %[slot],   %%xmm6    \n"
1413
        "punpckldq  %%xmm6, %%xmm6            \n"
1414
        "punpcklqdq %%xmm6, %%xmm6            \n"
1415
        :: [slot]  "m" (slot)
3031 serge 1416
        :"xmm6");
2361 Serge 1417
1418
 
1419
1420
 
1421
        dst_offset+= get_display_map();
1422
1423
 
1424
1425
 
1426
        while( tmp_h--)
1427
        {
1428
            int tmp_w = mask_bitmap->width;
1429
1430
 
1431
            u8* tmp_dst = dst_offset;
1432
1433
 
1434
            dst_offset+= os_display->width;
1435
1436
 
1437
//            {
1438
//                *(tmp_src) = (*tmp_dst==slot)?0x1:0x00;
1439
//                tmp_src++;
1440
//                tmp_dst++;
1441
//            };
1442
            while(tmp_w >= 64)
1443
            {
1444
                __asm__ __volatile__ (
1445
                "movdqu     (%0),   %%xmm0            \n"
1446
                "movdqu   16(%0),   %%xmm1            \n"
1447
                "movdqu   32(%0),   %%xmm2            \n"
1448
                "movdqu   48(%0),   %%xmm3            \n"
1449
                "pcmpeqb    %%xmm6, %%xmm0            \n"
1450
                "pcmpeqb    %%xmm6, %%xmm1            \n"
1451
                "pcmpeqb    %%xmm6, %%xmm2            \n"
1452
                "pcmpeqb    %%xmm6, %%xmm3            \n"
1453
                "movdqa     %%xmm0,   (%%edi)         \n"
1454
                "movdqa     %%xmm1, 16(%%edi)         \n"
1455
                "movdqa     %%xmm2, 32(%%edi)         \n"
1456
                "movdqa     %%xmm3, 48(%%edi)         \n"
1457
1458
 
1459
                :"xmm0","xmm1","xmm2","xmm3");
1460
                tmp_w -= 64;
1461
                tmp_src += 64;
1462
                tmp_dst += 64;
1463
            }
1464
1465
 
1466
            {
1467
                __asm__ __volatile__ (
1468
                "movdqu     (%0),   %%xmm0            \n"
1469
                "movdqu   16(%0),   %%xmm1            \n"
1470
                "pcmpeqb    %%xmm6, %%xmm0            \n"
1471
                "pcmpeqb    %%xmm6, %%xmm1            \n"
1472
                "movdqa     %%xmm0,   (%%edi)         \n"
1473
                "movdqa     %%xmm1, 16(%%edi)         \n"
1474
1475
 
1476
                :"xmm0","xmm1");
1477
                tmp_w -= 32;
1478
                tmp_src += 32;
1479
                tmp_dst += 32;
1480
            }
1481
1482
 
1483
            {
1484
                __asm__ __volatile__ (
1485
                "movdqu     (%0),   %%xmm0            \n"
1486
                "pcmpeqb    %%xmm6, %%xmm0            \n"
1487
                "movdqa     %%xmm0,   (%%edi)         \n"
1488
                :: "r" (tmp_dst), "D" (tmp_src)
1489
                :"xmm0");
1490
                tmp_w -= 16;
1491
                tmp_src += 16;
1492
                tmp_dst += 16;
1493
            }
1494
        };
1495
      safe_sti(ifl);
1496
      ctx->seqno = os_display->mask_seqno;
1497
    }
1498
1499
 
1500
    screen.gaddr  = 0;
1501
    screen.width  = os_display->width;
1502
    screen.height = os_display->height;
1503
    screen.obj    = (void*)-1;
1504
1505
 
1506
1507
 
1508
 
1509
                 mask_bitmap);
1510
1511
 
1512
};
1513
1514
 
1515
 
3031 serge 1516
2361 Serge 1517
 
1518
 
3243 Serge 1519
2361 Serge 1520
 
1521
 
1522
 
1523
 
1524
 
2360 Serge 1525
{
1526
    unsigned long irqflags;
1527
1528
 
3266 Serge 1529
//               cwq, &cwq->worklist, cwq->worklist.next);
1530
2360 Serge 1531
 
1532
1533
 
1534
    {
1535
        struct work_struct *work = list_entry(cwq->worklist.next,
1536
                                        struct work_struct, entry);
1537
        work_func_t f = work->func;
1538
        list_del_init(cwq->worklist.next);
1539
//        dbgprintf("head %x, next %x\n",
3266 Serge 1540
//                  &cwq->worklist, cwq->worklist.next);
1541
2360 Serge 1542
 
1543
        f(work);
1544
        spin_lock_irqsave(&cwq->lock, irqflags);
1545
    }
1546
1547
 
1548
}
1549
1550
 
1551
 
1552
int __queue_work(struct workqueue_struct *wq,
1553
                         struct work_struct *work)
1554
{
1555
    unsigned long flags;
1556
1557
 
3266 Serge 1558
//               wq, work );
1559
2360 Serge 1560
 
1561
        return 0;
1562
1563
 
1564
1565
 
1566
        TimerHs(0,0, run_workqueue, wq);
1567
1568
 
1569
1570
 
1571
//    dbgprintf("wq: %x head %x, next %x\n",
3266 Serge 1572
//               wq, &wq->worklist, wq->worklist.next);
1573
2360 Serge 1574
 
1575
};
1576
1577
 
1578
{
1579
    struct delayed_work *dwork = (struct delayed_work *)__data;
1580
    struct workqueue_struct *wq = dwork->work.data;
1581
1582
 
3266 Serge 1583
//               wq, &dwork->work );
1584
2360 Serge 1585
 
1586
}
1587
1588
 
1589
 
1590
                        struct delayed_work *dwork, unsigned long delay)
1591
{
1592
    struct work_struct *work = &dwork->work;
1593
1594
 
1595
    TimerHs(0,0, delayed_work_timer_fn, dwork);
1596
    return 1;
1597
}
1598
1599
 
1600
                        struct delayed_work *dwork, unsigned long delay)
1601
{
1602
    u32  flags;
1603
1604
 
3266 Serge 1605
//               wq, &dwork->work );
1606
2360 Serge 1607
 
1608
        return __queue_work(wq, &dwork->work);
1609
1610
 
1611
}
1612
1613
 
1614
 
1615
                           unsigned int flags,
1616
                           int max_active)
1617
{
1618
    struct workqueue_struct *wq;
1619
1620
 
1621
    if (!wq)
1622
        goto err;
1623
1624
 
1625
1626
 
1627
err:
1628
    return NULL;
1629
}
1630
1631
 
3031 serge 1632
2360 Serge 1633
 
3031 serge 1634
{
1635
    u32 tmp = GetTimerTicks();
1636
2360 Serge 1637
 
3031 serge 1638
    ts->tv_nsec = (tmp - ts->tv_sec*100)*10000000;
1639
}
1640
2360 Serge 1641
 
3031 serge 1642
{
1643
        while (nsec >= NSEC_PER_SEC) {
1644
                nsec -= NSEC_PER_SEC;
1645
                ++sec;
1646
        }
1647
        while (nsec < 0) {
1648
                nsec += NSEC_PER_SEC;
1649
                --sec;
1650
        }
1651
        ts->tv_sec = sec;
1652
        ts->tv_nsec = nsec;
1653
}
1654
2360 Serge 1655
 
3031 serge 1656
 
1657