Subversion Repositories Kolibri OS

#include "drm.h"

#include "i915_drm.h"

#include "i915_drv.h"

#include "intel_drv.h"

#include 

#include 

#include 

#include 

{

    kobj_t     header;

    uint32_t   hot_x;

    uint32_t   hot_y;

    struct drm_i915_gem_object  *cobj;

}cursor_t;

#define CURSOR_HEIGHT 64

{

    int  x;

    int  y;

    int  width;

    int  height;

    int  bpp;

    int  vrefresh;

    int  pitch;

    int  lfb;

    struct drm_device    *ddev;

    struct drm_connector *connector;

    struct drm_crtc      *crtc;

    int       (*init_cursor)(cursor_t*);

    cursor_t* (__stdcall *select_cursor)(cursor_t*);

    void      (*show_cursor)(int show);

    void      (__stdcall *move_cursor)(cursor_t *cursor, int x, int y);

    void      (__stdcall *restore_cursor)(int x, int y);

    void      (*disable_mouse)(void);

};

u32_t cmd_offset;

static cursor_t*  __stdcall select_cursor_kms(cursor_t *cursor);

static void       __stdcall move_cursor_kms(cursor_t *cursor, int x, int y);

{};

{};

{

    struct drm_display_mode  *mode;

    int count = 0;

    {

        count++;

    };

    return count;

};

{

    struct drm_connector    *connector;

    struct drm_connector_helper_funcs *connector_funcs;

    struct drm_encoder      *encoder;

    struct drm_crtc         *crtc = NULL;

    struct drm_framebuffer  *fb;

    u32_t      ifl;

    {

        if( connector->status != connector_status_connected)

            continue;

        encoder = connector_funcs->best_encoder(connector);

        if( encoder == NULL)

        {

            dbgprintf("CONNECTOR %x ID: %d no active encoders\n",

                      connector, connector->base.id);

            continue;

        }

        connector->encoder = encoder;

               connector, connector->base.id,

               connector->status, connector->encoder,

               encoder->crtc);

        break;

    };

    {

        dbgprintf("No active connectors!\n");

        return -1;

    };

    {

        struct drm_crtc *tmp_crtc;

        int crtc_mask = 1;

        {

            if (encoder->possible_crtcs & crtc_mask)

            {

                crtc = tmp_crtc;

                encoder->crtc = crtc;

                break;

            };

            crtc_mask <<= 1;

        };

    };

    {

        dbgprintf("No CRTC for encoder %d\n", encoder->base.id);

        return -1;

    };

    os_display->connector = connector;

    os_display->crtc = crtc;

    {

        struct intel_crtc *intel_crtc = to_intel_crtc(os_display->crtc);

        {

            init_cursor(cursor);

        };

        os_display->init_cursor    = init_cursor;

        os_display->select_cursor  = select_cursor_kms;

        os_display->show_cursor    = NULL;

        os_display->move_cursor    = move_cursor_kms;

        os_display->restore_cursor = restore_cursor;

        os_display->disable_mouse  = disable_mouse;

        intel_crtc->cursor_y = os_display->height/2;

    };

    safe_sti(ifl);

#define XY_COLOR_BLT        ((2<<29)|(0x50<<22)|(0x4))

#define BLT_WRITE_ALPHA     (1<<21)

#define BLT_WRITE_RGB       (1<<20)

        struct drm_i915_gem_object *obj;

        struct intel_ring_buffer *ring;

        br13 = os_display->pitch;

        br13 |= 0xF0 << 16;

        br13 |= 3 << 24;

        i915_gem_object_pin(obj, 4096, true);

        cmd_offset = obj->gtt_offset;

        b[n++] = cmd;

        b[n++] = br13;

        b[n++] = 0; // top, left

        b[n++] = (128 << 16) | 128; // bottom, right

        b[n++] = 0; // dst

        b[n++] = 0x0000FF00;

        b[n++] = MI_BATCH_BUFFER_END;

        if( n & 1)

            b[n++] = MI_NOOP;

//        i915_gem_object_set_to_gtt_domain(obj, false);

        ring->dispatch_execbuffer(ring,cmd_offset, n*4);

};

              videomode_t *reqmode, bool strict)

{

    struct drm_display_mode  *mode = NULL, *tmpmode;

    drm_i915_private_t *dev_priv = dev->dev_private;

    struct drm_fb_helper *fb_helper = &dev_priv->fbdev->helper;

               reqmode->width, reqmode->height, reqmode->freq);

    {

        if( (drm_mode_width(tmpmode)    == reqmode->width)  &&

            (drm_mode_height(tmpmode)   == reqmode->height) &&

            (drm_mode_vrefresh(tmpmode) == reqmode->freq) )

        {

            mode = tmpmode;

            goto do_set;

        }

    };

    {

        list_for_each_entry(tmpmode, &connector->modes, head)

        {

            if( (drm_mode_width(tmpmode)  == reqmode->width)  &&

                (drm_mode_height(tmpmode) == reqmode->height) )

            {

                mode = tmpmode;

                goto do_set;

            }

        };

    };

    {

        struct drm_framebuffer   *fb;

        struct drm_encoder       *encoder;

        struct drm_crtc          *crtc;

        char *enc_name;

        crtc = encoder->crtc;

        enc_name = drm_get_encoder_name(encoder);

                   reqmode->width, reqmode->height, con_name, enc_name);

        fb->height = reqmode->height;

        fb->pitch  = ALIGN(reqmode->width * 4, 64);

        fb->bits_per_pixel = 32;

        fb->depth == 24;

        crtc->enabled = true;

        os_display->crtc = crtc;

//        radeon_show_cursor_kms(crtc);

        {

            os_display->width    = fb->width;

            os_display->height   = fb->height;

            os_display->pitch    = fb->pitch;

            os_display->vrefresh = drm_mode_vrefresh(mode);

                       fb->width, fb->height, fb->pitch);

        }

        else

            DRM_ERROR("failed to set mode %d_%d on crtc %p\n",

                       fb->width, fb->height, crtc);

    }

    return ret;

};

{

    int err = -1;

    {

        *count = os_display->supported_modes;

        err = 0;

    }

    else if( mode != NULL )

    {

        struct drm_display_mode  *drmmode;

        int i = 0;

            *count = os_display->supported_modes;

        {

            if( i < *count)

            {

                mode->width  = drm_mode_width(drmmode);

                mode->height = drm_mode_height(drmmode);

                mode->bpp    = 32;

                mode->freq   = drm_mode_vrefresh(drmmode);

                i++;

                mode++;

            }

            else break;

        };

        *count = i;

        err = 0;

    };

    LEAVE();

    return err;

};

{

    int err = -1;

               mode->width, mode->height, mode->freq);

        (mode->height != 0)  &&

        (mode->freq   != 0 ) &&

        ( (mode->width   != os_display->width)  ||

          (mode->height  != os_display->height) ||

          (mode->freq    != os_display->vrefresh) ) )

    {

        if( set_mode(os_display->ddev, os_display->connector, mode, true) )

            err = 0;

    };

    return err;

};

{

    list_del(&cursor->list);

//    radeon_bo_unpin(cursor->robj);

//    KernelFree(cursor->data);

    __DestroyObject(cursor);

};

{

    struct drm_i915_private *dev_priv = os_display->ddev->dev_private;

    struct drm_i915_gem_object *obj;

    uint32_t *bits;

    uint32_t *src;

    int       ret;

    {

        bits = (uint32_t*)KernelAlloc(CURSOR_WIDTH*CURSOR_HEIGHT*4);

        if (unlikely(bits == NULL))

            return ENOMEM;

        cursor->cobj = (struct drm_i915_gem_object *)GetPgAddr(bits);

    }

    else

    {

        obj = i915_gem_alloc_object(os_display->ddev, CURSOR_WIDTH*CURSOR_HEIGHT*4);

        if (unlikely(obj == NULL))

            return -ENOMEM;

        if (ret) {

//           drm_gem_object_unreference(&obj->base);

            return ret;

        }

 * GTT space is continuous. I guarantee it.                           */

                    CURSOR_WIDTH*CURSOR_HEIGHT*4, PG_SW);

        {

//          i915_gem_object_unpin(obj);

//           drm_gem_object_unreference(&obj->base);

            return -ENOMEM;

        };

        cursor->cobj = obj;

    };

    {

        for(j = 0; j < 32; j++)

            *bits++ = *src++;

        for(j = 32; j < CURSOR_WIDTH; j++)

            *bits++ = 0;

    }

    for(i = 0; i < CURSOR_WIDTH*(CURSOR_HEIGHT-32); i++)

        *bits++ = 0;

    LEAVE();

}

{

    struct drm_device *dev = crtc->dev;

    struct drm_i915_private *dev_priv = dev->dev_private;

    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

    int pipe = intel_crtc->pipe;

    bool visible = base != 0;

        uint32_t cntl = I915_READ(CURCNTR(pipe));

        if (base) {

            cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);

            cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;

            cntl |= pipe << 28; /* Connect to correct pipe */

        } else {

            cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);

            cntl |= CURSOR_MODE_DISABLE;

        }

        I915_WRITE(CURCNTR(pipe), cntl);

    }

    /* and commit changes on next vblank */

    I915_WRITE(CURBASE(pipe), base);

}

{

    struct drm_i915_private *dev_priv = os_display->ddev->dev_private;

    struct intel_crtc *intel_crtc = to_intel_crtc(os_display->crtc);

    u32 base, pos;

    bool visible;

    intel_crtc->cursor_y = y;

    y = y - cursor->hot_y;

    if (x >= os_display->width)

        base = 0;

        base = 0;

    {

        if (x + intel_crtc->cursor_width < 0)

            base = 0;

        x = -x;

    }

    pos |= x << CURSOR_X_SHIFT;

    {

        if (y + intel_crtc->cursor_height < 0)

            base = 0;

        y = -y;

    }

    pos |= y << CURSOR_Y_SHIFT;

    if (!visible && !intel_crtc->cursor_visible)

        return;

//    if (IS_845G(dev) || IS_I865G(dev))

//        i845_update_cursor(crtc, base);

//    else

        i9xx_update_cursor(os_display->crtc, base);

{

    struct drm_i915_private *dev_priv = os_display->ddev->dev_private;

    struct intel_crtc *intel_crtc = to_intel_crtc(os_display->crtc);

    cursor_t *old;

    os_display->cursor = cursor;

       intel_crtc->cursor_addr = cursor->cobj->gtt_offset;

    else

        intel_crtc->cursor_addr = cursor->cobj;

    intel_crtc->cursor_height = 32;

    return old;

};

                    int w, int h, int pitch)

{

    struct intel_ring_buffer *ring;

    u32_t offset;

//        cmd_buffer&= 0xFFFFF000;

    br13 = os_display->pitch;

    br13 |= 0xCC << 16;

    br13 |= 3 << 24;

    b[n++] = br13;

    b[n++] = (y << 16) | x;

    b[n++] = ( (y+h) << 16) | (x+w); // bottom, right

    b[n++] = 0; // dst_offset

    b[n++] = 0; //src_top|src_left

    b[n++] = (u32_t)src_offset;

    if( n & 1)

        b[n++] = MI_NOOP;

    ring->dispatch_execbuffer(ring, cmd_offset, n*4);

//    if (ret)

//        return ret;

//    if (invalidate & I915_GEM_GPU_DOMAINS)

//        cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;

    intel_ring_emit(ring, MI_FLUSH_DW);

    intel_ring_emit(ring, 0);

    intel_ring_emit(ring, 0);

    intel_ring_emit(ring, MI_NOOP);

    intel_ring_advance(ring);

    return -1;

};

               int src_x, int src_y, u32 w, u32 h)

{

    drm_i915_private_t *dev_priv = main_device->dev_private;

    struct intel_ring_buffer *ring;

    u32_t br13, cmd, *b;

    u32_t offset;

        return -1;

        return -1;

//        cmd_buffer&= 0xFFFFF000;

    br13 = os_display->pitch;

    br13 |= 0xCC << 16;

    br13 |= 3 << 24;

    b[n++] = br13;

    b[n++] = (dst_y << 16) | dst_x;

    b[n++] = ( (dst_y+h) << 16) | (dst_x+w); // bottom, right

    b[n++] = 0; // dst_offset

    b[n++] = (src_y << 16) | src_x;

    b[n++] = bitmap->gaddr;

    if( n & 1)

        b[n++] = MI_NOOP;

    ring->dispatch_execbuffer(ring, cmd_offset, n*4);

//    if (ret)

//        return ret;

    intel_ring_emit(ring, 0);

    intel_ring_emit(ring, 0);

    intel_ring_emit(ring, MI_NOOP);

    intel_ring_advance(ring);

fail:

    return -1;

};