WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/intel_uncore.c

Rev	Author	Line No.	Line
4104	Serge	1	/*
		2	* Copyright © 2013 Intel Corporation
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
		21	* IN THE SOFTWARE.
		22	*/
		23
		24	#include "i915_drv.h"
		25	#include "intel_drv.h"
		26
		27	#define FORCEWAKE_ACK_TIMEOUT_MS 2
		28
		29	#define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
		30	#define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
		31
		32	#define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
		33	#define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
		34
		35	#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
		36	#define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
		37
		38	#define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
		39	#define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
		40
		41	#define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
		42
5060	serge	43	static void
		44	assert_device_not_suspended(struct drm_i915_private *dev_priv)
		45	{
5354	serge	46	WARN_ONCE(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
5060	serge	47	"Device suspended\n");
		48	}
4104	Serge	49
		50	static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
		51	{
		52	/* w/a for a sporadic read returning 0 by waiting for the GT
		53	* thread to wake up.
		54	*/
5354	serge	55	if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
		56	GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
4104	Serge	57	DRM_ERROR("GT thread status wait timed out\n");
		58	}
		59
		60	static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
		61	{
		62	__raw_i915_write32(dev_priv, FORCEWAKE, 0);
		63	/* something from same cacheline, but !FORCEWAKE */
		64	__raw_posting_read(dev_priv, ECOBUS);
		65	}
		66
4560	Serge	67	static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,
		68	int fw_engine)
4104	Serge	69	{
		70	if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0,
		71	FORCEWAKE_ACK_TIMEOUT_MS))
		72	DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
		73
		74	__raw_i915_write32(dev_priv, FORCEWAKE, 1);
		75	/* something from same cacheline, but !FORCEWAKE */
		76	__raw_posting_read(dev_priv, ECOBUS);
		77
		78	if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),
		79	FORCEWAKE_ACK_TIMEOUT_MS))
		80	DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
		81
		82	/* WaRsForcewakeWaitTC0:snb */
		83	__gen6_gt_wait_for_thread_c0(dev_priv);
		84	}
		85
5060	serge	86	static void __gen7_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
4104	Serge	87	{
		88	__raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
		89	/* something from same cacheline, but !FORCEWAKE_MT */
		90	__raw_posting_read(dev_priv, ECOBUS);
		91	}
		92
5060	serge	93	static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
4560	Serge	94	int fw_engine)
4104	Serge	95	{
		96	u32 forcewake_ack;
		97
5354	serge	98	if (IS_HASWELL(dev_priv->dev) \|\| IS_BROADWELL(dev_priv->dev))
4104	Serge	99	forcewake_ack = FORCEWAKE_ACK_HSW;
		100	else
		101	forcewake_ack = FORCEWAKE_MT_ACK;
		102
		103	if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0,
		104	FORCEWAKE_ACK_TIMEOUT_MS))
		105	DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
		106
		107	__raw_i915_write32(dev_priv, FORCEWAKE_MT,
		108	_MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
		109	/* something from same cacheline, but !FORCEWAKE_MT */
		110	__raw_posting_read(dev_priv, ECOBUS);
		111
		112	if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL),
		113	FORCEWAKE_ACK_TIMEOUT_MS))
		114	DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
		115
		116	/* WaRsForcewakeWaitTC0:ivb,hsw */
		117	__gen6_gt_wait_for_thread_c0(dev_priv);
		118	}
		119
		120	static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
		121	{
		122	u32 gtfifodbg;
		123
		124	gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
4560	Serge	125	if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
		126	__raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
4104	Serge	127	}
		128
4560	Serge	129	static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,
		130	int fw_engine)
4104	Serge	131	{
		132	__raw_i915_write32(dev_priv, FORCEWAKE, 0);
		133	/* something from same cacheline, but !FORCEWAKE */
		134	__raw_posting_read(dev_priv, ECOBUS);
		135	gen6_gt_check_fifodbg(dev_priv);
		136	}
		137
5060	serge	138	static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv,
4560	Serge	139	int fw_engine)
4104	Serge	140	{
		141	__raw_i915_write32(dev_priv, FORCEWAKE_MT,
		142	_MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
		143	/* something from same cacheline, but !FORCEWAKE_MT */
		144	__raw_posting_read(dev_priv, ECOBUS);
5060	serge	145
		146	if (IS_GEN7(dev_priv->dev))
4104	Serge	147	gen6_gt_check_fifodbg(dev_priv);
		148	}
		149
		150	static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
		151	{
		152	int ret = 0;
		153
4560	Serge	154	/* On VLV, FIFO will be shared by both SW and HW.
		155	* So, we need to read the FREE_ENTRIES everytime */
		156	if (IS_VALLEYVIEW(dev_priv->dev))
		157	dev_priv->uncore.fifo_count =
		158	__raw_i915_read32(dev_priv, GTFIFOCTL) &
		159	GT_FIFO_FREE_ENTRIES_MASK;
		160
4104	Serge	161	if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
		162	int loop = 500;
4560	Serge	163	u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
4104	Serge	164	while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
		165	udelay(10);
4560	Serge	166	fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
4104	Serge	167	}
		168	if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
		169	++ret;
		170	dev_priv->uncore.fifo_count = fifo;
		171	}
		172	dev_priv->uncore.fifo_count--;
		173
		174	return ret;
		175	}
		176
		177	static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
		178	{
		179	__raw_i915_write32(dev_priv, FORCEWAKE_VLV,
		180	_MASKED_BIT_DISABLE(0xffff));
5060	serge	181	__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
		182	_MASKED_BIT_DISABLE(0xffff));
4104	Serge	183	/* something from same cacheline, but !FORCEWAKE_VLV */
		184	__raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
		185	}
		186
4560	Serge	187	static void __vlv_force_wake_get(struct drm_i915_private *dev_priv,
		188	int fw_engine)
4104	Serge	189	{
4560	Serge	190	/* Check for Render Engine */
		191	if (FORCEWAKE_RENDER & fw_engine) {
		192	if (wait_for_atomic((__raw_i915_read32(dev_priv,
		193	FORCEWAKE_ACK_VLV) &
		194	FORCEWAKE_KERNEL) == 0,
4104	Serge	195	FORCEWAKE_ACK_TIMEOUT_MS))
4560	Serge	196	DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
4104	Serge	197
		198	__raw_i915_write32(dev_priv, FORCEWAKE_VLV,
		199	_MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4560	Serge	200
		201	if (wait_for_atomic((__raw_i915_read32(dev_priv,
		202	FORCEWAKE_ACK_VLV) &
		203	FORCEWAKE_KERNEL),
		204	FORCEWAKE_ACK_TIMEOUT_MS))
		205	DRM_ERROR("Timed out: waiting for Render to ack.\n");
		206	}
		207
		208	/* Check for Media Engine */
		209	if (FORCEWAKE_MEDIA & fw_engine) {
		210	if (wait_for_atomic((__raw_i915_read32(dev_priv,
		211	FORCEWAKE_ACK_MEDIA_VLV) &
		212	FORCEWAKE_KERNEL) == 0,
		213	FORCEWAKE_ACK_TIMEOUT_MS))
		214	DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
		215
4104	Serge	216	__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
		217	_MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
		218
4560	Serge	219	if (wait_for_atomic((__raw_i915_read32(dev_priv,
		220	FORCEWAKE_ACK_MEDIA_VLV) &
4104	Serge	221	FORCEWAKE_KERNEL),
		222	FORCEWAKE_ACK_TIMEOUT_MS))
4560	Serge	223	DRM_ERROR("Timed out: waiting for media to ack.\n");
		224	}
4104	Serge	225	}
		226
4560	Serge	227	static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
		228	int fw_engine)
4104	Serge	229	{
4560	Serge	230
		231	/* Check for Render Engine */
		232	if (FORCEWAKE_RENDER & fw_engine)
4104	Serge	233	__raw_i915_write32(dev_priv, FORCEWAKE_VLV,
		234	_MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4560	Serge	235
		236
		237	/* Check for Media Engine */
		238	if (FORCEWAKE_MEDIA & fw_engine)
4104	Serge	239	__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
		240	_MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4560	Serge	241
5060	serge	242	/* something from same cacheline, but !FORCEWAKE_VLV */
		243	__raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
		244	if (!IS_CHERRYVIEW(dev_priv->dev))
4104	Serge	245	gen6_gt_check_fifodbg(dev_priv);
		246	}
		247
5060	serge	248	static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
4560	Serge	249	{
		250	unsigned long irqflags;
		251
		252	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
		253
5060	serge	254	if (fw_engine & FORCEWAKE_RENDER &&
		255	dev_priv->uncore.fw_rendercount++ != 0)
		256	fw_engine &= ~FORCEWAKE_RENDER;
		257	if (fw_engine & FORCEWAKE_MEDIA &&
		258	dev_priv->uncore.fw_mediacount++ != 0)
		259	fw_engine &= ~FORCEWAKE_MEDIA;
		260
		261	if (fw_engine)
		262	dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_engine);
		263
4560	Serge	264	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
		265	}
		266
5060	serge	267	static void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
4560	Serge	268	{
		269	unsigned long irqflags;
		270
		271	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
		272
5060	serge	273	if (fw_engine & FORCEWAKE_RENDER) {
		274	WARN_ON(!dev_priv->uncore.fw_rendercount);
		275	if (--dev_priv->uncore.fw_rendercount != 0)
		276	fw_engine &= ~FORCEWAKE_RENDER;
4560	Serge	277	}
		278
5060	serge	279	if (fw_engine & FORCEWAKE_MEDIA) {
		280	WARN_ON(!dev_priv->uncore.fw_mediacount);
		281	if (--dev_priv->uncore.fw_mediacount != 0)
		282	fw_engine &= ~FORCEWAKE_MEDIA;
4560	Serge	283	}
		284
5060	serge	285	if (fw_engine)
		286	dev_priv->uncore.funcs.force_wake_put(dev_priv, fw_engine);
		287
4560	Serge	288	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
		289	}
		290
5354	serge	291	static void __gen9_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
		292	{
		293	__raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9,
		294	_MASKED_BIT_DISABLE(0xffff));
		295
		296	__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9,
		297	_MASKED_BIT_DISABLE(0xffff));
		298
		299	__raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9,
		300	_MASKED_BIT_DISABLE(0xffff));
		301	}
		302
		303	static void
		304	__gen9_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
		305	{
		306	/* Check for Render Engine */
		307	if (FORCEWAKE_RENDER & fw_engine) {
		308	if (wait_for_atomic((__raw_i915_read32(dev_priv,
		309	FORCEWAKE_ACK_RENDER_GEN9) &
		310	FORCEWAKE_KERNEL) == 0,
		311	FORCEWAKE_ACK_TIMEOUT_MS))
		312	DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
		313
		314	__raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9,
		315	_MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
		316
		317	if (wait_for_atomic((__raw_i915_read32(dev_priv,
		318	FORCEWAKE_ACK_RENDER_GEN9) &
		319	FORCEWAKE_KERNEL),
		320	FORCEWAKE_ACK_TIMEOUT_MS))
		321	DRM_ERROR("Timed out: waiting for Render to ack.\n");
		322	}
		323
		324	/* Check for Media Engine */
		325	if (FORCEWAKE_MEDIA & fw_engine) {
		326	if (wait_for_atomic((__raw_i915_read32(dev_priv,
		327	FORCEWAKE_ACK_MEDIA_GEN9) &
		328	FORCEWAKE_KERNEL) == 0,
		329	FORCEWAKE_ACK_TIMEOUT_MS))
		330	DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
		331
		332	__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9,
		333	_MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
		334
		335	if (wait_for_atomic((__raw_i915_read32(dev_priv,
		336	FORCEWAKE_ACK_MEDIA_GEN9) &
		337	FORCEWAKE_KERNEL),
		338	FORCEWAKE_ACK_TIMEOUT_MS))
		339	DRM_ERROR("Timed out: waiting for Media to ack.\n");
		340	}
		341
		342	/* Check for Blitter Engine */
		343	if (FORCEWAKE_BLITTER & fw_engine) {
		344	if (wait_for_atomic((__raw_i915_read32(dev_priv,
		345	FORCEWAKE_ACK_BLITTER_GEN9) &
		346	FORCEWAKE_KERNEL) == 0,
		347	FORCEWAKE_ACK_TIMEOUT_MS))
		348	DRM_ERROR("Timed out: Blitter forcewake old ack to clear.\n");
		349
		350	__raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9,
		351	_MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
		352
		353	if (wait_for_atomic((__raw_i915_read32(dev_priv,
		354	FORCEWAKE_ACK_BLITTER_GEN9) &
		355	FORCEWAKE_KERNEL),
		356	FORCEWAKE_ACK_TIMEOUT_MS))
		357	DRM_ERROR("Timed out: waiting for Blitter to ack.\n");
		358	}
		359	}
		360
		361	static void
		362	__gen9_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
		363	{
		364	/* Check for Render Engine */
		365	if (FORCEWAKE_RENDER & fw_engine)
		366	__raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9,
		367	_MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
		368
		369	/* Check for Media Engine */
		370	if (FORCEWAKE_MEDIA & fw_engine)
		371	__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9,
		372	_MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
		373
		374	/* Check for Blitter Engine */
		375	if (FORCEWAKE_BLITTER & fw_engine)
		376	__raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9,
		377	_MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
		378	}
		379
		380	static void
		381	gen9_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
		382	{
		383	unsigned long irqflags;
		384
		385	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
		386
		387	if (FORCEWAKE_RENDER & fw_engine) {
		388	if (dev_priv->uncore.fw_rendercount++ == 0)
		389	dev_priv->uncore.funcs.force_wake_get(dev_priv,
		390	FORCEWAKE_RENDER);
		391	}
		392
		393	if (FORCEWAKE_MEDIA & fw_engine) {
		394	if (dev_priv->uncore.fw_mediacount++ == 0)
		395	dev_priv->uncore.funcs.force_wake_get(dev_priv,
		396	FORCEWAKE_MEDIA);
		397	}
		398
		399	if (FORCEWAKE_BLITTER & fw_engine) {
		400	if (dev_priv->uncore.fw_blittercount++ == 0)
		401	dev_priv->uncore.funcs.force_wake_get(dev_priv,
		402	FORCEWAKE_BLITTER);
		403	}
		404
		405	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
		406	}
		407
		408	static void
		409	gen9_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
		410	{
		411	unsigned long irqflags;
		412
		413	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
		414
		415	if (FORCEWAKE_RENDER & fw_engine) {
		416	WARN_ON(dev_priv->uncore.fw_rendercount == 0);
		417	if (--dev_priv->uncore.fw_rendercount == 0)
		418	dev_priv->uncore.funcs.force_wake_put(dev_priv,
		419	FORCEWAKE_RENDER);
		420	}
		421
		422	if (FORCEWAKE_MEDIA & fw_engine) {
		423	WARN_ON(dev_priv->uncore.fw_mediacount == 0);
		424	if (--dev_priv->uncore.fw_mediacount == 0)
		425	dev_priv->uncore.funcs.force_wake_put(dev_priv,
		426	FORCEWAKE_MEDIA);
		427	}
		428
		429	if (FORCEWAKE_BLITTER & fw_engine) {
		430	WARN_ON(dev_priv->uncore.fw_blittercount == 0);
		431	if (--dev_priv->uncore.fw_blittercount == 0)
		432	dev_priv->uncore.funcs.force_wake_put(dev_priv,
		433	FORCEWAKE_BLITTER);
		434	}
		435
		436	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
		437	}
		438
5060	serge	439	static void gen6_force_wake_timer(unsigned long arg)
4560	Serge	440	{
5060	serge	441	struct drm_i915_private dev_priv = (void )arg;
4560	Serge	442	unsigned long irqflags;
		443
5060	serge	444	assert_device_not_suspended(dev_priv);
		445
4560	Serge	446	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
5060	serge	447	WARN_ON(!dev_priv->uncore.forcewake_count);
		448
4560	Serge	449	if (--dev_priv->uncore.forcewake_count == 0)
		450	dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
		451	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
5060	serge	452
		453	intel_runtime_pm_put(dev_priv);
4560	Serge	454	}
		455
5060	serge	456	void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
4371	Serge	457	{
		458	struct drm_i915_private *dev_priv = dev->dev_private;
5060	serge	459	unsigned long irqflags;
4371	Serge	460
5060	serge	461	if (del_timer_sync(&dev_priv->uncore.force_wake_timer))
		462	gen6_force_wake_timer((unsigned long)dev_priv);
		463
		464	/* Hold uncore.lock across reset to prevent any register access
		465	* with forcewake not set correctly
		466	*/
		467	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
		468
		469	if (IS_VALLEYVIEW(dev))
4371	Serge	470	vlv_force_wake_reset(dev_priv);
5060	serge	471	else if (IS_GEN6(dev) \|\| IS_GEN7(dev))
4371	Serge	472	__gen6_gt_force_wake_reset(dev_priv);
5060	serge	473
5354	serge	474	if (IS_IVYBRIDGE(dev) \|\| IS_HASWELL(dev) \|\| IS_BROADWELL(dev))
5060	serge	475	__gen7_gt_force_wake_mt_reset(dev_priv);
		476
5354	serge	477	if (IS_GEN9(dev))
		478	__gen9_gt_force_wake_mt_reset(dev_priv);
		479
5060	serge	480	if (restore) { /* If reset with a user forcewake, try to restore */
		481	unsigned fw = 0;
		482
		483	if (IS_VALLEYVIEW(dev)) {
		484	if (dev_priv->uncore.fw_rendercount)
		485	fw \|= FORCEWAKE_RENDER;
		486
		487	if (dev_priv->uncore.fw_mediacount)
		488	fw \|= FORCEWAKE_MEDIA;
5354	serge	489	} else if (IS_GEN9(dev)) {
		490	if (dev_priv->uncore.fw_rendercount)
		491	fw \|= FORCEWAKE_RENDER;
		492
		493	if (dev_priv->uncore.fw_mediacount)
		494	fw \|= FORCEWAKE_MEDIA;
		495
		496	if (dev_priv->uncore.fw_blittercount)
		497	fw \|= FORCEWAKE_BLITTER;
5060	serge	498	} else {
		499	if (dev_priv->uncore.forcewake_count)
		500	fw = FORCEWAKE_ALL;
4371	Serge	501	}
5060	serge	502
		503	if (fw)
		504	dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
		505
		506	if (IS_GEN6(dev) \|\| IS_GEN7(dev))
		507	dev_priv->uncore.fifo_count =
		508	__raw_i915_read32(dev_priv, GTFIFOCTL) &
		509	GT_FIFO_FREE_ENTRIES_MASK;
		510	}
		511
		512	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4371	Serge	513	}
		514
5354	serge	515	static void __intel_uncore_early_sanitize(struct drm_device *dev,
		516	bool restore_forcewake)
4104	Serge	517	{
		518	struct drm_i915_private *dev_priv = dev->dev_private;
		519
		520	if (HAS_FPGA_DBG_UNCLAIMED(dev))
		521	__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
		522
5060	serge	523	if ((IS_HASWELL(dev) \|\| IS_BROADWELL(dev)) &&
4560	Serge	524	(__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
		525	/* The docs do not explain exactly how the calculation can be
		526	* made. It is somewhat guessable, but for now, it's always
		527	* 128MB.
		528	* NB: We can't write IDICR yet because we do not have gt funcs
		529	* set up */
		530	dev_priv->ellc_size = 128;
		531	DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
		532	}
4104	Serge	533
4560	Serge	534	/* clear out old GT FIFO errors */
		535	if (IS_GEN6(dev) \|\| IS_GEN7(dev))
		536	__raw_i915_write32(dev_priv, GTFIFODBG,
		537	__raw_i915_read32(dev_priv, GTFIFODBG));
4104	Serge	538
5060	serge	539	intel_uncore_forcewake_reset(dev, restore_forcewake);
4104	Serge	540	}
		541
5354	serge	542	void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
		543	{
		544	__intel_uncore_early_sanitize(dev, restore_forcewake);
		545	i915_check_and_clear_faults(dev);
		546	}
		547
4104	Serge	548	void intel_uncore_sanitize(struct drm_device *dev)
		549	{
		550	/* BIOS often leaves RC6 enabled, but disable it for hw init */
		551	intel_disable_gt_powersave(dev);
		552	}
		553
		554	/*
		555	* Generally this is called implicitly by the register read function. However,
		556	* if some sequence requires the GT to not power down then this function should
		557	* be called at the beginning of the sequence followed by a call to
		558	* gen6_gt_force_wake_put() at the end of the sequence.
		559	*/
4560	Serge	560	void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
4104	Serge	561	{
		562	unsigned long irqflags;
		563
4560	Serge	564	if (!dev_priv->uncore.funcs.force_wake_get)
		565	return;
		566
		567	intel_runtime_pm_get(dev_priv);
		568
5354	serge	569	/* Redirect to Gen9 specific routine */
		570	if (IS_GEN9(dev_priv->dev))
		571	return gen9_force_wake_get(dev_priv, fw_engine);
		572
4560	Serge	573	/* Redirect to VLV specific routine */
		574	if (IS_VALLEYVIEW(dev_priv->dev))
		575	return vlv_force_wake_get(dev_priv, fw_engine);
		576
4104	Serge	577	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
		578	if (dev_priv->uncore.forcewake_count++ == 0)
4560	Serge	579	dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
4104	Serge	580	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
		581	}
		582
		583	/*
		584	* see gen6_gt_force_wake_get()
		585	*/
4560	Serge	586	void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
4104	Serge	587	{
		588	unsigned long irqflags;
5060	serge	589	bool delayed = false;
4104	Serge	590
4560	Serge	591	if (!dev_priv->uncore.funcs.force_wake_put)
		592	return;
		593
5354	serge	594	/* Redirect to Gen9 specific routine */
		595	if (IS_GEN9(dev_priv->dev)) {
		596	gen9_force_wake_put(dev_priv, fw_engine);
		597	goto out;
		598	}
		599
4560	Serge	600	/* Redirect to VLV specific routine */
5060	serge	601	if (IS_VALLEYVIEW(dev_priv->dev)) {
		602	vlv_force_wake_put(dev_priv, fw_engine);
		603	goto out;
		604	}
4560	Serge	605
		606
4104	Serge	607	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
5060	serge	608	WARN_ON(!dev_priv->uncore.forcewake_count);
		609
4560	Serge	610	if (--dev_priv->uncore.forcewake_count == 0) {
		611	dev_priv->uncore.forcewake_count++;
5060	serge	612	delayed = true;
		613	// mod_timer_pinned(&dev_priv->uncore.force_wake_timer,
		614	// GetTimerTicks() + 1);
4560	Serge	615	}
4104	Serge	616	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4560	Serge	617
5060	serge	618	out:
		619	if (!delayed)
4560	Serge	620	intel_runtime_pm_put(dev_priv);
4104	Serge	621	}
		622
5060	serge	623	void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
		624	{
		625	if (!dev_priv->uncore.funcs.force_wake_get)
		626	return;
		627
		628	WARN_ON(dev_priv->uncore.forcewake_count > 0);
		629	}
		630
4104	Serge	631	/* We give fast paths for the really cool registers */
		632	#define NEEDS_FORCE_WAKE(dev_priv, reg) \
4560	Serge	633	((reg) < 0x40000 && (reg) != FORCEWAKE)
4104	Serge	634
5060	serge	635	#define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
		636
		637	#define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
		638	(REG_RANGE((reg), 0x2000, 0x4000) \|\| \
		639	REG_RANGE((reg), 0x5000, 0x8000) \|\| \
		640	REG_RANGE((reg), 0xB000, 0x12000) \|\| \
		641	REG_RANGE((reg), 0x2E000, 0x30000))
		642
		643	#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
		644	(REG_RANGE((reg), 0x12000, 0x14000) \|\| \
		645	REG_RANGE((reg), 0x22000, 0x24000) \|\| \
		646	REG_RANGE((reg), 0x30000, 0x40000))
		647
		648	#define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
		649	(REG_RANGE((reg), 0x2000, 0x4000) \|\| \
		650	REG_RANGE((reg), 0x5000, 0x8000) \|\| \
		651	REG_RANGE((reg), 0x8300, 0x8500) \|\| \
		652	REG_RANGE((reg), 0xB000, 0xC000) \|\| \
		653	REG_RANGE((reg), 0xE000, 0xE800))
		654
		655	#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
		656	(REG_RANGE((reg), 0x8800, 0x8900) \|\| \
		657	REG_RANGE((reg), 0xD000, 0xD800) \|\| \
		658	REG_RANGE((reg), 0x12000, 0x14000) \|\| \
		659	REG_RANGE((reg), 0x1A000, 0x1C000) \|\| \
		660	REG_RANGE((reg), 0x1E800, 0x1EA00) \|\| \
		661	REG_RANGE((reg), 0x30000, 0x40000))
		662
		663	#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
		664	(REG_RANGE((reg), 0x4000, 0x5000) \|\| \
		665	REG_RANGE((reg), 0x8000, 0x8300) \|\| \
		666	REG_RANGE((reg), 0x8500, 0x8600) \|\| \
		667	REG_RANGE((reg), 0x9000, 0xB000) \|\| \
		668	REG_RANGE((reg), 0xC000, 0xC800) \|\| \
		669	REG_RANGE((reg), 0xF000, 0x10000) \|\| \
		670	REG_RANGE((reg), 0x14000, 0x14400) \|\| \
		671	REG_RANGE((reg), 0x22000, 0x24000))
		672
5354	serge	673	#define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
		674	REG_RANGE((reg), 0xB00, 0x2000)
		675
		676	#define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
		677	(REG_RANGE((reg), 0x2000, 0x2700) \|\| \
		678	REG_RANGE((reg), 0x3000, 0x4000) \|\| \
		679	REG_RANGE((reg), 0x5200, 0x8000) \|\| \
		680	REG_RANGE((reg), 0x8140, 0x8160) \|\| \
		681	REG_RANGE((reg), 0x8300, 0x8500) \|\| \
		682	REG_RANGE((reg), 0x8C00, 0x8D00) \|\| \
		683	REG_RANGE((reg), 0xB000, 0xB480) \|\| \
		684	REG_RANGE((reg), 0xE000, 0xE900) \|\| \
		685	REG_RANGE((reg), 0x24400, 0x24800))
		686
		687	#define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
		688	(REG_RANGE((reg), 0x8130, 0x8140) \|\| \
		689	REG_RANGE((reg), 0x8800, 0x8A00) \|\| \
		690	REG_RANGE((reg), 0xD000, 0xD800) \|\| \
		691	REG_RANGE((reg), 0x12000, 0x14000) \|\| \
		692	REG_RANGE((reg), 0x1A000, 0x1EA00) \|\| \
		693	REG_RANGE((reg), 0x30000, 0x40000))
		694
		695	#define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
		696	REG_RANGE((reg), 0x9400, 0x9800)
		697
		698	#define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
		699	((reg) < 0x40000 &&\
		700	!FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
		701	!FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
		702	!FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
		703	!FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
		704
4104	Serge	705	static void
		706	ilk_dummy_write(struct drm_i915_private *dev_priv)
		707	{
		708	/* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
		709	* the chip from rc6 before touching it for real. MI_MODE is masked,
		710	* hence harmless to write 0 into. */
		711	__raw_i915_write32(dev_priv, MI_MODE, 0);
		712	}
		713
		714	static void
5060	serge	715	hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
		716	bool before)
4104	Serge	717	{
5060	serge	718	const char *op = read ? "reading" : "writing to";
		719	const char *when = before ? "before" : "after";
		720
		721	if (!i915.mmio_debug)
		722	return;
		723
4560	Serge	724	if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
5060	serge	725	WARN(1, "Unclaimed register detected %s %s register 0x%x\n",
		726	when, op, reg);
4104	Serge	727	__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
		728	}
		729	}
		730
		731	static void
5060	serge	732	hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
4104	Serge	733	{
5060	serge	734	if (i915.mmio_debug)
		735	return;
		736
4560	Serge	737	if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
5060	serge	738	DRM_ERROR("Unclaimed register detected. Please use the i915.mmio_debug=1 to debug this problem.");
4104	Serge	739	__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
		740	}
		741	}
		742
4560	Serge	743	#define REG_READ_HEADER(x) \
4104	Serge	744	unsigned long irqflags; \
		745	u##x val = 0; \
5060	serge	746	assert_device_not_suspended(dev_priv); \
4560	Serge	747	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
		748
		749	#define REG_READ_FOOTER \
		750	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
		751	trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
		752	return val
		753
		754	#define __gen4_read(x) \
		755	static u##x \
		756	gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
		757	REG_READ_HEADER(x); \
		758	val = __raw_i915_read##x(dev_priv, reg); \
		759	REG_READ_FOOTER; \
		760	}
		761
		762	#define __gen5_read(x) \
		763	static u##x \
		764	gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
		765	REG_READ_HEADER(x); \
4104	Serge	766	ilk_dummy_write(dev_priv); \
4560	Serge	767	val = __raw_i915_read##x(dev_priv, reg); \
		768	REG_READ_FOOTER; \
		769	}
		770
		771	#define __gen6_read(x) \
		772	static u##x \
		773	gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
		774	REG_READ_HEADER(x); \
5060	serge	775	hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
		776	if (dev_priv->uncore.forcewake_count == 0 && \
		777	NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
4560	Serge	778	dev_priv->uncore.funcs.force_wake_get(dev_priv, \
		779	FORCEWAKE_ALL); \
4104	Serge	780	val = __raw_i915_read##x(dev_priv, reg); \
4560	Serge	781	dev_priv->uncore.funcs.force_wake_put(dev_priv, \
		782	FORCEWAKE_ALL); \
4104	Serge	783	} else { \
		784	val = __raw_i915_read##x(dev_priv, reg); \
		785	} \
5060	serge	786	hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
4560	Serge	787	REG_READ_FOOTER; \
4104	Serge	788	}
		789
4560	Serge	790	#define __vlv_read(x) \
		791	static u##x \
		792	vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
		793	unsigned fwengine = 0; \
		794	REG_READ_HEADER(x); \
		795	if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \
5060	serge	796	if (dev_priv->uncore.fw_rendercount == 0) \
4560	Serge	797	fwengine = FORCEWAKE_RENDER; \
5060	serge	798	} else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \
		799	if (dev_priv->uncore.fw_mediacount == 0) \
		800	fwengine = FORCEWAKE_MEDIA; \
4560	Serge	801	} \
5060	serge	802	if (fwengine) \
		803	dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
		804	val = __raw_i915_read##x(dev_priv, reg); \
		805	if (fwengine) \
		806	dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
		807	REG_READ_FOOTER; \
		808	}
		809
		810	#define __chv_read(x) \
		811	static u##x \
		812	chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
		813	unsigned fwengine = 0; \
		814	REG_READ_HEADER(x); \
		815	if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
		816	if (dev_priv->uncore.fw_rendercount == 0) \
		817	fwengine = FORCEWAKE_RENDER; \
		818	} else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
		819	if (dev_priv->uncore.fw_mediacount == 0) \
4560	Serge	820	fwengine = FORCEWAKE_MEDIA; \
5060	serge	821	} else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
		822	if (dev_priv->uncore.fw_rendercount == 0) \
		823	fwengine \|= FORCEWAKE_RENDER; \
		824	if (dev_priv->uncore.fw_mediacount == 0) \
		825	fwengine \|= FORCEWAKE_MEDIA; \
4560	Serge	826	} \
5060	serge	827	if (fwengine) \
		828	dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
4560	Serge	829	val = __raw_i915_read##x(dev_priv, reg); \
5060	serge	830	if (fwengine) \
		831	dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
4560	Serge	832	REG_READ_FOOTER; \
		833	}
4104	Serge	834
5354	serge	835	#define SKL_NEEDS_FORCE_WAKE(dev_priv, reg) \
		836	((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
		837
		838	#define __gen9_read(x) \
		839	static u##x \
		840	gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
		841	REG_READ_HEADER(x); \
		842	if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
		843	val = __raw_i915_read##x(dev_priv, reg); \
		844	} else { \
		845	unsigned fwengine = 0; \
		846	if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) { \
		847	if (dev_priv->uncore.fw_rendercount == 0) \
		848	fwengine = FORCEWAKE_RENDER; \
		849	} else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) { \
		850	if (dev_priv->uncore.fw_mediacount == 0) \
		851	fwengine = FORCEWAKE_MEDIA; \
		852	} else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) { \
		853	if (dev_priv->uncore.fw_rendercount == 0) \
		854	fwengine \|= FORCEWAKE_RENDER; \
		855	if (dev_priv->uncore.fw_mediacount == 0) \
		856	fwengine \|= FORCEWAKE_MEDIA; \
		857	} else { \
		858	if (dev_priv->uncore.fw_blittercount == 0) \
		859	fwengine = FORCEWAKE_BLITTER; \
		860	} \
		861	if (fwengine) \
		862	dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
		863	val = __raw_i915_read##x(dev_priv, reg); \
		864	if (fwengine) \
		865	dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
		866	} \
		867	REG_READ_FOOTER; \
		868	}
		869
		870	__gen9_read(8)
		871	__gen9_read(16)
		872	__gen9_read(32)
		873	__gen9_read(64)
5060	serge	874	__chv_read(8)
		875	__chv_read(16)
		876	__chv_read(32)
		877	__chv_read(64)
4560	Serge	878	__vlv_read(8)
		879	__vlv_read(16)
		880	__vlv_read(32)
		881	__vlv_read(64)
		882	__gen6_read(8)
		883	__gen6_read(16)
		884	__gen6_read(32)
		885	__gen6_read(64)
		886	__gen5_read(8)
		887	__gen5_read(16)
		888	__gen5_read(32)
		889	__gen5_read(64)
		890	__gen4_read(8)
		891	__gen4_read(16)
		892	__gen4_read(32)
		893	__gen4_read(64)
		894
5354	serge	895	#undef __gen9_read
5060	serge	896	#undef __chv_read
4560	Serge	897	#undef __vlv_read
		898	#undef __gen6_read
		899	#undef __gen5_read
		900	#undef __gen4_read
		901	#undef REG_READ_FOOTER
		902	#undef REG_READ_HEADER
		903
		904	#define REG_WRITE_HEADER \
4104	Serge	905	unsigned long irqflags; \
4560	Serge	906	trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
5060	serge	907	assert_device_not_suspended(dev_priv); \
4560	Serge	908	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
		909
		910	#define REG_WRITE_FOOTER \
		911	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
		912
		913	#define __gen4_write(x) \
		914	static void \
		915	gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
		916	REG_WRITE_HEADER; \
		917	__raw_i915_write##x(dev_priv, reg, val); \
		918	REG_WRITE_FOOTER; \
		919	}
		920
		921	#define __gen5_write(x) \
		922	static void \
		923	gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
		924	REG_WRITE_HEADER; \
		925	ilk_dummy_write(dev_priv); \
		926	__raw_i915_write##x(dev_priv, reg, val); \
		927	REG_WRITE_FOOTER; \
		928	}
		929
		930	#define __gen6_write(x) \
		931	static void \
		932	gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
4104	Serge	933	u32 __fifo_ret = 0; \
4560	Serge	934	REG_WRITE_HEADER; \
4104	Serge	935	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
		936	__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
		937	} \
4560	Serge	938	__raw_i915_write##x(dev_priv, reg, val); \
		939	if (unlikely(__fifo_ret)) { \
		940	gen6_gt_check_fifodbg(dev_priv); \
		941	} \
		942	REG_WRITE_FOOTER; \
		943	}
		944
		945	#define __hsw_write(x) \
		946	static void \
		947	hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
		948	u32 __fifo_ret = 0; \
		949	REG_WRITE_HEADER; \
		950	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
		951	__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
		952	} \
5060	serge	953	hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
4104	Serge	954	__raw_i915_write##x(dev_priv, reg, val); \
		955	if (unlikely(__fifo_ret)) { \
		956	gen6_gt_check_fifodbg(dev_priv); \
		957	} \
5060	serge	958	hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
		959	hsw_unclaimed_reg_detect(dev_priv); \
4560	Serge	960	REG_WRITE_FOOTER; \
4104	Serge	961	}
		962
4560	Serge	963	static const u32 gen8_shadowed_regs[] = {
		964	FORCEWAKE_MT,
		965	GEN6_RPNSWREQ,
		966	GEN6_RC_VIDEO_FREQ,
		967	RING_TAIL(RENDER_RING_BASE),
		968	RING_TAIL(GEN6_BSD_RING_BASE),
		969	RING_TAIL(VEBOX_RING_BASE),
		970	RING_TAIL(BLT_RING_BASE),
		971	/* TODO: Other registers are not yet used */
		972	};
		973
		974	static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
		975	{
		976	int i;
		977	for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
		978	if (reg == gen8_shadowed_regs[i])
		979	return true;
		980
		981	return false;
		982	}
		983
		984	#define __gen8_write(x) \
		985	static void \
		986	gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
		987	REG_WRITE_HEADER; \
5060	serge	988	hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
		989	if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \
		990	if (dev_priv->uncore.forcewake_count == 0) \
4560	Serge	991	dev_priv->uncore.funcs.force_wake_get(dev_priv, \
		992	FORCEWAKE_ALL); \
		993	__raw_i915_write##x(dev_priv, reg, val); \
5060	serge	994	if (dev_priv->uncore.forcewake_count == 0) \
4560	Serge	995	dev_priv->uncore.funcs.force_wake_put(dev_priv, \
		996	FORCEWAKE_ALL); \
5060	serge	997	} else { \
		998	__raw_i915_write##x(dev_priv, reg, val); \
4560	Serge	999	} \
5060	serge	1000	hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
		1001	hsw_unclaimed_reg_detect(dev_priv); \
4560	Serge	1002	REG_WRITE_FOOTER; \
		1003	}
		1004
5060	serge	1005	#define __chv_write(x) \
		1006	static void \
		1007	chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
		1008	unsigned fwengine = 0; \
		1009	bool shadowed = is_gen8_shadowed(dev_priv, reg); \
		1010	REG_WRITE_HEADER; \
		1011	if (!shadowed) { \
		1012	if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
		1013	if (dev_priv->uncore.fw_rendercount == 0) \
		1014	fwengine = FORCEWAKE_RENDER; \
		1015	} else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
		1016	if (dev_priv->uncore.fw_mediacount == 0) \
		1017	fwengine = FORCEWAKE_MEDIA; \
		1018	} else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
		1019	if (dev_priv->uncore.fw_rendercount == 0) \
		1020	fwengine \|= FORCEWAKE_RENDER; \
		1021	if (dev_priv->uncore.fw_mediacount == 0) \
		1022	fwengine \|= FORCEWAKE_MEDIA; \
		1023	} \
		1024	} \
		1025	if (fwengine) \
		1026	dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
		1027	__raw_i915_write##x(dev_priv, reg, val); \
		1028	if (fwengine) \
		1029	dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
		1030	REG_WRITE_FOOTER; \
		1031	}
		1032
5354	serge	1033	static const u32 gen9_shadowed_regs[] = {
		1034	RING_TAIL(RENDER_RING_BASE),
		1035	RING_TAIL(GEN6_BSD_RING_BASE),
		1036	RING_TAIL(VEBOX_RING_BASE),
		1037	RING_TAIL(BLT_RING_BASE),
		1038	FORCEWAKE_BLITTER_GEN9,
		1039	FORCEWAKE_RENDER_GEN9,
		1040	FORCEWAKE_MEDIA_GEN9,
		1041	GEN6_RPNSWREQ,
		1042	GEN6_RC_VIDEO_FREQ,
		1043	/* TODO: Other registers are not yet used */
		1044	};
		1045
		1046	static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg)
		1047	{
		1048	int i;
		1049	for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
		1050	if (reg == gen9_shadowed_regs[i])
		1051	return true;
		1052
		1053	return false;
		1054	}
		1055
		1056	#define __gen9_write(x) \
		1057	static void \
		1058	gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
		1059	bool trace) { \
		1060	REG_WRITE_HEADER; \
		1061	if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) \|\| \
		1062	is_gen9_shadowed(dev_priv, reg)) { \
		1063	__raw_i915_write##x(dev_priv, reg, val); \
		1064	} else { \
		1065	unsigned fwengine = 0; \
		1066	if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) { \
		1067	if (dev_priv->uncore.fw_rendercount == 0) \
		1068	fwengine = FORCEWAKE_RENDER; \
		1069	} else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) { \
		1070	if (dev_priv->uncore.fw_mediacount == 0) \
		1071	fwengine = FORCEWAKE_MEDIA; \
		1072	} else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) { \
		1073	if (dev_priv->uncore.fw_rendercount == 0) \
		1074	fwengine \|= FORCEWAKE_RENDER; \
		1075	if (dev_priv->uncore.fw_mediacount == 0) \
		1076	fwengine \|= FORCEWAKE_MEDIA; \
		1077	} else { \
		1078	if (dev_priv->uncore.fw_blittercount == 0) \
		1079	fwengine = FORCEWAKE_BLITTER; \
		1080	} \
		1081	if (fwengine) \
		1082	dev_priv->uncore.funcs.force_wake_get(dev_priv, \
		1083	fwengine); \
		1084	__raw_i915_write##x(dev_priv, reg, val); \
		1085	if (fwengine) \
		1086	dev_priv->uncore.funcs.force_wake_put(dev_priv, \
		1087	fwengine); \
		1088	} \
		1089	REG_WRITE_FOOTER; \
		1090	}
		1091
		1092	__gen9_write(8)
		1093	__gen9_write(16)
		1094	__gen9_write(32)
		1095	__gen9_write(64)
5060	serge	1096	__chv_write(8)
		1097	__chv_write(16)
		1098	__chv_write(32)
		1099	__chv_write(64)
4560	Serge	1100	__gen8_write(8)
		1101	__gen8_write(16)
		1102	__gen8_write(32)
		1103	__gen8_write(64)
		1104	__hsw_write(8)
		1105	__hsw_write(16)
		1106	__hsw_write(32)
		1107	__hsw_write(64)
		1108	__gen6_write(8)
		1109	__gen6_write(16)
		1110	__gen6_write(32)
		1111	__gen6_write(64)
		1112	__gen5_write(8)
		1113	__gen5_write(16)
		1114	__gen5_write(32)
		1115	__gen5_write(64)
		1116	__gen4_write(8)
		1117	__gen4_write(16)
		1118	__gen4_write(32)
		1119	__gen4_write(64)
		1120
5354	serge	1121	#undef __gen9_write
5060	serge	1122	#undef __chv_write
4560	Serge	1123	#undef __gen8_write
		1124	#undef __hsw_write
		1125	#undef __gen6_write
		1126	#undef __gen5_write
		1127	#undef __gen4_write
		1128	#undef REG_WRITE_FOOTER
		1129	#undef REG_WRITE_HEADER
		1130
5354	serge	1131	#define ASSIGN_WRITE_MMIO_VFUNCS(x) \
		1132	do { \
		1133	dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
		1134	dev_priv->uncore.funcs.mmio_writew = x##_write16; \
		1135	dev_priv->uncore.funcs.mmio_writel = x##_write32; \
		1136	dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
		1137	} while (0)
		1138
		1139	#define ASSIGN_READ_MMIO_VFUNCS(x) \
		1140	do { \
		1141	dev_priv->uncore.funcs.mmio_readb = x##_read8; \
		1142	dev_priv->uncore.funcs.mmio_readw = x##_read16; \
		1143	dev_priv->uncore.funcs.mmio_readl = x##_read32; \
		1144	dev_priv->uncore.funcs.mmio_readq = x##_read64; \
		1145	} while (0)
		1146
4560	Serge	1147	void intel_uncore_init(struct drm_device *dev)
		1148	{
		1149	struct drm_i915_private *dev_priv = dev->dev_private;
		1150
5060	serge	1151	setup_timer(&dev_priv->uncore.force_wake_timer,
		1152	gen6_force_wake_timer, (unsigned long)dev_priv);
4560	Serge	1153
5354	serge	1154	__intel_uncore_early_sanitize(dev, false);
5060	serge	1155
5354	serge	1156	if (IS_GEN9(dev)) {
		1157	dev_priv->uncore.funcs.force_wake_get = __gen9_force_wake_get;
		1158	dev_priv->uncore.funcs.force_wake_put = __gen9_force_wake_put;
		1159	} else if (IS_VALLEYVIEW(dev)) {
4560	Serge	1160	dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get;
		1161	dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put;
5354	serge	1162	} else if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev)) {
5060	serge	1163	dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get;
		1164	dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put;
4560	Serge	1165	} else if (IS_IVYBRIDGE(dev)) {
		1166	u32 ecobus;
		1167
		1168	/* IVB configs may use multi-threaded forcewake */
		1169
		1170	/* A small trick here - if the bios hasn't configured
		1171	* MT forcewake, and if the device is in RC6, then
		1172	* force_wake_mt_get will not wake the device and the
		1173	* ECOBUS read will return zero. Which will be
		1174	* (correctly) interpreted by the test below as MT
		1175	* forcewake being disabled.
		1176	*/
		1177	mutex_lock(&dev->struct_mutex);
5060	serge	1178	__gen7_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL);
4560	Serge	1179	ecobus = __raw_i915_read32(dev_priv, ECOBUS);
5060	serge	1180	__gen7_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL);
4560	Serge	1181	mutex_unlock(&dev->struct_mutex);
		1182
		1183	if (ecobus & FORCEWAKE_MT_ENABLE) {
		1184	dev_priv->uncore.funcs.force_wake_get =
5060	serge	1185	__gen7_gt_force_wake_mt_get;
4560	Serge	1186	dev_priv->uncore.funcs.force_wake_put =
5060	serge	1187	__gen7_gt_force_wake_mt_put;
4560	Serge	1188	} else {
		1189	DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
		1190	DRM_INFO("when using vblank-synced partial screen updates.\n");
		1191	dev_priv->uncore.funcs.force_wake_get =
		1192	__gen6_gt_force_wake_get;
		1193	dev_priv->uncore.funcs.force_wake_put =
		1194	__gen6_gt_force_wake_put;
		1195	}
		1196	} else if (IS_GEN6(dev)) {
		1197	dev_priv->uncore.funcs.force_wake_get =
		1198	__gen6_gt_force_wake_get;
		1199	dev_priv->uncore.funcs.force_wake_put =
		1200	__gen6_gt_force_wake_put;
		1201	}
		1202
		1203	switch (INTEL_INFO(dev)->gen) {
		1204	default:
5354	serge	1205	WARN_ON(1);
		1206	return;
		1207	case 9:
		1208	ASSIGN_WRITE_MMIO_VFUNCS(gen9);
		1209	ASSIGN_READ_MMIO_VFUNCS(gen9);
		1210	break;
		1211	case 8:
5060	serge	1212	if (IS_CHERRYVIEW(dev)) {
5354	serge	1213	ASSIGN_WRITE_MMIO_VFUNCS(chv);
		1214	ASSIGN_READ_MMIO_VFUNCS(chv);
5060	serge	1215
		1216	} else {
5354	serge	1217	ASSIGN_WRITE_MMIO_VFUNCS(gen8);
		1218	ASSIGN_READ_MMIO_VFUNCS(gen6);
5060	serge	1219	}
4560	Serge	1220	break;
		1221	case 7:
		1222	case 6:
		1223	if (IS_HASWELL(dev)) {
5354	serge	1224	ASSIGN_WRITE_MMIO_VFUNCS(hsw);
4560	Serge	1225	} else {
5354	serge	1226	ASSIGN_WRITE_MMIO_VFUNCS(gen6);
4560	Serge	1227	}
		1228
		1229	if (IS_VALLEYVIEW(dev)) {
5354	serge	1230	ASSIGN_READ_MMIO_VFUNCS(vlv);
4560	Serge	1231	} else {
5354	serge	1232	ASSIGN_READ_MMIO_VFUNCS(gen6);
4560	Serge	1233	}
		1234	break;
		1235	case 5:
5354	serge	1236	ASSIGN_WRITE_MMIO_VFUNCS(gen5);
		1237	ASSIGN_READ_MMIO_VFUNCS(gen5);
4560	Serge	1238	break;
		1239	case 4:
		1240	case 3:
		1241	case 2:
5354	serge	1242	ASSIGN_WRITE_MMIO_VFUNCS(gen4);
		1243	ASSIGN_READ_MMIO_VFUNCS(gen4);
4560	Serge	1244	break;
		1245	}
5354	serge	1246
		1247	i915_check_and_clear_faults(dev);
4560	Serge	1248	}
5354	serge	1249	#undef ASSIGN_WRITE_MMIO_VFUNCS
		1250	#undef ASSIGN_READ_MMIO_VFUNCS
4560	Serge	1251
		1252	void intel_uncore_fini(struct drm_device *dev)
		1253	{
		1254	/* Paranoia: make sure we have disabled everything before we exit. */
		1255	intel_uncore_sanitize(dev);
5060	serge	1256	intel_uncore_forcewake_reset(dev, false);
4560	Serge	1257	}
		1258
5060	serge	1259	#define GEN_RANGE(l, h) GENMASK(h, l)
		1260
4104	Serge	1261	static const struct register_whitelist {
		1262	uint64_t offset;
		1263	uint32_t size;
5060	serge	1264	/* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
		1265	uint32_t gen_bitmask;
4104	Serge	1266	} whitelist[] = {
5354	serge	1267	{ RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 9) },
4104	Serge	1268	};
		1269
		1270	int i915_reg_read_ioctl(struct drm_device *dev,
		1271	void data, struct drm_file file)
		1272	{
		1273	struct drm_i915_private *dev_priv = dev->dev_private;
		1274	struct drm_i915_reg_read *reg = data;
		1275	struct register_whitelist const *entry = whitelist;
5060	serge	1276	int i, ret = 0;
4104	Serge	1277
		1278	for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
		1279	if (entry->offset == reg->offset &&
		1280	(1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
		1281	break;
		1282	}
		1283
		1284	if (i == ARRAY_SIZE(whitelist))
		1285	return -EINVAL;
		1286
		1287	switch (entry->size) {
		1288	case 8:
		1289	reg->val = I915_READ64(reg->offset);
		1290	break;
		1291	case 4:
		1292	reg->val = I915_READ(reg->offset);
		1293	break;
		1294	case 2:
		1295	reg->val = I915_READ16(reg->offset);
		1296	break;
		1297	case 1:
		1298	reg->val = I915_READ8(reg->offset);
		1299	break;
		1300	default:
		1301	WARN_ON(1);
5060	serge	1302	ret = -EINVAL;
		1303	goto out;
4104	Serge	1304	}
		1305
5060	serge	1306	out:
		1307	return ret;
4104	Serge	1308	}
		1309
4560	Serge	1310	int i915_get_reset_stats_ioctl(struct drm_device *dev,
		1311	void data, struct drm_file file)
4104	Serge	1312	{
		1313	struct drm_i915_private *dev_priv = dev->dev_private;
4560	Serge	1314	struct drm_i915_reset_stats *args = data;
		1315	struct i915_ctx_hang_stats *hs;
5060	serge	1316	struct intel_context *ctx;
4560	Serge	1317	int ret;
4104	Serge	1318
4560	Serge	1319	if (args->flags \|\| args->pad)
		1320	return -EINVAL;
4104	Serge	1321
4560	Serge	1322	ret = mutex_lock_interruptible(&dev->struct_mutex);
		1323	if (ret)
		1324	return ret;
4104	Serge	1325
5060	serge	1326	ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
		1327	if (IS_ERR(ctx)) {
4560	Serge	1328	mutex_unlock(&dev->struct_mutex);
5060	serge	1329	return PTR_ERR(ctx);
4104	Serge	1330	}
5060	serge	1331	hs = &ctx->hang_stats;
4104	Serge	1332
4560	Serge	1333	args->reset_count = i915_reset_count(&dev_priv->gpu_error);
4104	Serge	1334
4560	Serge	1335	args->batch_active = hs->batch_active;
		1336	args->batch_pending = hs->batch_pending;
4104	Serge	1337
4560	Serge	1338	mutex_unlock(&dev->struct_mutex);
		1339
4104	Serge	1340	return 0;
		1341	}
		1342
5354	serge	1343	static int i915_reset_complete(struct drm_device *dev)
4104	Serge	1344	{
		1345	u8 gdrst;
5354	serge	1346	pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
		1347	return (gdrst & GRDOM_RESET_STATUS) == 0;
4104	Serge	1348	}
		1349
5354	serge	1350	static int i915_do_reset(struct drm_device *dev)
4104	Serge	1351	{
5354	serge	1352	/* assert reset for at least 20 usec */
		1353	pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
		1354	udelay(20);
		1355	pci_write_config_byte(dev->pdev, I915_GDRST, 0);
4104	Serge	1356
5354	serge	1357	return wait_for(i915_reset_complete(dev), 500);
		1358	}
5060	serge	1359
5354	serge	1360	static int g4x_reset_complete(struct drm_device *dev)
		1361	{
		1362	u8 gdrst;
		1363	pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
		1364	return (gdrst & GRDOM_RESET_ENABLE) == 0;
		1365	}
4104	Serge	1366
5354	serge	1367	static int g33_do_reset(struct drm_device *dev)
		1368	{
		1369	pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
		1370	return wait_for(g4x_reset_complete(dev), 500);
4104	Serge	1371	}
		1372
5060	serge	1373	static int g4x_do_reset(struct drm_device *dev)
		1374	{
		1375	struct drm_i915_private *dev_priv = dev->dev_private;
		1376	int ret;
		1377
5354	serge	1378	pci_write_config_byte(dev->pdev, I915_GDRST,
5060	serge	1379	GRDOM_RENDER \| GRDOM_RESET_ENABLE);
5354	serge	1380	ret = wait_for(g4x_reset_complete(dev), 500);
5060	serge	1381	if (ret)
		1382	return ret;
		1383
		1384	/* WaVcpClkGateDisableForMediaReset:ctg,elk */
		1385	I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) \| VCP_UNIT_CLOCK_GATE_DISABLE);
		1386	POSTING_READ(VDECCLK_GATE_D);
		1387
5354	serge	1388	pci_write_config_byte(dev->pdev, I915_GDRST,
5060	serge	1389	GRDOM_MEDIA \| GRDOM_RESET_ENABLE);
5354	serge	1390	ret = wait_for(g4x_reset_complete(dev), 500);
5060	serge	1391	if (ret)
		1392	return ret;
		1393
		1394	/* WaVcpClkGateDisableForMediaReset:ctg,elk */
		1395	I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
		1396	POSTING_READ(VDECCLK_GATE_D);
		1397
5354	serge	1398	pci_write_config_byte(dev->pdev, I915_GDRST, 0);
5060	serge	1399
		1400	return 0;
		1401	}
		1402
4104	Serge	1403	static int ironlake_do_reset(struct drm_device *dev)
		1404	{
		1405	struct drm_i915_private *dev_priv = dev->dev_private;
		1406	int ret;
		1407
		1408	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
5060	serge	1409	ILK_GRDOM_RENDER \| ILK_GRDOM_RESET_ENABLE);
		1410	ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
		1411	ILK_GRDOM_RESET_ENABLE) == 0, 500);
4104	Serge	1412	if (ret)
		1413	return ret;
		1414
		1415	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
5060	serge	1416	ILK_GRDOM_MEDIA \| ILK_GRDOM_RESET_ENABLE);
		1417	ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
		1418	ILK_GRDOM_RESET_ENABLE) == 0, 500);
		1419	if (ret)
		1420	return ret;
		1421
		1422	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0);
		1423
		1424	return 0;
4104	Serge	1425	}
		1426
		1427	static int gen6_do_reset(struct drm_device *dev)
		1428	{
		1429	struct drm_i915_private *dev_priv = dev->dev_private;
		1430	int ret;
		1431
		1432	/* Reset the chip */
		1433
		1434	/* GEN6_GDRST is not in the gt power well, no need to check
		1435	* for fifo space for the write or forcewake the chip for
		1436	* the read
		1437	*/
		1438	__raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
		1439
		1440	/* Spin waiting for the device to ack the reset request */
		1441	ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
		1442
5060	serge	1443	intel_uncore_forcewake_reset(dev, true);
4104	Serge	1444
		1445	return ret;
		1446	}
		1447
		1448	int intel_gpu_reset(struct drm_device *dev)
		1449	{
5060	serge	1450	if (INTEL_INFO(dev)->gen >= 6)
		1451	return gen6_do_reset(dev);
		1452	else if (IS_GEN5(dev))
		1453	return ironlake_do_reset(dev);
		1454	else if (IS_G4X(dev))
		1455	return g4x_do_reset(dev);
5354	serge	1456	else if (IS_G33(dev))
		1457	return g33_do_reset(dev);
		1458	else if (INTEL_INFO(dev)->gen >= 3)
		1459	return i915_do_reset(dev);
5060	serge	1460	else
		1461	return -ENODEV;
4104	Serge	1462	}
		1463
		1464	void intel_uncore_check_errors(struct drm_device *dev)
		1465	{
		1466	struct drm_i915_private *dev_priv = dev->dev_private;
		1467
		1468	if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
		1469	(__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
		1470	DRM_ERROR("Unclaimed register before interrupt\n");
		1471	__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
		1472	}
		1473	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_uncore.c – Rev 5354