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/*

 * Copyright © 2013 Intel Corporation

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice (including the next

 * paragraph) shall be included in all copies or substantial portions of the

 * Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS

 * IN THE SOFTWARE.

 */

#include "i915_drv.h"

#include "intel_drv.h"

#define FORCEWAKE_ACK_TIMEOUT_MS 2

#define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))

#define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))

#define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))

#define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))

#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))

#define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))

#define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))

#define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))

#define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)

static void

assert_device_not_suspended(struct drm_i915_private *dev_priv)

{

	WARN(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,

	     "Device suspended\n");

}

static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)

{

	u32 gt_thread_status_mask;

	if (IS_HASWELL(dev_priv->dev))

		gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;

	else

		gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;

	/* w/a for a sporadic read returning 0 by waiting for the GT

	 * thread to wake up.

	 */

	if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))

		DRM_ERROR("GT thread status wait timed out\n");

}

static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)

{

	__raw_i915_write32(dev_priv, FORCEWAKE, 0);

	/* something from same cacheline, but !FORCEWAKE */

	__raw_posting_read(dev_priv, ECOBUS);

}

static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,

							int fw_engine)

{

	if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0,

			    FORCEWAKE_ACK_TIMEOUT_MS))

		DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");

	__raw_i915_write32(dev_priv, FORCEWAKE, 1);

	/* something from same cacheline, but !FORCEWAKE */

	__raw_posting_read(dev_priv, ECOBUS);

	if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),

			    FORCEWAKE_ACK_TIMEOUT_MS))

		DRM_ERROR("Timed out waiting for forcewake to ack request.\n");

	/* WaRsForcewakeWaitTC0:snb */

	__gen6_gt_wait_for_thread_c0(dev_priv);

}

static void __gen7_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)

{

	__raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));

	/* something from same cacheline, but !FORCEWAKE_MT */

	__raw_posting_read(dev_priv, ECOBUS);

}

static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,

							int fw_engine)

{

	u32 forcewake_ack;

	if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev))

		forcewake_ack = FORCEWAKE_ACK_HSW;

	else

		forcewake_ack = FORCEWAKE_MT_ACK;

	if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0,

			    FORCEWAKE_ACK_TIMEOUT_MS))

		DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");

	__raw_i915_write32(dev_priv, FORCEWAKE_MT,

			   _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));

	/* something from same cacheline, but !FORCEWAKE_MT */

	__raw_posting_read(dev_priv, ECOBUS);

	if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL),

			    FORCEWAKE_ACK_TIMEOUT_MS))

		DRM_ERROR("Timed out waiting for forcewake to ack request.\n");

	/* WaRsForcewakeWaitTC0:ivb,hsw */

	if (INTEL_INFO(dev_priv->dev)->gen < 8)

	__gen6_gt_wait_for_thread_c0(dev_priv);

}

static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)

{

	u32 gtfifodbg;

	gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);

	if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))

		__raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);

}

static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,

							int fw_engine)

{

	__raw_i915_write32(dev_priv, FORCEWAKE, 0);

	/* something from same cacheline, but !FORCEWAKE */

	__raw_posting_read(dev_priv, ECOBUS);

	gen6_gt_check_fifodbg(dev_priv);

}

static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv,

							int fw_engine)

{

	__raw_i915_write32(dev_priv, FORCEWAKE_MT,

			   _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));

	/* something from same cacheline, but !FORCEWAKE_MT */

	__raw_posting_read(dev_priv, ECOBUS);

	if (IS_GEN7(dev_priv->dev))

	gen6_gt_check_fifodbg(dev_priv);

}

static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)

{

	int ret = 0;

	/* On VLV, FIFO will be shared by both SW and HW.

	 * So, we need to read the FREE_ENTRIES everytime */

	if (IS_VALLEYVIEW(dev_priv->dev))

		dev_priv->uncore.fifo_count =

			__raw_i915_read32(dev_priv, GTFIFOCTL) &

						GT_FIFO_FREE_ENTRIES_MASK;

	if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {

		int loop = 500;

		u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;

		while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {

			udelay(10);

			fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;

		}

		if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))

			++ret;

		dev_priv->uncore.fifo_count = fifo;

	}

	dev_priv->uncore.fifo_count--;

	return ret;

}

static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)

{

	__raw_i915_write32(dev_priv, FORCEWAKE_VLV,

			   _MASKED_BIT_DISABLE(0xffff));

	__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,

			   _MASKED_BIT_DISABLE(0xffff));

	/* something from same cacheline, but !FORCEWAKE_VLV */

	__raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);

}

static void __vlv_force_wake_get(struct drm_i915_private *dev_priv,

						int fw_engine)

{

	/* Check for Render Engine */

	if (FORCEWAKE_RENDER & fw_engine) {

		if (wait_for_atomic((__raw_i915_read32(dev_priv,

						FORCEWAKE_ACK_VLV) &

						FORCEWAKE_KERNEL) == 0,

			    FORCEWAKE_ACK_TIMEOUT_MS))

			DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");

	__raw_i915_write32(dev_priv, FORCEWAKE_VLV,

			   _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));

		if (wait_for_atomic((__raw_i915_read32(dev_priv,

						FORCEWAKE_ACK_VLV) &

						FORCEWAKE_KERNEL),

					FORCEWAKE_ACK_TIMEOUT_MS))

			DRM_ERROR("Timed out: waiting for Render to ack.\n");

	}

	/* Check for Media Engine */

	if (FORCEWAKE_MEDIA & fw_engine) {

		if (wait_for_atomic((__raw_i915_read32(dev_priv,

						FORCEWAKE_ACK_MEDIA_VLV) &

						FORCEWAKE_KERNEL) == 0,

					FORCEWAKE_ACK_TIMEOUT_MS))

			DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");

	__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,

			   _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));

		if (wait_for_atomic((__raw_i915_read32(dev_priv,

						FORCEWAKE_ACK_MEDIA_VLV) &