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2342 | Serge | 1 | /* |
2 | * Copyright © 2011 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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21 | * SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Jesse Barnes |
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25 | * |
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26 | * New plane/sprite handling. |
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27 | * |
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28 | * The older chips had a separate interface for programming plane related |
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29 | * registers; newer ones are much simpler and we can use the new DRM plane |
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30 | * support. |
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31 | */ |
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3031 | serge | 32 | #include |
33 | #include |
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34 | #include |
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2342 | Serge | 35 | #include "intel_drv.h" |
3031 | serge | 36 | #include |
2342 | Serge | 37 | #include "i915_drv.h" |
38 | |||
39 | static void |
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3746 | Serge | 40 | vlv_update_plane(struct drm_plane *dplane, struct drm_framebuffer *fb, |
41 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, |
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42 | unsigned int crtc_w, unsigned int crtc_h, |
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43 | uint32_t x, uint32_t y, |
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44 | uint32_t src_w, uint32_t src_h) |
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45 | { |
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46 | struct drm_device *dev = dplane->dev; |
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47 | struct drm_i915_private *dev_priv = dev->dev_private; |
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48 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
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49 | int pipe = intel_plane->pipe; |
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50 | int plane = intel_plane->plane; |
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51 | u32 sprctl; |
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52 | unsigned long sprsurf_offset, linear_offset; |
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53 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
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54 | |||
55 | sprctl = I915_READ(SPCNTR(pipe, plane)); |
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56 | |||
57 | /* Mask out pixel format bits in case we change it */ |
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58 | sprctl &= ~SP_PIXFORMAT_MASK; |
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59 | sprctl &= ~SP_YUV_BYTE_ORDER_MASK; |
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60 | sprctl &= ~SP_TILED; |
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61 | |||
62 | switch (fb->pixel_format) { |
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63 | case DRM_FORMAT_YUYV: |
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64 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; |
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65 | break; |
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66 | case DRM_FORMAT_YVYU: |
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67 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; |
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68 | break; |
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69 | case DRM_FORMAT_UYVY: |
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70 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; |
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71 | break; |
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72 | case DRM_FORMAT_VYUY: |
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73 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; |
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74 | break; |
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75 | case DRM_FORMAT_RGB565: |
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76 | sprctl |= SP_FORMAT_BGR565; |
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77 | break; |
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78 | case DRM_FORMAT_XRGB8888: |
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79 | sprctl |= SP_FORMAT_BGRX8888; |
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80 | break; |
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81 | case DRM_FORMAT_ARGB8888: |
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82 | sprctl |= SP_FORMAT_BGRA8888; |
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83 | break; |
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84 | case DRM_FORMAT_XBGR2101010: |
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85 | sprctl |= SP_FORMAT_RGBX1010102; |
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86 | break; |
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87 | case DRM_FORMAT_ABGR2101010: |
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88 | sprctl |= SP_FORMAT_RGBA1010102; |
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89 | break; |
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90 | case DRM_FORMAT_XBGR8888: |
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91 | sprctl |= SP_FORMAT_RGBX8888; |
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92 | break; |
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93 | case DRM_FORMAT_ABGR8888: |
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94 | sprctl |= SP_FORMAT_RGBA8888; |
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95 | break; |
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96 | default: |
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97 | /* |
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98 | * If we get here one of the upper layers failed to filter |
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99 | * out the unsupported plane formats |
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100 | */ |
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101 | BUG(); |
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102 | break; |
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103 | } |
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104 | |||
105 | if (obj->tiling_mode != I915_TILING_NONE) |
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106 | sprctl |= SP_TILED; |
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107 | |||
108 | sprctl |= SP_ENABLE; |
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109 | |||
110 | /* Sizes are 0 based */ |
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111 | src_w--; |
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112 | src_h--; |
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113 | crtc_w--; |
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114 | crtc_h--; |
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115 | |||
116 | intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size); |
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117 | |||
118 | I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); |
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119 | I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); |
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120 | |||
121 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
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122 | sprsurf_offset = intel_gen4_compute_page_offset(&x, &y, |
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123 | obj->tiling_mode, |
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124 | pixel_size, |
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125 | fb->pitches[0]); |
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126 | linear_offset -= sprsurf_offset; |
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127 | |||
128 | if (obj->tiling_mode != I915_TILING_NONE) |
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129 | I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x); |
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130 | else |
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131 | I915_WRITE(SPLINOFF(pipe, plane), linear_offset); |
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132 | |||
133 | I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); |
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134 | I915_WRITE(SPCNTR(pipe, plane), sprctl); |
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135 | I915_MODIFY_DISPBASE(SPSURF(pipe, plane), obj->gtt_offset + |
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136 | sprsurf_offset); |
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137 | POSTING_READ(SPSURF(pipe, plane)); |
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138 | } |
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139 | |||
140 | static void |
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141 | vlv_disable_plane(struct drm_plane *dplane) |
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142 | { |
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143 | struct drm_device *dev = dplane->dev; |
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144 | struct drm_i915_private *dev_priv = dev->dev_private; |
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145 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
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146 | int pipe = intel_plane->pipe; |
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147 | int plane = intel_plane->plane; |
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148 | |||
149 | I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) & |
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150 | ~SP_ENABLE); |
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151 | /* Activate double buffered register update */ |
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152 | I915_MODIFY_DISPBASE(SPSURF(pipe, plane), 0); |
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153 | POSTING_READ(SPSURF(pipe, plane)); |
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154 | } |
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155 | |||
156 | static int |
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157 | vlv_update_colorkey(struct drm_plane *dplane, |
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158 | struct drm_intel_sprite_colorkey *key) |
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159 | { |
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160 | struct drm_device *dev = dplane->dev; |
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161 | struct drm_i915_private *dev_priv = dev->dev_private; |
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162 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
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163 | int pipe = intel_plane->pipe; |
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164 | int plane = intel_plane->plane; |
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165 | u32 sprctl; |
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166 | |||
167 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
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168 | return -EINVAL; |
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169 | |||
170 | I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value); |
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171 | I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value); |
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172 | I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask); |
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173 | |||
174 | sprctl = I915_READ(SPCNTR(pipe, plane)); |
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175 | sprctl &= ~SP_SOURCE_KEY; |
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176 | if (key->flags & I915_SET_COLORKEY_SOURCE) |
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177 | sprctl |= SP_SOURCE_KEY; |
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178 | I915_WRITE(SPCNTR(pipe, plane), sprctl); |
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179 | |||
180 | POSTING_READ(SPKEYMSK(pipe, plane)); |
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181 | |||
182 | return 0; |
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183 | } |
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184 | |||
185 | static void |
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186 | vlv_get_colorkey(struct drm_plane *dplane, |
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187 | struct drm_intel_sprite_colorkey *key) |
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188 | { |
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189 | struct drm_device *dev = dplane->dev; |
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190 | struct drm_i915_private *dev_priv = dev->dev_private; |
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191 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
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192 | int pipe = intel_plane->pipe; |
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193 | int plane = intel_plane->plane; |
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194 | u32 sprctl; |
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195 | |||
196 | key->min_value = I915_READ(SPKEYMINVAL(pipe, plane)); |
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197 | key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane)); |
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198 | key->channel_mask = I915_READ(SPKEYMSK(pipe, plane)); |
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199 | |||
200 | sprctl = I915_READ(SPCNTR(pipe, plane)); |
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201 | if (sprctl & SP_SOURCE_KEY) |
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202 | key->flags = I915_SET_COLORKEY_SOURCE; |
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203 | else |
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204 | key->flags = I915_SET_COLORKEY_NONE; |
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205 | } |
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206 | |||
207 | static void |
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2342 | Serge | 208 | ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, |
209 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, |
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210 | unsigned int crtc_w, unsigned int crtc_h, |
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211 | uint32_t x, uint32_t y, |
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212 | uint32_t src_w, uint32_t src_h) |
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213 | { |
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214 | struct drm_device *dev = plane->dev; |
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215 | struct drm_i915_private *dev_priv = dev->dev_private; |
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216 | struct intel_plane *intel_plane = to_intel_plane(plane); |
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217 | int pipe = intel_plane->pipe; |
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218 | u32 sprctl, sprscale = 0; |
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3243 | Serge | 219 | unsigned long sprsurf_offset, linear_offset; |
220 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
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3480 | Serge | 221 | bool scaling_was_enabled = dev_priv->sprite_scaling_enabled; |
2342 | Serge | 222 | |
223 | sprctl = I915_READ(SPRCTL(pipe)); |
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224 | |||
225 | /* Mask out pixel format bits in case we change it */ |
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226 | sprctl &= ~SPRITE_PIXFORMAT_MASK; |
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227 | sprctl &= ~SPRITE_RGB_ORDER_RGBX; |
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228 | sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK; |
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3031 | serge | 229 | sprctl &= ~SPRITE_TILED; |
2342 | Serge | 230 | |
231 | switch (fb->pixel_format) { |
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232 | case DRM_FORMAT_XBGR8888: |
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3031 | serge | 233 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; |
2342 | Serge | 234 | break; |
235 | case DRM_FORMAT_XRGB8888: |
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3031 | serge | 236 | sprctl |= SPRITE_FORMAT_RGBX888; |
2342 | Serge | 237 | break; |
238 | case DRM_FORMAT_YUYV: |
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239 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; |
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240 | break; |
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241 | case DRM_FORMAT_YVYU: |
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242 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; |
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243 | break; |
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244 | case DRM_FORMAT_UYVY: |
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245 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; |
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246 | break; |
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247 | case DRM_FORMAT_VYUY: |
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248 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; |
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249 | break; |
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250 | default: |
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3243 | Serge | 251 | BUG(); |
2342 | Serge | 252 | } |
253 | |||
254 | if (obj->tiling_mode != I915_TILING_NONE) |
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255 | sprctl |= SPRITE_TILED; |
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256 | |||
257 | /* must disable */ |
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258 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; |
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259 | sprctl |= SPRITE_ENABLE; |
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260 | |||
3480 | Serge | 261 | if (IS_HASWELL(dev)) |
262 | sprctl |= SPRITE_PIPE_CSC_ENABLE; |
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263 | |||
2342 | Serge | 264 | /* Sizes are 0 based */ |
265 | src_w--; |
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266 | src_h--; |
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267 | crtc_w--; |
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268 | crtc_h--; |
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269 | |||
270 | intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size); |
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271 | |||
272 | /* |
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273 | * IVB workaround: must disable low power watermarks for at least |
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274 | * one frame before enabling scaling. LP watermarks can be re-enabled |
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275 | * when scaling is disabled. |
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276 | */ |
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277 | if (crtc_w != src_w || crtc_h != src_h) { |
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3480 | Serge | 278 | dev_priv->sprite_scaling_enabled |= 1 << pipe; |
279 | |||
280 | if (!scaling_was_enabled) { |
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3031 | serge | 281 | intel_update_watermarks(dev); |
2342 | Serge | 282 | intel_wait_for_vblank(dev, pipe); |
3031 | serge | 283 | } |
2342 | Serge | 284 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; |
3480 | Serge | 285 | } else |
286 | dev_priv->sprite_scaling_enabled &= ~(1 << pipe); |
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2342 | Serge | 287 | |
288 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); |
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289 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); |
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3243 | Serge | 290 | |
291 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
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292 | sprsurf_offset = |
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3480 | Serge | 293 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
3243 | Serge | 294 | pixel_size, fb->pitches[0]); |
295 | linear_offset -= sprsurf_offset; |
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296 | |||
297 | /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET |
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298 | * register */ |
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299 | if (IS_HASWELL(dev)) |
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300 | I915_WRITE(SPROFFSET(pipe), (y << 16) | x); |
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301 | else if (obj->tiling_mode != I915_TILING_NONE) |
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2342 | Serge | 302 | I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); |
3243 | Serge | 303 | else |
304 | I915_WRITE(SPRLINOFF(pipe), linear_offset); |
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2342 | Serge | 305 | |
306 | I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); |
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3243 | Serge | 307 | if (intel_plane->can_scale) |
2342 | Serge | 308 | I915_WRITE(SPRSCALE(pipe), sprscale); |
309 | I915_WRITE(SPRCTL(pipe), sprctl); |
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3243 | Serge | 310 | I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset + sprsurf_offset); |
2342 | Serge | 311 | POSTING_READ(SPRSURF(pipe)); |
3480 | Serge | 312 | |
313 | /* potentially re-enable LP watermarks */ |
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314 | if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled) |
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315 | intel_update_watermarks(dev); |
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2342 | Serge | 316 | } |
317 | |||
318 | static void |
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319 | ivb_disable_plane(struct drm_plane *plane) |
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320 | { |
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321 | struct drm_device *dev = plane->dev; |
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322 | struct drm_i915_private *dev_priv = dev->dev_private; |
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323 | struct intel_plane *intel_plane = to_intel_plane(plane); |
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324 | int pipe = intel_plane->pipe; |
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3480 | Serge | 325 | bool scaling_was_enabled = dev_priv->sprite_scaling_enabled; |
2342 | Serge | 326 | |
327 | I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); |
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328 | /* Can't leave the scaler enabled... */ |
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3243 | Serge | 329 | if (intel_plane->can_scale) |
2342 | Serge | 330 | I915_WRITE(SPRSCALE(pipe), 0); |
331 | /* Activate double buffered register update */ |
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3031 | serge | 332 | I915_MODIFY_DISPBASE(SPRSURF(pipe), 0); |
2342 | Serge | 333 | POSTING_READ(SPRSURF(pipe)); |
3031 | serge | 334 | |
3480 | Serge | 335 | dev_priv->sprite_scaling_enabled &= ~(1 << pipe); |
336 | |||
337 | /* potentially re-enable LP watermarks */ |
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338 | if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled) |
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3031 | serge | 339 | intel_update_watermarks(dev); |
2342 | Serge | 340 | } |
341 | |||
342 | static int |
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343 | ivb_update_colorkey(struct drm_plane *plane, |
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344 | struct drm_intel_sprite_colorkey *key) |
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345 | { |
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346 | struct drm_device *dev = plane->dev; |
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347 | struct drm_i915_private *dev_priv = dev->dev_private; |
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348 | struct intel_plane *intel_plane; |
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349 | u32 sprctl; |
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350 | int ret = 0; |
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351 | |||
352 | intel_plane = to_intel_plane(plane); |
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353 | |||
354 | I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value); |
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355 | I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value); |
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356 | I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask); |
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357 | |||
358 | sprctl = I915_READ(SPRCTL(intel_plane->pipe)); |
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359 | sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY); |
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360 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
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361 | sprctl |= SPRITE_DEST_KEY; |
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362 | else if (key->flags & I915_SET_COLORKEY_SOURCE) |
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363 | sprctl |= SPRITE_SOURCE_KEY; |
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364 | I915_WRITE(SPRCTL(intel_plane->pipe), sprctl); |
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365 | |||
366 | POSTING_READ(SPRKEYMSK(intel_plane->pipe)); |
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367 | |||
368 | return ret; |
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369 | } |
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370 | |||
371 | static void |
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372 | ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key) |
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373 | { |
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374 | struct drm_device *dev = plane->dev; |
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375 | struct drm_i915_private *dev_priv = dev->dev_private; |
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376 | struct intel_plane *intel_plane; |
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377 | u32 sprctl; |
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378 | |||
379 | intel_plane = to_intel_plane(plane); |
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380 | |||
381 | key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe)); |
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382 | key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe)); |
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383 | key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe)); |
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384 | key->flags = 0; |
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385 | |||
386 | sprctl = I915_READ(SPRCTL(intel_plane->pipe)); |
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387 | |||
388 | if (sprctl & SPRITE_DEST_KEY) |
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389 | key->flags = I915_SET_COLORKEY_DESTINATION; |
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390 | else if (sprctl & SPRITE_SOURCE_KEY) |
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391 | key->flags = I915_SET_COLORKEY_SOURCE; |
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392 | else |
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393 | key->flags = I915_SET_COLORKEY_NONE; |
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394 | } |
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395 | |||
396 | static void |
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3031 | serge | 397 | ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, |
2342 | Serge | 398 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, |
399 | unsigned int crtc_w, unsigned int crtc_h, |
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400 | uint32_t x, uint32_t y, |
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401 | uint32_t src_w, uint32_t src_h) |
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402 | { |
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403 | struct drm_device *dev = plane->dev; |
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404 | struct drm_i915_private *dev_priv = dev->dev_private; |
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405 | struct intel_plane *intel_plane = to_intel_plane(plane); |
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3243 | Serge | 406 | int pipe = intel_plane->pipe; |
407 | unsigned long dvssurf_offset, linear_offset; |
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3031 | serge | 408 | u32 dvscntr, dvsscale; |
3243 | Serge | 409 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
2342 | Serge | 410 | |
411 | dvscntr = I915_READ(DVSCNTR(pipe)); |
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412 | |||
413 | /* Mask out pixel format bits in case we change it */ |
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414 | dvscntr &= ~DVS_PIXFORMAT_MASK; |
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3031 | serge | 415 | dvscntr &= ~DVS_RGB_ORDER_XBGR; |
2342 | Serge | 416 | dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK; |
3031 | serge | 417 | dvscntr &= ~DVS_TILED; |
2342 | Serge | 418 | |
419 | switch (fb->pixel_format) { |
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420 | case DRM_FORMAT_XBGR8888: |
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3031 | serge | 421 | dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; |
2342 | Serge | 422 | break; |
423 | case DRM_FORMAT_XRGB8888: |
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3031 | serge | 424 | dvscntr |= DVS_FORMAT_RGBX888; |
2342 | Serge | 425 | break; |
426 | case DRM_FORMAT_YUYV: |
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427 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; |
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428 | break; |
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429 | case DRM_FORMAT_YVYU: |
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430 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; |
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431 | break; |
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432 | case DRM_FORMAT_UYVY: |
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433 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; |
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434 | break; |
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435 | case DRM_FORMAT_VYUY: |
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436 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; |
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437 | break; |
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438 | default: |
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3243 | Serge | 439 | BUG(); |
2342 | Serge | 440 | } |
441 | |||
442 | if (obj->tiling_mode != I915_TILING_NONE) |
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443 | dvscntr |= DVS_TILED; |
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444 | |||
3031 | serge | 445 | if (IS_GEN6(dev)) |
446 | dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ |
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2342 | Serge | 447 | dvscntr |= DVS_ENABLE; |
448 | |||
449 | /* Sizes are 0 based */ |
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450 | src_w--; |
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451 | src_h--; |
||
452 | crtc_w--; |
||
453 | crtc_h--; |
||
454 | |||
455 | intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size); |
||
456 | |||
3031 | serge | 457 | dvsscale = 0; |
458 | if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h) |
||
2342 | Serge | 459 | dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; |
460 | |||
461 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); |
||
462 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); |
||
3243 | Serge | 463 | |
464 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
||
465 | dvssurf_offset = |
||
3480 | Serge | 466 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
3243 | Serge | 467 | pixel_size, fb->pitches[0]); |
468 | linear_offset -= dvssurf_offset; |
||
469 | |||
470 | if (obj->tiling_mode != I915_TILING_NONE) |
||
2342 | Serge | 471 | I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); |
3243 | Serge | 472 | else |
473 | I915_WRITE(DVSLINOFF(pipe), linear_offset); |
||
2342 | Serge | 474 | |
475 | I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); |
||
476 | I915_WRITE(DVSSCALE(pipe), dvsscale); |
||
477 | I915_WRITE(DVSCNTR(pipe), dvscntr); |
||
3243 | Serge | 478 | I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset + dvssurf_offset); |
2342 | Serge | 479 | POSTING_READ(DVSSURF(pipe)); |
480 | } |
||
481 | |||
482 | static void |
||
3031 | serge | 483 | ilk_disable_plane(struct drm_plane *plane) |
2342 | Serge | 484 | { |
485 | struct drm_device *dev = plane->dev; |
||
486 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
487 | struct intel_plane *intel_plane = to_intel_plane(plane); |
||
488 | int pipe = intel_plane->pipe; |
||
489 | |||
490 | I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE); |
||
491 | /* Disable the scaler */ |
||
492 | I915_WRITE(DVSSCALE(pipe), 0); |
||
493 | /* Flush double buffered register updates */ |
||
3031 | serge | 494 | I915_MODIFY_DISPBASE(DVSSURF(pipe), 0); |
2342 | Serge | 495 | POSTING_READ(DVSSURF(pipe)); |
496 | } |
||
497 | |||
498 | static void |
||
499 | intel_enable_primary(struct drm_crtc *crtc) |
||
500 | { |
||
501 | struct drm_device *dev = crtc->dev; |
||
502 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
503 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
504 | int reg = DSPCNTR(intel_crtc->plane); |
||
505 | |||
3031 | serge | 506 | if (!intel_crtc->primary_disabled) |
507 | return; |
||
508 | |||
509 | intel_crtc->primary_disabled = false; |
||
510 | intel_update_fbc(dev); |
||
511 | |||
2342 | Serge | 512 | I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE); |
513 | } |
||
514 | |||
515 | static void |
||
516 | intel_disable_primary(struct drm_crtc *crtc) |
||
517 | { |
||
518 | struct drm_device *dev = crtc->dev; |
||
519 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
520 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
521 | int reg = DSPCNTR(intel_crtc->plane); |
||
522 | |||
3031 | serge | 523 | if (intel_crtc->primary_disabled) |
524 | return; |
||
525 | |||
2342 | Serge | 526 | I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE); |
3031 | serge | 527 | |
528 | intel_crtc->primary_disabled = true; |
||
529 | intel_update_fbc(dev); |
||
2342 | Serge | 530 | } |
531 | |||
532 | static int |
||
3031 | serge | 533 | ilk_update_colorkey(struct drm_plane *plane, |
2342 | Serge | 534 | struct drm_intel_sprite_colorkey *key) |
535 | { |
||
536 | struct drm_device *dev = plane->dev; |
||
537 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
538 | struct intel_plane *intel_plane; |
||
539 | u32 dvscntr; |
||
540 | int ret = 0; |
||
541 | |||
542 | intel_plane = to_intel_plane(plane); |
||
543 | |||
544 | I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value); |
||
545 | I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value); |
||
546 | I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask); |
||
547 | |||
548 | dvscntr = I915_READ(DVSCNTR(intel_plane->pipe)); |
||
549 | dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY); |
||
550 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
||
551 | dvscntr |= DVS_DEST_KEY; |
||
552 | else if (key->flags & I915_SET_COLORKEY_SOURCE) |
||
553 | dvscntr |= DVS_SOURCE_KEY; |
||
554 | I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr); |
||
555 | |||
556 | POSTING_READ(DVSKEYMSK(intel_plane->pipe)); |
||
557 | |||
558 | return ret; |
||
559 | } |
||
560 | |||
561 | static void |
||
3031 | serge | 562 | ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key) |
2342 | Serge | 563 | { |
564 | struct drm_device *dev = plane->dev; |
||
565 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
566 | struct intel_plane *intel_plane; |
||
567 | u32 dvscntr; |
||
568 | |||
569 | intel_plane = to_intel_plane(plane); |
||
570 | |||
571 | key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe)); |
||
572 | key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe)); |
||
573 | key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe)); |
||
574 | key->flags = 0; |
||
575 | |||
576 | dvscntr = I915_READ(DVSCNTR(intel_plane->pipe)); |
||
577 | |||
578 | if (dvscntr & DVS_DEST_KEY) |
||
579 | key->flags = I915_SET_COLORKEY_DESTINATION; |
||
580 | else if (dvscntr & DVS_SOURCE_KEY) |
||
581 | key->flags = I915_SET_COLORKEY_SOURCE; |
||
582 | else |
||
583 | key->flags = I915_SET_COLORKEY_NONE; |
||
584 | } |
||
585 | |||
586 | static int |
||
587 | intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
||
588 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, |
||
589 | unsigned int crtc_w, unsigned int crtc_h, |
||
590 | uint32_t src_x, uint32_t src_y, |
||
591 | uint32_t src_w, uint32_t src_h) |
||
592 | { |
||
593 | struct drm_device *dev = plane->dev; |
||
594 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
595 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
596 | struct intel_plane *intel_plane = to_intel_plane(plane); |
||
597 | struct intel_framebuffer *intel_fb; |
||
598 | struct drm_i915_gem_object *obj, *old_obj; |
||
599 | int pipe = intel_plane->pipe; |
||
3243 | Serge | 600 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
601 | pipe); |
||
2342 | Serge | 602 | int ret = 0; |
603 | int x = src_x >> 16, y = src_y >> 16; |
||
604 | int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay; |
||
605 | bool disable_primary = false; |
||
606 | |||
607 | intel_fb = to_intel_framebuffer(fb); |
||
608 | obj = intel_fb->obj; |
||
609 | |||
610 | old_obj = intel_plane->obj; |
||
611 | |||
3746 | Serge | 612 | intel_plane->crtc_x = crtc_x; |
613 | intel_plane->crtc_y = crtc_y; |
||
614 | intel_plane->crtc_w = crtc_w; |
||
615 | intel_plane->crtc_h = crtc_h; |
||
616 | intel_plane->src_x = src_x; |
||
617 | intel_plane->src_y = src_y; |
||
618 | intel_plane->src_w = src_w; |
||
619 | intel_plane->src_h = src_h; |
||
620 | |||
3031 | serge | 621 | src_w = src_w >> 16; |
622 | src_h = src_h >> 16; |
||
623 | |||
2342 | Serge | 624 | /* Pipe must be running... */ |
3243 | Serge | 625 | if (!(I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE)) |
2342 | Serge | 626 | return -EINVAL; |
627 | |||
628 | if (crtc_x >= primary_w || crtc_y >= primary_h) |
||
629 | return -EINVAL; |
||
630 | |||
631 | /* Don't modify another pipe's plane */ |
||
632 | if (intel_plane->pipe != intel_crtc->pipe) |
||
633 | return -EINVAL; |
||
634 | |||
3243 | Serge | 635 | /* Sprite planes can be linear or x-tiled surfaces */ |
636 | switch (obj->tiling_mode) { |
||
637 | case I915_TILING_NONE: |
||
638 | case I915_TILING_X: |
||
639 | break; |
||
640 | default: |
||
641 | return -EINVAL; |
||
642 | } |
||
643 | |||
2342 | Serge | 644 | /* |
645 | * Clamp the width & height into the visible area. Note we don't |
||
646 | * try to scale the source if part of the visible region is offscreen. |
||
647 | * The caller must handle that by adjusting source offset and size. |
||
648 | */ |
||
649 | if ((crtc_x < 0) && ((crtc_x + crtc_w) > 0)) { |
||
650 | crtc_w += crtc_x; |
||
651 | crtc_x = 0; |
||
652 | } |
||
653 | if ((crtc_x + crtc_w) <= 0) /* Nothing to display */ |
||
654 | goto out; |
||
655 | if ((crtc_x + crtc_w) > primary_w) |
||
656 | crtc_w = primary_w - crtc_x; |
||
657 | |||
658 | if ((crtc_y < 0) && ((crtc_y + crtc_h) > 0)) { |
||
659 | crtc_h += crtc_y; |
||
660 | crtc_y = 0; |
||
661 | } |
||
662 | if ((crtc_y + crtc_h) <= 0) /* Nothing to display */ |
||
663 | goto out; |
||
664 | if (crtc_y + crtc_h > primary_h) |
||
665 | crtc_h = primary_h - crtc_y; |
||
666 | |||
667 | if (!crtc_w || !crtc_h) /* Again, nothing to display */ |
||
668 | goto out; |
||
669 | |||
670 | /* |
||
3243 | Serge | 671 | * We may not have a scaler, eg. HSW does not have it any more |
672 | */ |
||
673 | if (!intel_plane->can_scale && (crtc_w != src_w || crtc_h != src_h)) |
||
674 | return -EINVAL; |
||
675 | |||
676 | /* |
||
2342 | Serge | 677 | * We can take a larger source and scale it down, but |
678 | * only so much... 16x is the max on SNB. |
||
679 | */ |
||
680 | if (((src_w * src_h) / (crtc_w * crtc_h)) > intel_plane->max_downscale) |
||
681 | return -EINVAL; |
||
682 | |||
683 | /* |
||
684 | * If the sprite is completely covering the primary plane, |
||
685 | * we can disable the primary and save power. |
||
686 | */ |
||
687 | if ((crtc_x == 0) && (crtc_y == 0) && |
||
688 | (crtc_w == primary_w) && (crtc_h == primary_h)) |
||
689 | disable_primary = true; |
||
690 | |||
691 | mutex_lock(&dev->struct_mutex); |
||
692 | |||
3746 | Serge | 693 | /* Note that this will apply the VT-d workaround for scanouts, |
694 | * which is more restrictive than required for sprites. (The |
||
695 | * primary plane requires 256KiB alignment with 64 PTE padding, |
||
696 | * the sprite planes only require 128KiB alignment and 32 PTE padding. |
||
697 | */ |
||
2342 | Serge | 698 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
699 | if (ret) |
||
700 | goto out_unlock; |
||
701 | |||
702 | intel_plane->obj = obj; |
||
703 | |||
704 | /* |
||
705 | * Be sure to re-enable the primary before the sprite is no longer |
||
706 | * covering it fully. |
||
707 | */ |
||
3031 | serge | 708 | if (!disable_primary) |
2342 | Serge | 709 | intel_enable_primary(crtc); |
710 | |||
711 | intel_plane->update_plane(plane, fb, obj, crtc_x, crtc_y, |
||
712 | crtc_w, crtc_h, x, y, src_w, src_h); |
||
713 | |||
3031 | serge | 714 | if (disable_primary) |
2342 | Serge | 715 | intel_disable_primary(crtc); |
716 | |||
717 | /* Unpin old obj after new one is active to avoid ugliness */ |
||
718 | if (old_obj) { |
||
719 | /* |
||
720 | * It's fairly common to simply update the position of |
||
721 | * an existing object. In that case, we don't need to |
||
722 | * wait for vblank to avoid ugliness, we only need to |
||
723 | * do the pin & ref bookkeeping. |
||
724 | */ |
||
725 | if (old_obj != obj) { |
||
726 | mutex_unlock(&dev->struct_mutex); |
||
727 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); |
||
728 | mutex_lock(&dev->struct_mutex); |
||
729 | } |
||
3031 | serge | 730 | intel_unpin_fb_obj(old_obj); |
2342 | Serge | 731 | } |
732 | |||
733 | out_unlock: |
||
734 | mutex_unlock(&dev->struct_mutex); |
||
735 | out: |
||
736 | return ret; |
||
737 | } |
||
738 | |||
739 | static int |
||
740 | intel_disable_plane(struct drm_plane *plane) |
||
741 | { |
||
742 | struct drm_device *dev = plane->dev; |
||
743 | struct intel_plane *intel_plane = to_intel_plane(plane); |
||
744 | int ret = 0; |
||
745 | |||
3031 | serge | 746 | if (plane->crtc) |
2342 | Serge | 747 | intel_enable_primary(plane->crtc); |
748 | intel_plane->disable_plane(plane); |
||
749 | |||
750 | if (!intel_plane->obj) |
||
751 | goto out; |
||
752 | |||
3746 | Serge | 753 | intel_wait_for_vblank(dev, intel_plane->pipe); |
754 | |||
2342 | Serge | 755 | mutex_lock(&dev->struct_mutex); |
3031 | serge | 756 | intel_unpin_fb_obj(intel_plane->obj); |
2342 | Serge | 757 | intel_plane->obj = NULL; |
758 | mutex_unlock(&dev->struct_mutex); |
||
759 | out: |
||
760 | |||
761 | return ret; |
||
762 | } |
||
763 | |||
764 | static void intel_destroy_plane(struct drm_plane *plane) |
||
765 | { |
||
766 | struct intel_plane *intel_plane = to_intel_plane(plane); |
||
767 | intel_disable_plane(plane); |
||
768 | drm_plane_cleanup(plane); |
||
769 | kfree(intel_plane); |
||
770 | } |
||
771 | |||
772 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
||
773 | struct drm_file *file_priv) |
||
774 | { |
||
775 | struct drm_intel_sprite_colorkey *set = data; |
||
776 | struct drm_mode_object *obj; |
||
777 | struct drm_plane *plane; |
||
778 | struct intel_plane *intel_plane; |
||
779 | int ret = 0; |
||
780 | |||
3482 | Serge | 781 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
782 | return -ENODEV; |
||
2342 | Serge | 783 | |
784 | /* Make sure we don't try to enable both src & dest simultaneously */ |
||
785 | if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) |
||
786 | return -EINVAL; |
||
787 | |||
3480 | Serge | 788 | drm_modeset_lock_all(dev); |
2342 | Serge | 789 | |
790 | obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE); |
||
791 | if (!obj) { |
||
792 | ret = -EINVAL; |
||
793 | goto out_unlock; |
||
794 | } |
||
795 | |||
796 | plane = obj_to_plane(obj); |
||
797 | intel_plane = to_intel_plane(plane); |
||
798 | ret = intel_plane->update_colorkey(plane, set); |
||
799 | |||
800 | out_unlock: |
||
3480 | Serge | 801 | drm_modeset_unlock_all(dev); |
2342 | Serge | 802 | return ret; |
803 | } |
||
804 | |||
805 | int intel_sprite_get_colorkey(struct drm_device *dev, void *data, |
||
806 | struct drm_file *file_priv) |
||
807 | { |
||
808 | struct drm_intel_sprite_colorkey *get = data; |
||
809 | struct drm_mode_object *obj; |
||
810 | struct drm_plane *plane; |
||
811 | struct intel_plane *intel_plane; |
||
812 | int ret = 0; |
||
813 | |||
3482 | Serge | 814 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
815 | return -ENODEV; |
||
2342 | Serge | 816 | |
3480 | Serge | 817 | drm_modeset_lock_all(dev); |
2342 | Serge | 818 | |
819 | obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE); |
||
820 | if (!obj) { |
||
821 | ret = -EINVAL; |
||
822 | goto out_unlock; |
||
823 | } |
||
824 | |||
825 | plane = obj_to_plane(obj); |
||
826 | intel_plane = to_intel_plane(plane); |
||
827 | intel_plane->get_colorkey(plane, get); |
||
828 | |||
829 | out_unlock: |
||
3480 | Serge | 830 | drm_modeset_unlock_all(dev); |
2342 | Serge | 831 | return ret; |
832 | } |
||
833 | |||
3746 | Serge | 834 | void intel_plane_restore(struct drm_plane *plane) |
835 | { |
||
836 | struct intel_plane *intel_plane = to_intel_plane(plane); |
||
837 | |||
838 | if (!plane->crtc || !plane->fb) |
||
839 | return; |
||
840 | |||
841 | intel_update_plane(plane, plane->crtc, plane->fb, |
||
842 | intel_plane->crtc_x, intel_plane->crtc_y, |
||
843 | intel_plane->crtc_w, intel_plane->crtc_h, |
||
844 | intel_plane->src_x, intel_plane->src_y, |
||
845 | intel_plane->src_w, intel_plane->src_h); |
||
846 | } |
||
847 | |||
2342 | Serge | 848 | static const struct drm_plane_funcs intel_plane_funcs = { |
849 | .update_plane = intel_update_plane, |
||
850 | .disable_plane = intel_disable_plane, |
||
851 | .destroy = intel_destroy_plane, |
||
852 | }; |
||
853 | |||
3031 | serge | 854 | static uint32_t ilk_plane_formats[] = { |
855 | DRM_FORMAT_XRGB8888, |
||
856 | DRM_FORMAT_YUYV, |
||
857 | DRM_FORMAT_YVYU, |
||
858 | DRM_FORMAT_UYVY, |
||
859 | DRM_FORMAT_VYUY, |
||
860 | }; |
||
861 | |||
2342 | Serge | 862 | static uint32_t snb_plane_formats[] = { |
863 | DRM_FORMAT_XBGR8888, |
||
864 | DRM_FORMAT_XRGB8888, |
||
865 | DRM_FORMAT_YUYV, |
||
866 | DRM_FORMAT_YVYU, |
||
867 | DRM_FORMAT_UYVY, |
||
868 | DRM_FORMAT_VYUY, |
||
869 | }; |
||
870 | |||
3746 | Serge | 871 | static uint32_t vlv_plane_formats[] = { |
872 | DRM_FORMAT_RGB565, |
||
873 | DRM_FORMAT_ABGR8888, |
||
874 | DRM_FORMAT_ARGB8888, |
||
875 | DRM_FORMAT_XBGR8888, |
||
876 | DRM_FORMAT_XRGB8888, |
||
877 | DRM_FORMAT_XBGR2101010, |
||
878 | DRM_FORMAT_ABGR2101010, |
||
879 | DRM_FORMAT_YUYV, |
||
880 | DRM_FORMAT_YVYU, |
||
881 | DRM_FORMAT_UYVY, |
||
882 | DRM_FORMAT_VYUY, |
||
883 | }; |
||
884 | |||
2342 | Serge | 885 | int |
3746 | Serge | 886 | intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) |
2342 | Serge | 887 | { |
888 | struct intel_plane *intel_plane; |
||
889 | unsigned long possible_crtcs; |
||
3031 | serge | 890 | const uint32_t *plane_formats; |
891 | int num_plane_formats; |
||
2342 | Serge | 892 | int ret; |
893 | |||
3031 | serge | 894 | if (INTEL_INFO(dev)->gen < 5) |
2342 | Serge | 895 | return -ENODEV; |
896 | |||
897 | intel_plane = kzalloc(sizeof(struct intel_plane), GFP_KERNEL); |
||
898 | if (!intel_plane) |
||
899 | return -ENOMEM; |
||
900 | |||
3031 | serge | 901 | switch (INTEL_INFO(dev)->gen) { |
902 | case 5: |
||
903 | case 6: |
||
3243 | Serge | 904 | intel_plane->can_scale = true; |
3031 | serge | 905 | intel_plane->max_downscale = 16; |
906 | intel_plane->update_plane = ilk_update_plane; |
||
907 | intel_plane->disable_plane = ilk_disable_plane; |
||
908 | intel_plane->update_colorkey = ilk_update_colorkey; |
||
909 | intel_plane->get_colorkey = ilk_get_colorkey; |
||
910 | |||
2342 | Serge | 911 | if (IS_GEN6(dev)) { |
3031 | serge | 912 | plane_formats = snb_plane_formats; |
913 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); |
||
914 | } else { |
||
915 | plane_formats = ilk_plane_formats; |
||
916 | num_plane_formats = ARRAY_SIZE(ilk_plane_formats); |
||
917 | } |
||
918 | break; |
||
919 | |||
920 | case 7: |
||
3243 | Serge | 921 | if (IS_HASWELL(dev) || IS_VALLEYVIEW(dev)) |
922 | intel_plane->can_scale = false; |
||
923 | else |
||
924 | intel_plane->can_scale = true; |
||
3746 | Serge | 925 | |
926 | if (IS_VALLEYVIEW(dev)) { |
||
927 | intel_plane->max_downscale = 1; |
||
928 | intel_plane->update_plane = vlv_update_plane; |
||
929 | intel_plane->disable_plane = vlv_disable_plane; |
||
930 | intel_plane->update_colorkey = vlv_update_colorkey; |
||
931 | intel_plane->get_colorkey = vlv_get_colorkey; |
||
932 | |||
933 | plane_formats = vlv_plane_formats; |
||
934 | num_plane_formats = ARRAY_SIZE(vlv_plane_formats); |
||
935 | } else { |
||
2342 | Serge | 936 | intel_plane->max_downscale = 2; |
937 | intel_plane->update_plane = ivb_update_plane; |
||
938 | intel_plane->disable_plane = ivb_disable_plane; |
||
939 | intel_plane->update_colorkey = ivb_update_colorkey; |
||
940 | intel_plane->get_colorkey = ivb_get_colorkey; |
||
3031 | serge | 941 | |
942 | plane_formats = snb_plane_formats; |
||
943 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); |
||
3746 | Serge | 944 | } |
3031 | serge | 945 | break; |
946 | |||
947 | default: |
||
948 | kfree(intel_plane); |
||
949 | return -ENODEV; |
||
2342 | Serge | 950 | } |
951 | |||
952 | intel_plane->pipe = pipe; |
||
3746 | Serge | 953 | intel_plane->plane = plane; |
2342 | Serge | 954 | possible_crtcs = (1 << pipe); |
955 | ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs, |
||
3031 | serge | 956 | &intel_plane_funcs, |
957 | plane_formats, num_plane_formats, |
||
958 | false); |
||
2342 | Serge | 959 | if (ret) |
960 | kfree(intel_plane); |
||
961 | |||
962 | return ret; |
||
963 | }><>>=>>=>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |