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Rev | Author | Line No. | Line |
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2342 | Serge | 1 | /* |
2 | * Copyright © 2011 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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21 | * SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Jesse Barnes |
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25 | * |
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26 | * New plane/sprite handling. |
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27 | * |
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28 | * The older chips had a separate interface for programming plane related |
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29 | * registers; newer ones are much simpler and we can use the new DRM plane |
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30 | * support. |
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31 | */ |
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3031 | serge | 32 | #include |
33 | #include |
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34 | #include |
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2342 | Serge | 35 | #include "intel_drv.h" |
3031 | serge | 36 | #include |
2342 | Serge | 37 | #include "i915_drv.h" |
38 | |||
39 | static void |
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40 | ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, |
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41 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, |
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42 | unsigned int crtc_w, unsigned int crtc_h, |
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43 | uint32_t x, uint32_t y, |
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44 | uint32_t src_w, uint32_t src_h) |
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45 | { |
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46 | struct drm_device *dev = plane->dev; |
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47 | struct drm_i915_private *dev_priv = dev->dev_private; |
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48 | struct intel_plane *intel_plane = to_intel_plane(plane); |
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49 | int pipe = intel_plane->pipe; |
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50 | u32 sprctl, sprscale = 0; |
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51 | int pixel_size; |
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52 | |||
53 | sprctl = I915_READ(SPRCTL(pipe)); |
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54 | |||
55 | /* Mask out pixel format bits in case we change it */ |
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56 | sprctl &= ~SPRITE_PIXFORMAT_MASK; |
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57 | sprctl &= ~SPRITE_RGB_ORDER_RGBX; |
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58 | sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK; |
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3031 | serge | 59 | sprctl &= ~SPRITE_TILED; |
2342 | Serge | 60 | |
61 | switch (fb->pixel_format) { |
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62 | case DRM_FORMAT_XBGR8888: |
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3031 | serge | 63 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; |
2342 | Serge | 64 | pixel_size = 4; |
65 | break; |
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66 | case DRM_FORMAT_XRGB8888: |
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3031 | serge | 67 | sprctl |= SPRITE_FORMAT_RGBX888; |
2342 | Serge | 68 | pixel_size = 4; |
69 | break; |
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70 | case DRM_FORMAT_YUYV: |
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71 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; |
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72 | pixel_size = 2; |
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73 | break; |
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74 | case DRM_FORMAT_YVYU: |
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75 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; |
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76 | pixel_size = 2; |
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77 | break; |
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78 | case DRM_FORMAT_UYVY: |
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79 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; |
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80 | pixel_size = 2; |
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81 | break; |
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82 | case DRM_FORMAT_VYUY: |
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83 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; |
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84 | pixel_size = 2; |
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85 | break; |
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86 | default: |
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87 | DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888\n"); |
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3031 | serge | 88 | sprctl |= SPRITE_FORMAT_RGBX888; |
2342 | Serge | 89 | pixel_size = 4; |
90 | break; |
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91 | } |
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92 | |||
93 | if (obj->tiling_mode != I915_TILING_NONE) |
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94 | sprctl |= SPRITE_TILED; |
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95 | |||
96 | /* must disable */ |
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97 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; |
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98 | sprctl |= SPRITE_ENABLE; |
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99 | |||
100 | /* Sizes are 0 based */ |
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101 | src_w--; |
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102 | src_h--; |
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103 | crtc_w--; |
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104 | crtc_h--; |
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105 | |||
106 | intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size); |
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107 | |||
108 | /* |
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109 | * IVB workaround: must disable low power watermarks for at least |
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110 | * one frame before enabling scaling. LP watermarks can be re-enabled |
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111 | * when scaling is disabled. |
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112 | */ |
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113 | if (crtc_w != src_w || crtc_h != src_h) { |
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3031 | serge | 114 | if (!dev_priv->sprite_scaling_enabled) { |
2342 | Serge | 115 | dev_priv->sprite_scaling_enabled = true; |
3031 | serge | 116 | intel_update_watermarks(dev); |
2342 | Serge | 117 | intel_wait_for_vblank(dev, pipe); |
3031 | serge | 118 | } |
2342 | Serge | 119 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; |
120 | } else { |
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3031 | serge | 121 | if (dev_priv->sprite_scaling_enabled) { |
2342 | Serge | 122 | dev_priv->sprite_scaling_enabled = false; |
123 | /* potentially re-enable LP watermarks */ |
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3031 | serge | 124 | intel_update_watermarks(dev); |
125 | } |
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2342 | Serge | 126 | } |
127 | |||
128 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); |
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129 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); |
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130 | if (obj->tiling_mode != I915_TILING_NONE) { |
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131 | I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); |
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132 | } else { |
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133 | unsigned long offset; |
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134 | |||
135 | offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
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136 | I915_WRITE(SPRLINOFF(pipe), offset); |
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137 | } |
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138 | I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); |
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139 | I915_WRITE(SPRSCALE(pipe), sprscale); |
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140 | I915_WRITE(SPRCTL(pipe), sprctl); |
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3031 | serge | 141 | I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset); |
2342 | Serge | 142 | POSTING_READ(SPRSURF(pipe)); |
143 | } |
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144 | |||
145 | static void |
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146 | ivb_disable_plane(struct drm_plane *plane) |
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147 | { |
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148 | struct drm_device *dev = plane->dev; |
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149 | struct drm_i915_private *dev_priv = dev->dev_private; |
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150 | struct intel_plane *intel_plane = to_intel_plane(plane); |
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151 | int pipe = intel_plane->pipe; |
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152 | |||
153 | I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); |
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154 | /* Can't leave the scaler enabled... */ |
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155 | I915_WRITE(SPRSCALE(pipe), 0); |
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156 | /* Activate double buffered register update */ |
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3031 | serge | 157 | I915_MODIFY_DISPBASE(SPRSURF(pipe), 0); |
2342 | Serge | 158 | POSTING_READ(SPRSURF(pipe)); |
3031 | serge | 159 | |
160 | dev_priv->sprite_scaling_enabled = false; |
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161 | intel_update_watermarks(dev); |
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2342 | Serge | 162 | } |
163 | |||
164 | static int |
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165 | ivb_update_colorkey(struct drm_plane *plane, |
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166 | struct drm_intel_sprite_colorkey *key) |
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167 | { |
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168 | struct drm_device *dev = plane->dev; |
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169 | struct drm_i915_private *dev_priv = dev->dev_private; |
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170 | struct intel_plane *intel_plane; |
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171 | u32 sprctl; |
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172 | int ret = 0; |
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173 | |||
174 | intel_plane = to_intel_plane(plane); |
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175 | |||
176 | I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value); |
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177 | I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value); |
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178 | I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask); |
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179 | |||
180 | sprctl = I915_READ(SPRCTL(intel_plane->pipe)); |
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181 | sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY); |
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182 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
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183 | sprctl |= SPRITE_DEST_KEY; |
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184 | else if (key->flags & I915_SET_COLORKEY_SOURCE) |
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185 | sprctl |= SPRITE_SOURCE_KEY; |
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186 | I915_WRITE(SPRCTL(intel_plane->pipe), sprctl); |
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187 | |||
188 | POSTING_READ(SPRKEYMSK(intel_plane->pipe)); |
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189 | |||
190 | return ret; |
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191 | } |
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192 | |||
193 | static void |
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194 | ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key) |
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195 | { |
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196 | struct drm_device *dev = plane->dev; |
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197 | struct drm_i915_private *dev_priv = dev->dev_private; |
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198 | struct intel_plane *intel_plane; |
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199 | u32 sprctl; |
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200 | |||
201 | intel_plane = to_intel_plane(plane); |
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202 | |||
203 | key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe)); |
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204 | key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe)); |
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205 | key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe)); |
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206 | key->flags = 0; |
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207 | |||
208 | sprctl = I915_READ(SPRCTL(intel_plane->pipe)); |
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209 | |||
210 | if (sprctl & SPRITE_DEST_KEY) |
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211 | key->flags = I915_SET_COLORKEY_DESTINATION; |
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212 | else if (sprctl & SPRITE_SOURCE_KEY) |
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213 | key->flags = I915_SET_COLORKEY_SOURCE; |
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214 | else |
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215 | key->flags = I915_SET_COLORKEY_NONE; |
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216 | } |
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217 | |||
218 | static void |
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3031 | serge | 219 | ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, |
2342 | Serge | 220 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, |
221 | unsigned int crtc_w, unsigned int crtc_h, |
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222 | uint32_t x, uint32_t y, |
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223 | uint32_t src_w, uint32_t src_h) |
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224 | { |
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225 | struct drm_device *dev = plane->dev; |
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226 | struct drm_i915_private *dev_priv = dev->dev_private; |
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227 | struct intel_plane *intel_plane = to_intel_plane(plane); |
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228 | int pipe = intel_plane->pipe, pixel_size; |
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3031 | serge | 229 | u32 dvscntr, dvsscale; |
2342 | Serge | 230 | |
231 | dvscntr = I915_READ(DVSCNTR(pipe)); |
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232 | |||
233 | /* Mask out pixel format bits in case we change it */ |
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234 | dvscntr &= ~DVS_PIXFORMAT_MASK; |
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3031 | serge | 235 | dvscntr &= ~DVS_RGB_ORDER_XBGR; |
2342 | Serge | 236 | dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK; |
3031 | serge | 237 | dvscntr &= ~DVS_TILED; |
2342 | Serge | 238 | |
239 | switch (fb->pixel_format) { |
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240 | case DRM_FORMAT_XBGR8888: |
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3031 | serge | 241 | dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; |
2342 | Serge | 242 | pixel_size = 4; |
243 | break; |
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244 | case DRM_FORMAT_XRGB8888: |
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3031 | serge | 245 | dvscntr |= DVS_FORMAT_RGBX888; |
2342 | Serge | 246 | pixel_size = 4; |
247 | break; |
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248 | case DRM_FORMAT_YUYV: |
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249 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; |
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250 | pixel_size = 2; |
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251 | break; |
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252 | case DRM_FORMAT_YVYU: |
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253 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; |
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254 | pixel_size = 2; |
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255 | break; |
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256 | case DRM_FORMAT_UYVY: |
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257 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; |
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258 | pixel_size = 2; |
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259 | break; |
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260 | case DRM_FORMAT_VYUY: |
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261 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; |
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262 | pixel_size = 2; |
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263 | break; |
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264 | default: |
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265 | DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888\n"); |
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266 | dvscntr |= DVS_FORMAT_RGBX888; |
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267 | pixel_size = 4; |
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268 | break; |
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269 | } |
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270 | |||
271 | if (obj->tiling_mode != I915_TILING_NONE) |
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272 | dvscntr |= DVS_TILED; |
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273 | |||
3031 | serge | 274 | if (IS_GEN6(dev)) |
275 | dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ |
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2342 | Serge | 276 | dvscntr |= DVS_ENABLE; |
277 | |||
278 | /* Sizes are 0 based */ |
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279 | src_w--; |
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280 | src_h--; |
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281 | crtc_w--; |
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282 | crtc_h--; |
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283 | |||
284 | intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size); |
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285 | |||
3031 | serge | 286 | dvsscale = 0; |
287 | if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h) |
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2342 | Serge | 288 | dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; |
289 | |||
290 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); |
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291 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); |
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292 | if (obj->tiling_mode != I915_TILING_NONE) { |
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293 | I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); |
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294 | } else { |
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295 | unsigned long offset; |
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296 | |||
297 | offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
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298 | I915_WRITE(DVSLINOFF(pipe), offset); |
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299 | } |
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300 | I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); |
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301 | I915_WRITE(DVSSCALE(pipe), dvsscale); |
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302 | I915_WRITE(DVSCNTR(pipe), dvscntr); |
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3031 | serge | 303 | I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset); |
2342 | Serge | 304 | POSTING_READ(DVSSURF(pipe)); |
305 | } |
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306 | |||
307 | static void |
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3031 | serge | 308 | ilk_disable_plane(struct drm_plane *plane) |
2342 | Serge | 309 | { |
310 | struct drm_device *dev = plane->dev; |
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311 | struct drm_i915_private *dev_priv = dev->dev_private; |
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312 | struct intel_plane *intel_plane = to_intel_plane(plane); |
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313 | int pipe = intel_plane->pipe; |
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314 | |||
315 | I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE); |
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316 | /* Disable the scaler */ |
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317 | I915_WRITE(DVSSCALE(pipe), 0); |
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318 | /* Flush double buffered register updates */ |
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3031 | serge | 319 | I915_MODIFY_DISPBASE(DVSSURF(pipe), 0); |
2342 | Serge | 320 | POSTING_READ(DVSSURF(pipe)); |
321 | } |
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322 | |||
323 | static void |
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324 | intel_enable_primary(struct drm_crtc *crtc) |
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325 | { |
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326 | struct drm_device *dev = crtc->dev; |
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327 | struct drm_i915_private *dev_priv = dev->dev_private; |
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328 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
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329 | int reg = DSPCNTR(intel_crtc->plane); |
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330 | |||
3031 | serge | 331 | if (!intel_crtc->primary_disabled) |
332 | return; |
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333 | |||
334 | intel_crtc->primary_disabled = false; |
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335 | intel_update_fbc(dev); |
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336 | |||
2342 | Serge | 337 | I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE); |
338 | } |
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339 | |||
340 | static void |
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341 | intel_disable_primary(struct drm_crtc *crtc) |
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342 | { |
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343 | struct drm_device *dev = crtc->dev; |
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344 | struct drm_i915_private *dev_priv = dev->dev_private; |
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345 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
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346 | int reg = DSPCNTR(intel_crtc->plane); |
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347 | |||
3031 | serge | 348 | if (intel_crtc->primary_disabled) |
349 | return; |
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350 | |||
2342 | Serge | 351 | I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE); |
3031 | serge | 352 | |
353 | intel_crtc->primary_disabled = true; |
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354 | intel_update_fbc(dev); |
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2342 | Serge | 355 | } |
356 | |||
357 | static int |
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3031 | serge | 358 | ilk_update_colorkey(struct drm_plane *plane, |
2342 | Serge | 359 | struct drm_intel_sprite_colorkey *key) |
360 | { |
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361 | struct drm_device *dev = plane->dev; |
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362 | struct drm_i915_private *dev_priv = dev->dev_private; |
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363 | struct intel_plane *intel_plane; |
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364 | u32 dvscntr; |
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365 | int ret = 0; |
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366 | |||
367 | intel_plane = to_intel_plane(plane); |
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368 | |||
369 | I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value); |
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370 | I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value); |
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371 | I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask); |
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372 | |||
373 | dvscntr = I915_READ(DVSCNTR(intel_plane->pipe)); |
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374 | dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY); |
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375 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
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376 | dvscntr |= DVS_DEST_KEY; |
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377 | else if (key->flags & I915_SET_COLORKEY_SOURCE) |
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378 | dvscntr |= DVS_SOURCE_KEY; |
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379 | I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr); |
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380 | |||
381 | POSTING_READ(DVSKEYMSK(intel_plane->pipe)); |
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382 | |||
383 | return ret; |
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384 | } |
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385 | |||
386 | static void |
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3031 | serge | 387 | ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key) |
2342 | Serge | 388 | { |
389 | struct drm_device *dev = plane->dev; |
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390 | struct drm_i915_private *dev_priv = dev->dev_private; |
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391 | struct intel_plane *intel_plane; |
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392 | u32 dvscntr; |
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393 | |||
394 | intel_plane = to_intel_plane(plane); |
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395 | |||
396 | key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe)); |
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397 | key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe)); |
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398 | key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe)); |
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399 | key->flags = 0; |
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400 | |||
401 | dvscntr = I915_READ(DVSCNTR(intel_plane->pipe)); |
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402 | |||
403 | if (dvscntr & DVS_DEST_KEY) |
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404 | key->flags = I915_SET_COLORKEY_DESTINATION; |
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405 | else if (dvscntr & DVS_SOURCE_KEY) |
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406 | key->flags = I915_SET_COLORKEY_SOURCE; |
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407 | else |
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408 | key->flags = I915_SET_COLORKEY_NONE; |
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409 | } |
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410 | |||
411 | static int |
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412 | intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
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413 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, |
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414 | unsigned int crtc_w, unsigned int crtc_h, |
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415 | uint32_t src_x, uint32_t src_y, |
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416 | uint32_t src_w, uint32_t src_h) |
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417 | { |
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418 | struct drm_device *dev = plane->dev; |
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419 | struct drm_i915_private *dev_priv = dev->dev_private; |
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420 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
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421 | struct intel_plane *intel_plane = to_intel_plane(plane); |
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422 | struct intel_framebuffer *intel_fb; |
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423 | struct drm_i915_gem_object *obj, *old_obj; |
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424 | int pipe = intel_plane->pipe; |
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425 | int ret = 0; |
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426 | int x = src_x >> 16, y = src_y >> 16; |
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427 | int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay; |
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428 | bool disable_primary = false; |
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429 | |||
430 | intel_fb = to_intel_framebuffer(fb); |
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431 | obj = intel_fb->obj; |
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432 | |||
433 | old_obj = intel_plane->obj; |
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434 | |||
3031 | serge | 435 | src_w = src_w >> 16; |
436 | src_h = src_h >> 16; |
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437 | |||
2342 | Serge | 438 | /* Pipe must be running... */ |
439 | if (!(I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE)) |
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440 | return -EINVAL; |
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441 | |||
442 | if (crtc_x >= primary_w || crtc_y >= primary_h) |
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443 | return -EINVAL; |
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444 | |||
445 | /* Don't modify another pipe's plane */ |
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446 | if (intel_plane->pipe != intel_crtc->pipe) |
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447 | return -EINVAL; |
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448 | |||
449 | /* |
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450 | * Clamp the width & height into the visible area. Note we don't |
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451 | * try to scale the source if part of the visible region is offscreen. |
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452 | * The caller must handle that by adjusting source offset and size. |
||
453 | */ |
||
454 | if ((crtc_x < 0) && ((crtc_x + crtc_w) > 0)) { |
||
455 | crtc_w += crtc_x; |
||
456 | crtc_x = 0; |
||
457 | } |
||
458 | if ((crtc_x + crtc_w) <= 0) /* Nothing to display */ |
||
459 | goto out; |
||
460 | if ((crtc_x + crtc_w) > primary_w) |
||
461 | crtc_w = primary_w - crtc_x; |
||
462 | |||
463 | if ((crtc_y < 0) && ((crtc_y + crtc_h) > 0)) { |
||
464 | crtc_h += crtc_y; |
||
465 | crtc_y = 0; |
||
466 | } |
||
467 | if ((crtc_y + crtc_h) <= 0) /* Nothing to display */ |
||
468 | goto out; |
||
469 | if (crtc_y + crtc_h > primary_h) |
||
470 | crtc_h = primary_h - crtc_y; |
||
471 | |||
472 | if (!crtc_w || !crtc_h) /* Again, nothing to display */ |
||
473 | goto out; |
||
474 | |||
475 | /* |
||
476 | * We can take a larger source and scale it down, but |
||
477 | * only so much... 16x is the max on SNB. |
||
478 | */ |
||
479 | if (((src_w * src_h) / (crtc_w * crtc_h)) > intel_plane->max_downscale) |
||
480 | return -EINVAL; |
||
481 | |||
482 | /* |
||
483 | * If the sprite is completely covering the primary plane, |
||
484 | * we can disable the primary and save power. |
||
485 | */ |
||
486 | if ((crtc_x == 0) && (crtc_y == 0) && |
||
487 | (crtc_w == primary_w) && (crtc_h == primary_h)) |
||
488 | disable_primary = true; |
||
489 | |||
490 | mutex_lock(&dev->struct_mutex); |
||
491 | |||
492 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
||
493 | if (ret) |
||
494 | goto out_unlock; |
||
495 | |||
496 | intel_plane->obj = obj; |
||
497 | |||
498 | /* |
||
499 | * Be sure to re-enable the primary before the sprite is no longer |
||
500 | * covering it fully. |
||
501 | */ |
||
3031 | serge | 502 | if (!disable_primary) |
2342 | Serge | 503 | intel_enable_primary(crtc); |
504 | |||
505 | intel_plane->update_plane(plane, fb, obj, crtc_x, crtc_y, |
||
506 | crtc_w, crtc_h, x, y, src_w, src_h); |
||
507 | |||
3031 | serge | 508 | if (disable_primary) |
2342 | Serge | 509 | intel_disable_primary(crtc); |
510 | |||
511 | /* Unpin old obj after new one is active to avoid ugliness */ |
||
512 | if (old_obj) { |
||
513 | /* |
||
514 | * It's fairly common to simply update the position of |
||
515 | * an existing object. In that case, we don't need to |
||
516 | * wait for vblank to avoid ugliness, we only need to |
||
517 | * do the pin & ref bookkeeping. |
||
518 | */ |
||
519 | if (old_obj != obj) { |
||
520 | mutex_unlock(&dev->struct_mutex); |
||
521 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); |
||
522 | mutex_lock(&dev->struct_mutex); |
||
523 | } |
||
3031 | serge | 524 | intel_unpin_fb_obj(old_obj); |
2342 | Serge | 525 | } |
526 | |||
527 | out_unlock: |
||
528 | mutex_unlock(&dev->struct_mutex); |
||
529 | out: |
||
530 | return ret; |
||
531 | } |
||
532 | |||
533 | static int |
||
534 | intel_disable_plane(struct drm_plane *plane) |
||
535 | { |
||
536 | struct drm_device *dev = plane->dev; |
||
537 | struct intel_plane *intel_plane = to_intel_plane(plane); |
||
538 | int ret = 0; |
||
539 | |||
3031 | serge | 540 | if (plane->crtc) |
2342 | Serge | 541 | intel_enable_primary(plane->crtc); |
542 | intel_plane->disable_plane(plane); |
||
543 | |||
544 | if (!intel_plane->obj) |
||
545 | goto out; |
||
546 | |||
547 | mutex_lock(&dev->struct_mutex); |
||
3031 | serge | 548 | intel_unpin_fb_obj(intel_plane->obj); |
2342 | Serge | 549 | intel_plane->obj = NULL; |
550 | mutex_unlock(&dev->struct_mutex); |
||
551 | out: |
||
552 | |||
553 | return ret; |
||
554 | } |
||
555 | |||
556 | static void intel_destroy_plane(struct drm_plane *plane) |
||
557 | { |
||
558 | struct intel_plane *intel_plane = to_intel_plane(plane); |
||
559 | intel_disable_plane(plane); |
||
560 | drm_plane_cleanup(plane); |
||
561 | kfree(intel_plane); |
||
562 | } |
||
563 | |||
564 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
||
565 | struct drm_file *file_priv) |
||
566 | { |
||
567 | struct drm_intel_sprite_colorkey *set = data; |
||
568 | struct drm_mode_object *obj; |
||
569 | struct drm_plane *plane; |
||
570 | struct intel_plane *intel_plane; |
||
571 | int ret = 0; |
||
572 | |||
3031 | serge | 573 | // if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
574 | // return -ENODEV; |
||
2342 | Serge | 575 | |
576 | /* Make sure we don't try to enable both src & dest simultaneously */ |
||
577 | if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) |
||
578 | return -EINVAL; |
||
579 | |||
580 | mutex_lock(&dev->mode_config.mutex); |
||
581 | |||
582 | obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE); |
||
583 | if (!obj) { |
||
584 | ret = -EINVAL; |
||
585 | goto out_unlock; |
||
586 | } |
||
587 | |||
588 | plane = obj_to_plane(obj); |
||
589 | intel_plane = to_intel_plane(plane); |
||
590 | ret = intel_plane->update_colorkey(plane, set); |
||
591 | |||
592 | out_unlock: |
||
593 | mutex_unlock(&dev->mode_config.mutex); |
||
594 | return ret; |
||
595 | } |
||
596 | |||
597 | int intel_sprite_get_colorkey(struct drm_device *dev, void *data, |
||
598 | struct drm_file *file_priv) |
||
599 | { |
||
600 | struct drm_intel_sprite_colorkey *get = data; |
||
601 | struct drm_mode_object *obj; |
||
602 | struct drm_plane *plane; |
||
603 | struct intel_plane *intel_plane; |
||
604 | int ret = 0; |
||
605 | |||
3031 | serge | 606 | // if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
607 | // return -ENODEV; |
||
2342 | Serge | 608 | |
609 | mutex_lock(&dev->mode_config.mutex); |
||
610 | |||
611 | obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE); |
||
612 | if (!obj) { |
||
613 | ret = -EINVAL; |
||
614 | goto out_unlock; |
||
615 | } |
||
616 | |||
617 | plane = obj_to_plane(obj); |
||
618 | intel_plane = to_intel_plane(plane); |
||
619 | intel_plane->get_colorkey(plane, get); |
||
620 | |||
621 | out_unlock: |
||
622 | mutex_unlock(&dev->mode_config.mutex); |
||
623 | return ret; |
||
624 | } |
||
625 | |||
626 | static const struct drm_plane_funcs intel_plane_funcs = { |
||
627 | .update_plane = intel_update_plane, |
||
628 | .disable_plane = intel_disable_plane, |
||
629 | .destroy = intel_destroy_plane, |
||
630 | }; |
||
631 | |||
3031 | serge | 632 | static uint32_t ilk_plane_formats[] = { |
633 | DRM_FORMAT_XRGB8888, |
||
634 | DRM_FORMAT_YUYV, |
||
635 | DRM_FORMAT_YVYU, |
||
636 | DRM_FORMAT_UYVY, |
||
637 | DRM_FORMAT_VYUY, |
||
638 | }; |
||
639 | |||
2342 | Serge | 640 | static uint32_t snb_plane_formats[] = { |
641 | DRM_FORMAT_XBGR8888, |
||
642 | DRM_FORMAT_XRGB8888, |
||
643 | DRM_FORMAT_YUYV, |
||
644 | DRM_FORMAT_YVYU, |
||
645 | DRM_FORMAT_UYVY, |
||
646 | DRM_FORMAT_VYUY, |
||
647 | }; |
||
648 | |||
649 | int |
||
650 | intel_plane_init(struct drm_device *dev, enum pipe pipe) |
||
651 | { |
||
652 | struct intel_plane *intel_plane; |
||
653 | unsigned long possible_crtcs; |
||
3031 | serge | 654 | const uint32_t *plane_formats; |
655 | int num_plane_formats; |
||
2342 | Serge | 656 | int ret; |
657 | |||
3031 | serge | 658 | if (INTEL_INFO(dev)->gen < 5) |
2342 | Serge | 659 | return -ENODEV; |
660 | |||
661 | intel_plane = kzalloc(sizeof(struct intel_plane), GFP_KERNEL); |
||
662 | if (!intel_plane) |
||
663 | return -ENOMEM; |
||
664 | |||
3031 | serge | 665 | switch (INTEL_INFO(dev)->gen) { |
666 | case 5: |
||
667 | case 6: |
||
668 | intel_plane->max_downscale = 16; |
||
669 | intel_plane->update_plane = ilk_update_plane; |
||
670 | intel_plane->disable_plane = ilk_disable_plane; |
||
671 | intel_plane->update_colorkey = ilk_update_colorkey; |
||
672 | intel_plane->get_colorkey = ilk_get_colorkey; |
||
673 | |||
2342 | Serge | 674 | if (IS_GEN6(dev)) { |
3031 | serge | 675 | plane_formats = snb_plane_formats; |
676 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); |
||
677 | } else { |
||
678 | plane_formats = ilk_plane_formats; |
||
679 | num_plane_formats = ARRAY_SIZE(ilk_plane_formats); |
||
680 | } |
||
681 | break; |
||
682 | |||
683 | case 7: |
||
2342 | Serge | 684 | intel_plane->max_downscale = 2; |
685 | intel_plane->update_plane = ivb_update_plane; |
||
686 | intel_plane->disable_plane = ivb_disable_plane; |
||
687 | intel_plane->update_colorkey = ivb_update_colorkey; |
||
688 | intel_plane->get_colorkey = ivb_get_colorkey; |
||
3031 | serge | 689 | |
690 | plane_formats = snb_plane_formats; |
||
691 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); |
||
692 | break; |
||
693 | |||
694 | default: |
||
695 | kfree(intel_plane); |
||
696 | return -ENODEV; |
||
2342 | Serge | 697 | } |
698 | |||
699 | intel_plane->pipe = pipe; |
||
700 | possible_crtcs = (1 << pipe); |
||
701 | ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs, |
||
3031 | serge | 702 | &intel_plane_funcs, |
703 | plane_formats, num_plane_formats, |
||
704 | false); |
||
2342 | Serge | 705 | if (ret) |
706 | kfree(intel_plane); |
||
707 | |||
708 | return ret; |
||
709 | }><>>=>>=>>><>><>><>><>><>><>><>><> |