Rev 6084 | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
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4104 | Serge | 1 | /* |
2 | * Copyright © 2013 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | */ |
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24 | |||
25 | #include "i915_drv.h" |
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26 | #include "intel_drv.h" |
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27 | |||
4560 | Serge | 28 | /* |
29 | * IOSF sideband, see VLV2_SidebandMsg_HAS.docx and |
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30 | * VLV_VLV2_PUNIT_HAS_0.8.docx |
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31 | */ |
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5060 | serge | 32 | |
33 | /* Standard MMIO read, non-posted */ |
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34 | #define SB_MRD_NP 0x00 |
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35 | /* Standard MMIO write, non-posted */ |
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36 | #define SB_MWR_NP 0x01 |
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37 | /* Private register read, double-word addressing, non-posted */ |
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38 | #define SB_CRRDDA_NP 0x06 |
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39 | /* Private register write, double-word addressing, non-posted */ |
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40 | #define SB_CRWRDA_NP 0x07 |
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41 | |||
4104 | Serge | 42 | static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn, |
43 | u32 port, u32 opcode, u32 addr, u32 *val) |
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44 | { |
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45 | u32 cmd, be = 0xf, bar = 0; |
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5060 | serge | 46 | bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP); |
4104 | Serge | 47 | |
48 | cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) | |
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49 | (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) | |
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50 | (bar << IOSF_BAR_SHIFT); |
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51 | |||
6084 | serge | 52 | WARN_ON(!mutex_is_locked(&dev_priv->sb_lock)); |
4104 | Serge | 53 | |
54 | if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) { |
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55 | DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n", |
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56 | is_read ? "read" : "write"); |
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57 | return -EAGAIN; |
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58 | } |
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59 | |||
60 | I915_WRITE(VLV_IOSF_ADDR, addr); |
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61 | if (!is_read) |
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62 | I915_WRITE(VLV_IOSF_DATA, *val); |
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63 | I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd); |
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64 | |||
65 | if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) { |
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66 | DRM_DEBUG_DRIVER("IOSF sideband finish wait (%s) timed out\n", |
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67 | is_read ? "read" : "write"); |
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68 | return -ETIMEDOUT; |
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69 | } |
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70 | |||
71 | if (is_read) |
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72 | *val = I915_READ(VLV_IOSF_DATA); |
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73 | I915_WRITE(VLV_IOSF_DATA, 0); |
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74 | |||
75 | return 0; |
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76 | } |
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77 | |||
6084 | serge | 78 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr) |
4104 | Serge | 79 | { |
80 | u32 val = 0; |
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81 | |||
82 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
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83 | |||
6084 | serge | 84 | mutex_lock(&dev_priv->sb_lock); |
85 | vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT, |
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5060 | serge | 86 | SB_CRRDDA_NP, addr, &val); |
6084 | serge | 87 | mutex_unlock(&dev_priv->sb_lock); |
4104 | Serge | 88 | |
89 | return val; |
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90 | } |
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91 | |||
6084 | serge | 92 | void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val) |
4104 | Serge | 93 | { |
94 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
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95 | |||
6084 | serge | 96 | mutex_lock(&dev_priv->sb_lock); |
97 | vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT, |
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5060 | serge | 98 | SB_CRWRDA_NP, addr, &val); |
6084 | serge | 99 | mutex_unlock(&dev_priv->sb_lock); |
4104 | Serge | 100 | } |
101 | |||
4560 | Serge | 102 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg) |
103 | { |
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104 | u32 val = 0; |
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105 | |||
6084 | serge | 106 | vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT, |
5060 | serge | 107 | SB_CRRDDA_NP, reg, &val); |
4560 | Serge | 108 | |
109 | return val; |
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110 | } |
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111 | |||
112 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
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113 | { |
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6084 | serge | 114 | vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT, |
5060 | serge | 115 | SB_CRWRDA_NP, reg, &val); |
4560 | Serge | 116 | } |
117 | |||
4104 | Serge | 118 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr) |
119 | { |
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120 | u32 val = 0; |
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121 | |||
122 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
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123 | |||
6084 | serge | 124 | mutex_lock(&dev_priv->sb_lock); |
125 | vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_NC, |
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5060 | serge | 126 | SB_CRRDDA_NP, addr, &val); |
6084 | serge | 127 | mutex_unlock(&dev_priv->sb_lock); |
4104 | Serge | 128 | |
129 | return val; |
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130 | } |
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131 | |||
7144 | serge | 132 | u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg) |
4104 | Serge | 133 | { |
134 | u32 val = 0; |
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7144 | serge | 135 | vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), port, |
5060 | serge | 136 | SB_CRRDDA_NP, reg, &val); |
4560 | Serge | 137 | return val; |
138 | } |
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4104 | Serge | 139 | |
7144 | serge | 140 | void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, |
141 | u8 port, u32 reg, u32 val) |
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4560 | Serge | 142 | { |
7144 | serge | 143 | vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), port, |
5060 | serge | 144 | SB_CRWRDA_NP, reg, &val); |
4560 | Serge | 145 | } |
4104 | Serge | 146 | |
4560 | Serge | 147 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg) |
148 | { |
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149 | u32 val = 0; |
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6084 | serge | 150 | vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCK, |
5060 | serge | 151 | SB_CRRDDA_NP, reg, &val); |
4104 | Serge | 152 | return val; |
153 | } |
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154 | |||
4560 | Serge | 155 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
4104 | Serge | 156 | { |
6084 | serge | 157 | vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCK, |
5060 | serge | 158 | SB_CRWRDA_NP, reg, &val); |
4560 | Serge | 159 | } |
160 | |||
161 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg) |
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162 | { |
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163 | u32 val = 0; |
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6084 | serge | 164 | vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCU, |
5060 | serge | 165 | SB_CRRDDA_NP, reg, &val); |
4560 | Serge | 166 | return val; |
167 | } |
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168 | |||
169 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
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170 | { |
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6084 | serge | 171 | vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCU, |
5060 | serge | 172 | SB_CRWRDA_NP, reg, &val); |
4560 | Serge | 173 | } |
174 | |||
175 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg) |
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176 | { |
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177 | u32 val = 0; |
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178 | |||
179 | vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)), |
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5060 | serge | 180 | SB_MRD_NP, reg, &val); |
181 | |||
182 | /* |
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183 | * FIXME: There might be some registers where all 1's is a valid value, |
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184 | * so ideally we should check the register offset instead... |
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185 | */ |
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186 | WARN(val == 0xffffffff, "DPIO read pipe %c reg 0x%x == 0x%x\n", |
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187 | pipe_name(pipe), reg, val); |
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188 | |||
4560 | Serge | 189 | return val; |
190 | } |
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191 | |||
192 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val) |
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193 | { |
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194 | vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)), |
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5060 | serge | 195 | SB_MWR_NP, reg, &val); |
4104 | Serge | 196 | } |
197 | |||
198 | /* SBI access */ |
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199 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
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200 | enum intel_sbi_destination destination) |
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201 | { |
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202 | u32 value = 0; |
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6084 | serge | 203 | WARN_ON(!mutex_is_locked(&dev_priv->sb_lock)); |
4104 | Serge | 204 | |
205 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
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206 | 100)) { |
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207 | DRM_ERROR("timeout waiting for SBI to become ready\n"); |
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208 | return 0; |
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209 | } |
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210 | |||
211 | I915_WRITE(SBI_ADDR, (reg << 16)); |
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212 | |||
213 | if (destination == SBI_ICLK) |
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214 | value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD; |
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215 | else |
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216 | value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD; |
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217 | I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY); |
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218 | |||
219 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
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220 | 100)) { |
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221 | DRM_ERROR("timeout waiting for SBI to complete read transaction\n"); |
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222 | return 0; |
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223 | } |
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224 | |||
225 | return I915_READ(SBI_DATA); |
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226 | } |
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227 | |||
228 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, |
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229 | enum intel_sbi_destination destination) |
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230 | { |
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231 | u32 tmp; |
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232 | |||
6084 | serge | 233 | WARN_ON(!mutex_is_locked(&dev_priv->sb_lock)); |
4104 | Serge | 234 | |
235 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
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236 | 100)) { |
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237 | DRM_ERROR("timeout waiting for SBI to become ready\n"); |
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238 | return; |
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239 | } |
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240 | |||
241 | I915_WRITE(SBI_ADDR, (reg << 16)); |
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242 | I915_WRITE(SBI_DATA, value); |
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243 | |||
244 | if (destination == SBI_ICLK) |
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245 | tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR; |
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246 | else |
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247 | tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR; |
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248 | I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp); |
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249 | |||
250 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
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251 | 100)) { |
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252 | DRM_ERROR("timeout waiting for SBI to complete write transaction\n"); |
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253 | return; |
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254 | } |
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255 | } |
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4560 | Serge | 256 | |
257 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg) |
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258 | { |
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259 | u32 val = 0; |
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5060 | serge | 260 | vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP, |
261 | reg, &val); |
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4560 | Serge | 262 | return val; |
263 | } |
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264 | |||
265 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
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266 | { |
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5060 | serge | 267 | vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP, |
268 | reg, &val); |
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4560 | Serge | 269 | }><>><>><>><>><>><>><> |