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4104 | Serge | 1 | /* |
2 | * Copyright © 2013 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | */ |
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24 | |||
25 | #include "i915_drv.h" |
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26 | #include "intel_drv.h" |
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27 | |||
4560 | Serge | 28 | /* |
29 | * IOSF sideband, see VLV2_SidebandMsg_HAS.docx and |
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30 | * VLV_VLV2_PUNIT_HAS_0.8.docx |
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31 | */ |
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4104 | Serge | 32 | static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn, |
33 | u32 port, u32 opcode, u32 addr, u32 *val) |
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34 | { |
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35 | u32 cmd, be = 0xf, bar = 0; |
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36 | bool is_read = (opcode == PUNIT_OPCODE_REG_READ || |
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37 | opcode == DPIO_OPCODE_REG_READ); |
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38 | |||
39 | cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) | |
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40 | (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) | |
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41 | (bar << IOSF_BAR_SHIFT); |
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42 | |||
43 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
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44 | |||
45 | if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) { |
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46 | DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n", |
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47 | is_read ? "read" : "write"); |
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48 | return -EAGAIN; |
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49 | } |
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50 | |||
51 | I915_WRITE(VLV_IOSF_ADDR, addr); |
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52 | if (!is_read) |
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53 | I915_WRITE(VLV_IOSF_DATA, *val); |
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54 | I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd); |
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55 | |||
56 | if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) { |
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57 | DRM_DEBUG_DRIVER("IOSF sideband finish wait (%s) timed out\n", |
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58 | is_read ? "read" : "write"); |
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59 | return -ETIMEDOUT; |
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60 | } |
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61 | |||
62 | if (is_read) |
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63 | *val = I915_READ(VLV_IOSF_DATA); |
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64 | I915_WRITE(VLV_IOSF_DATA, 0); |
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65 | |||
66 | return 0; |
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67 | } |
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68 | |||
69 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr) |
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70 | { |
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71 | u32 val = 0; |
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72 | |||
73 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
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74 | |||
75 | mutex_lock(&dev_priv->dpio_lock); |
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76 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT, |
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77 | PUNIT_OPCODE_REG_READ, addr, &val); |
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78 | mutex_unlock(&dev_priv->dpio_lock); |
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79 | |||
80 | return val; |
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81 | } |
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82 | |||
83 | void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val) |
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84 | { |
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85 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
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86 | |||
87 | mutex_lock(&dev_priv->dpio_lock); |
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88 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT, |
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89 | PUNIT_OPCODE_REG_WRITE, addr, &val); |
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90 | mutex_unlock(&dev_priv->dpio_lock); |
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91 | } |
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92 | |||
4560 | Serge | 93 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg) |
94 | { |
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95 | u32 val = 0; |
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96 | |||
97 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT, |
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98 | PUNIT_OPCODE_REG_READ, reg, &val); |
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99 | |||
100 | return val; |
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101 | } |
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102 | |||
103 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
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104 | { |
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105 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT, |
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106 | PUNIT_OPCODE_REG_WRITE, reg, &val); |
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107 | } |
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108 | |||
4104 | Serge | 109 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr) |
110 | { |
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111 | u32 val = 0; |
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112 | |||
113 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
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114 | |||
115 | mutex_lock(&dev_priv->dpio_lock); |
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116 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_NC, |
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117 | PUNIT_OPCODE_REG_READ, addr, &val); |
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118 | mutex_unlock(&dev_priv->dpio_lock); |
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119 | |||
120 | return val; |
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121 | } |
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122 | |||
4560 | Serge | 123 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg) |
4104 | Serge | 124 | { |
125 | u32 val = 0; |
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4560 | Serge | 126 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC, |
127 | PUNIT_OPCODE_REG_READ, reg, &val); |
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128 | return val; |
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129 | } |
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4104 | Serge | 130 | |
4560 | Serge | 131 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
132 | { |
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133 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC, |
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134 | PUNIT_OPCODE_REG_WRITE, reg, &val); |
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135 | } |
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4104 | Serge | 136 | |
4560 | Serge | 137 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg) |
138 | { |
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139 | u32 val = 0; |
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140 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK, |
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141 | PUNIT_OPCODE_REG_READ, reg, &val); |
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4104 | Serge | 142 | return val; |
143 | } |
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144 | |||
4560 | Serge | 145 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
4104 | Serge | 146 | { |
4560 | Serge | 147 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK, |
148 | PUNIT_OPCODE_REG_WRITE, reg, &val); |
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149 | } |
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150 | |||
151 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg) |
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152 | { |
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153 | u32 val = 0; |
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154 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU, |
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155 | PUNIT_OPCODE_REG_READ, reg, &val); |
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156 | return val; |
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157 | } |
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158 | |||
159 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
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160 | { |
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161 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU, |
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162 | PUNIT_OPCODE_REG_WRITE, reg, &val); |
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163 | } |
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164 | |||
165 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg) |
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166 | { |
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167 | u32 val = 0; |
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168 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE, |
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169 | PUNIT_OPCODE_REG_READ, reg, &val); |
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170 | return val; |
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171 | } |
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172 | |||
173 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
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174 | { |
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175 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE, |
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176 | PUNIT_OPCODE_REG_WRITE, reg, &val); |
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177 | } |
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178 | |||
179 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg) |
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180 | { |
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181 | u32 val = 0; |
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182 | |||
183 | vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)), |
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184 | DPIO_OPCODE_REG_READ, reg, &val); |
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185 | return val; |
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186 | } |
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187 | |||
188 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val) |
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189 | { |
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190 | vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)), |
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4104 | Serge | 191 | DPIO_OPCODE_REG_WRITE, reg, &val); |
192 | } |
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193 | |||
194 | /* SBI access */ |
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195 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
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196 | enum intel_sbi_destination destination) |
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197 | { |
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198 | u32 value = 0; |
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199 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
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200 | |||
201 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
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202 | 100)) { |
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203 | DRM_ERROR("timeout waiting for SBI to become ready\n"); |
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204 | return 0; |
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205 | } |
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206 | |||
207 | I915_WRITE(SBI_ADDR, (reg << 16)); |
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208 | |||
209 | if (destination == SBI_ICLK) |
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210 | value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD; |
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211 | else |
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212 | value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD; |
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213 | I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY); |
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214 | |||
215 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
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216 | 100)) { |
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217 | DRM_ERROR("timeout waiting for SBI to complete read transaction\n"); |
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218 | return 0; |
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219 | } |
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220 | |||
221 | return I915_READ(SBI_DATA); |
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222 | } |
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223 | |||
224 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, |
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225 | enum intel_sbi_destination destination) |
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226 | { |
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227 | u32 tmp; |
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228 | |||
229 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
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230 | |||
231 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
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232 | 100)) { |
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233 | DRM_ERROR("timeout waiting for SBI to become ready\n"); |
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234 | return; |
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235 | } |
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236 | |||
237 | I915_WRITE(SBI_ADDR, (reg << 16)); |
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238 | I915_WRITE(SBI_DATA, value); |
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239 | |||
240 | if (destination == SBI_ICLK) |
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241 | tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR; |
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242 | else |
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243 | tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR; |
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244 | I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp); |
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245 | |||
246 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
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247 | 100)) { |
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248 | DRM_ERROR("timeout waiting for SBI to complete write transaction\n"); |
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249 | return; |
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250 | } |
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251 | } |
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4560 | Serge | 252 | |
253 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg) |
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254 | { |
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255 | u32 val = 0; |
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256 | vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, |
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257 | DPIO_OPCODE_REG_READ, reg, &val); |
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258 | return val; |
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259 | } |
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260 | |||
261 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
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262 | { |
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263 | vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, |
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264 | DPIO_OPCODE_REG_WRITE, reg, &val); |
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265 | }><>><>><>><>><>><>><> |