WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/intel_sdvo.c

Rev	Author	Line No.	Line
2330	Serge	1	/*
		2	* Copyright 2006 Dave Airlie
		3	* Copyright © 2006-2007 Intel Corporation
		4	* Jesse Barnes
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice (including the next
		14	* paragraph) shall be included in all copies or substantial portions of the
		15	* Software.
		16	*
		17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		22	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
		23	* DEALINGS IN THE SOFTWARE.
		24	*
		25	* Authors:
6084	serge	26	* Eric Anholt
2330	Serge	27	*/
		28	#include
		29	#include
3243	Serge	30	#include
3031	serge	31	#include
		32	#include
6084	serge	33	#include
3031	serge	34	#include
		35	#include
2330	Serge	36	#include "intel_drv.h"
3031	serge	37	#include
2330	Serge	38	#include "i915_drv.h"
		39	#include "intel_sdvo_regs.h"
		40
		41	#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 \| SDVO_OUTPUT_TMDS1)
		42	#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 \| SDVO_OUTPUT_RGB1)
		43	#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 \| SDVO_OUTPUT_LVDS1)
3031	serge	44	#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 \| SDVO_OUTPUT_SVID0 \| SDVO_OUTPUT_YPRPB0)
2330	Serge	45
		46	#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK \| SDVO_RGB_MASK \| SDVO_LVDS_MASK \|\
6084	serge	47	SDVO_TV_MASK)
2330	Serge	48
6084	serge	49	#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
		50	#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
		51	#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
2330	Serge	52	#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK \| SDVO_LVDS_MASK))
2342	Serge	53	#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK \| SDVO_LVDS_MASK))
2330	Serge	54
		55
6084	serge	56	static const char * const tv_format_names[] = {
		57	"NTSC_M" , "NTSC_J" , "NTSC_443",
		58	"PAL_B" , "PAL_D" , "PAL_G" ,
		59	"PAL_H" , "PAL_I" , "PAL_M" ,
		60	"PAL_N" , "PAL_NC" , "PAL_60" ,
		61	"SECAM_B" , "SECAM_D" , "SECAM_G" ,
		62	"SECAM_K" , "SECAM_K1", "SECAM_L" ,
		63	"SECAM_60"
2330	Serge	64	};
		65
6084	serge	66	#define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names)
2330	Serge	67
		68	struct intel_sdvo {
6084	serge	69	struct intel_encoder base;
2330	Serge	70
6084	serge	71	struct i2c_adapter *i2c;
		72	u8 slave_addr;
2330	Serge	73
6084	serge	74	struct i2c_adapter ddc;
2330	Serge	75
6084	serge	76	/* Register for the SDVO device: SDVOB or SDVOC */
3031	serge	77	uint32_t sdvo_reg;
2330	Serge	78
6084	serge	79	/* Active outputs controlled by this SDVO output */
		80	uint16_t controlled_output;
2330	Serge	81
6084	serge	82	/*
		83	* Capabilities of the SDVO device returned by
4104	Serge	84	* intel_sdvo_get_capabilities()
6084	serge	85	*/
		86	struct intel_sdvo_caps caps;
2330	Serge	87
6084	serge	88	/* Pixel clock limitations reported by the SDVO device, in kHz */
		89	int pixel_clock_min, pixel_clock_max;
2330	Serge	90
6084	serge	91	/*
		92	* For multiple function SDVO device,
		93	* this is for current attached outputs.
		94	*/
		95	uint16_t attached_output;
2330	Serge	96
2342	Serge	97	/*
		98	* Hotplug activation bits for this device
		99	*/
3031	serge	100	uint16_t hotplug_active;
2342	Serge	101
6084	serge	102	/**
		103	* This is used to select the color range of RBG outputs in HDMI mode.
		104	* It is only valid when using TMDS encoding and 8 bit per color mode.
		105	*/
		106	uint32_t color_range;
3480	Serge	107	bool color_range_auto;
2330	Serge	108
6084	serge	109	/**
		110	* HDMI user specified aspect ratio
		111	*/
		112	enum hdmi_picture_aspect aspect_ratio;
2330	Serge	113
6084	serge	114	/**
		115	* This is set if we're going to treat the device as TV-out.
		116	*
		117	* While we have these nice friendly flags for output types that ought
		118	* to decide this for us, the S-Video output on our HDMI+S-Video card
		119	* shows up as RGB1 (VGA).
		120	*/
		121	bool is_tv;
		122
3031	serge	123	/* On different gens SDVOB is at different places. */
		124	bool is_sdvob;
		125
6084	serge	126	/* This is for current tv format name */
		127	int tv_format_index;
2330	Serge	128
6084	serge	129	/**
		130	* This is set if we treat the device as HDMI, instead of DVI.
		131	*/
		132	bool is_hdmi;
		133	bool has_hdmi_monitor;
		134	bool has_hdmi_audio;
3480	Serge	135	bool rgb_quant_range_selectable;
2330	Serge	136
6084	serge	137	/**
		138	* This is set if we detect output of sdvo device as LVDS and
		139	* have a valid fixed mode to use with the panel.
		140	*/
		141	bool is_lvds;
2330	Serge	142
6084	serge	143	/**
		144	* This is sdvo fixed pannel mode pointer
		145	*/
		146	struct drm_display_mode *sdvo_lvds_fixed_mode;
2330	Serge	147
6084	serge	148	/* DDC bus used by this SDVO encoder */
		149	uint8_t ddc_bus;
2330	Serge	150
3031	serge	151	/*
		152	* the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
		153	*/
		154	uint8_t dtd_sdvo_flags;
2330	Serge	155	};
		156
		157	struct intel_sdvo_connector {
6084	serge	158	struct intel_connector base;
2330	Serge	159
6084	serge	160	/* Mark the type of connector */
		161	uint16_t output_flag;
2330	Serge	162
3031	serge	163	enum hdmi_force_audio force_audio;
2330	Serge	164
6084	serge	165	/* This contains all current supported TV format */
		166	u8 tv_format_supported[TV_FORMAT_NUM];
		167	int format_supported_num;
		168	struct drm_property *tv_format;
2330	Serge	169
6084	serge	170	/* add the property for the SDVO-TV */
		171	struct drm_property *left;
		172	struct drm_property *right;
		173	struct drm_property *top;
		174	struct drm_property *bottom;
		175	struct drm_property *hpos;
		176	struct drm_property *vpos;
		177	struct drm_property *contrast;
		178	struct drm_property *saturation;
		179	struct drm_property *hue;
		180	struct drm_property *sharpness;
		181	struct drm_property *flicker_filter;
		182	struct drm_property *flicker_filter_adaptive;
		183	struct drm_property *flicker_filter_2d;
		184	struct drm_property *tv_chroma_filter;
		185	struct drm_property *tv_luma_filter;
		186	struct drm_property *dot_crawl;
2330	Serge	187
6084	serge	188	/* add the property for the SDVO-TV/LVDS */
		189	struct drm_property *brightness;
2330	Serge	190
6084	serge	191	/* Add variable to record current setting for the above property */
		192	u32 left_margin, right_margin, top_margin, bottom_margin;
2330	Serge	193
6084	serge	194	/* this is to get the range of margin.*/
		195	u32 max_hscan, max_vscan;
		196	u32 max_hpos, cur_hpos;
		197	u32 max_vpos, cur_vpos;
		198	u32 cur_brightness, max_brightness;
		199	u32 cur_contrast, max_contrast;
		200	u32 cur_saturation, max_saturation;
		201	u32 cur_hue, max_hue;
		202	u32 cur_sharpness, max_sharpness;
		203	u32 cur_flicker_filter, max_flicker_filter;
		204	u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
		205	u32 cur_flicker_filter_2d, max_flicker_filter_2d;
		206	u32 cur_tv_chroma_filter, max_tv_chroma_filter;
		207	u32 cur_tv_luma_filter, max_tv_luma_filter;
		208	u32 cur_dot_crawl, max_dot_crawl;
2330	Serge	209	};
		210
4104	Serge	211	static struct intel_sdvo to_sdvo(struct intel_encoder encoder)
2330	Serge	212	{
4104	Serge	213	return container_of(encoder, struct intel_sdvo, base);
2330	Serge	214	}
		215
		216	static struct intel_sdvo intel_attached_sdvo(struct drm_connector connector)
		217	{
4104	Serge	218	return to_sdvo(intel_attached_encoder(connector));
2330	Serge	219	}
		220
		221	static struct intel_sdvo_connector to_intel_sdvo_connector(struct drm_connector connector)
		222	{
		223	return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
		224	}
		225
		226	static bool
		227	intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
		228	static bool
		229	intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
		230	struct intel_sdvo_connector *intel_sdvo_connector,
		231	int type);
		232	static bool
		233	intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
		234	struct intel_sdvo_connector *intel_sdvo_connector);
		235
		236	/**
		237	* Writes the SDVOB or SDVOC with the given value, but always writes both
		238	* SDVOB and SDVOC to work around apparent hardware issues (according to
		239	* comments in the BIOS).
		240	*/
		241	static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
		242	{
		243	struct drm_device *dev = intel_sdvo->base.base.dev;
		244	struct drm_i915_private *dev_priv = dev->dev_private;
		245	u32 bval = val, cval = val;
		246	int i;
		247
		248	if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
		249	I915_WRITE(intel_sdvo->sdvo_reg, val);
6084	serge	250	POSTING_READ(intel_sdvo->sdvo_reg);
		251	/*
		252	* HW workaround, need to write this twice for issue
		253	* that may result in first write getting masked.
		254	*/
		255	if (HAS_PCH_IBX(dev)) {
		256	I915_WRITE(intel_sdvo->sdvo_reg, val);
		257	POSTING_READ(intel_sdvo->sdvo_reg);
		258	}
2330	Serge	259	return;
		260	}
		261
3746	Serge	262	if (intel_sdvo->sdvo_reg == GEN3_SDVOB)
		263	cval = I915_READ(GEN3_SDVOC);
		264	else
		265	bval = I915_READ(GEN3_SDVOB);
		266
2330	Serge	267	/*
		268	* Write the registers twice for luck. Sometimes,
		269	* writing them only once doesn't appear to 'stick'.
		270	* The BIOS does this too. Yay, magic
		271	*/
		272	for (i = 0; i < 2; i++)
		273	{
3746	Serge	274	I915_WRITE(GEN3_SDVOB, bval);
6084	serge	275	POSTING_READ(GEN3_SDVOB);
3746	Serge	276	I915_WRITE(GEN3_SDVOC, cval);
6084	serge	277	POSTING_READ(GEN3_SDVOC);
2330	Serge	278	}
		279	}
		280
		281	static bool intel_sdvo_read_byte(struct intel_sdvo intel_sdvo, u8 addr, u8 ch)
		282	{
		283	struct i2c_msg msgs[] = {
		284	{
		285	.addr = intel_sdvo->slave_addr,
		286	.flags = 0,
		287	.len = 1,
		288	.buf = &addr,
		289	},
		290	{
		291	.addr = intel_sdvo->slave_addr,
		292	.flags = I2C_M_RD,
		293	.len = 1,
		294	.buf = ch,
		295	}
		296	};
		297	int ret;
		298
		299	if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
		300	return true;
		301
		302	DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
		303	return false;
		304	}
		305
		306	#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
		307	/** Mapping of command numbers to names, for debug output */
		308	static const struct _sdvo_cmd_name {
		309	u8 cmd;
		310	const char *name;
		311	} sdvo_cmd_names[] = {
6084	serge	312	SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
		313	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
		314	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
		315	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
		316	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
		317	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
		318	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
		319	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
		320	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
		321	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
		322	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
		323	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
		324	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
		325	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
		326	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
		327	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
		328	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
		329	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
		330	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
		331	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
		332	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
		333	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
		334	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
		335	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
		336	SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
		337	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
		338	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
		339	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
		340	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
		341	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
		342	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
		343	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
		344	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
		345	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
		346	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
		347	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
		348	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
		349	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
		350	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
		351	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
		352	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
		353	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
		354	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
2330	Serge	355
6084	serge	356	/* Add the op code for SDVO enhancements */
		357	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
		358	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
		359	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
		360	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
		361	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
		362	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
		363	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
		364	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
		365	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
		366	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
		367	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
		368	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
		369	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
		370	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
		371	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
		372	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
		373	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
		374	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
		375	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
		376	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
		377	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
		378	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
		379	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
		380	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
		381	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
		382	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
		383	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
		384	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
		385	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
		386	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
		387	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
		388	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
		389	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
		390	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
		391	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
		392	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
		393	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
		394	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
		395	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
		396	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
		397	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
		398	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
		399	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
		400	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
2330	Serge	401
6084	serge	402	/* HDMI op code */
		403	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
		404	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
		405	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
		406	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
		407	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
		408	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
		409	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
		410	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
		411	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
		412	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
		413	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
		414	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
		415	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
		416	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
		417	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
		418	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
		419	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
		420	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
		421	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
		422	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
2330	Serge	423	};
		424
3031	serge	425	#define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
2330	Serge	426
		427	static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
		428	const void *args, int args_len)
		429	{
4560	Serge	430	int i, pos = 0;
		431	#define BUF_LEN 256
		432	char buffer[BUF_LEN];
2330	Serge	433
4560	Serge	434	#define BUF_PRINT(args...) \
		435	pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
		436
		437
		438	for (i = 0; i < args_len; i++) {
		439	BUF_PRINT("%02X ", ((u8 *)args)[i]);
		440	}
		441	for (; i < 8; i++) {
		442	BUF_PRINT(" ");
		443	}
2330	Serge	444	for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
		445	if (cmd == sdvo_cmd_names[i].cmd) {
4560	Serge	446	BUF_PRINT("(%s)", sdvo_cmd_names[i].name);
2330	Serge	447	break;
		448	}
		449	}
4560	Serge	450	if (i == ARRAY_SIZE(sdvo_cmd_names)) {
		451	BUF_PRINT("(%02X)", cmd);
		452	}
		453	BUG_ON(pos >= BUF_LEN - 1);
		454	#undef BUF_PRINT
		455	#undef BUF_LEN
		456
		457	DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
2330	Serge	458	}
		459
6084	serge	460	static const char * const cmd_status_names[] = {
2330	Serge	461	"Power on",
		462	"Success",
		463	"Not supported",
		464	"Invalid arg",
		465	"Pending",
		466	"Target not specified",
		467	"Scaling not supported"
		468	};
		469
		470	static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
		471	const void *args, int args_len)
		472	{
3031	serge	473	u8 *buf, status;
		474	struct i2c_msg *msgs;
		475	int i, ret = true;
2330	Serge	476
3031	serge	477	/* Would be simpler to allocate both in one go ? */
3746	Serge	478	buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
3031	serge	479	if (!buf)
		480	return false;
		481
		482	msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
		483	if (!msgs) {
		484	kfree(buf);
		485	return false;
		486	}
		487
2330	Serge	488	intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
		489
		490	for (i = 0; i < args_len; i++) {
		491	msgs[i].addr = intel_sdvo->slave_addr;
		492	msgs[i].flags = 0;
		493	msgs[i].len = 2;
		494	msgs[i].buf = buf + 2 *i;
		495	buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
		496	buf[2i + 1] = ((u8)args)[i];
		497	}
		498	msgs[i].addr = intel_sdvo->slave_addr;
		499	msgs[i].flags = 0;
		500	msgs[i].len = 2;
		501	msgs[i].buf = buf + 2*i;
		502	buf[2*i + 0] = SDVO_I2C_OPCODE;
		503	buf[2*i + 1] = cmd;
		504
		505	/* the following two are to read the response */
		506	status = SDVO_I2C_CMD_STATUS;
		507	msgs[i+1].addr = intel_sdvo->slave_addr;
		508	msgs[i+1].flags = 0;
		509	msgs[i+1].len = 1;
		510	msgs[i+1].buf = &status;
		511
		512	msgs[i+2].addr = intel_sdvo->slave_addr;
		513	msgs[i+2].flags = I2C_M_RD;
		514	msgs[i+2].len = 1;
		515	msgs[i+2].buf = &status;
		516
		517	ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
		518	if (ret < 0) {
		519	DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3031	serge	520	ret = false;
		521	goto out;
2330	Serge	522	}
		523	if (ret != i+3) {
		524	/* failure in I2C transfer */
		525	DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3031	serge	526	ret = false;
2330	Serge	527	}
		528
3031	serge	529	out:
		530	kfree(msgs);
		531	kfree(buf);
		532	return ret;
2330	Serge	533	}
		534
		535	static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
		536	void *response, int response_len)
		537	{
3243	Serge	538	u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
2330	Serge	539	u8 status;
4560	Serge	540	int i, pos = 0;
		541	#define BUF_LEN 256
		542	char buffer[BUF_LEN];
2330	Serge	543
		544
		545	/*
		546	* The documentation states that all commands will be
		547	* processed within 15µs, and that we need only poll
		548	* the status byte a maximum of 3 times in order for the
		549	* command to be complete.
		550	*
		551	* Check 5 times in case the hardware failed to read the docs.
3243	Serge	552	*
		553	* Also beware that the first response by many devices is to
		554	* reply PENDING and stall for time. TVs are notorious for
		555	* requiring longer than specified to complete their replies.
		556	* Originally (in the DDX long ago), the delay was only ever 15ms
		557	* with an additional delay of 30ms applied for TVs added later after
		558	* many experiments. To accommodate both sets of delays, we do a
		559	* sequence of slow checks if the device is falling behind and fails
		560	* to reply within 5*15µs.
2330	Serge	561	*/
		562	if (!intel_sdvo_read_byte(intel_sdvo,
		563	SDVO_I2C_CMD_STATUS,
		564	&status))
		565	goto log_fail;
		566
4104	Serge	567	while ((status == SDVO_CMD_STATUS_PENDING \|\|
6084	serge	568	status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
3243	Serge	569	if (retry < 10)
		570	msleep(15);
		571	else
		572	udelay(15);
		573
2330	Serge	574	if (!intel_sdvo_read_byte(intel_sdvo,
		575	SDVO_I2C_CMD_STATUS,
		576	&status))
		577	goto log_fail;
		578	}
		579
4560	Serge	580	#define BUF_PRINT(args...) \
		581	pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
		582
2330	Serge	583	if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
4560	Serge	584	BUF_PRINT("(%s)", cmd_status_names[status]);
2330	Serge	585	else
4560	Serge	586	BUF_PRINT("(??? %d)", status);
2330	Serge	587
		588	if (status != SDVO_CMD_STATUS_SUCCESS)
		589	goto log_fail;
		590
		591	/* Read the command response */
		592	for (i = 0; i < response_len; i++) {
		593	if (!intel_sdvo_read_byte(intel_sdvo,
		594	SDVO_I2C_RETURN_0 + i,
		595	&((u8 *)response)[i]))
		596	goto log_fail;
4560	Serge	597	BUF_PRINT(" %02X", ((u8 *)response)[i]);
2330	Serge	598	}
4560	Serge	599	BUG_ON(pos >= BUF_LEN - 1);
		600	#undef BUF_PRINT
		601	#undef BUF_LEN
		602
		603	DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
2330	Serge	604	return true;
		605
		606	log_fail:
4560	Serge	607	DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo));
2330	Serge	608	return false;
		609	}
		610
6084	serge	611	static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode)
2330	Serge	612	{
6084	serge	613	if (adjusted_mode->crtc_clock >= 100000)
2330	Serge	614	return 1;
6084	serge	615	else if (adjusted_mode->crtc_clock >= 50000)
2330	Serge	616	return 2;
		617	else
		618	return 4;
		619	}
		620
		621	static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
		622	u8 ddc_bus)
		623	{
		624	/* This must be the immediately preceding write before the i2c xfer */
		625	return intel_sdvo_write_cmd(intel_sdvo,
		626	SDVO_CMD_SET_CONTROL_BUS_SWITCH,
		627	&ddc_bus, 1);
		628	}
		629
		630	static bool intel_sdvo_set_value(struct intel_sdvo intel_sdvo, u8 cmd, const void data, int len)
		631	{
		632	if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
		633	return false;
		634
		635	return intel_sdvo_read_response(intel_sdvo, NULL, 0);
		636	}
		637
		638	static bool
		639	intel_sdvo_get_value(struct intel_sdvo intel_sdvo, u8 cmd, void value, int len)
		640	{
		641	if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
		642	return false;
		643
		644	return intel_sdvo_read_response(intel_sdvo, value, len);
		645	}
		646
		647	static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
		648	{
		649	struct intel_sdvo_set_target_input_args targets = {0};
		650	return intel_sdvo_set_value(intel_sdvo,
		651	SDVO_CMD_SET_TARGET_INPUT,
		652	&targets, sizeof(targets));
		653	}
		654
		655	/**
		656	* Return whether each input is trained.
		657	*
		658	* This function is making an assumption about the layout of the response,
		659	* which should be checked against the docs.
		660	*/
		661	static bool intel_sdvo_get_trained_inputs(struct intel_sdvo intel_sdvo, bool input_1, bool *input_2)
		662	{
		663	struct intel_sdvo_get_trained_inputs_response response;
		664
		665	BUILD_BUG_ON(sizeof(response) != 1);
		666	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
		667	&response, sizeof(response)))
		668	return false;
		669
		670	*input_1 = response.input0_trained;
		671	*input_2 = response.input1_trained;
		672	return true;
		673	}
		674
		675	static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
		676	u16 outputs)
		677	{
		678	return intel_sdvo_set_value(intel_sdvo,
		679	SDVO_CMD_SET_ACTIVE_OUTPUTS,
		680	&outputs, sizeof(outputs));
		681	}
		682
3031	serge	683	static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
		684	u16 *outputs)
		685	{
		686	return intel_sdvo_get_value(intel_sdvo,
		687	SDVO_CMD_GET_ACTIVE_OUTPUTS,
		688	outputs, sizeof(*outputs));
		689	}
		690
2340	Serge	691	static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
		692	int mode)
		693	{
		694	u8 state = SDVO_ENCODER_STATE_ON;
2330	Serge	695
2340	Serge	696	switch (mode) {
		697	case DRM_MODE_DPMS_ON:
		698	state = SDVO_ENCODER_STATE_ON;
		699	break;
		700	case DRM_MODE_DPMS_STANDBY:
		701	state = SDVO_ENCODER_STATE_STANDBY;
		702	break;
		703	case DRM_MODE_DPMS_SUSPEND:
		704	state = SDVO_ENCODER_STATE_SUSPEND;
		705	break;
		706	case DRM_MODE_DPMS_OFF:
		707	state = SDVO_ENCODER_STATE_OFF;
		708	break;
		709	}
2330	Serge	710
2340	Serge	711	return intel_sdvo_set_value(intel_sdvo,
		712	SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
		713	}
2330	Serge	714
		715	static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
		716	int *clock_min,
		717	int *clock_max)
		718	{
		719	struct intel_sdvo_pixel_clock_range clocks;
		720
		721	BUILD_BUG_ON(sizeof(clocks) != 4);
		722	if (!intel_sdvo_get_value(intel_sdvo,
		723	SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
		724	&clocks, sizeof(clocks)))
		725	return false;
		726
		727	/* Convert the values from units of 10 kHz to kHz. */
		728	clock_min = clocks.min 10;
		729	clock_max = clocks.max 10;
		730	return true;
		731	}
		732
		733	static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
		734	u16 outputs)
		735	{
		736	return intel_sdvo_set_value(intel_sdvo,
		737	SDVO_CMD_SET_TARGET_OUTPUT,
		738	&outputs, sizeof(outputs));
		739	}
		740
		741	static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
		742	struct intel_sdvo_dtd *dtd)
		743	{
		744	return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
		745	intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
		746	}
		747
4104	Serge	748	static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
		749	struct intel_sdvo_dtd *dtd)
		750	{
		751	return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
		752	intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
		753	}
		754
2330	Serge	755	static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
		756	struct intel_sdvo_dtd *dtd)
		757	{
		758	return intel_sdvo_set_timing(intel_sdvo,
		759	SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
		760	}
		761
		762	static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
		763	struct intel_sdvo_dtd *dtd)
		764	{
		765	return intel_sdvo_set_timing(intel_sdvo,
		766	SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
		767	}
		768
4104	Serge	769	static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
		770	struct intel_sdvo_dtd *dtd)
		771	{
		772	return intel_sdvo_get_timing(intel_sdvo,
		773	SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
		774	}
		775
2330	Serge	776	static bool
		777	intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
		778	uint16_t clock,
		779	uint16_t width,
		780	uint16_t height)
		781	{
		782	struct intel_sdvo_preferred_input_timing_args args;
		783
		784	memset(&args, 0, sizeof(args));
		785	args.clock = clock;
		786	args.width = width;
		787	args.height = height;
		788	args.interlace = 0;
		789
		790	if (intel_sdvo->is_lvds &&
		791	(intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width \|\|
		792	intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
		793	args.scaled = 1;
		794
		795	return intel_sdvo_set_value(intel_sdvo,
		796	SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
		797	&args, sizeof(args));
		798	}
		799
		800	static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
		801	struct intel_sdvo_dtd *dtd)
		802	{
		803	BUILD_BUG_ON(sizeof(dtd->part1) != 8);
		804	BUILD_BUG_ON(sizeof(dtd->part2) != 8);
		805	return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
		806	&dtd->part1, sizeof(dtd->part1)) &&
		807	intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
		808	&dtd->part2, sizeof(dtd->part2));
		809	}
		810
		811	static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
		812	{
		813	return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
		814	}
		815
		816	static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
		817	const struct drm_display_mode *mode)
		818	{
		819	uint16_t width, height;
		820	uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
		821	uint16_t h_sync_offset, v_sync_offset;
3031	serge	822	int mode_clock;
2330	Serge	823
4104	Serge	824	memset(dtd, 0, sizeof(*dtd));
		825
3031	serge	826	width = mode->hdisplay;
		827	height = mode->vdisplay;
2330	Serge	828
		829	/* do some mode translations */
3031	serge	830	h_blank_len = mode->htotal - mode->hdisplay;
		831	h_sync_len = mode->hsync_end - mode->hsync_start;
2330	Serge	832
3031	serge	833	v_blank_len = mode->vtotal - mode->vdisplay;
		834	v_sync_len = mode->vsync_end - mode->vsync_start;
2330	Serge	835
3031	serge	836	h_sync_offset = mode->hsync_start - mode->hdisplay;
		837	v_sync_offset = mode->vsync_start - mode->vdisplay;
2330	Serge	838
3031	serge	839	mode_clock = mode->clock;
		840	mode_clock /= 10;
		841	dtd->part1.clock = mode_clock;
		842
2330	Serge	843	dtd->part1.h_active = width & 0xff;
		844	dtd->part1.h_blank = h_blank_len & 0xff;
		845	dtd->part1.h_high = (((width >> 8) & 0xf) << 4) \|
		846	((h_blank_len >> 8) & 0xf);
		847	dtd->part1.v_active = height & 0xff;
		848	dtd->part1.v_blank = v_blank_len & 0xff;
		849	dtd->part1.v_high = (((height >> 8) & 0xf) << 4) \|
		850	((v_blank_len >> 8) & 0xf);
		851
		852	dtd->part2.h_sync_off = h_sync_offset & 0xff;
		853	dtd->part2.h_sync_width = h_sync_len & 0xff;
		854	dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 \|
		855	(v_sync_len & 0xf);
		856	dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) \|
		857	((h_sync_len & 0x300) >> 4) \| ((v_sync_offset & 0x30) >> 2) \|
		858	((v_sync_len & 0x30) >> 4);
		859
		860	dtd->part2.dtd_flags = 0x18;
3031	serge	861	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		862	dtd->part2.dtd_flags \|= DTD_FLAG_INTERLACE;
2330	Serge	863	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
3031	serge	864	dtd->part2.dtd_flags \|= DTD_FLAG_HSYNC_POSITIVE;
2330	Serge	865	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
3031	serge	866	dtd->part2.dtd_flags \|= DTD_FLAG_VSYNC_POSITIVE;
2330	Serge	867
		868	dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
		869	}
		870
4104	Serge	871	static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
2330	Serge	872	const struct intel_sdvo_dtd *dtd)
		873	{
4104	Serge	874	struct drm_display_mode mode = {};
2330	Serge	875
4104	Serge	876	mode.hdisplay = dtd->part1.h_active;
		877	mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
		878	mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
		879	mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
		880	mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
		881	mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
		882	mode.htotal = mode.hdisplay + dtd->part1.h_blank;
		883	mode.htotal += (dtd->part1.h_high & 0xf) << 8;
		884
		885	mode.vdisplay = dtd->part1.v_active;
		886	mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
		887	mode.vsync_start = mode.vdisplay;
		888	mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
		889	mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
		890	mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
		891	mode.vsync_end = mode.vsync_start +
2330	Serge	892	(dtd->part2.v_sync_off_width & 0xf);
4104	Serge	893	mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
		894	mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
		895	mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
2330	Serge	896
4104	Serge	897	mode.clock = dtd->part1.clock * 10;
2330	Serge	898
3031	serge	899	if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
4104	Serge	900	mode.flags \|= DRM_MODE_FLAG_INTERLACE;
3031	serge	901	if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
4104	Serge	902	mode.flags \|= DRM_MODE_FLAG_PHSYNC;
		903	else
		904	mode.flags \|= DRM_MODE_FLAG_NHSYNC;
3031	serge	905	if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
4104	Serge	906	mode.flags \|= DRM_MODE_FLAG_PVSYNC;
		907	else
		908	mode.flags \|= DRM_MODE_FLAG_NVSYNC;
		909
		910	drm_mode_set_crtcinfo(&mode, 0);
		911
		912	drm_mode_copy(pmode, &mode);
2330	Serge	913	}
		914
		915	static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
		916	{
		917	struct intel_sdvo_encode encode;
		918
		919	BUILD_BUG_ON(sizeof(encode) != 2);
		920	return intel_sdvo_get_value(intel_sdvo,
		921	SDVO_CMD_GET_SUPP_ENCODE,
		922	&encode, sizeof(encode));
		923	}
		924
		925	static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
		926	uint8_t mode)
		927	{
		928	return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
		929	}
		930
		931	static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
		932	uint8_t mode)
		933	{
		934	return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
		935	}
		936
		937	#if 0
		938	static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
		939	{
		940	int i, j;
		941	uint8_t set_buf_index[2];
		942	uint8_t av_split;
		943	uint8_t buf_size;
		944	uint8_t buf[48];
		945	uint8_t *pos;
		946
		947	intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
		948
		949	for (i = 0; i <= av_split; i++) {
		950	set_buf_index[0] = i; set_buf_index[1] = 0;
		951	intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
		952	set_buf_index, 2);
		953	intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
		954	intel_sdvo_read_response(encoder, &buf_size, 1);
		955
		956	pos = buf;
		957	for (j = 0; j <= buf_size; j += 8) {
		958	intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
		959	NULL, 0);
		960	intel_sdvo_read_response(encoder, pos, 8);
		961	pos += 8;
		962	}
		963	}
		964	}
		965	#endif
		966
3031	serge	967	static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
		968	unsigned if_index, uint8_t tx_rate,
4560	Serge	969	const uint8_t *data, unsigned length)
2330	Serge	970	{
3031	serge	971	uint8_t set_buf_index[2] = { if_index, 0 };
		972	uint8_t hbuf_size, tmp[8];
		973	int i;
2330	Serge	974
		975	if (!intel_sdvo_set_value(intel_sdvo,
		976	SDVO_CMD_SET_HBUF_INDEX,
		977	set_buf_index, 2))
		978	return false;
		979
3031	serge	980	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
		981	&hbuf_size, 1))
		982	return false;
		983
		984	/* Buffer size is 0 based, hooray! */
		985	hbuf_size++;
		986
		987	DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
		988	if_index, length, hbuf_size);
		989
		990	for (i = 0; i < hbuf_size; i += 8) {
		991	memset(tmp, 0, 8);
		992	if (i < length)
		993	memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
		994
2330	Serge	995	if (!intel_sdvo_set_value(intel_sdvo,
		996	SDVO_CMD_SET_HBUF_DATA,
3031	serge	997	tmp, 8))
2330	Serge	998	return false;
		999	}
		1000
		1001	return intel_sdvo_set_value(intel_sdvo,
		1002	SDVO_CMD_SET_HBUF_TXRATE,
		1003	&tx_rate, 1);
		1004	}
		1005
3480	Serge	1006	static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
		1007	const struct drm_display_mode *adjusted_mode)
3031	serge	1008	{
4104	Serge	1009	uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
		1010	struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
		1011	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1012	union hdmi_infoframe frame;
		1013	int ret;
		1014	ssize_t len;
3031	serge	1015
4104	Serge	1016	ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
		1017	adjusted_mode);
		1018	if (ret < 0) {
		1019	DRM_ERROR("couldn't fill AVI infoframe\n");
		1020	return false;
		1021	}
		1022
3480	Serge	1023	if (intel_sdvo->rgb_quant_range_selectable) {
6084	serge	1024	if (intel_crtc->config->limited_color_range)
4104	Serge	1025	frame.avi.quantization_range =
		1026	HDMI_QUANTIZATION_RANGE_LIMITED;
3480	Serge	1027	else
4104	Serge	1028	frame.avi.quantization_range =
		1029	HDMI_QUANTIZATION_RANGE_FULL;
3480	Serge	1030	}
		1031
4104	Serge	1032	len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data));
		1033	if (len < 0)
		1034	return false;
3746	Serge	1035
3031	serge	1036	return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
		1037	SDVO_HBUF_TX_VSYNC,
		1038	sdvo_data, sizeof(sdvo_data));
		1039	}
		1040
2330	Serge	1041	static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
		1042	{
		1043	struct intel_sdvo_tv_format format;
		1044	uint32_t format_map;
		1045
		1046	format_map = 1 << intel_sdvo->tv_format_index;
		1047	memset(&format, 0, sizeof(format));
		1048	memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
		1049
		1050	BUILD_BUG_ON(sizeof(format) != 6);
		1051	return intel_sdvo_set_value(intel_sdvo,
		1052	SDVO_CMD_SET_TV_FORMAT,
		1053	&format, sizeof(format));
		1054	}
		1055
		1056	static bool
		1057	intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
3031	serge	1058	const struct drm_display_mode *mode)
2330	Serge	1059	{
		1060	struct intel_sdvo_dtd output_dtd;
		1061
		1062	if (!intel_sdvo_set_target_output(intel_sdvo,
		1063	intel_sdvo->attached_output))
		1064	return false;
		1065
		1066	intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
		1067	if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
		1068	return false;
		1069
		1070	return true;
		1071	}
		1072
3031	serge	1073	/* Asks the sdvo controller for the preferred input mode given the output mode.
		1074	* Unfortunately we have to set up the full output mode to do that. */
2330	Serge	1075	static bool
3031	serge	1076	intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
		1077	const struct drm_display_mode *mode,
6084	serge	1078	struct drm_display_mode *adjusted_mode)
2330	Serge	1079	{
3031	serge	1080	struct intel_sdvo_dtd input_dtd;
		1081
2330	Serge	1082	/* Reset the input timing to the screen. Assume always input 0. */
		1083	if (!intel_sdvo_set_target_input(intel_sdvo))
		1084	return false;
		1085
		1086	if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
		1087	mode->clock / 10,
		1088	mode->hdisplay,
		1089	mode->vdisplay))
		1090	return false;
		1091
		1092	if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
3031	serge	1093	&input_dtd))
2330	Serge	1094	return false;
		1095
3031	serge	1096	intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
		1097	intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
2330	Serge	1098
		1099	return true;
		1100	}
		1101
6084	serge	1102	static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
4104	Serge	1103	{
4560	Serge	1104	unsigned dotclock = pipe_config->port_clock;
4104	Serge	1105	struct dpll *clock = &pipe_config->dpll;
		1106
		1107	/* SDVO TV has fixed PLL values depend on its clock range,
		1108	this mirrors vbios setting. */
		1109	if (dotclock >= 100000 && dotclock < 140500) {
		1110	clock->p1 = 2;
		1111	clock->p2 = 10;
		1112	clock->n = 3;
		1113	clock->m1 = 16;
		1114	clock->m2 = 8;
		1115	} else if (dotclock >= 140500 && dotclock <= 200000) {
		1116	clock->p1 = 1;
		1117	clock->p2 = 10;
		1118	clock->n = 6;
		1119	clock->m1 = 12;
		1120	clock->m2 = 8;
		1121	} else {
		1122	WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
		1123	}
		1124
		1125	pipe_config->clock_set = true;
		1126	}
		1127
3746	Serge	1128	static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
6084	serge	1129	struct intel_crtc_state *pipe_config)
2330	Serge	1130	{
4104	Serge	1131	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
6084	serge	1132	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
		1133	struct drm_display_mode *mode = &pipe_config->base.mode;
2330	Serge	1134
3746	Serge	1135	DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
		1136	pipe_config->pipe_bpp = 8*3;
		1137
		1138	if (HAS_PCH_SPLIT(encoder->base.dev))
		1139	pipe_config->has_pch_encoder = true;
		1140
2330	Serge	1141	/* We need to construct preferred input timings based on our
		1142	* output timings. To do that, we have to set the output
		1143	* timings, even though this isn't really the right place in
		1144	* the sequence to do it. Oh well.
		1145	*/
		1146	if (intel_sdvo->is_tv) {
		1147	if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
		1148	return false;
		1149
3031	serge	1150	(void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
6084	serge	1151	mode,
		1152	adjusted_mode);
4104	Serge	1153	pipe_config->sdvo_tv_clock = true;
2330	Serge	1154	} else if (intel_sdvo->is_lvds) {
		1155	if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
		1156	intel_sdvo->sdvo_lvds_fixed_mode))
		1157	return false;
		1158
3031	serge	1159	(void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
6084	serge	1160	mode,
		1161	adjusted_mode);
2330	Serge	1162	}
		1163
		1164	/* Make the CRTC code factor in the SDVO pixel multiplier. The
		1165	* SDVO device will factor out the multiplier during mode_set.
		1166	*/
3746	Serge	1167	pipe_config->pixel_multiplier =
		1168	intel_sdvo_get_pixel_multiplier(adjusted_mode);
2330	Serge	1169
5060	serge	1170	pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor;
		1171
3480	Serge	1172	if (intel_sdvo->color_range_auto) {
		1173	/* See CEA-861-E - 5.1 Default Encoding Parameters */
3746	Serge	1174	/* FIXME: This bit is only valid when using TMDS encoding and 8
		1175	* bit per color mode. */
5060	serge	1176	if (pipe_config->has_hdmi_sink &&
3480	Serge	1177	drm_match_cea_mode(adjusted_mode) > 1)
5060	serge	1178	pipe_config->limited_color_range = true;
		1179	} else {
		1180	if (pipe_config->has_hdmi_sink &&
		1181	intel_sdvo->color_range == HDMI_COLOR_RANGE_16_235)
		1182	pipe_config->limited_color_range = true;
3480	Serge	1183	}
		1184
4104	Serge	1185	/* Clock computation needs to happen after pixel multiplier. */
		1186	if (intel_sdvo->is_tv)
		1187	i9xx_adjust_sdvo_tv_clock(pipe_config);
		1188
6084	serge	1189	/* Set user selected PAR to incoming mode's member */
		1190	if (intel_sdvo->is_hdmi)
		1191	adjusted_mode->picture_aspect_ratio = intel_sdvo->aspect_ratio;
		1192
2330	Serge	1193	return true;
		1194	}
		1195
5060	serge	1196	static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
2330	Serge	1197	{
3746	Serge	1198	struct drm_device *dev = intel_encoder->base.dev;
2330	Serge	1199	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	1200	struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc);
6084	serge	1201	const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
		1202	struct drm_display_mode *mode = &crtc->config->base.mode;
4104	Serge	1203	struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
2330	Serge	1204	u32 sdvox;
		1205	struct intel_sdvo_in_out_map in_out;
3031	serge	1206	struct intel_sdvo_dtd input_dtd, output_dtd;
2330	Serge	1207	int rate;
		1208
		1209	if (!mode)
		1210	return;
		1211
		1212	/* First, set the input mapping for the first input to our controlled
		1213	* output. This is only correct if we're a single-input device, in
		1214	* which case the first input is the output from the appropriate SDVO
		1215	* channel on the motherboard. In a two-input device, the first input
		1216	* will be SDVOB and the second SDVOC.
		1217	*/
		1218	in_out.in0 = intel_sdvo->attached_output;
		1219	in_out.in1 = 0;
		1220
		1221	intel_sdvo_set_value(intel_sdvo,
		1222	SDVO_CMD_SET_IN_OUT_MAP,
		1223	&in_out, sizeof(in_out));
		1224
		1225	/* Set the output timings to the screen */
		1226	if (!intel_sdvo_set_target_output(intel_sdvo,
		1227	intel_sdvo->attached_output))
		1228	return;
		1229
3031	serge	1230	/* lvds has a special fixed output timing. */
		1231	if (intel_sdvo->is_lvds)
		1232	intel_sdvo_get_dtd_from_mode(&output_dtd,
		1233	intel_sdvo->sdvo_lvds_fixed_mode);
		1234	else
		1235	intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
		1236	if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
		1237	DRM_INFO("Setting output timings on %s failed\n",
		1238	SDVO_NAME(intel_sdvo));
2330	Serge	1239
		1240	/* Set the input timing to the screen. Assume always input 0. */
		1241	if (!intel_sdvo_set_target_input(intel_sdvo))
		1242	return;
		1243
6084	serge	1244	if (crtc->config->has_hdmi_sink) {
2330	Serge	1245	intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
		1246	intel_sdvo_set_colorimetry(intel_sdvo,
		1247	SDVO_COLORIMETRY_RGB256);
3480	Serge	1248	intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
2330	Serge	1249	} else
		1250	intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
		1251
		1252	if (intel_sdvo->is_tv &&
		1253	!intel_sdvo_set_tv_format(intel_sdvo))
		1254	return;
		1255
3031	serge	1256	intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
4104	Serge	1257
3031	serge	1258	if (intel_sdvo->is_tv \|\| intel_sdvo->is_lvds)
		1259	input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
		1260	if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
		1261	DRM_INFO("Setting input timings on %s failed\n",
		1262	SDVO_NAME(intel_sdvo));
2330	Serge	1263
6084	serge	1264	switch (crtc->config->pixel_multiplier) {
2330	Serge	1265	default:
6084	serge	1266	WARN(1, "unknown pixel multiplier specified\n");
2330	Serge	1267	case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
		1268	case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
		1269	case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
		1270	}
		1271	if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
		1272	return;
		1273
		1274	/* Set the SDVO control regs. */
		1275	if (INTEL_INFO(dev)->gen >= 4) {
2342	Serge	1276	/* The real mode polarity is set by the SDVO commands, using
		1277	* struct intel_sdvo_dtd. */
		1278	sdvox = SDVO_VSYNC_ACTIVE_HIGH \| SDVO_HSYNC_ACTIVE_HIGH;
6084	serge	1279	if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
5060	serge	1280	sdvox \|= HDMI_COLOR_RANGE_16_235;
2330	Serge	1281	if (INTEL_INFO(dev)->gen < 5)
		1282	sdvox \|= SDVO_BORDER_ENABLE;
		1283	} else {
		1284	sdvox = I915_READ(intel_sdvo->sdvo_reg);
		1285	switch (intel_sdvo->sdvo_reg) {
3746	Serge	1286	case GEN3_SDVOB:
2330	Serge	1287	sdvox &= SDVOB_PRESERVE_MASK;
		1288	break;
3746	Serge	1289	case GEN3_SDVOC:
2330	Serge	1290	sdvox &= SDVOC_PRESERVE_MASK;
		1291	break;
		1292	}
		1293	sdvox \|= (9 << 19) \| SDVO_BORDER_ENABLE;
		1294	}
2342	Serge	1295
		1296	if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
4104	Serge	1297	sdvox \|= SDVO_PIPE_SEL_CPT(crtc->pipe);
2342	Serge	1298	else
4104	Serge	1299	sdvox \|= SDVO_PIPE_SEL(crtc->pipe);
2342	Serge	1300
2330	Serge	1301	if (intel_sdvo->has_hdmi_audio)
		1302	sdvox \|= SDVO_AUDIO_ENABLE;
		1303
		1304	if (INTEL_INFO(dev)->gen >= 4) {
		1305	/* done in crtc_mode_set as the dpll_md reg must be written early */
		1306	} else if (IS_I945G(dev) \|\| IS_I945GM(dev) \|\| IS_G33(dev)) {
		1307	/* done in crtc_mode_set as it lives inside the dpll register */
		1308	} else {
6084	serge	1309	sdvox \|= (crtc->config->pixel_multiplier - 1)
3746	Serge	1310	<< SDVO_PORT_MULTIPLY_SHIFT;
2330	Serge	1311	}
		1312
		1313	if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
		1314	INTEL_INFO(dev)->gen < 5)
		1315	sdvox \|= SDVO_STALL_SELECT;
		1316	intel_sdvo_write_sdvox(intel_sdvo, sdvox);
		1317	}
		1318
3031	serge	1319	static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
2330	Serge	1320	{
3031	serge	1321	struct intel_sdvo_connector *intel_sdvo_connector =
		1322	to_intel_sdvo_connector(&connector->base);
		1323	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
4104	Serge	1324	u16 active_outputs = 0;
3031	serge	1325
		1326	intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
		1327
		1328	if (active_outputs & intel_sdvo_connector->output_flag)
		1329	return true;
		1330	else
		1331	return false;
		1332	}
		1333
		1334	static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
		1335	enum pipe *pipe)
		1336	{
		1337	struct drm_device *dev = encoder->base.dev;
2330	Serge	1338	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	1339	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
		1340	u16 active_outputs = 0;
3031	serge	1341	u32 tmp;
		1342
		1343	tmp = I915_READ(intel_sdvo->sdvo_reg);
3746	Serge	1344	intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
3031	serge	1345
3746	Serge	1346	if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
3031	serge	1347	return false;
		1348
		1349	if (HAS_PCH_CPT(dev))
		1350	*pipe = PORT_TO_PIPE_CPT(tmp);
		1351	else
		1352	*pipe = PORT_TO_PIPE(tmp);
		1353
		1354	return true;
		1355	}
		1356
4104	Serge	1357	static void intel_sdvo_get_config(struct intel_encoder *encoder,
6084	serge	1358	struct intel_crtc_state *pipe_config)
4104	Serge	1359	{
		1360	struct drm_device *dev = encoder->base.dev;
		1361	struct drm_i915_private *dev_priv = dev->dev_private;
		1362	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
		1363	struct intel_sdvo_dtd dtd;
		1364	int encoder_pixel_multiplier = 0;
4560	Serge	1365	int dotclock;
4104	Serge	1366	u32 flags = 0, sdvox;
		1367	u8 val;
		1368	bool ret;
		1369
5060	serge	1370	sdvox = I915_READ(intel_sdvo->sdvo_reg);
		1371
4104	Serge	1372	ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
		1373	if (!ret) {
		1374	/* Some sdvo encoders are not spec compliant and don't
		1375	* implement the mandatory get_timings function. */
		1376	DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
		1377	pipe_config->quirks \|= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
		1378	} else {
		1379	if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
		1380	flags \|= DRM_MODE_FLAG_PHSYNC;
		1381	else
		1382	flags \|= DRM_MODE_FLAG_NHSYNC;
		1383
		1384	if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
		1385	flags \|= DRM_MODE_FLAG_PVSYNC;
		1386	else
		1387	flags \|= DRM_MODE_FLAG_NVSYNC;
		1388	}
		1389
6084	serge	1390	pipe_config->base.adjusted_mode.flags \|= flags;
4104	Serge	1391
		1392	/*
		1393	* pixel multiplier readout is tricky: Only on i915g/gm it is stored in
		1394	* the sdvo port register, on all other platforms it is part of the dpll
		1395	* state. Since the general pipe state readout happens before the
		1396	* encoder->get_config we so already have a valid pixel multplier on all
		1397	* other platfroms.
		1398	*/
		1399	if (IS_I915G(dev) \|\| IS_I915GM(dev)) {
		1400	pipe_config->pixel_multiplier =
		1401	((sdvox & SDVO_PORT_MULTIPLY_MASK)
		1402	>> SDVO_PORT_MULTIPLY_SHIFT) + 1;
		1403	}
		1404
5060	serge	1405	dotclock = pipe_config->port_clock;
		1406	if (pipe_config->pixel_multiplier)
		1407	dotclock /= pipe_config->pixel_multiplier;
4560	Serge	1408
		1409	if (HAS_PCH_SPLIT(dev))
		1410	ironlake_check_encoder_dotclock(pipe_config, dotclock);
		1411
6084	serge	1412	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
4560	Serge	1413
4104	Serge	1414	/* Cross check the port pixel multiplier with the sdvo encoder state. */
		1415	if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
		1416	&val, 1)) {
6084	serge	1417	switch (val) {
		1418	case SDVO_CLOCK_RATE_MULT_1X:
		1419	encoder_pixel_multiplier = 1;
		1420	break;
		1421	case SDVO_CLOCK_RATE_MULT_2X:
		1422	encoder_pixel_multiplier = 2;
		1423	break;
		1424	case SDVO_CLOCK_RATE_MULT_4X:
		1425	encoder_pixel_multiplier = 4;
		1426	break;
		1427	}
4104	Serge	1428	}
		1429
5060	serge	1430	if (sdvox & HDMI_COLOR_RANGE_16_235)
		1431	pipe_config->limited_color_range = true;
		1432
		1433	if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
		1434	&val, 1)) {
		1435	if (val == SDVO_ENCODE_HDMI)
		1436	pipe_config->has_hdmi_sink = true;
		1437	}
		1438
4104	Serge	1439	WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
		1440	"SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
		1441	pipe_config->pixel_multiplier, encoder_pixel_multiplier);
		1442	}
		1443
3031	serge	1444	static void intel_disable_sdvo(struct intel_encoder *encoder)
		1445	{
		1446	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
4104	Serge	1447	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
6084	serge	1448	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2330	Serge	1449	u32 temp;
		1450
6084	serge	1451	intel_sdvo_set_active_outputs(intel_sdvo, 0);
		1452	if (0)
3031	serge	1453	intel_sdvo_set_encoder_power_state(intel_sdvo,
		1454	DRM_MODE_DPMS_OFF);
2330	Serge	1455
6084	serge	1456	temp = I915_READ(intel_sdvo->sdvo_reg);
3243	Serge	1457
6084	serge	1458	temp &= ~SDVO_ENABLE;
		1459	intel_sdvo_write_sdvox(intel_sdvo, temp);
3243	Serge	1460
6084	serge	1461	/*
		1462	* HW workaround for IBX, we need to move the port
		1463	* to transcoder A after disabling it to allow the
		1464	* matching DP port to be enabled on transcoder A.
		1465	*/
		1466	if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
		1467	temp &= ~SDVO_PIPE_B_SELECT;
		1468	temp \|= SDVO_ENABLE;
		1469	intel_sdvo_write_sdvox(intel_sdvo, temp);
3243	Serge	1470
6084	serge	1471	temp &= ~SDVO_ENABLE;
		1472	intel_sdvo_write_sdvox(intel_sdvo, temp);
		1473	}
		1474	}
3243	Serge	1475
6084	serge	1476	static void pch_disable_sdvo(struct intel_encoder *encoder)
		1477	{
3031	serge	1478	}
		1479
6084	serge	1480	static void pch_post_disable_sdvo(struct intel_encoder *encoder)
		1481	{
		1482	intel_disable_sdvo(encoder);
		1483	}
		1484
3031	serge	1485	static void intel_enable_sdvo(struct intel_encoder *encoder)
		1486	{
		1487	struct drm_device *dev = encoder->base.dev;
		1488	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	1489	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
3031	serge	1490	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
		1491	u32 temp;
6084	serge	1492	bool input1, input2;
		1493	int i;
5060	serge	1494	bool success;
2330	Serge	1495
6084	serge	1496	temp = I915_READ(intel_sdvo->sdvo_reg);
		1497	temp \|= SDVO_ENABLE;
		1498	intel_sdvo_write_sdvox(intel_sdvo, temp);
3243	Serge	1499
6084	serge	1500	for (i = 0; i < 2; i++)
		1501	intel_wait_for_vblank(dev, intel_crtc->pipe);
2330	Serge	1502
5060	serge	1503	success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
6084	serge	1504	/* Warn if the device reported failure to sync.
		1505	* A lot of SDVO devices fail to notify of sync, but it's
		1506	* a given it the status is a success, we succeeded.
		1507	*/
5060	serge	1508	if (success && !input1) {
6084	serge	1509	DRM_DEBUG_KMS("First %s output reported failure to "
		1510	"sync\n", SDVO_NAME(intel_sdvo));
		1511	}
2330	Serge	1512
6084	serge	1513	if (0)
3031	serge	1514	intel_sdvo_set_encoder_power_state(intel_sdvo,
		1515	DRM_MODE_DPMS_ON);
		1516	intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
		1517	}
		1518
4560	Serge	1519	static enum drm_mode_status
		1520	intel_sdvo_mode_valid(struct drm_connector *connector,
6084	serge	1521	struct drm_display_mode *mode)
2330	Serge	1522	{
		1523	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
		1524
		1525	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		1526	return MODE_NO_DBLESCAN;
		1527
		1528	if (intel_sdvo->pixel_clock_min > mode->clock)
		1529	return MODE_CLOCK_LOW;
		1530
		1531	if (intel_sdvo->pixel_clock_max < mode->clock)
		1532	return MODE_CLOCK_HIGH;
		1533
		1534	if (intel_sdvo->is_lvds) {
		1535	if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
		1536	return MODE_PANEL;
		1537
		1538	if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
		1539	return MODE_PANEL;
		1540	}
		1541
		1542	return MODE_OK;
		1543	}
		1544
		1545	static bool intel_sdvo_get_capabilities(struct intel_sdvo intel_sdvo, struct intel_sdvo_caps caps)
		1546	{
		1547	BUILD_BUG_ON(sizeof(*caps) != 8);
		1548	if (!intel_sdvo_get_value(intel_sdvo,
		1549	SDVO_CMD_GET_DEVICE_CAPS,
		1550	caps, sizeof(*caps)))
		1551	return false;
		1552
		1553	DRM_DEBUG_KMS("SDVO capabilities:\n"
		1554	" vendor_id: %d\n"
		1555	" device_id: %d\n"
		1556	" device_rev_id: %d\n"
		1557	" sdvo_version_major: %d\n"
		1558	" sdvo_version_minor: %d\n"
		1559	" sdvo_inputs_mask: %d\n"
		1560	" smooth_scaling: %d\n"
		1561	" sharp_scaling: %d\n"
		1562	" up_scaling: %d\n"
		1563	" down_scaling: %d\n"
		1564	" stall_support: %d\n"
		1565	" output_flags: %d\n",
		1566	caps->vendor_id,
		1567	caps->device_id,
		1568	caps->device_rev_id,
		1569	caps->sdvo_version_major,
		1570	caps->sdvo_version_minor,
		1571	caps->sdvo_inputs_mask,
		1572	caps->smooth_scaling,
		1573	caps->sharp_scaling,
		1574	caps->up_scaling,
		1575	caps->down_scaling,
		1576	caps->stall_support,
		1577	caps->output_flags);
		1578
		1579	return true;
		1580	}
		1581
3031	serge	1582	static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
2330	Serge	1583	{
3031	serge	1584	struct drm_device *dev = intel_sdvo->base.base.dev;
		1585	uint16_t hotplug;
2330	Serge	1586
6084	serge	1587	if (!I915_HAS_HOTPLUG(dev))
		1588	return 0;
		1589
3031	serge	1590	/* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
		1591	* on the line. */
		1592	if (IS_I945G(dev) \|\| IS_I945GM(dev))
		1593	return 0;
		1594
		1595	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
		1596	&hotplug, sizeof(hotplug)))
		1597	return 0;
		1598
		1599	return hotplug;
2330	Serge	1600	}
		1601
2342	Serge	1602	static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
2330	Serge	1603	{
4104	Serge	1604	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
2330	Serge	1605
3031	serge	1606	intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
		1607	&intel_sdvo->hotplug_active, 2);
2330	Serge	1608	}
		1609
		1610	static bool
		1611	intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
		1612	{
		1613	/* Is there more than one type of output? */
2342	Serge	1614	return hweight16(intel_sdvo->caps.output_flags) > 1;
2330	Serge	1615	}
		1616
		1617	static struct edid *
		1618	intel_sdvo_get_edid(struct drm_connector *connector)
		1619	{
		1620	struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
		1621	return drm_get_edid(connector, &sdvo->ddc);
		1622	}
		1623
		1624	/* Mac mini hack -- use the same DDC as the analog connector */
		1625	static struct edid *
		1626	intel_sdvo_get_analog_edid(struct drm_connector *connector)
		1627	{
		1628	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		1629
		1630	return drm_get_edid(connector,
3031	serge	1631	intel_gmbus_get_adapter(dev_priv,
4104	Serge	1632	dev_priv->vbt.crt_ddc_pin));
2330	Serge	1633	}
		1634
3031	serge	1635	static enum drm_connector_status
2342	Serge	1636	intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
2330	Serge	1637	{
		1638	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
		1639	enum drm_connector_status status;
		1640	struct edid *edid;
		1641
		1642	edid = intel_sdvo_get_edid(connector);
		1643
		1644	if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
		1645	u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
		1646
		1647	/*
		1648	* Don't use the 1 as the argument of DDC bus switch to get
		1649	* the EDID. It is used for SDVO SPD ROM.
		1650	*/
		1651	for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
		1652	intel_sdvo->ddc_bus = ddc;
		1653	edid = intel_sdvo_get_edid(connector);
		1654	if (edid)
		1655	break;
		1656	}
		1657	/*
		1658	* If we found the EDID on the other bus,
		1659	* assume that is the correct DDC bus.
		1660	*/
		1661	if (edid == NULL)
		1662	intel_sdvo->ddc_bus = saved_ddc;
		1663	}
		1664
		1665	/*
		1666	* When there is no edid and no monitor is connected with VGA
		1667	* port, try to use the CRT ddc to read the EDID for DVI-connector.
		1668	*/
		1669	if (edid == NULL)
		1670	edid = intel_sdvo_get_analog_edid(connector);
		1671
		1672	status = connector_status_unknown;
		1673	if (edid != NULL) {
		1674	/* DDC bus is shared, match EDID to connector type */
		1675	if (edid->input & DRM_EDID_INPUT_DIGITAL) {
		1676	status = connector_status_connected;
		1677	if (intel_sdvo->is_hdmi) {
		1678	intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
		1679	intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
3480	Serge	1680	intel_sdvo->rgb_quant_range_selectable =
		1681	drm_rgb_quant_range_selectable(edid);
2330	Serge	1682	}
		1683	} else
		1684	status = connector_status_disconnected;
		1685	kfree(edid);
		1686	}
		1687
		1688	if (status == connector_status_connected) {
		1689	struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
3031	serge	1690	if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
		1691	intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
2330	Serge	1692	}
		1693
		1694	return status;
		1695	}
		1696
2342	Serge	1697	static bool
		1698	intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
		1699	struct edid *edid)
		1700	{
		1701	bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
		1702	bool connector_is_digital = !!IS_DIGITAL(sdvo);
		1703
		1704	DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
		1705	connector_is_digital, monitor_is_digital);
		1706	return connector_is_digital == monitor_is_digital;
		1707	}
		1708
2330	Serge	1709	static enum drm_connector_status
		1710	intel_sdvo_detect(struct drm_connector *connector, bool force)
		1711	{
		1712	uint16_t response;
		1713	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
		1714	struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
		1715	enum drm_connector_status ret;
		1716
4104	Serge	1717	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5060	serge	1718	connector->base.id, connector->name);
4104	Serge	1719
3243	Serge	1720	if (!intel_sdvo_get_value(intel_sdvo,
		1721	SDVO_CMD_GET_ATTACHED_DISPLAYS,
		1722	&response, 2))
2330	Serge	1723	return connector_status_unknown;
		1724
		1725	DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
		1726	response & 0xff, response >> 8,
		1727	intel_sdvo_connector->output_flag);
		1728
		1729	if (response == 0)
		1730	return connector_status_disconnected;
		1731
		1732	intel_sdvo->attached_output = response;
		1733
		1734	intel_sdvo->has_hdmi_monitor = false;
		1735	intel_sdvo->has_hdmi_audio = false;
3480	Serge	1736	intel_sdvo->rgb_quant_range_selectable = false;
2330	Serge	1737
		1738	if ((intel_sdvo_connector->output_flag & response) == 0)
		1739	ret = connector_status_disconnected;
		1740	else if (IS_TMDS(intel_sdvo_connector))
2342	Serge	1741	ret = intel_sdvo_tmds_sink_detect(connector);
2330	Serge	1742	else {
		1743	struct edid *edid;
		1744
		1745	/* if we have an edid check it matches the connection */
		1746	edid = intel_sdvo_get_edid(connector);
		1747	if (edid == NULL)
		1748	edid = intel_sdvo_get_analog_edid(connector);
		1749	if (edid != NULL) {
2342	Serge	1750	if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
		1751	edid))
		1752	ret = connector_status_connected;
		1753	else
2330	Serge	1754	ret = connector_status_disconnected;
2342	Serge	1755
2330	Serge	1756	kfree(edid);
		1757	} else
		1758	ret = connector_status_connected;
		1759	}
		1760
		1761	/* May update encoder flag for like clock for SDVO TV, etc.*/
		1762	if (ret == connector_status_connected) {
		1763	intel_sdvo->is_tv = false;
		1764	intel_sdvo->is_lvds = false;
		1765
4104	Serge	1766	if (response & SDVO_TV_MASK)
2330	Serge	1767	intel_sdvo->is_tv = true;
		1768	if (response & SDVO_LVDS_MASK)
		1769	intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
		1770	}
		1771
		1772	return ret;
		1773	}
		1774
		1775	static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
		1776	{
		1777	struct edid *edid;
		1778
4560	Serge	1779	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5060	serge	1780	connector->base.id, connector->name);
4560	Serge	1781
2330	Serge	1782	/* set the bus switch and get the modes */
		1783	edid = intel_sdvo_get_edid(connector);
		1784
		1785	/*
		1786	* Mac mini hack. On this device, the DVI-I connector shares one DDC
		1787	* link between analog and digital outputs. So, if the regular SDVO
		1788	* DDC fails, check to see if the analog output is disconnected, in
		1789	* which case we'll look there for the digital DDC data.
		1790	*/
		1791	if (edid == NULL)
		1792	edid = intel_sdvo_get_analog_edid(connector);
		1793
		1794	if (edid != NULL) {
2342	Serge	1795	if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
		1796	edid)) {
2330	Serge	1797	drm_mode_connector_update_edid_property(connector, edid);
		1798	drm_add_edid_modes(connector, edid);
		1799	}
		1800
		1801	kfree(edid);
		1802	}
		1803	}
		1804
		1805	/*
		1806	* Set of SDVO TV modes.
		1807	* Note! This is in reply order (see loop in get_tv_modes).
		1808	* XXX: all 60Hz refresh?
		1809	*/
		1810	static const struct drm_display_mode sdvo_tv_modes[] = {
		1811	{ DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
		1812	416, 0, 200, 201, 232, 233, 0,
		1813	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1814	{ DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
		1815	416, 0, 240, 241, 272, 273, 0,
		1816	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1817	{ DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
		1818	496, 0, 300, 301, 332, 333, 0,
		1819	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1820	{ DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
		1821	736, 0, 350, 351, 382, 383, 0,
		1822	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1823	{ DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
		1824	736, 0, 400, 401, 432, 433, 0,
		1825	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1826	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
		1827	736, 0, 480, 481, 512, 513, 0,
		1828	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1829	{ DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
		1830	800, 0, 480, 481, 512, 513, 0,
		1831	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1832	{ DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
		1833	800, 0, 576, 577, 608, 609, 0,
		1834	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1835	{ DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
		1836	816, 0, 350, 351, 382, 383, 0,
		1837	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1838	{ DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
		1839	816, 0, 400, 401, 432, 433, 0,
		1840	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1841	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
		1842	816, 0, 480, 481, 512, 513, 0,
		1843	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1844	{ DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
		1845	816, 0, 540, 541, 572, 573, 0,
		1846	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1847	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
		1848	816, 0, 576, 577, 608, 609, 0,
		1849	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1850	{ DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
		1851	864, 0, 576, 577, 608, 609, 0,
		1852	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1853	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
		1854	896, 0, 600, 601, 632, 633, 0,
		1855	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1856	{ DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
		1857	928, 0, 624, 625, 656, 657, 0,
		1858	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1859	{ DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
		1860	1016, 0, 766, 767, 798, 799, 0,
		1861	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1862	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
		1863	1120, 0, 768, 769, 800, 801, 0,
		1864	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1865	{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
		1866	1376, 0, 1024, 1025, 1056, 1057, 0,
		1867	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1868	};
		1869
		1870	static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
		1871	{
		1872	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
		1873	struct intel_sdvo_sdtv_resolution_request tv_res;
		1874	uint32_t reply = 0, format_map = 0;
		1875	int i;
		1876
4560	Serge	1877	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5060	serge	1878	connector->base.id, connector->name);
4560	Serge	1879
2330	Serge	1880	/* Read the list of supported input resolutions for the selected TV
		1881	* format.
		1882	*/
		1883	format_map = 1 << intel_sdvo->tv_format_index;
		1884	memcpy(&tv_res, &format_map,
		1885	min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
		1886
		1887	if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
		1888	return;
		1889
		1890	BUILD_BUG_ON(sizeof(tv_res) != 3);
		1891	if (!intel_sdvo_write_cmd(intel_sdvo,
		1892	SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
		1893	&tv_res, sizeof(tv_res)))
		1894	return;
		1895	if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
		1896	return;
		1897
		1898	for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
		1899	if (reply & (1 << i)) {
		1900	struct drm_display_mode *nmode;
		1901	nmode = drm_mode_duplicate(connector->dev,
		1902	&sdvo_tv_modes[i]);
		1903	if (nmode)
		1904	drm_mode_probed_add(connector, nmode);
		1905	}
		1906	}
		1907
		1908	static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
		1909	{
		1910	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
		1911	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		1912	struct drm_display_mode *newmode;
		1913
4560	Serge	1914	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5060	serge	1915	connector->base.id, connector->name);
4560	Serge	1916
2330	Serge	1917	/*
3746	Serge	1918	* Fetch modes from VBT. For SDVO prefer the VBT mode since some
4104	Serge	1919	* SDVO->LVDS transcoders can't cope with the EDID mode.
3746	Serge	1920	*/
4104	Serge	1921	if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
2330	Serge	1922	newmode = drm_mode_duplicate(connector->dev,
4104	Serge	1923	dev_priv->vbt.sdvo_lvds_vbt_mode);
2330	Serge	1924	if (newmode != NULL) {
		1925	/* Guarantee the mode is preferred */
		1926	newmode->type = (DRM_MODE_TYPE_PREFERRED \|
		1927	DRM_MODE_TYPE_DRIVER);
		1928	drm_mode_probed_add(connector, newmode);
		1929	}
		1930	}
		1931
4104	Serge	1932	/*
		1933	* Attempt to get the mode list from DDC.
		1934	* Assume that the preferred modes are
		1935	* arranged in priority order.
		1936	*/
		1937	intel_ddc_get_modes(connector, &intel_sdvo->ddc);
		1938
2330	Serge	1939	list_for_each_entry(newmode, &connector->probed_modes, head) {
		1940	if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
		1941	intel_sdvo->sdvo_lvds_fixed_mode =
		1942	drm_mode_duplicate(connector->dev, newmode);
		1943
		1944	intel_sdvo->is_lvds = true;
		1945	break;
		1946	}
		1947	}
		1948	}
		1949
		1950	static int intel_sdvo_get_modes(struct drm_connector *connector)
		1951	{
		1952	struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
		1953
		1954	if (IS_TV(intel_sdvo_connector))
		1955	intel_sdvo_get_tv_modes(connector);
		1956	else if (IS_LVDS(intel_sdvo_connector))
		1957	intel_sdvo_get_lvds_modes(connector);
		1958	else
		1959	intel_sdvo_get_ddc_modes(connector);
		1960
		1961	return !list_empty(&connector->probed_modes);
		1962	}
		1963
		1964	static void intel_sdvo_destroy(struct drm_connector *connector)
		1965	{
		1966	struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
		1967
		1968	drm_connector_cleanup(connector);
3243	Serge	1969	kfree(intel_sdvo_connector);
2330	Serge	1970	}
		1971
3031	serge	1972	static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
		1973	{
		1974	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
		1975	struct edid *edid;
		1976	bool has_audio = false;
2330	Serge	1977
3031	serge	1978	if (!intel_sdvo->is_hdmi)
		1979	return false;
2330	Serge	1980
3031	serge	1981	edid = intel_sdvo_get_edid(connector);
		1982	if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
		1983	has_audio = drm_detect_monitor_audio(edid);
		1984	kfree(edid);
2330	Serge	1985
3031	serge	1986	return has_audio;
		1987	}
2330	Serge	1988
		1989	static int
		1990	intel_sdvo_set_property(struct drm_connector *connector,
		1991	struct drm_property *property,
		1992	uint64_t val)
		1993	{
		1994	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
		1995	struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
		1996	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		1997	uint16_t temp_value;
		1998	uint8_t cmd;
		1999	int ret;
		2000
3243	Serge	2001	ret = drm_object_property_set_value(&connector->base, property, val);
2330	Serge	2002	if (ret)
		2003	return ret;
		2004
		2005	if (property == dev_priv->force_audio_property) {
		2006	int i = val;
		2007	bool has_audio;
		2008
		2009	if (i == intel_sdvo_connector->force_audio)
		2010	return 0;
		2011
		2012	intel_sdvo_connector->force_audio = i;
		2013
3031	serge	2014	if (i == HDMI_AUDIO_AUTO)
2330	Serge	2015	has_audio = intel_sdvo_detect_hdmi_audio(connector);
		2016	else
3031	serge	2017	has_audio = (i == HDMI_AUDIO_ON);
2330	Serge	2018
		2019	if (has_audio == intel_sdvo->has_hdmi_audio)
		2020	return 0;
		2021
		2022	intel_sdvo->has_hdmi_audio = has_audio;
		2023	goto done;
		2024	}
		2025
		2026	if (property == dev_priv->broadcast_rgb_property) {
3746	Serge	2027	bool old_auto = intel_sdvo->color_range_auto;
		2028	uint32_t old_range = intel_sdvo->color_range;
		2029
3480	Serge	2030	switch (val) {
		2031	case INTEL_BROADCAST_RGB_AUTO:
		2032	intel_sdvo->color_range_auto = true;
		2033	break;
		2034	case INTEL_BROADCAST_RGB_FULL:
		2035	intel_sdvo->color_range_auto = false;
		2036	intel_sdvo->color_range = 0;
		2037	break;
		2038	case INTEL_BROADCAST_RGB_LIMITED:
		2039	intel_sdvo->color_range_auto = false;
3746	Serge	2040	/* FIXME: this bit is only valid when using TMDS
		2041	* encoding and 8 bit per color mode. */
		2042	intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
3480	Serge	2043	break;
		2044	default:
		2045	return -EINVAL;
		2046	}
3746	Serge	2047
		2048	if (old_auto == intel_sdvo->color_range_auto &&
		2049	old_range == intel_sdvo->color_range)
		2050	return 0;
		2051
2330	Serge	2052	goto done;
		2053	}
		2054
6084	serge	2055	if (property == connector->dev->mode_config.aspect_ratio_property) {
		2056	switch (val) {
		2057	case DRM_MODE_PICTURE_ASPECT_NONE:
		2058	intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
		2059	break;
		2060	case DRM_MODE_PICTURE_ASPECT_4_3:
		2061	intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
		2062	break;
		2063	case DRM_MODE_PICTURE_ASPECT_16_9:
		2064	intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
		2065	break;
		2066	default:
		2067	return -EINVAL;
		2068	}
		2069	goto done;
		2070	}
		2071
2330	Serge	2072	#define CHECK_PROPERTY(name, NAME) \
		2073	if (intel_sdvo_connector->name == property) { \
		2074	if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
		2075	if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
		2076	cmd = SDVO_CMD_SET_##NAME; \
		2077	intel_sdvo_connector->cur_##name = temp_value; \
		2078	goto set_value; \
		2079	}
		2080
		2081	if (property == intel_sdvo_connector->tv_format) {
		2082	if (val >= TV_FORMAT_NUM)
		2083	return -EINVAL;
		2084
		2085	if (intel_sdvo->tv_format_index ==
		2086	intel_sdvo_connector->tv_format_supported[val])
		2087	return 0;
		2088
		2089	intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
		2090	goto done;
		2091	} else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
		2092	temp_value = val;
		2093	if (intel_sdvo_connector->left == property) {
3243	Serge	2094	drm_object_property_set_value(&connector->base,
2330	Serge	2095	intel_sdvo_connector->right, val);
		2096	if (intel_sdvo_connector->left_margin == temp_value)
		2097	return 0;
		2098
		2099	intel_sdvo_connector->left_margin = temp_value;
		2100	intel_sdvo_connector->right_margin = temp_value;
		2101	temp_value = intel_sdvo_connector->max_hscan -
		2102	intel_sdvo_connector->left_margin;
		2103	cmd = SDVO_CMD_SET_OVERSCAN_H;
		2104	goto set_value;
		2105	} else if (intel_sdvo_connector->right == property) {
3243	Serge	2106	drm_object_property_set_value(&connector->base,
2330	Serge	2107	intel_sdvo_connector->left, val);
		2108	if (intel_sdvo_connector->right_margin == temp_value)
		2109	return 0;
		2110
		2111	intel_sdvo_connector->left_margin = temp_value;
		2112	intel_sdvo_connector->right_margin = temp_value;
		2113	temp_value = intel_sdvo_connector->max_hscan -
		2114	intel_sdvo_connector->left_margin;
		2115	cmd = SDVO_CMD_SET_OVERSCAN_H;
		2116	goto set_value;
		2117	} else if (intel_sdvo_connector->top == property) {
3243	Serge	2118	drm_object_property_set_value(&connector->base,
2330	Serge	2119	intel_sdvo_connector->bottom, val);
		2120	if (intel_sdvo_connector->top_margin == temp_value)
		2121	return 0;
		2122
		2123	intel_sdvo_connector->top_margin = temp_value;
		2124	intel_sdvo_connector->bottom_margin = temp_value;
		2125	temp_value = intel_sdvo_connector->max_vscan -
		2126	intel_sdvo_connector->top_margin;
		2127	cmd = SDVO_CMD_SET_OVERSCAN_V;
		2128	goto set_value;
		2129	} else if (intel_sdvo_connector->bottom == property) {
3243	Serge	2130	drm_object_property_set_value(&connector->base,
2330	Serge	2131	intel_sdvo_connector->top, val);
		2132	if (intel_sdvo_connector->bottom_margin == temp_value)
		2133	return 0;
		2134
		2135	intel_sdvo_connector->top_margin = temp_value;
		2136	intel_sdvo_connector->bottom_margin = temp_value;
		2137	temp_value = intel_sdvo_connector->max_vscan -
		2138	intel_sdvo_connector->top_margin;
		2139	cmd = SDVO_CMD_SET_OVERSCAN_V;
		2140	goto set_value;
		2141	}
		2142	CHECK_PROPERTY(hpos, HPOS)
		2143	CHECK_PROPERTY(vpos, VPOS)
		2144	CHECK_PROPERTY(saturation, SATURATION)
		2145	CHECK_PROPERTY(contrast, CONTRAST)
		2146	CHECK_PROPERTY(hue, HUE)
		2147	CHECK_PROPERTY(brightness, BRIGHTNESS)
		2148	CHECK_PROPERTY(sharpness, SHARPNESS)
		2149	CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
		2150	CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
		2151	CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
		2152	CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
		2153	CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
		2154	CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
		2155	}
		2156
		2157	return -EINVAL; /* unknown property */
		2158
		2159	set_value:
		2160	if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
		2161	return -EIO;
		2162
		2163
		2164	done:
3480	Serge	2165	if (intel_sdvo->base.base.crtc)
		2166	intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
2330	Serge	2167
		2168	return 0;
		2169	#undef CHECK_PROPERTY
		2170	}
		2171
		2172	static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
6084	serge	2173	.dpms = drm_atomic_helper_connector_dpms,
2330	Serge	2174	.detect = intel_sdvo_detect,
		2175	.fill_modes = drm_helper_probe_single_connector_modes,
		2176	.set_property = intel_sdvo_set_property,
6084	serge	2177	.atomic_get_property = intel_connector_atomic_get_property,
2330	Serge	2178	.destroy = intel_sdvo_destroy,
6084	serge	2179	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
		2180	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2330	Serge	2181	};
		2182
		2183	static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
		2184	.get_modes = intel_sdvo_get_modes,
		2185	.mode_valid = intel_sdvo_mode_valid,
		2186	.best_encoder = intel_best_encoder,
		2187	};
		2188
		2189	static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
		2190	{
4104	Serge	2191	struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
2330	Serge	2192
		2193	if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
		2194	drm_mode_destroy(encoder->dev,
		2195	intel_sdvo->sdvo_lvds_fixed_mode);
		2196
3243	Serge	2197	i2c_del_adapter(&intel_sdvo->ddc);
2330	Serge	2198	intel_encoder_destroy(encoder);
		2199	}
		2200
		2201	static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
		2202	.destroy = intel_sdvo_enc_destroy,
		2203	};
		2204
		2205	static void
		2206	intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
		2207	{
		2208	uint16_t mask = 0;
		2209	unsigned int num_bits;
		2210
		2211	/* Make a mask of outputs less than or equal to our own priority in the
		2212	* list.
		2213	*/
		2214	switch (sdvo->controlled_output) {
		2215	case SDVO_OUTPUT_LVDS1:
		2216	mask \|= SDVO_OUTPUT_LVDS1;
		2217	case SDVO_OUTPUT_LVDS0:
		2218	mask \|= SDVO_OUTPUT_LVDS0;
		2219	case SDVO_OUTPUT_TMDS1:
		2220	mask \|= SDVO_OUTPUT_TMDS1;
		2221	case SDVO_OUTPUT_TMDS0:
		2222	mask \|= SDVO_OUTPUT_TMDS0;
		2223	case SDVO_OUTPUT_RGB1:
		2224	mask \|= SDVO_OUTPUT_RGB1;
		2225	case SDVO_OUTPUT_RGB0:
		2226	mask \|= SDVO_OUTPUT_RGB0;
		2227	break;
		2228	}
		2229
		2230	/* Count bits to find what number we are in the priority list. */
		2231	mask &= sdvo->caps.output_flags;
		2232	num_bits = hweight16(mask);
		2233	/* If more than 3 outputs, default to DDC bus 3 for now. */
		2234	if (num_bits > 3)
		2235	num_bits = 3;
		2236
		2237	/* Corresponds to SDVO_CONTROL_BUS_DDCx */
		2238	sdvo->ddc_bus = 1 << num_bits;
		2239	}
		2240
		2241	/**
		2242	* Choose the appropriate DDC bus for control bus switch command for this
		2243	* SDVO output based on the controlled output.
		2244	*
		2245	* DDC bus number assignment is in a priority order of RGB outputs, then TMDS
		2246	* outputs, then LVDS outputs.
		2247	*/
		2248	static void
		2249	intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
6084	serge	2250	struct intel_sdvo *sdvo)
2330	Serge	2251	{
		2252	struct sdvo_device_mapping *mapping;
		2253
3031	serge	2254	if (sdvo->is_sdvob)
2330	Serge	2255	mapping = &(dev_priv->sdvo_mappings[0]);
		2256	else
		2257	mapping = &(dev_priv->sdvo_mappings[1]);
		2258
		2259	if (mapping->initialized)
		2260	sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
		2261	else
		2262	intel_sdvo_guess_ddc_bus(sdvo);
		2263	}
		2264
		2265	static void
		2266	intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
6084	serge	2267	struct intel_sdvo *sdvo)
2330	Serge	2268	{
		2269	struct sdvo_device_mapping *mapping;
2342	Serge	2270	u8 pin;
2330	Serge	2271
3031	serge	2272	if (sdvo->is_sdvob)
2330	Serge	2273	mapping = &dev_priv->sdvo_mappings[0];
		2274	else
		2275	mapping = &dev_priv->sdvo_mappings[1];
		2276
6084	serge	2277	if (mapping->initialized &&
		2278	intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
3243	Serge	2279	pin = mapping->i2c_pin;
		2280	else
6084	serge	2281	pin = GMBUS_PIN_DPB;
2330	Serge	2282
6084	serge	2283	sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
3243	Serge	2284
		2285	/* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
		2286	* our code totally fails once we start using gmbus. Hence fall back to
		2287	* bit banging for now. */
6084	serge	2288	intel_gmbus_force_bit(sdvo->i2c, true);
2330	Serge	2289	}
		2290
3243	Serge	2291	/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
		2292	static void
		2293	intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
		2294	{
		2295	intel_gmbus_force_bit(sdvo->i2c, false);
		2296	}
		2297
2330	Serge	2298	static bool
		2299	intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
		2300	{
		2301	return intel_sdvo_check_supp_encode(intel_sdvo);
		2302	}
		2303
		2304	static u8
3031	serge	2305	intel_sdvo_get_slave_addr(struct drm_device dev, struct intel_sdvo sdvo)
2330	Serge	2306	{
		2307	struct drm_i915_private *dev_priv = dev->dev_private;
		2308	struct sdvo_device_mapping my_mapping, other_mapping;
		2309
3031	serge	2310	if (sdvo->is_sdvob) {
2330	Serge	2311	my_mapping = &dev_priv->sdvo_mappings[0];
		2312	other_mapping = &dev_priv->sdvo_mappings[1];
		2313	} else {
		2314	my_mapping = &dev_priv->sdvo_mappings[1];
		2315	other_mapping = &dev_priv->sdvo_mappings[0];
		2316	}
		2317
		2318	/* If the BIOS described our SDVO device, take advantage of it. */
		2319	if (my_mapping->slave_addr)
		2320	return my_mapping->slave_addr;
		2321
		2322	/* If the BIOS only described a different SDVO device, use the
		2323	* address that it isn't using.
		2324	*/
		2325	if (other_mapping->slave_addr) {
		2326	if (other_mapping->slave_addr == 0x70)
		2327	return 0x72;
		2328	else
		2329	return 0x70;
		2330	}
		2331
		2332	/* No SDVO device info is found for another DVO port,
		2333	* so use mapping assumption we had before BIOS parsing.
		2334	*/
3031	serge	2335	if (sdvo->is_sdvob)
2330	Serge	2336	return 0x70;
		2337	else
		2338	return 0x72;
		2339	}
		2340
		2341	static void
5060	serge	2342	intel_sdvo_connector_unregister(struct intel_connector *intel_connector)
		2343	{
		2344	struct drm_connector *drm_connector;
		2345	struct intel_sdvo *sdvo_encoder;
		2346
		2347	drm_connector = &intel_connector->base;
		2348	sdvo_encoder = intel_attached_sdvo(&intel_connector->base);
		2349
		2350	intel_connector_unregister(intel_connector);
		2351	}
		2352
		2353	static int
2330	Serge	2354	intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
		2355	struct intel_sdvo *encoder)
		2356	{
5060	serge	2357	struct drm_connector *drm_connector;
		2358	int ret;
		2359
		2360	drm_connector = &connector->base.base;
		2361	ret = drm_connector_init(encoder->base.base.dev,
		2362	drm_connector,
2330	Serge	2363	&intel_sdvo_connector_funcs,
		2364	connector->base.base.connector_type);
5060	serge	2365	if (ret < 0)
		2366	return ret;
2330	Serge	2367
5060	serge	2368	drm_connector_helper_add(drm_connector,
2330	Serge	2369	&intel_sdvo_connector_helper_funcs);
		2370
3031	serge	2371	connector->base.base.interlace_allowed = 1;
2330	Serge	2372	connector->base.base.doublescan_allowed = 0;
		2373	connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
3031	serge	2374	connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
5060	serge	2375	connector->base.unregister = intel_sdvo_connector_unregister;
2330	Serge	2376
		2377	intel_connector_attach_encoder(&connector->base, &encoder->base);
5367	serge	2378	ret = drm_connector_register(drm_connector);
		2379	if (ret < 0)
		2380	goto err1;
5060	serge	2381
5367	serge	2382	return 0;
		2383
		2384	err2:
		2385	drm_connector_unregister(drm_connector);
		2386	err1:
		2387	drm_connector_cleanup(drm_connector);
		2388
5060	serge	2389	return ret;
2330	Serge	2390	}
		2391
		2392	static void
3480	Serge	2393	intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
		2394	struct intel_sdvo_connector *connector)
2330	Serge	2395	{
		2396	struct drm_device *dev = connector->base.base.dev;
		2397
		2398	intel_attach_force_audio_property(&connector->base.base);
3480	Serge	2399	if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
2330	Serge	2400	intel_attach_broadcast_rgb_property(&connector->base.base);
3480	Serge	2401	intel_sdvo->color_range_auto = true;
		2402	}
6084	serge	2403	intel_attach_aspect_ratio_property(&connector->base.base);
		2404	intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2330	Serge	2405	}
		2406
6084	serge	2407	static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void)
		2408	{
		2409	struct intel_sdvo_connector *sdvo_connector;
		2410
		2411	sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL);
		2412	if (!sdvo_connector)
		2413	return NULL;
		2414
		2415	if (intel_connector_init(&sdvo_connector->base) < 0) {
		2416	kfree(sdvo_connector);
		2417	return NULL;
		2418	}
		2419
		2420	return sdvo_connector;
		2421	}
		2422
2330	Serge	2423	static bool
		2424	intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
		2425	{
		2426	struct drm_encoder *encoder = &intel_sdvo->base.base;
		2427	struct drm_connector *connector;
2342	Serge	2428	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2330	Serge	2429	struct intel_connector *intel_connector;
		2430	struct intel_sdvo_connector *intel_sdvo_connector;
		2431
4560	Serge	2432	DRM_DEBUG_KMS("initialising DVI device %d\n", device);
		2433
6084	serge	2434	intel_sdvo_connector = intel_sdvo_connector_alloc();
2330	Serge	2435	if (!intel_sdvo_connector)
		2436	return false;
		2437
		2438	if (device == 0) {
		2439	intel_sdvo->controlled_output \|= SDVO_OUTPUT_TMDS0;
		2440	intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
		2441	} else if (device == 1) {
		2442	intel_sdvo->controlled_output \|= SDVO_OUTPUT_TMDS1;
		2443	intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
		2444	}
		2445
		2446	intel_connector = &intel_sdvo_connector->base;
		2447	connector = &intel_connector->base;
3031	serge	2448	if (intel_sdvo_get_hotplug_support(intel_sdvo) &
		2449	intel_sdvo_connector->output_flag) {
		2450	intel_sdvo->hotplug_active \|= intel_sdvo_connector->output_flag;
2342	Serge	2451	/* Some SDVO devices have one-shot hotplug interrupts.
		2452	* Ensure that they get re-enabled when an interrupt happens.
		2453	*/
		2454	intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
		2455	intel_sdvo_enable_hotplug(intel_encoder);
3031	serge	2456	} else {
3746	Serge	2457	intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT \| DRM_CONNECTOR_POLL_DISCONNECT;
2342	Serge	2458	}
2330	Serge	2459	encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
		2460	connector->connector_type = DRM_MODE_CONNECTOR_DVID;
		2461
		2462	if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
		2463	connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
		2464	intel_sdvo->is_hdmi = true;
		2465	}
		2466
5060	serge	2467	if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
		2468	kfree(intel_sdvo_connector);
		2469	return false;
		2470	}
		2471
2330	Serge	2472	if (intel_sdvo->is_hdmi)
3480	Serge	2473	intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
2330	Serge	2474
		2475	return true;
		2476	}
		2477
		2478	static bool
		2479	intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
		2480	{
		2481	struct drm_encoder *encoder = &intel_sdvo->base.base;
		2482	struct drm_connector *connector;
		2483	struct intel_connector *intel_connector;
		2484	struct intel_sdvo_connector *intel_sdvo_connector;
		2485
4560	Serge	2486	DRM_DEBUG_KMS("initialising TV type %d\n", type);
		2487
6084	serge	2488	intel_sdvo_connector = intel_sdvo_connector_alloc();
2330	Serge	2489	if (!intel_sdvo_connector)
		2490	return false;
		2491
		2492	intel_connector = &intel_sdvo_connector->base;
		2493	connector = &intel_connector->base;
		2494	encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
		2495	connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
		2496
		2497	intel_sdvo->controlled_output \|= type;
		2498	intel_sdvo_connector->output_flag = type;
		2499
		2500	intel_sdvo->is_tv = true;
		2501
5060	serge	2502	if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
		2503	kfree(intel_sdvo_connector);
		2504	return false;
		2505	}
2330	Serge	2506
		2507	if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
		2508	goto err;
		2509
		2510	if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
		2511	goto err;
		2512
		2513	return true;
		2514
		2515	err:
5060	serge	2516	drm_connector_unregister(connector);
2330	Serge	2517	intel_sdvo_destroy(connector);
		2518	return false;
		2519	}
		2520
		2521	static bool
		2522	intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
		2523	{
		2524	struct drm_encoder *encoder = &intel_sdvo->base.base;
		2525	struct drm_connector *connector;
		2526	struct intel_connector *intel_connector;
		2527	struct intel_sdvo_connector *intel_sdvo_connector;
		2528
4560	Serge	2529	DRM_DEBUG_KMS("initialising analog device %d\n", device);
		2530
6084	serge	2531	intel_sdvo_connector = intel_sdvo_connector_alloc();
2330	Serge	2532	if (!intel_sdvo_connector)
		2533	return false;
		2534
		2535	intel_connector = &intel_sdvo_connector->base;
		2536	connector = &intel_connector->base;
3746	Serge	2537	intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
2330	Serge	2538	encoder->encoder_type = DRM_MODE_ENCODER_DAC;
		2539	connector->connector_type = DRM_MODE_CONNECTOR_VGA;
		2540
		2541	if (device == 0) {
		2542	intel_sdvo->controlled_output \|= SDVO_OUTPUT_RGB0;
		2543	intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
		2544	} else if (device == 1) {
		2545	intel_sdvo->controlled_output \|= SDVO_OUTPUT_RGB1;
		2546	intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
		2547	}
		2548
5060	serge	2549	if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
		2550	kfree(intel_sdvo_connector);
		2551	return false;
		2552	}
		2553
2330	Serge	2554	return true;
		2555	}
		2556
		2557	static bool
		2558	intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
		2559	{
		2560	struct drm_encoder *encoder = &intel_sdvo->base.base;
		2561	struct drm_connector *connector;
		2562	struct intel_connector *intel_connector;
		2563	struct intel_sdvo_connector *intel_sdvo_connector;
		2564
4560	Serge	2565	DRM_DEBUG_KMS("initialising LVDS device %d\n", device);
		2566
6084	serge	2567	intel_sdvo_connector = intel_sdvo_connector_alloc();
2330	Serge	2568	if (!intel_sdvo_connector)
		2569	return false;
		2570
		2571	intel_connector = &intel_sdvo_connector->base;
		2572	connector = &intel_connector->base;
		2573	encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
		2574	connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
		2575
		2576	if (device == 0) {
		2577	intel_sdvo->controlled_output \|= SDVO_OUTPUT_LVDS0;
		2578	intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
		2579	} else if (device == 1) {
		2580	intel_sdvo->controlled_output \|= SDVO_OUTPUT_LVDS1;
		2581	intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
		2582	}
		2583
5060	serge	2584	if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
		2585	kfree(intel_sdvo_connector);
		2586	return false;
		2587	}
		2588
2330	Serge	2589	if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
		2590	goto err;
		2591
		2592	return true;
		2593
		2594	err:
5060	serge	2595	drm_connector_unregister(connector);
2330	Serge	2596	intel_sdvo_destroy(connector);
		2597	return false;
		2598	}
		2599
		2600	static bool
		2601	intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
		2602	{
		2603	intel_sdvo->is_tv = false;
		2604	intel_sdvo->is_lvds = false;
		2605
		2606	/* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
		2607
		2608	if (flags & SDVO_OUTPUT_TMDS0)
		2609	if (!intel_sdvo_dvi_init(intel_sdvo, 0))
		2610	return false;
		2611
		2612	if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
		2613	if (!intel_sdvo_dvi_init(intel_sdvo, 1))
		2614	return false;
		2615
		2616	/* TV has no XXX1 function block */
		2617	if (flags & SDVO_OUTPUT_SVID0)
		2618	if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
		2619	return false;
		2620
		2621	if (flags & SDVO_OUTPUT_CVBS0)
		2622	if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
		2623	return false;
		2624
3031	serge	2625	if (flags & SDVO_OUTPUT_YPRPB0)
		2626	if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
		2627	return false;
		2628
2330	Serge	2629	if (flags & SDVO_OUTPUT_RGB0)
		2630	if (!intel_sdvo_analog_init(intel_sdvo, 0))
		2631	return false;
		2632
		2633	if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
		2634	if (!intel_sdvo_analog_init(intel_sdvo, 1))
		2635	return false;
		2636
		2637	if (flags & SDVO_OUTPUT_LVDS0)
		2638	if (!intel_sdvo_lvds_init(intel_sdvo, 0))
		2639	return false;
		2640
		2641	if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
		2642	if (!intel_sdvo_lvds_init(intel_sdvo, 1))
		2643	return false;
		2644
		2645	if ((flags & SDVO_OUTPUT_MASK) == 0) {
		2646	unsigned char bytes[2];
		2647
		2648	intel_sdvo->controlled_output = 0;
		2649	memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
		2650	DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
		2651	SDVO_NAME(intel_sdvo),
		2652	bytes[0], bytes[1]);
		2653	return false;
		2654	}
2342	Serge	2655	intel_sdvo->base.crtc_mask = (1 << 0) \| (1 << 1) \| (1 << 2);
2330	Serge	2656
		2657	return true;
		2658	}
		2659
3120	serge	2660	static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
		2661	{
		2662	struct drm_device *dev = intel_sdvo->base.base.dev;
		2663	struct drm_connector connector, tmp;
		2664
		2665	list_for_each_entry_safe(connector, tmp,
		2666	&dev->mode_config.connector_list, head) {
4560	Serge	2667	if (intel_attached_encoder(connector) == &intel_sdvo->base) {
5060	serge	2668	drm_connector_unregister(connector);
3120	serge	2669	intel_sdvo_destroy(connector);
6084	serge	2670	}
3120	serge	2671	}
		2672	}
		2673
2330	Serge	2674	static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
		2675	struct intel_sdvo_connector *intel_sdvo_connector,
		2676	int type)
		2677	{
		2678	struct drm_device *dev = intel_sdvo->base.base.dev;
		2679	struct intel_sdvo_tv_format format;
		2680	uint32_t format_map, i;
		2681
		2682	if (!intel_sdvo_set_target_output(intel_sdvo, type))
		2683	return false;
		2684
		2685	BUILD_BUG_ON(sizeof(format) != 6);
		2686	if (!intel_sdvo_get_value(intel_sdvo,
		2687	SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
		2688	&format, sizeof(format)))
		2689	return false;
		2690
		2691	memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
		2692
		2693	if (format_map == 0)
		2694	return false;
		2695
		2696	intel_sdvo_connector->format_supported_num = 0;
		2697	for (i = 0 ; i < TV_FORMAT_NUM; i++)
		2698	if (format_map & (1 << i))
		2699	intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
		2700
		2701
		2702	intel_sdvo_connector->tv_format =
		2703	drm_property_create(dev, DRM_MODE_PROP_ENUM,
		2704	"mode", intel_sdvo_connector->format_supported_num);
		2705	if (!intel_sdvo_connector->tv_format)
		2706	return false;
		2707
		2708	for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
		2709	drm_property_add_enum(
		2710	intel_sdvo_connector->tv_format, i,
		2711	i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
		2712
		2713	intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
3243	Serge	2714	drm_object_attach_property(&intel_sdvo_connector->base.base.base,
2330	Serge	2715	intel_sdvo_connector->tv_format, 0);
		2716	return true;
		2717
		2718	}
		2719
		2720	#define ENHANCEMENT(name, NAME) do { \
		2721	if (enhancements.name) { \
		2722	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) \|\| \
		2723	!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
		2724	return false; \
		2725	intel_sdvo_connector->max_##name = data_value[0]; \
		2726	intel_sdvo_connector->cur_##name = response; \
		2727	intel_sdvo_connector->name = \
3031	serge	2728	drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
2330	Serge	2729	if (!intel_sdvo_connector->name) return false; \
3243	Serge	2730	drm_object_attach_property(&connector->base, \
2330	Serge	2731	intel_sdvo_connector->name, \
		2732	intel_sdvo_connector->cur_##name); \
		2733	DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
		2734	data_value[0], data_value[1], response); \
		2735	} \
2342	Serge	2736	} while (0)
2330	Serge	2737
		2738	static bool
		2739	intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
		2740	struct intel_sdvo_connector *intel_sdvo_connector,
		2741	struct intel_sdvo_enhancements_reply enhancements)
		2742	{
		2743	struct drm_device *dev = intel_sdvo->base.base.dev;
		2744	struct drm_connector *connector = &intel_sdvo_connector->base.base;
		2745	uint16_t response, data_value[2];
		2746
		2747	/* when horizontal overscan is supported, Add the left/right property */
		2748	if (enhancements.overscan_h) {
		2749	if (!intel_sdvo_get_value(intel_sdvo,
		2750	SDVO_CMD_GET_MAX_OVERSCAN_H,
		2751	&data_value, 4))
		2752	return false;
		2753
		2754	if (!intel_sdvo_get_value(intel_sdvo,
		2755	SDVO_CMD_GET_OVERSCAN_H,
		2756	&response, 2))
		2757	return false;
		2758
		2759	intel_sdvo_connector->max_hscan = data_value[0];
		2760	intel_sdvo_connector->left_margin = data_value[0] - response;
		2761	intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
		2762	intel_sdvo_connector->left =
3031	serge	2763	drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
2330	Serge	2764	if (!intel_sdvo_connector->left)
		2765	return false;
		2766
3243	Serge	2767	drm_object_attach_property(&connector->base,
2330	Serge	2768	intel_sdvo_connector->left,
		2769	intel_sdvo_connector->left_margin);
		2770
		2771	intel_sdvo_connector->right =
3031	serge	2772	drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
2330	Serge	2773	if (!intel_sdvo_connector->right)
		2774	return false;
		2775
3243	Serge	2776	drm_object_attach_property(&connector->base,
2330	Serge	2777	intel_sdvo_connector->right,
		2778	intel_sdvo_connector->right_margin);
		2779	DRM_DEBUG_KMS("h_overscan: max %d, "
		2780	"default %d, current %d\n",
		2781	data_value[0], data_value[1], response);
		2782	}
		2783
		2784	if (enhancements.overscan_v) {
		2785	if (!intel_sdvo_get_value(intel_sdvo,
		2786	SDVO_CMD_GET_MAX_OVERSCAN_V,
		2787	&data_value, 4))
		2788	return false;
		2789
		2790	if (!intel_sdvo_get_value(intel_sdvo,
		2791	SDVO_CMD_GET_OVERSCAN_V,
		2792	&response, 2))
		2793	return false;
		2794
		2795	intel_sdvo_connector->max_vscan = data_value[0];
		2796	intel_sdvo_connector->top_margin = data_value[0] - response;
		2797	intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
		2798	intel_sdvo_connector->top =
3031	serge	2799	drm_property_create_range(dev, 0,
		2800	"top_margin", 0, data_value[0]);
2330	Serge	2801	if (!intel_sdvo_connector->top)
		2802	return false;
		2803
3243	Serge	2804	drm_object_attach_property(&connector->base,
2330	Serge	2805	intel_sdvo_connector->top,
		2806	intel_sdvo_connector->top_margin);
		2807
		2808	intel_sdvo_connector->bottom =
3031	serge	2809	drm_property_create_range(dev, 0,
		2810	"bottom_margin", 0, data_value[0]);
2330	Serge	2811	if (!intel_sdvo_connector->bottom)
		2812	return false;
		2813
3243	Serge	2814	drm_object_attach_property(&connector->base,
2330	Serge	2815	intel_sdvo_connector->bottom,
		2816	intel_sdvo_connector->bottom_margin);
		2817	DRM_DEBUG_KMS("v_overscan: max %d, "
		2818	"default %d, current %d\n",
		2819	data_value[0], data_value[1], response);
		2820	}
		2821
		2822	ENHANCEMENT(hpos, HPOS);
		2823	ENHANCEMENT(vpos, VPOS);
		2824	ENHANCEMENT(saturation, SATURATION);
		2825	ENHANCEMENT(contrast, CONTRAST);
		2826	ENHANCEMENT(hue, HUE);
		2827	ENHANCEMENT(sharpness, SHARPNESS);
		2828	ENHANCEMENT(brightness, BRIGHTNESS);
		2829	ENHANCEMENT(flicker_filter, FLICKER_FILTER);
		2830	ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
		2831	ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
		2832	ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
		2833	ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
		2834
		2835	if (enhancements.dot_crawl) {
		2836	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
		2837	return false;
		2838
		2839	intel_sdvo_connector->max_dot_crawl = 1;
		2840	intel_sdvo_connector->cur_dot_crawl = response & 0x1;
		2841	intel_sdvo_connector->dot_crawl =
3031	serge	2842	drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
2330	Serge	2843	if (!intel_sdvo_connector->dot_crawl)
		2844	return false;
		2845
3243	Serge	2846	drm_object_attach_property(&connector->base,
2330	Serge	2847	intel_sdvo_connector->dot_crawl,
		2848	intel_sdvo_connector->cur_dot_crawl);
		2849	DRM_DEBUG_KMS("dot crawl: current %d\n", response);
		2850	}
		2851
		2852	return true;
		2853	}
		2854
		2855	static bool
		2856	intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
		2857	struct intel_sdvo_connector *intel_sdvo_connector,
		2858	struct intel_sdvo_enhancements_reply enhancements)
		2859	{
		2860	struct drm_device *dev = intel_sdvo->base.base.dev;
		2861	struct drm_connector *connector = &intel_sdvo_connector->base.base;
		2862	uint16_t response, data_value[2];
		2863
		2864	ENHANCEMENT(brightness, BRIGHTNESS);
		2865
		2866	return true;
		2867	}
		2868	#undef ENHANCEMENT
		2869
		2870	static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
		2871	struct intel_sdvo_connector *intel_sdvo_connector)
		2872	{
		2873	union {
		2874	struct intel_sdvo_enhancements_reply reply;
		2875	uint16_t response;
		2876	} enhancements;
		2877
		2878	BUILD_BUG_ON(sizeof(enhancements) != 2);
		2879
		2880	enhancements.response = 0;
		2881	intel_sdvo_get_value(intel_sdvo,
		2882	SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
		2883	&enhancements, sizeof(enhancements));
		2884	if (enhancements.response == 0) {
		2885	DRM_DEBUG_KMS("No enhancement is supported\n");
		2886	return true;
		2887	}
		2888
		2889	if (IS_TV(intel_sdvo_connector))
		2890	return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2342	Serge	2891	else if (IS_LVDS(intel_sdvo_connector))
2330	Serge	2892	return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
		2893	else
		2894	return true;
		2895	}
		2896
		2897	static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
		2898	struct i2c_msg *msgs,
		2899	int num)
		2900	{
		2901	struct intel_sdvo *sdvo = adapter->algo_data;
		2902
		2903	if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
		2904	return -EIO;
		2905
		2906	return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
		2907	}
		2908
		2909	static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
		2910	{
		2911	struct intel_sdvo *sdvo = adapter->algo_data;
		2912	return sdvo->i2c->algo->functionality(sdvo->i2c);
		2913	}
		2914
		2915	static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
		2916	.master_xfer = intel_sdvo_ddc_proxy_xfer,
		2917	.functionality = intel_sdvo_ddc_proxy_func
		2918	};
		2919
		2920	static bool
		2921	intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
		2922	struct drm_device *dev)
		2923	{
3031	serge	2924	sdvo->ddc.owner = THIS_MODULE;
2330	Serge	2925	sdvo->ddc.class = I2C_CLASS_DDC;
		2926	snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
		2927	sdvo->ddc.dev.parent = &dev->pdev->dev;
		2928	sdvo->ddc.algo_data = sdvo;
		2929	sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
		2930
3243	Serge	2931	return i2c_add_adapter(&sdvo->ddc) == 0;
2330	Serge	2932	}
		2933
3031	serge	2934	bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
2330	Serge	2935	{
6084	serge	2936	struct drm_i915_private *dev_priv = dev->dev_private;
		2937	struct intel_encoder *intel_encoder;
		2938	struct intel_sdvo *intel_sdvo;
		2939	int i;
4560	Serge	2940	intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
6084	serge	2941	if (!intel_sdvo)
		2942	return false;
2330	Serge	2943
6084	serge	2944	intel_sdvo->sdvo_reg = sdvo_reg;
3031	serge	2945	intel_sdvo->is_sdvob = is_sdvob;
		2946	intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
6084	serge	2947	intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo);
3243	Serge	2948	if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
		2949	goto err_i2c_bus;
2330	Serge	2950
6084	serge	2951	/* encoder type will be decided later */
		2952	intel_encoder = &intel_sdvo->base;
		2953	intel_encoder->type = INTEL_OUTPUT_SDVO;
		2954	drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
2330	Serge	2955
6084	serge	2956	/* Read the regs to test if we can talk to the device */
		2957	for (i = 0; i < 0x40; i++) {
		2958	u8 byte;
2330	Serge	2959
6084	serge	2960	if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
3031	serge	2961	DRM_DEBUG_KMS("No SDVO device found on %s\n",
		2962	SDVO_NAME(intel_sdvo));
6084	serge	2963	goto err;
		2964	}
		2965	}
2330	Serge	2966
3746	Serge	2967	intel_encoder->compute_config = intel_sdvo_compute_config;
6084	serge	2968	if (HAS_PCH_SPLIT(dev)) {
		2969	intel_encoder->disable = pch_disable_sdvo;
		2970	intel_encoder->post_disable = pch_post_disable_sdvo;
		2971	} else {
		2972	intel_encoder->disable = intel_disable_sdvo;
		2973	}
5060	serge	2974	intel_encoder->pre_enable = intel_sdvo_pre_enable;
3031	serge	2975	intel_encoder->enable = intel_enable_sdvo;
		2976	intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
4104	Serge	2977	intel_encoder->get_config = intel_sdvo_get_config;
3031	serge	2978
6084	serge	2979	/* In default case sdvo lvds is false */
		2980	if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
		2981	goto err;
2330	Serge	2982
6084	serge	2983	if (intel_sdvo_output_setup(intel_sdvo,
		2984	intel_sdvo->caps.output_flags) != true) {
3031	serge	2985	DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
		2986	SDVO_NAME(intel_sdvo));
3120	serge	2987	/* Output_setup can leave behind connectors! */
		2988	goto err_output;
6084	serge	2989	}
2330	Serge	2990
3746	Serge	2991	/* Only enable the hotplug irq if we need it, to work around noisy
		2992	* hotplug lines.
		2993	*/
		2994	if (intel_sdvo->hotplug_active) {
		2995	intel_encoder->hpd_pin =
		2996	intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C;
		2997	}
		2998
3120	serge	2999	/*
		3000	* Cloning SDVO with anything is often impossible, since the SDVO
		3001	* encoder can request a special input timing mode. And even if that's
		3002	* not the case we have evidence that cloning a plain unscaled mode with
		3003	* VGA doesn't really work. Furthermore the cloning flags are way too
		3004	* simplistic anyway to express such constraints, so just give up on
		3005	* cloning for SDVO encoders.
		3006	*/
5060	serge	3007	intel_sdvo->base.cloneable = 0;
3120	serge	3008
6084	serge	3009	intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo);
2330	Serge	3010
6084	serge	3011	/* Set the input timing to the screen. Assume always input 0. */
		3012	if (!intel_sdvo_set_target_input(intel_sdvo))
3120	serge	3013	goto err_output;
2330	Serge	3014
6084	serge	3015	if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
		3016	&intel_sdvo->pixel_clock_min,
		3017	&intel_sdvo->pixel_clock_max))
3120	serge	3018	goto err_output;
2330	Serge	3019
6084	serge	3020	DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
		3021	"clock range %dMHz - %dMHz, "
		3022	"input 1: %c, input 2: %c, "
		3023	"output 1: %c, output 2: %c\n",
		3024	SDVO_NAME(intel_sdvo),
		3025	intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
		3026	intel_sdvo->caps.device_rev_id,
		3027	intel_sdvo->pixel_clock_min / 1000,
		3028	intel_sdvo->pixel_clock_max / 1000,
		3029	(intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
		3030	(intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
		3031	/* check currently supported outputs */
		3032	intel_sdvo->caps.output_flags &
		3033	(SDVO_OUTPUT_TMDS0 \| SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
		3034	intel_sdvo->caps.output_flags &
		3035	(SDVO_OUTPUT_TMDS1 \| SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
		3036	return true;
2330	Serge	3037
3120	serge	3038	err_output:
		3039	intel_sdvo_output_cleanup(intel_sdvo);
		3040
2330	Serge	3041	err:
6084	serge	3042	drm_encoder_cleanup(&intel_encoder->base);
3243	Serge	3043	i2c_del_adapter(&intel_sdvo->ddc);
		3044	err_i2c_bus:
		3045	intel_sdvo_unselect_i2c_bus(intel_sdvo);
6084	serge	3046	kfree(intel_sdvo);
2330	Serge	3047
6084	serge	3048	return false;
2330	Serge	3049	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_sdvo.c – Rev 6084