Subversion Repositories Kolibri OS

/*

 * Copyright 2006 Dave Airlie 

 * Copyright © 2006-2007 Intel Corporation

 *   Jesse Barnes 

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice (including the next

 * paragraph) shall be included in all copies or substantial portions of the

 * Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

 * DEALINGS IN THE SOFTWARE.

 *

 * Authors:

 *  Eric Anholt 

 */

#include 

#include 

//#include 

#include "drmP.h"

#include "drm.h"

#include "drm_crtc.h"

#include "drm_edid.h"

#include "intel_drv.h"

#include "i915_drm.h"

#include "i915_drv.h"

#include "intel_sdvo_regs.h"

unsigned int hweight16(unsigned int w)

{

    unsigned int res = w - ((w >> 1) & 0x5555);

    res = (res & 0x3333) + ((res >> 2) & 0x3333);

    res = (res + (res >> 4)) & 0x0F0F;

    return (res + (res >> 8)) & 0x00FF;

}

#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)

#define SDVO_RGB_MASK  (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)

#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)

#define SDVO_TV_MASK   (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)

#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\

                         SDVO_TV_MASK)

#define IS_TV(c)    (c->output_flag & SDVO_TV_MASK)

#define IS_TMDS(c)  (c->output_flag & SDVO_TMDS_MASK)

#define IS_LVDS(c)  (c->output_flag & SDVO_LVDS_MASK)

#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))

static const char *tv_format_names[] = {

    "NTSC_M"   , "NTSC_J"  , "NTSC_443",

    "PAL_B"    , "PAL_D"   , "PAL_G"   ,

    "PAL_H"    , "PAL_I"   , "PAL_M"   ,

    "PAL_N"    , "PAL_NC"  , "PAL_60"  ,

    "SECAM_B"  , "SECAM_D" , "SECAM_G" ,

    "SECAM_K"  , "SECAM_K1", "SECAM_L" ,

    "SECAM_60"

};

#define TV_FORMAT_NUM  (sizeof(tv_format_names) / sizeof(*tv_format_names))

struct intel_sdvo {

    struct intel_encoder base;

    struct i2c_adapter *i2c;

    u8 slave_addr;

    struct i2c_adapter ddc;

    /* Register for the SDVO device: SDVOB or SDVOC */

    int sdvo_reg;

    /* Active outputs controlled by this SDVO output */

    uint16_t controlled_output;

    /*

     * Capabilities of the SDVO device returned by

     * i830_sdvo_get_capabilities()

     */

    struct intel_sdvo_caps caps;

    /* Pixel clock limitations reported by the SDVO device, in kHz */

    int pixel_clock_min, pixel_clock_max;

    /*

    * For multiple function SDVO device,

    * this is for current attached outputs.

    */

    uint16_t attached_output;

    /**

     * This is used to select the color range of RBG outputs in HDMI mode.

     * It is only valid when using TMDS encoding and 8 bit per color mode.

     */

    uint32_t color_range;

    /**

     * This is set if we're going to treat the device as TV-out.

     *

     * While we have these nice friendly flags for output types that ought

     * to decide this for us, the S-Video output on our HDMI+S-Video card

     * shows up as RGB1 (VGA).

     */

    bool is_tv;

    /* This is for current tv format name */

    int tv_format_index;

    /**

     * This is set if we treat the device as HDMI, instead of DVI.

     */

    bool is_hdmi;

    bool has_hdmi_monitor;

    bool has_hdmi_audio;

    /**

     * This is set if we detect output of sdvo device as LVDS and

     * have a valid fixed mode to use with the panel.

     */

    bool is_lvds;

    /**

     * This is sdvo fixed pannel mode pointer

     */

    struct drm_display_mode *sdvo_lvds_fixed_mode;

    /* DDC bus used by this SDVO encoder */

    uint8_t ddc_bus;

    /* Input timings for adjusted_mode */

    struct intel_sdvo_dtd input_dtd;

};

struct intel_sdvo_connector {

    struct intel_connector base;

    /* Mark the type of connector */

    uint16_t output_flag;

    int force_audio;

    /* This contains all current supported TV format */

    u8 tv_format_supported[TV_FORMAT_NUM];

    int   format_supported_num;

    struct drm_property *tv_format;

    /* add the property for the SDVO-TV */

    struct drm_property *left;

    struct drm_property *right;

    struct drm_property *top;

    struct drm_property *bottom;

    struct drm_property *hpos;

    struct drm_property *vpos;

    struct drm_property *contrast;

    struct drm_property *saturation;

    struct drm_property *hue;

    struct drm_property *sharpness;

    struct drm_property *flicker_filter;

    struct drm_property *flicker_filter_adaptive;

    struct drm_property *flicker_filter_2d;

    struct drm_property *tv_chroma_filter;

    struct drm_property *tv_luma_filter;

    struct drm_property *dot_crawl;

    /* add the property for the SDVO-TV/LVDS */

    struct drm_property *brightness;

    /* Add variable to record current setting for the above property */

    u32 left_margin, right_margin, top_margin, bottom_margin;

    /* this is to get the range of margin.*/

    u32 max_hscan,  max_vscan;

    u32 max_hpos, cur_hpos;

    u32 max_vpos, cur_vpos;

    u32 cur_brightness, max_brightness;

    u32 cur_contrast,   max_contrast;

    u32 cur_saturation, max_saturation;

    u32 cur_hue,    max_hue;

    u32 cur_sharpness,  max_sharpness;

    u32 cur_flicker_filter,     max_flicker_filter;

    u32 cur_flicker_filter_adaptive,    max_flicker_filter_adaptive;

    u32 cur_flicker_filter_2d,      max_flicker_filter_2d;

    u32 cur_tv_chroma_filter,   max_tv_chroma_filter;

    u32 cur_tv_luma_filter, max_tv_luma_filter;

    u32 cur_dot_crawl,  max_dot_crawl;

};

static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)

{

    return container_of(encoder, struct intel_sdvo, base.base);

}

static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)

{

	return container_of(intel_attached_encoder(connector),

			    struct intel_sdvo, base);

}

static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)

{

	return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);

}

static bool

intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);

static bool

intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,

			      struct intel_sdvo_connector *intel_sdvo_connector,

			      int type);

static bool

intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,

				   struct intel_sdvo_connector *intel_sdvo_connector);

/**

 * Writes the SDVOB or SDVOC with the given value, but always writes both

 * SDVOB and SDVOC to work around apparent hardware issues (according to

 * comments in the BIOS).

 */

static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)

{

	struct drm_device *dev = intel_sdvo->base.base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 bval = val, cval = val;

	int i;

	if (intel_sdvo->sdvo_reg == PCH_SDVOB) {

		I915_WRITE(intel_sdvo->sdvo_reg, val);

		I915_READ(intel_sdvo->sdvo_reg);

		return;

	}

	if (intel_sdvo->sdvo_reg == SDVOB) {

		cval = I915_READ(SDVOC);

	} else {

		bval = I915_READ(SDVOB);

	}

	/*

	 * Write the registers twice for luck. Sometimes,

	 * writing them only once doesn't appear to 'stick'.

	 * The BIOS does this too. Yay, magic

	 */

	for (i = 0; i < 2; i++)

	{

		I915_WRITE(SDVOB, bval);

		I915_READ(SDVOB);

		I915_WRITE(SDVOC, cval);

		I915_READ(SDVOC);

	}

}

static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)

{

	struct i2c_msg msgs[] = {

		{

			.addr = intel_sdvo->slave_addr,

			.flags = 0,

			.len = 1,

			.buf = &addr,

		},

		{

			.addr = intel_sdvo->slave_addr,

			.flags = I2C_M_RD,

			.len = 1,

			.buf = ch,

		}

	};

	int ret;

	if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)

		return true;

	DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);

	return false;

}

#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}

/** Mapping of command numbers to names, for debug output */

static const struct _sdvo_cmd_name {

	u8 cmd;

	const char *name;

} sdvo_cmd_names[] = {

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),

    /* Add the op code for SDVO enhancements */

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),

    /* HDMI op code */

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),

    SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),

};

#define IS_SDVOB(reg)	(reg == SDVOB || reg == PCH_SDVOB)

#define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")

static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,

				   const void *args, int args_len)

{

	int i;

	DRM_DEBUG_KMS("%s: W: %02X ",

				SDVO_NAME(intel_sdvo), cmd);

	for (i = 0; i < args_len; i++)

		DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);

	for (; i < 8; i++)

		DRM_LOG_KMS("   ");

	for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {

		if (cmd == sdvo_cmd_names[i].cmd) {

			DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);

			break;

		}

	}

	if (i == ARRAY_SIZE(sdvo_cmd_names))

		DRM_LOG_KMS("(%02X)", cmd);

	DRM_LOG_KMS("\n");

}

static const char *cmd_status_names[] = {

	"Power on",

	"Success",

	"Not supported",

	"Invalid arg",

	"Pending",

	"Target not specified",

	"Scaling not supported"

};

static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,

				 const void *args, int args_len)

{

	u8 buf[args_len*2 + 2], status;

	struct i2c_msg msgs[args_len + 3];

	int i, ret;

	intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);

	for (i = 0; i < args_len; i++) {

		msgs[i].addr = intel_sdvo->slave_addr;

		msgs[i].flags = 0;

		msgs[i].len = 2;

		msgs[i].buf = buf + 2 *i;

		buf[2*i + 0] = SDVO_I2C_ARG_0 - i;

		buf[2*i + 1] = ((u8*)args)[i];

	}

	msgs[i].addr = intel_sdvo->slave_addr;

	msgs[i].flags = 0;

	msgs[i].len = 2;

	msgs[i].buf = buf + 2*i;

	buf[2*i + 0] = SDVO_I2C_OPCODE;

	buf[2*i + 1] = cmd;

	/* the following two are to read the response */

	status = SDVO_I2C_CMD_STATUS;

	msgs[i+1].addr = intel_sdvo->slave_addr;

	msgs[i+1].flags = 0;

	msgs[i+1].len = 1;

	msgs[i+1].buf = &status;

	msgs[i+2].addr = intel_sdvo->slave_addr;

	msgs[i+2].flags = I2C_M_RD;

	msgs[i+2].len = 1;

	msgs[i+2].buf = &status;

	ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);

	if (ret < 0) {

		DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);

		return false;

	}

	if (ret != i+3) {

		/* failure in I2C transfer */

		DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);

		return false;

	}

	return true;

}

static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,

				     void *response, int response_len)

{

	u8 retry = 5;

	u8 status;

	int i;

	DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));

	/*

	 * The documentation states that all commands will be

	 * processed within 15µs, and that we need only poll

	 * the status byte a maximum of 3 times in order for the

	 * command to be complete.

	 *

	 * Check 5 times in case the hardware failed to read the docs.

	 */

	if (!intel_sdvo_read_byte(intel_sdvo,

				  SDVO_I2C_CMD_STATUS,

				  &status))

		goto log_fail;

	while (status == SDVO_CMD_STATUS_PENDING && retry--) {

		udelay(15);

		if (!intel_sdvo_read_byte(intel_sdvo,

					  SDVO_I2C_CMD_STATUS,

					  &status))

			goto log_fail;

	}

	if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)

		DRM_LOG_KMS("(%s)", cmd_status_names[status]);

	else

		DRM_LOG_KMS("(??? %d)", status);

	if (status != SDVO_CMD_STATUS_SUCCESS)

		goto log_fail;

	/* Read the command response */

	for (i = 0; i < response_len; i++) {

		if (!intel_sdvo_read_byte(intel_sdvo,

					  SDVO_I2C_RETURN_0 + i,

					  &((u8 *)response)[i]))

			goto log_fail;

		DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);

	}

	DRM_LOG_KMS("\n");

	return true;

log_fail:

	DRM_LOG_KMS("... failed\n");

	return false;

}

static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)

{

	if (mode->clock >= 100000)

		return 1;

	else if (mode->clock >= 50000)

		return 2;

	else

		return 4;

}

static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,

					      u8 ddc_bus)

{

	/* This must be the immediately preceding write before the i2c xfer */

	return intel_sdvo_write_cmd(intel_sdvo,

				    SDVO_CMD_SET_CONTROL_BUS_SWITCH,

				    &ddc_bus, 1);

}

static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)

{

	if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))

		return false;

	return intel_sdvo_read_response(intel_sdvo, NULL, 0);

}

static bool

intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)

{

	if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))

		return false;

	return intel_sdvo_read_response(intel_sdvo, value, len);

}

static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)

{

	struct intel_sdvo_set_target_input_args targets = {0};

	return intel_sdvo_set_value(intel_sdvo,

				    SDVO_CMD_SET_TARGET_INPUT,

				    &targets, sizeof(targets));

}

/**

 * Return whether each input is trained.

 *

 * This function is making an assumption about the layout of the response,

 * which should be checked against the docs.

 */

static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)

{

	struct intel_sdvo_get_trained_inputs_response response;

	BUILD_BUG_ON(sizeof(response) != 1);

	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,

				  &response, sizeof(response)))

		return false;

	*input_1 = response.input0_trained;

	*input_2 = response.input1_trained;

	return true;

}

static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,

					  u16 outputs)

{

	return intel_sdvo_set_value(intel_sdvo,

				    SDVO_CMD_SET_ACTIVE_OUTPUTS,

				    &outputs, sizeof(outputs));

}

static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,

						   int *clock_min,

						   int *clock_max)

{

	struct intel_sdvo_pixel_clock_range clocks;

	BUILD_BUG_ON(sizeof(clocks) != 4);

	if (!intel_sdvo_get_value(intel_sdvo,

				  SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,

				  &clocks, sizeof(clocks)))

		return false;

	/* Convert the values from units of 10 kHz to kHz. */

	*clock_min = clocks.min * 10;

	*clock_max = clocks.max * 10;

	return true;

}

static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,

					 u16 outputs)

{

	return intel_sdvo_set_value(intel_sdvo,

				    SDVO_CMD_SET_TARGET_OUTPUT,

				    &outputs, sizeof(outputs));

}

static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,

				  struct intel_sdvo_dtd *dtd)

{

	return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&

		intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));

}

static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,

					 struct intel_sdvo_dtd *dtd)

{

	return intel_sdvo_set_timing(intel_sdvo,

				     SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);

}

static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,

					 struct intel_sdvo_dtd *dtd)

{

	return intel_sdvo_set_timing(intel_sdvo,

				     SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);

}

static bool

intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,

					 uint16_t clock,

					 uint16_t width,

					 uint16_t height)

{

	struct intel_sdvo_preferred_input_timing_args args;

	memset(&args, 0, sizeof(args));

	args.clock = clock;

	args.width = width;

	args.height = height;

	args.interlace = 0;

	if (intel_sdvo->is_lvds &&

	   (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||

	    intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))

		args.scaled = 1;

	return intel_sdvo_set_value(intel_sdvo,

				    SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,

				    &args, sizeof(args));

}

static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,

						  struct intel_sdvo_dtd *dtd)

{

	BUILD_BUG_ON(sizeof(dtd->part1) != 8);

	BUILD_BUG_ON(sizeof(dtd->part2) != 8);

	return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,

				    &dtd->part1, sizeof(dtd->part1)) &&

		intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,

				     &dtd->part2, sizeof(dtd->part2));

}

static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)

{

	return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);

}

static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,

					 const struct drm_display_mode *mode)

{

	uint16_t width, height;

	uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;

	uint16_t h_sync_offset, v_sync_offset;

	width = mode->crtc_hdisplay;

	height = mode->crtc_vdisplay;

	/* do some mode translations */

	h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;

	h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;

	v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;

	v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;

	h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;

	v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;

	dtd->part1.clock = mode->clock / 10;

	dtd->part1.h_active = width & 0xff;

	dtd->part1.h_blank = h_blank_len & 0xff;

	dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |

		((h_blank_len >> 8) & 0xf);

	dtd->part1.v_active = height & 0xff;

	dtd->part1.v_blank = v_blank_len & 0xff;

	dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |

		((v_blank_len >> 8) & 0xf);

	dtd->part2.h_sync_off = h_sync_offset & 0xff;

	dtd->part2.h_sync_width = h_sync_len & 0xff;

	dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |

		(v_sync_len & 0xf);

	dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |

		((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |

		((v_sync_len & 0x30) >> 4);

	dtd->part2.dtd_flags = 0x18;

	if (mode->flags & DRM_MODE_FLAG_PHSYNC)

		dtd->part2.dtd_flags |= 0x2;

	if (mode->flags & DRM_MODE_FLAG_PVSYNC)

		dtd->part2.dtd_flags |= 0x4;

	dtd->part2.sdvo_flags = 0;

	dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;

	dtd->part2.reserved = 0;

}

static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,

					 const struct intel_sdvo_dtd *dtd)

{

	mode->hdisplay = dtd->part1.h_active;

	mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;

	mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;

	mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;

	mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;

	mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;

	mode->htotal = mode->hdisplay + dtd->part1.h_blank;

	mode->htotal += (dtd->part1.h_high & 0xf) << 8;

	mode->vdisplay = dtd->part1.v_active;

	mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;

	mode->vsync_start = mode->vdisplay;

	mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;

	mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;

	mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;

	mode->vsync_end = mode->vsync_start +

		(dtd->part2.v_sync_off_width & 0xf);

	mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;

	mode->vtotal = mode->vdisplay + dtd->part1.v_blank;

	mode->vtotal += (dtd->part1.v_high & 0xf) << 8;

	mode->clock = dtd->part1.clock * 10;

	mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);

	if (dtd->part2.dtd_flags & 0x2)

		mode->flags |= DRM_MODE_FLAG_PHSYNC;

	if (dtd->part2.dtd_flags & 0x4)

		mode->flags |= DRM_MODE_FLAG_PVSYNC;

}

static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)

{

	struct intel_sdvo_encode encode;

	BUILD_BUG_ON(sizeof(encode) != 2);

	return intel_sdvo_get_value(intel_sdvo,

				  SDVO_CMD_GET_SUPP_ENCODE,

				  &encode, sizeof(encode));

}

static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,

				  uint8_t mode)

{

	return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);

}

static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,

				       uint8_t mode)

{

	return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);

}

#if 0

static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)

{

	int i, j;

	uint8_t set_buf_index[2];

	uint8_t av_split;

	uint8_t buf_size;

	uint8_t buf[48];

	uint8_t *pos;

	intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);

	for (i = 0; i <= av_split; i++) {

		set_buf_index[0] = i; set_buf_index[1] = 0;

		intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,

				     set_buf_index, 2);

		intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);

		intel_sdvo_read_response(encoder, &buf_size, 1);

		pos = buf;

		for (j = 0; j <= buf_size; j += 8) {

			intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,

					     NULL, 0);

			intel_sdvo_read_response(encoder, pos, 8);

			pos += 8;

		}

	}

}

#endif

static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)

{

	struct dip_infoframe avi_if = {

		.type = DIP_TYPE_AVI,

		.ver = DIP_VERSION_AVI,

		.len = DIP_LEN_AVI,

	};

	uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;

	uint8_t set_buf_index[2] = { 1, 0 };

	uint64_t *data = (uint64_t *)&avi_if;

	unsigned i;

	intel_dip_infoframe_csum(&avi_if);

	if (!intel_sdvo_set_value(intel_sdvo,

				  SDVO_CMD_SET_HBUF_INDEX,

				  set_buf_index, 2))

		return false;

	for (i = 0; i < sizeof(avi_if); i += 8) {

		if (!intel_sdvo_set_value(intel_sdvo,

					  SDVO_CMD_SET_HBUF_DATA,

					  data, 8))

			return false;

		data++;

	}

	return intel_sdvo_set_value(intel_sdvo,

				    SDVO_CMD_SET_HBUF_TXRATE,

				    &tx_rate, 1);

}

static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)

{

	struct intel_sdvo_tv_format format;

	uint32_t format_map;

	format_map = 1 << intel_sdvo->tv_format_index;

	memset(&format, 0, sizeof(format));

	memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));

	BUILD_BUG_ON(sizeof(format) != 6);

	return intel_sdvo_set_value(intel_sdvo,

				    SDVO_CMD_SET_TV_FORMAT,

				    &format, sizeof(format));

}

static bool

intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,

					struct drm_display_mode *mode)

{

	struct intel_sdvo_dtd output_dtd;

	if (!intel_sdvo_set_target_output(intel_sdvo,

					  intel_sdvo->attached_output))

		return false;

	intel_sdvo_get_dtd_from_mode(&output_dtd, mode);

	if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))

		return false;

	return true;

}

static bool

intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,

					struct drm_display_mode *mode,

					struct drm_display_mode *adjusted_mode)

{

	/* Reset the input timing to the screen. Assume always input 0. */

	if (!intel_sdvo_set_target_input(intel_sdvo))

		return false;

	if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,

						      mode->clock / 10,

						      mode->hdisplay,

						      mode->vdisplay))

		return false;

	if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,

						   &intel_sdvo->input_dtd))

		return false;

	intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd);

	drm_mode_set_crtcinfo(adjusted_mode, 0);

	return true;

}

static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,

				  struct drm_display_mode *mode,

				  struct drm_display_mode *adjusted_mode)

{

	struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);

	int multiplier;

	/* We need to construct preferred input timings based on our

	 * output timings.  To do that, we have to set the output

	 * timings, even though this isn't really the right place in

	 * the sequence to do it. Oh well.

	 */

	if (intel_sdvo->is_tv) {

		if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))

			return false;

		(void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,

							     mode,

							     adjusted_mode);

	} else if (intel_sdvo->is_lvds) {

		if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,

							     intel_sdvo->sdvo_lvds_fixed_mode))

			return false;

		(void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,

							     mode,

							     adjusted_mode);

	}

	/* Make the CRTC code factor in the SDVO pixel multiplier.  The

	 * SDVO device will factor out the multiplier during mode_set.

	 */

	multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);

	intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);

	return true;

}

static void intel_sdvo_mode_set(struct drm_encoder *encoder,

				struct drm_display_mode *mode,

				struct drm_display_mode *adjusted_mode)

{

	struct drm_device *dev = encoder->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_crtc *crtc = encoder->crtc;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);

	u32 sdvox;

	struct intel_sdvo_in_out_map in_out;

	struct intel_sdvo_dtd input_dtd;

	int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);

	int rate;

	if (!mode)

		return;

	/* First, set the input mapping for the first input to our controlled

	 * output. This is only correct if we're a single-input device, in

	 * which case the first input is the output from the appropriate SDVO

	 * channel on the motherboard.  In a two-input device, the first input

	 * will be SDVOB and the second SDVOC.

	 */

	in_out.in0 = intel_sdvo->attached_output;

	in_out.in1 = 0;

	intel_sdvo_set_value(intel_sdvo,

			     SDVO_CMD_SET_IN_OUT_MAP,

			     &in_out, sizeof(in_out));

	/* Set the output timings to the screen */

	if (!intel_sdvo_set_target_output(intel_sdvo,

					  intel_sdvo->attached_output))

		return;

	/* We have tried to get input timing in mode_fixup, and filled into

	 * adjusted_mode.

	 */

	if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {

		input_dtd = intel_sdvo->input_dtd;

	} else {

		/* Set the output timing to the screen */

		if (!intel_sdvo_set_target_output(intel_sdvo,

						  intel_sdvo->attached_output))

			return;

		intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);

		(void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);

	}

	/* Set the input timing to the screen. Assume always input 0. */

	if (!intel_sdvo_set_target_input(intel_sdvo))

		return;

	if (intel_sdvo->has_hdmi_monitor) {

		intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);

		intel_sdvo_set_colorimetry(intel_sdvo,

					   SDVO_COLORIMETRY_RGB256);

		intel_sdvo_set_avi_infoframe(intel_sdvo);

	} else

		intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);

	if (intel_sdvo->is_tv &&

	    !intel_sdvo_set_tv_format(intel_sdvo))

		return;

	(void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);

	switch (pixel_multiplier) {

	default:

	case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;

	case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;

	case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;

	}

	if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))

		return;

	/* Set the SDVO control regs. */

	if (INTEL_INFO(dev)->gen >= 4) {

		sdvox = 0;

		if (intel_sdvo->is_hdmi)

			sdvox |= intel_sdvo->color_range;

		if (INTEL_INFO(dev)->gen < 5)

			sdvox |= SDVO_BORDER_ENABLE;

		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)

			sdvox |= SDVO_VSYNC_ACTIVE_HIGH;

		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)

			sdvox |= SDVO_HSYNC_ACTIVE_HIGH;

	} else {

		sdvox = I915_READ(intel_sdvo->sdvo_reg);

		switch (intel_sdvo->sdvo_reg) {

		case SDVOB:

			sdvox &= SDVOB_PRESERVE_MASK;

			break;

		case SDVOC:

			sdvox &= SDVOC_PRESERVE_MASK;

			break;

		}

		sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;

	}

	if (intel_crtc->pipe == 1)

		sdvox |= SDVO_PIPE_B_SELECT;

	if (intel_sdvo->has_hdmi_audio)

		sdvox |= SDVO_AUDIO_ENABLE;

	if (INTEL_INFO(dev)->gen >= 4) {

		/* done in crtc_mode_set as the dpll_md reg must be written early */

	} else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {

		/* done in crtc_mode_set as it lives inside the dpll register */

	} else {

		sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;

	}

	if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&

	    INTEL_INFO(dev)->gen < 5)

		sdvox |= SDVO_STALL_SELECT;

	intel_sdvo_write_sdvox(intel_sdvo, sdvox);

}

static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)

{

	struct drm_device *dev = encoder->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);

	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);

	u32 temp;

	if (mode != DRM_MODE_DPMS_ON) {

		intel_sdvo_set_active_outputs(intel_sdvo, 0);

		if (0)

			intel_sdvo_set_encoder_power_state(intel_sdvo, mode);

		if (mode == DRM_MODE_DPMS_OFF) {

			temp = I915_READ(intel_sdvo->sdvo_reg);

			if ((temp & SDVO_ENABLE) != 0) {

				intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);

			}

		}

	} else {

		bool input1, input2;

		int i;

		u8 status;

		temp = I915_READ(intel_sdvo->sdvo_reg);

		if ((temp & SDVO_ENABLE) == 0)

			intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);

		for (i = 0; i < 2; i++)

			intel_wait_for_vblank(dev, intel_crtc->pipe);

		status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);

		/* Warn if the device reported failure to sync.

		 * A lot of SDVO devices fail to notify of sync, but it's

		 * a given it the status is a success, we succeeded.

		 */

		if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {

			DRM_DEBUG_KMS("First %s output reported failure to "

					"sync\n", SDVO_NAME(intel_sdvo));

		}