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Rev | Author | Line No. | Line |
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2326 | Serge | 1 | #ifndef _INTEL_RINGBUFFER_H_ |
2 | #define _INTEL_RINGBUFFER_H_ |
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3 | |||
5060 | serge | 4 | #include |
5 | |||
6 | #define I915_CMD_HASH_ORDER 9 |
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7 | |||
5354 | serge | 8 | /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill, |
9 | * but keeps the logic simple. Indeed, the whole purpose of this macro is just |
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10 | * to give some inclination as to some of the magic values used in the various |
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11 | * workarounds! |
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12 | */ |
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13 | #define CACHELINE_BYTES 64 |
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14 | |||
3243 | Serge | 15 | /* |
16 | * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use" |
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17 | * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use" |
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18 | * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use" |
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19 | * |
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20 | * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same |
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21 | * cacheline, the Head Pointer must not be greater than the Tail |
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22 | * Pointer." |
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23 | */ |
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24 | #define I915_RING_FREE_SPACE 64 |
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25 | |||
2326 | Serge | 26 | struct intel_hw_status_page { |
3031 | serge | 27 | u32 *page_addr; |
2326 | Serge | 28 | unsigned int gfx_addr; |
29 | struct drm_i915_gem_object *obj; |
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30 | }; |
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31 | |||
32 | #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base)) |
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33 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) |
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34 | |||
35 | #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base)) |
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36 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) |
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37 | |||
38 | #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base)) |
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39 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) |
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40 | |||
41 | #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base)) |
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42 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) |
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43 | |||
44 | #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base)) |
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45 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) |
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46 | |||
5060 | serge | 47 | #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base)) |
48 | #define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val) |
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49 | |||
50 | /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to |
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51 | * do the writes, and that must have qw aligned offsets, simply pretend it's 8b. |
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52 | */ |
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53 | #define i915_semaphore_seqno_size sizeof(uint64_t) |
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54 | #define GEN8_SIGNAL_OFFSET(__ring, to) \ |
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55 | (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \ |
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56 | ((__ring)->id * I915_NUM_RINGS * i915_semaphore_seqno_size) + \ |
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57 | (i915_semaphore_seqno_size * (to))) |
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58 | |||
59 | #define GEN8_WAIT_OFFSET(__ring, from) \ |
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60 | (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \ |
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61 | ((from) * I915_NUM_RINGS * i915_semaphore_seqno_size) + \ |
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62 | (i915_semaphore_seqno_size * (__ring)->id)) |
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63 | |||
64 | #define GEN8_RING_SEMAPHORE_INIT do { \ |
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65 | if (!dev_priv->semaphore_obj) { \ |
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66 | break; \ |
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67 | } \ |
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68 | ring->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET(ring, RCS); \ |
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69 | ring->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET(ring, VCS); \ |
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70 | ring->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET(ring, BCS); \ |
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71 | ring->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET(ring, VECS); \ |
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72 | ring->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET(ring, VCS2); \ |
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73 | ring->semaphore.signal_ggtt[ring->id] = MI_SEMAPHORE_SYNC_INVALID; \ |
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74 | } while(0) |
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75 | |||
4104 | Serge | 76 | enum intel_ring_hangcheck_action { |
4560 | Serge | 77 | HANGCHECK_IDLE = 0, |
4104 | Serge | 78 | HANGCHECK_WAIT, |
79 | HANGCHECK_ACTIVE, |
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5060 | serge | 80 | HANGCHECK_ACTIVE_LOOP, |
4104 | Serge | 81 | HANGCHECK_KICK, |
82 | HANGCHECK_HUNG, |
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83 | }; |
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2326 | Serge | 84 | |
5060 | serge | 85 | #define HANGCHECK_SCORE_RING_HUNG 31 |
86 | |||
4104 | Serge | 87 | struct intel_ring_hangcheck { |
5060 | serge | 88 | u64 acthd; |
89 | u64 max_acthd; |
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4104 | Serge | 90 | u32 seqno; |
91 | int score; |
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92 | enum intel_ring_hangcheck_action action; |
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5060 | serge | 93 | int deadlock; |
4104 | Serge | 94 | }; |
95 | |||
5060 | serge | 96 | struct intel_ringbuffer { |
97 | struct drm_i915_gem_object *obj; |
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2326 | Serge | 98 | void __iomem *virtual_start; |
99 | |||
5354 | serge | 100 | struct intel_engine_cs *ring; |
101 | |||
102 | /* |
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103 | * FIXME: This backpointer is an artifact of the history of how the |
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104 | * execlist patches came into being. It will get removed once the basic |
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105 | * code has landed. |
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106 | */ |
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107 | struct intel_context *FIXME_lrc_ctx; |
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108 | |||
2326 | Serge | 109 | u32 head; |
110 | u32 tail; |
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111 | int space; |
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112 | int size; |
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113 | int effective_size; |
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114 | |||
3031 | serge | 115 | /** We track the position of the requests in the ring buffer, and |
116 | * when each is retired we increment last_retired_head as the GPU |
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117 | * must have finished processing the request and so we know we |
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118 | * can advance the ringbuffer up to that position. |
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119 | * |
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120 | * last_retired_head is set to -1 after the value is consumed so |
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121 | * we can detect new retirements. |
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122 | */ |
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123 | u32 last_retired_head; |
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5060 | serge | 124 | }; |
3031 | serge | 125 | |
5060 | serge | 126 | struct intel_engine_cs { |
127 | const char *name; |
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128 | enum intel_ring_id { |
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129 | RCS = 0x0, |
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130 | VCS, |
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131 | BCS, |
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132 | VECS, |
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133 | VCS2 |
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134 | } id; |
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135 | #define I915_NUM_RINGS 5 |
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136 | #define LAST_USER_RING (VECS + 1) |
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137 | u32 mmio_base; |
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138 | struct drm_device *dev; |
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139 | struct intel_ringbuffer *buffer; |
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140 | |||
141 | struct intel_hw_status_page status_page; |
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142 | |||
4104 | Serge | 143 | unsigned irq_refcount; /* protected by dev_priv->irq_lock */ |
3031 | serge | 144 | u32 irq_enable_mask; /* bitmask to enable ring interrupt */ |
2326 | Serge | 145 | u32 trace_irq_seqno; |
5060 | serge | 146 | bool __must_check (*irq_get)(struct intel_engine_cs *ring); |
147 | void (*irq_put)(struct intel_engine_cs *ring); |
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2326 | Serge | 148 | |
5060 | serge | 149 | int (*init)(struct intel_engine_cs *ring); |
2326 | Serge | 150 | |
5354 | serge | 151 | int (*init_context)(struct intel_engine_cs *ring, |
152 | struct intel_context *ctx); |
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153 | |||
5060 | serge | 154 | void (*write_tail)(struct intel_engine_cs *ring, |
2326 | Serge | 155 | u32 value); |
5060 | serge | 156 | int __must_check (*flush)(struct intel_engine_cs *ring, |
2326 | Serge | 157 | u32 invalidate_domains, |
158 | u32 flush_domains); |
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5060 | serge | 159 | int (*add_request)(struct intel_engine_cs *ring); |
3031 | serge | 160 | /* Some chipsets are not quite as coherent as advertised and need |
161 | * an expensive kick to force a true read of the up-to-date seqno. |
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162 | * However, the up-to-date seqno is not always required and the last |
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163 | * seen value is good enough. Note that the seqno will always be |
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164 | * monotonic, even if not coherent. |
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165 | */ |
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5060 | serge | 166 | u32 (*get_seqno)(struct intel_engine_cs *ring, |
3031 | serge | 167 | bool lazy_coherency); |
5060 | serge | 168 | void (*set_seqno)(struct intel_engine_cs *ring, |
3480 | Serge | 169 | u32 seqno); |
5060 | serge | 170 | int (*dispatch_execbuffer)(struct intel_engine_cs *ring, |
171 | u64 offset, u32 length, |
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3243 | Serge | 172 | unsigned flags); |
173 | #define I915_DISPATCH_SECURE 0x1 |
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174 | #define I915_DISPATCH_PINNED 0x2 |
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5060 | serge | 175 | void (*cleanup)(struct intel_engine_cs *ring); |
2326 | Serge | 176 | |
5060 | serge | 177 | /* GEN8 signal/wait table - never trust comments! |
178 | * signal to signal to signal to signal to signal to |
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179 | * RCS VCS BCS VECS VCS2 |
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180 | * -------------------------------------------------------------------- |
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181 | * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) | |
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182 | * |------------------------------------------------------------------- |
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183 | * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) | |
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184 | * |------------------------------------------------------------------- |
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185 | * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) | |
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186 | * |------------------------------------------------------------------- |
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187 | * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) | |
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188 | * |------------------------------------------------------------------- |
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189 | * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) | |
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190 | * |------------------------------------------------------------------- |
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191 | * |
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192 | * Generalization: |
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193 | * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id) |
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194 | * ie. transpose of g(x, y) |
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195 | * |
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196 | * sync from sync from sync from sync from sync from |
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197 | * RCS VCS BCS VECS VCS2 |
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198 | * -------------------------------------------------------------------- |
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199 | * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) | |
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200 | * |------------------------------------------------------------------- |
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201 | * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) | |
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202 | * |------------------------------------------------------------------- |
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203 | * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) | |
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204 | * |------------------------------------------------------------------- |
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205 | * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) | |
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206 | * |------------------------------------------------------------------- |
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207 | * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) | |
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208 | * |------------------------------------------------------------------- |
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209 | * |
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210 | * Generalization: |
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211 | * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id) |
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212 | * ie. transpose of f(x, y) |
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213 | */ |
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214 | struct { |
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215 | u32 sync_seqno[I915_NUM_RINGS-1]; |
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216 | |||
217 | union { |
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218 | struct { |
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4104 | Serge | 219 | /* our mbox written by others */ |
5060 | serge | 220 | u32 wait[I915_NUM_RINGS]; |
4104 | Serge | 221 | /* mboxes this ring signals to */ |
5060 | serge | 222 | u32 signal[I915_NUM_RINGS]; |
223 | } mbox; |
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224 | u64 signal_ggtt[I915_NUM_RINGS]; |
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225 | }; |
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4104 | Serge | 226 | |
5060 | serge | 227 | /* AKA wait() */ |
228 | int (*sync_to)(struct intel_engine_cs *ring, |
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229 | struct intel_engine_cs *to, |
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230 | u32 seqno); |
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231 | int (*signal)(struct intel_engine_cs *signaller, |
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232 | /* num_dwords needed by caller */ |
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233 | unsigned int num_dwords); |
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234 | } semaphore; |
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235 | |||
5354 | serge | 236 | /* Execlists */ |
237 | spinlock_t execlist_lock; |
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238 | struct list_head execlist_queue; |
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239 | struct list_head execlist_retired_req_list; |
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240 | u8 next_context_status_buffer; |
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241 | u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */ |
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242 | int (*emit_request)(struct intel_ringbuffer *ringbuf); |
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243 | int (*emit_flush)(struct intel_ringbuffer *ringbuf, |
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244 | u32 invalidate_domains, |
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245 | u32 flush_domains); |
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246 | int (*emit_bb_start)(struct intel_ringbuffer *ringbuf, |
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247 | u64 offset, unsigned flags); |
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248 | |||
2326 | Serge | 249 | /** |
250 | * List of objects currently involved in rendering from the |
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251 | * ringbuffer. |
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252 | * |
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253 | * Includes buffers having the contents of their GPU caches |
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254 | * flushed, not necessarily primitives. last_rendering_seqno |
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255 | * represents when the rendering involved will be completed. |
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256 | * |
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257 | * A reference is held on the buffer while on this list. |
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258 | */ |
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259 | struct list_head active_list; |
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260 | |||
261 | /** |
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262 | * List of breadcrumbs associated with GPU requests currently |
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263 | * outstanding. |
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264 | */ |
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265 | struct list_head request_list; |
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266 | |||
267 | /** |
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268 | * Do we have some not yet emitted requests outstanding? |
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269 | */ |
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4560 | Serge | 270 | struct drm_i915_gem_request *preallocated_lazy_request; |
271 | u32 outstanding_lazy_seqno; |
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3031 | serge | 272 | bool gpu_caches_dirty; |
4104 | Serge | 273 | bool fbc_dirty; |
2326 | Serge | 274 | |
2352 | Serge | 275 | wait_queue_head_t irq_queue; |
2326 | Serge | 276 | |
5060 | serge | 277 | struct intel_context *default_context; |
278 | struct intel_context *last_context; |
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3031 | serge | 279 | |
4104 | Serge | 280 | struct intel_ring_hangcheck hangcheck; |
281 | |||
282 | struct { |
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283 | struct drm_i915_gem_object *obj; |
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284 | u32 gtt_offset; |
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285 | volatile u32 *cpu_page; |
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286 | } scratch; |
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5060 | serge | 287 | |
288 | bool needs_cmd_parser; |
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289 | |||
290 | /* |
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291 | * Table of commands the command parser needs to know about |
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292 | * for this ring. |
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293 | */ |
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294 | DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER); |
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295 | |||
296 | /* |
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297 | * Table of registers allowed in commands that read/write registers. |
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298 | */ |
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299 | const u32 *reg_table; |
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300 | int reg_count; |
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301 | |||
302 | /* |
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303 | * Table of registers allowed in commands that read/write registers, but |
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304 | * only from the DRM master. |
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305 | */ |
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306 | const u32 *master_reg_table; |
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307 | int master_reg_count; |
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308 | |||
309 | /* |
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310 | * Returns the bitmask for the length field of the specified command. |
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311 | * Return 0 for an unrecognized/invalid command. |
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312 | * |
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313 | * If the command parser finds an entry for a command in the ring's |
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314 | * cmd_tables, it gets the command's length based on the table entry. |
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315 | * If not, it calls this function to determine the per-ring length field |
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316 | * encoding for the command (i.e. certain opcode ranges use certain bits |
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317 | * to encode the command length in the header). |
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318 | */ |
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319 | u32 (*get_cmd_length_mask)(u32 cmd_header); |
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2326 | Serge | 320 | }; |
321 | |||
5354 | serge | 322 | bool intel_ring_initialized(struct intel_engine_cs *ring); |
3031 | serge | 323 | |
324 | static inline unsigned |
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5060 | serge | 325 | intel_ring_flag(struct intel_engine_cs *ring) |
3031 | serge | 326 | { |
327 | return 1 << ring->id; |
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328 | } |
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329 | |||
2326 | Serge | 330 | static inline u32 |
5060 | serge | 331 | intel_ring_sync_index(struct intel_engine_cs *ring, |
332 | struct intel_engine_cs *other) |
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2326 | Serge | 333 | { |
334 | int idx; |
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335 | |||
336 | /* |
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5060 | serge | 337 | * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2; |
338 | * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs; |
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339 | * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs; |
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340 | * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs; |
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341 | * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs; |
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2326 | Serge | 342 | */ |
343 | |||
344 | idx = (other - ring) - 1; |
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345 | if (idx < 0) |
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346 | idx += I915_NUM_RINGS; |
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347 | |||
348 | return idx; |
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349 | } |
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350 | |||
351 | static inline u32 |
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5060 | serge | 352 | intel_read_status_page(struct intel_engine_cs *ring, |
2326 | Serge | 353 | int reg) |
354 | { |
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3031 | serge | 355 | /* Ensure that the compiler doesn't optimize away the load. */ |
356 | barrier(); |
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357 | return ring->status_page.page_addr[reg]; |
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2326 | Serge | 358 | } |
359 | |||
3480 | Serge | 360 | static inline void |
5060 | serge | 361 | intel_write_status_page(struct intel_engine_cs *ring, |
3480 | Serge | 362 | int reg, u32 value) |
363 | { |
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364 | ring->status_page.page_addr[reg] = value; |
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365 | } |
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366 | |||
2326 | Serge | 367 | /** |
368 | * Reads a dword out of the status page, which is written to from the command |
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369 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or |
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370 | * MI_STORE_DATA_IMM. |
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371 | * |
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372 | * The following dwords have a reserved meaning: |
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373 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. |
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374 | * 0x04: ring 0 head pointer |
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375 | * 0x05: ring 1 head pointer (915-class) |
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376 | * 0x06: ring 2 head pointer (915-class) |
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377 | * 0x10-0x1b: Context status DWords (GM45) |
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378 | * 0x1f: Last written status offset. (GM45) |
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379 | * |
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380 | * The area from dword 0x20 to 0x3ff is available for driver usage. |
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381 | */ |
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382 | #define I915_GEM_HWS_INDEX 0x20 |
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3243 | Serge | 383 | #define I915_GEM_HWS_SCRATCH_INDEX 0x30 |
384 | #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) |
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2326 | Serge | 385 | |
5354 | serge | 386 | void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf); |
387 | int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev, |
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388 | struct intel_ringbuffer *ringbuf); |
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389 | void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf); |
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390 | int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
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391 | struct intel_ringbuffer *ringbuf); |
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392 | |||
5060 | serge | 393 | void intel_stop_ring_buffer(struct intel_engine_cs *ring); |
394 | void intel_cleanup_ring_buffer(struct intel_engine_cs *ring); |
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2326 | Serge | 395 | |
5060 | serge | 396 | int __must_check intel_ring_begin(struct intel_engine_cs *ring, int n); |
397 | int __must_check intel_ring_cacheline_align(struct intel_engine_cs *ring); |
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398 | static inline void intel_ring_emit(struct intel_engine_cs *ring, |
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2326 | Serge | 399 | u32 data) |
400 | { |
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5060 | serge | 401 | struct intel_ringbuffer *ringbuf = ring->buffer; |
402 | iowrite32(data, ringbuf->virtual_start + ringbuf->tail); |
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403 | ringbuf->tail += 4; |
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2326 | Serge | 404 | } |
5060 | serge | 405 | static inline void intel_ring_advance(struct intel_engine_cs *ring) |
4560 | Serge | 406 | { |
5060 | serge | 407 | struct intel_ringbuffer *ringbuf = ring->buffer; |
408 | ringbuf->tail &= ringbuf->size - 1; |
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4560 | Serge | 409 | } |
5354 | serge | 410 | int __intel_ring_space(int head, int tail, int size); |
411 | int intel_ring_space(struct intel_ringbuffer *ringbuf); |
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412 | bool intel_ring_stopped(struct intel_engine_cs *ring); |
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5060 | serge | 413 | void __intel_ring_advance(struct intel_engine_cs *ring); |
4560 | Serge | 414 | |
5060 | serge | 415 | int __must_check intel_ring_idle(struct intel_engine_cs *ring); |
416 | void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno); |
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417 | int intel_ring_flush_all_caches(struct intel_engine_cs *ring); |
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418 | int intel_ring_invalidate_all_caches(struct intel_engine_cs *ring); |
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2326 | Serge | 419 | |
5354 | serge | 420 | void intel_fini_pipe_control(struct intel_engine_cs *ring); |
421 | int intel_init_pipe_control(struct intel_engine_cs *ring); |
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422 | |||
2326 | Serge | 423 | int intel_init_render_ring_buffer(struct drm_device *dev); |
424 | int intel_init_bsd_ring_buffer(struct drm_device *dev); |
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5060 | serge | 425 | int intel_init_bsd2_ring_buffer(struct drm_device *dev); |
2326 | Serge | 426 | int intel_init_blt_ring_buffer(struct drm_device *dev); |
4104 | Serge | 427 | int intel_init_vebox_ring_buffer(struct drm_device *dev); |
2326 | Serge | 428 | |
5060 | serge | 429 | u64 intel_ring_get_active_head(struct intel_engine_cs *ring); |
430 | void intel_ring_setup_status_page(struct intel_engine_cs *ring); |
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2326 | Serge | 431 | |
5354 | serge | 432 | int init_workarounds_ring(struct intel_engine_cs *ring); |
433 | |||
5060 | serge | 434 | static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf) |
3031 | serge | 435 | { |
5060 | serge | 436 | return ringbuf->tail; |
3031 | serge | 437 | } |
438 | |||
5060 | serge | 439 | static inline u32 intel_ring_get_seqno(struct intel_engine_cs *ring) |
3243 | Serge | 440 | { |
4560 | Serge | 441 | BUG_ON(ring->outstanding_lazy_seqno == 0); |
442 | return ring->outstanding_lazy_seqno; |
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3243 | Serge | 443 | } |
444 | |||
5060 | serge | 445 | static inline void i915_trace_irq_get(struct intel_engine_cs *ring, u32 seqno) |
2326 | Serge | 446 | { |
447 | if (ring->trace_irq_seqno == 0 && ring->irq_get(ring)) |
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448 | ring->trace_irq_seqno = seqno; |
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449 | } |
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450 | |||
451 | #endif /* _INTEL_RINGBUFFER_H_ */><>>><> |