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| 2330 | Serge | 1 | /* |
| 2 | * Copyright © 2006-2010 Intel Corporation |
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| 3 | * Copyright (c) 2006 Dave Airlie |
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| 4 | * |
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 6 | * copy of this software and associated documentation files (the "Software"), |
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| 7 | * to deal in the Software without restriction, including without limitation |
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| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 10 | * Software is furnished to do so, subject to the following conditions: |
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| 11 | * |
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| 12 | * The above copyright notice and this permission notice (including the next |
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| 13 | * paragraph) shall be included in all copies or substantial portions of the |
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| 14 | * Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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| 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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| 22 | * DEALINGS IN THE SOFTWARE. |
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| 23 | * |
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| 24 | * Authors: |
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| 25 | * Eric Anholt |
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| 26 | * Dave Airlie |
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| 27 | * Jesse Barnes |
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| 28 | * Chris Wilson |
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| 29 | */ |
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| 30 | |||
| 31 | #include "intel_drv.h" |
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| 32 | |||
| 33 | static inline int pci_read_config_byte(struct pci_dev *dev, int where, |
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| 34 | u8 *val) |
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| 35 | { |
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| 36 | *val = PciRead8(dev->busnr, dev->devfn, where); |
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| 37 | return 1; |
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| 38 | } |
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| 39 | |||
| 40 | static inline int pci_write_config_byte(struct pci_dev *dev, int where, |
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| 41 | u8 val) |
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| 42 | { |
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| 43 | PciWrite8(dev->busnr, dev->devfn, where, val); |
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| 44 | return 1; |
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| 45 | } |
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| 46 | |||
| 47 | |||
| 48 | #define PCI_LBPC 0xf4 /* legacy/combination backlight modes */ |
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| 49 | |||
| 50 | void |
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| 51 | intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, |
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| 52 | struct drm_display_mode *adjusted_mode) |
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| 53 | { |
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| 54 | adjusted_mode->hdisplay = fixed_mode->hdisplay; |
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| 55 | adjusted_mode->hsync_start = fixed_mode->hsync_start; |
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| 56 | adjusted_mode->hsync_end = fixed_mode->hsync_end; |
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| 57 | adjusted_mode->htotal = fixed_mode->htotal; |
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| 58 | |||
| 59 | adjusted_mode->vdisplay = fixed_mode->vdisplay; |
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| 60 | adjusted_mode->vsync_start = fixed_mode->vsync_start; |
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| 61 | adjusted_mode->vsync_end = fixed_mode->vsync_end; |
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| 62 | adjusted_mode->vtotal = fixed_mode->vtotal; |
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| 63 | |||
| 64 | adjusted_mode->clock = fixed_mode->clock; |
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| 65 | |||
| 66 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); |
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| 67 | } |
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| 68 | |||
| 69 | /* adjusted_mode has been preset to be the panel's fixed mode */ |
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| 70 | void |
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| 71 | intel_pch_panel_fitting(struct drm_device *dev, |
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| 72 | int fitting_mode, |
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| 73 | struct drm_display_mode *mode, |
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| 74 | struct drm_display_mode *adjusted_mode) |
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| 75 | { |
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| 76 | struct drm_i915_private *dev_priv = dev->dev_private; |
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| 77 | int x, y, width, height; |
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| 78 | |||
| 79 | x = y = width = height = 0; |
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| 80 | |||
| 81 | /* Native modes don't need fitting */ |
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| 82 | if (adjusted_mode->hdisplay == mode->hdisplay && |
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| 83 | adjusted_mode->vdisplay == mode->vdisplay) |
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| 84 | goto done; |
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| 85 | |||
| 86 | switch (fitting_mode) { |
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| 87 | case DRM_MODE_SCALE_CENTER: |
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| 88 | width = mode->hdisplay; |
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| 89 | height = mode->vdisplay; |
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| 90 | x = (adjusted_mode->hdisplay - width + 1)/2; |
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| 91 | y = (adjusted_mode->vdisplay - height + 1)/2; |
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| 92 | break; |
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| 93 | |||
| 94 | case DRM_MODE_SCALE_ASPECT: |
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| 95 | /* Scale but preserve the aspect ratio */ |
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| 96 | { |
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| 97 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
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| 98 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; |
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| 99 | if (scaled_width > scaled_height) { /* pillar */ |
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| 100 | width = scaled_height / mode->vdisplay; |
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| 101 | if (width & 1) |
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| 102 | width++; |
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| 103 | x = (adjusted_mode->hdisplay - width + 1) / 2; |
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| 104 | y = 0; |
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| 105 | height = adjusted_mode->vdisplay; |
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| 106 | } else if (scaled_width < scaled_height) { /* letter */ |
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| 107 | height = scaled_width / mode->hdisplay; |
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| 108 | if (height & 1) |
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| 109 | height++; |
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| 110 | y = (adjusted_mode->vdisplay - height + 1) / 2; |
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| 111 | x = 0; |
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| 112 | width = adjusted_mode->hdisplay; |
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| 113 | } else { |
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| 114 | x = y = 0; |
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| 115 | width = adjusted_mode->hdisplay; |
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| 116 | height = adjusted_mode->vdisplay; |
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| 117 | } |
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| 118 | } |
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| 119 | break; |
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| 120 | |||
| 121 | default: |
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| 122 | case DRM_MODE_SCALE_FULLSCREEN: |
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| 123 | x = y = 0; |
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| 124 | width = adjusted_mode->hdisplay; |
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| 125 | height = adjusted_mode->vdisplay; |
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| 126 | break; |
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| 127 | } |
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| 128 | |||
| 129 | done: |
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| 130 | dev_priv->pch_pf_pos = (x << 16) | y; |
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| 131 | dev_priv->pch_pf_size = (width << 16) | height; |
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| 132 | } |
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| 133 | |||
| 134 | static int is_backlight_combination_mode(struct drm_device *dev) |
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| 135 | { |
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| 136 | struct drm_i915_private *dev_priv = dev->dev_private; |
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| 137 | |||
| 138 | if (INTEL_INFO(dev)->gen >= 4) |
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| 139 | return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE; |
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| 140 | |||
| 141 | if (IS_GEN2(dev)) |
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| 142 | return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE; |
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| 143 | |||
| 144 | return 0; |
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| 145 | } |
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| 146 | |||
| 147 | static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv) |
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| 148 | { |
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| 149 | u32 val; |
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| 150 | |||
| 151 | /* Restore the CTL value if it lost, e.g. GPU reset */ |
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| 152 | |||
| 153 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
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| 154 | val = I915_READ(BLC_PWM_PCH_CTL2); |
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| 155 | if (dev_priv->saveBLC_PWM_CTL2 == 0) { |
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| 156 | dev_priv->saveBLC_PWM_CTL2 = val; |
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| 157 | } else if (val == 0) { |
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| 158 | I915_WRITE(BLC_PWM_PCH_CTL2, |
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| 159 | dev_priv->saveBLC_PWM_CTL); |
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| 160 | val = dev_priv->saveBLC_PWM_CTL; |
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| 161 | } |
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| 162 | } else { |
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| 163 | val = I915_READ(BLC_PWM_CTL); |
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| 164 | if (dev_priv->saveBLC_PWM_CTL == 0) { |
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| 165 | dev_priv->saveBLC_PWM_CTL = val; |
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| 166 | dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2); |
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| 167 | } else if (val == 0) { |
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| 168 | I915_WRITE(BLC_PWM_CTL, |
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| 169 | dev_priv->saveBLC_PWM_CTL); |
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| 170 | I915_WRITE(BLC_PWM_CTL2, |
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| 171 | dev_priv->saveBLC_PWM_CTL2); |
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| 172 | val = dev_priv->saveBLC_PWM_CTL; |
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| 173 | } |
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| 174 | } |
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| 175 | |||
| 176 | return val; |
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| 177 | } |
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| 178 | |||
| 179 | u32 intel_panel_get_max_backlight(struct drm_device *dev) |
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| 180 | { |
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| 181 | struct drm_i915_private *dev_priv = dev->dev_private; |
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| 182 | u32 max; |
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| 183 | |||
| 184 | max = i915_read_blc_pwm_ctl(dev_priv); |
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| 185 | if (max == 0) { |
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| 186 | /* XXX add code here to query mode clock or hardware clock |
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| 187 | * and program max PWM appropriately. |
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| 188 | */ |
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| 189 | printk(KERN_WARNING "fixme: max PWM is zero.\n"); |
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| 190 | return 1; |
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| 191 | } |
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| 192 | |||
| 193 | if (HAS_PCH_SPLIT(dev)) { |
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| 194 | max >>= 16; |
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| 195 | } else { |
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| 196 | if (IS_PINEVIEW(dev)) { |
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| 197 | max >>= 17; |
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| 198 | } else { |
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| 199 | max >>= 16; |
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| 200 | if (INTEL_INFO(dev)->gen < 4) |
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| 201 | max &= ~1; |
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| 202 | } |
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| 203 | |||
| 204 | if (is_backlight_combination_mode(dev)) |
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| 205 | max *= 0xff; |
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| 206 | } |
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| 207 | |||
| 208 | DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max); |
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| 209 | return max; |
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| 210 | } |
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| 211 | |||
| 212 | u32 intel_panel_get_backlight(struct drm_device *dev) |
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| 213 | { |
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| 214 | struct drm_i915_private *dev_priv = dev->dev_private; |
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| 215 | u32 val; |
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| 216 | |||
| 217 | if (HAS_PCH_SPLIT(dev)) { |
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| 218 | val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; |
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| 219 | } else { |
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| 220 | val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; |
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| 221 | if (IS_PINEVIEW(dev)) |
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| 222 | val >>= 1; |
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| 223 | |||
| 224 | if (is_backlight_combination_mode(dev)){ |
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| 225 | u8 lbpc; |
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| 226 | |||
| 227 | val &= ~1; |
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| 228 | pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc); |
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| 229 | val *= lbpc; |
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| 230 | } |
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| 231 | } |
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| 232 | |||
| 233 | DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val); |
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| 234 | return val; |
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| 235 | } |
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| 236 | |||
| 237 | static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level) |
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| 238 | { |
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| 239 | struct drm_i915_private *dev_priv = dev->dev_private; |
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| 240 | u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; |
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| 241 | I915_WRITE(BLC_PWM_CPU_CTL, val | level); |
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| 242 | } |
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| 243 | |||
| 244 | void intel_panel_set_backlight(struct drm_device *dev, u32 level) |
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| 245 | { |
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| 246 | struct drm_i915_private *dev_priv = dev->dev_private; |
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| 247 | u32 tmp; |
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| 248 | |||
| 249 | DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level); |
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| 250 | |||
| 251 | if (HAS_PCH_SPLIT(dev)) |
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| 252 | return intel_pch_panel_set_backlight(dev, level); |
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| 253 | |||
| 254 | if (is_backlight_combination_mode(dev)){ |
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| 255 | u32 max = intel_panel_get_max_backlight(dev); |
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| 256 | u8 lbpc; |
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| 257 | |||
| 258 | lbpc = level * 0xfe / max + 1; |
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| 259 | level /= lbpc; |
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| 260 | pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc); |
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| 261 | } |
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| 262 | |||
| 263 | tmp = I915_READ(BLC_PWM_CTL); |
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| 264 | if (IS_PINEVIEW(dev)) { |
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| 265 | tmp &= ~(BACKLIGHT_DUTY_CYCLE_MASK - 1); |
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| 266 | level <<= 1; |
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| 267 | } else |
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| 268 | tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK; |
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| 269 | I915_WRITE(BLC_PWM_CTL, tmp | level); |
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| 270 | } |
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| 271 | |||
| 272 | void intel_panel_disable_backlight(struct drm_device *dev) |
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| 273 | { |
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| 274 | struct drm_i915_private *dev_priv = dev->dev_private; |
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| 275 | |||
| 276 | if (dev_priv->backlight_enabled) { |
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| 277 | dev_priv->backlight_level = intel_panel_get_backlight(dev); |
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| 278 | dev_priv->backlight_enabled = false; |
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| 279 | } |
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| 280 | |||
| 281 | intel_panel_set_backlight(dev, 0); |
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| 282 | } |
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| 283 | |||
| 284 | void intel_panel_enable_backlight(struct drm_device *dev) |
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| 285 | { |
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| 286 | struct drm_i915_private *dev_priv = dev->dev_private; |
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| 287 | |||
| 288 | if (dev_priv->backlight_level == 0) |
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| 289 | dev_priv->backlight_level = intel_panel_get_max_backlight(dev); |
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| 290 | |||
| 291 | intel_panel_set_backlight(dev, dev_priv->backlight_level); |
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| 292 | dev_priv->backlight_enabled = true; |
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| 293 | } |
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| 294 | |||
| 295 | static void intel_panel_init_backlight(struct drm_device *dev) |
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| 296 | { |
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| 297 | struct drm_i915_private *dev_priv = dev->dev_private; |
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| 298 | |||
| 299 | dev_priv->backlight_level = intel_panel_get_backlight(dev); |
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| 300 | dev_priv->backlight_enabled = dev_priv->backlight_level != 0; |
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| 301 | } |
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| 302 | |||
| 303 | enum drm_connector_status |
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| 304 | intel_panel_detect(struct drm_device *dev) |
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| 305 | { |
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| 306 | #if 0 |
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| 307 | struct drm_i915_private *dev_priv = dev->dev_private; |
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| 308 | #endif |
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| 309 | |||
| 310 | if (i915_panel_ignore_lid) |
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| 311 | return i915_panel_ignore_lid > 0 ? |
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| 312 | connector_status_connected : |
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| 313 | connector_status_disconnected; |
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| 314 | |||
| 315 | /* opregion lid state on HP 2540p is wrong at boot up, |
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| 316 | * appears to be either the BIOS or Linux ACPI fault */ |
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| 317 | #if 0 |
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| 318 | /* Assume that the BIOS does not lie through the OpRegion... */ |
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| 319 | if (dev_priv->opregion.lid_state) |
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| 320 | return ioread32(dev_priv->opregion.lid_state) & 0x1 ? |
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| 321 | connector_status_connected : |
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| 322 | connector_status_disconnected; |
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| 323 | #endif |
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| 324 | |||
| 325 | return connector_status_unknown; |
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| 326 | } |
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| 327 | |||
| 328 | #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE |
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| 329 | static int intel_panel_update_status(struct backlight_device *bd) |
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| 330 | { |
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| 331 | struct drm_device *dev = bl_get_data(bd); |
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| 332 | intel_panel_set_backlight(dev, bd->props.brightness); |
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| 333 | return 0; |
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| 334 | } |
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| 335 | |||
| 336 | static int intel_panel_get_brightness(struct backlight_device *bd) |
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| 337 | { |
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| 338 | struct drm_device *dev = bl_get_data(bd); |
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| 339 | return intel_panel_get_backlight(dev); |
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| 340 | } |
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| 341 | |||
| 342 | static const struct backlight_ops intel_panel_bl_ops = { |
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| 343 | .update_status = intel_panel_update_status, |
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| 344 | .get_brightness = intel_panel_get_brightness, |
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| 345 | }; |
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| 346 | |||
| 347 | int intel_panel_setup_backlight(struct drm_device *dev) |
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| 348 | { |
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| 349 | struct drm_i915_private *dev_priv = dev->dev_private; |
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| 350 | struct backlight_properties props; |
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| 351 | struct drm_connector *connector; |
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| 352 | |||
| 353 | intel_panel_init_backlight(dev); |
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| 354 | |||
| 355 | if (dev_priv->int_lvds_connector) |
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| 356 | connector = dev_priv->int_lvds_connector; |
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| 357 | else if (dev_priv->int_edp_connector) |
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| 358 | connector = dev_priv->int_edp_connector; |
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| 359 | else |
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| 360 | return -ENODEV; |
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| 361 | |||
| 362 | props.type = BACKLIGHT_RAW; |
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| 363 | props.max_brightness = intel_panel_get_max_backlight(dev); |
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| 364 | dev_priv->backlight = |
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| 365 | backlight_device_register("intel_backlight", |
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| 366 | &connector->kdev, dev, |
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| 367 | &intel_panel_bl_ops, &props); |
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| 368 | |||
| 369 | if (IS_ERR(dev_priv->backlight)) { |
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| 370 | DRM_ERROR("Failed to register backlight: %ld\n", |
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| 371 | PTR_ERR(dev_priv->backlight)); |
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| 372 | dev_priv->backlight = NULL; |
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| 373 | return -ENODEV; |
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| 374 | } |
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| 375 | dev_priv->backlight->props.brightness = intel_panel_get_backlight(dev); |
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| 376 | return 0; |
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| 377 | } |
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| 378 | |||
| 379 | void intel_panel_destroy_backlight(struct drm_device *dev) |
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| 380 | { |
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| 381 | struct drm_i915_private *dev_priv = dev->dev_private; |
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| 382 | if (dev_priv->backlight) |
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| 383 | backlight_device_unregister(dev_priv->backlight); |
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| 384 | } |
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| 385 | #else |
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| 386 | int intel_panel_setup_backlight(struct drm_device *dev) |
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| 387 | { |
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| 388 | intel_panel_init_backlight(dev); |
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| 389 | return 0; |
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| 390 | } |
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| 391 | |||
| 392 | void intel_panel_destroy_backlight(struct drm_device *dev) |
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| 393 | { |
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| 394 | return; |
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| 395 | } |
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| 396 | #endif |