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Rev | Author | Line No. | Line |
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2330 | Serge | 1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation |
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3 | * Copyright (c) 2006 Dave Airlie |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice (including the next |
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13 | * paragraph) shall be included in all copies or substantial portions of the |
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14 | * Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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22 | * DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: |
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25 | * Eric Anholt |
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26 | * Dave Airlie |
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27 | * Jesse Barnes |
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28 | */ |
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29 | |||
30 | //#include |
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5097 | serge | 31 | #include |
2330 | Serge | 32 | #include |
33 | #include |
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3031 | serge | 34 | #include |
6084 | serge | 35 | #include |
3031 | serge | 36 | #include |
37 | #include |
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2330 | Serge | 38 | #include "intel_drv.h" |
3031 | serge | 39 | #include |
2330 | Serge | 40 | #include "i915_drv.h" |
6660 | serge | 41 | #include |
2330 | Serge | 42 | |
43 | /* Private structure for the integrated LVDS support */ |
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3243 | Serge | 44 | struct intel_lvds_connector { |
45 | struct intel_connector base; |
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46 | |||
6937 | serge | 47 | struct notifier_block lid_notifier; |
3243 | Serge | 48 | }; |
49 | |||
50 | struct intel_lvds_encoder { |
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2330 | Serge | 51 | struct intel_encoder base; |
52 | |||
3480 | Serge | 53 | bool is_dual_link; |
6937 | serge | 54 | i915_reg_t reg; |
5060 | serge | 55 | u32 a3_power; |
2330 | Serge | 56 | |
3243 | Serge | 57 | struct intel_lvds_connector *attached_connector; |
2330 | Serge | 58 | }; |
59 | |||
3243 | Serge | 60 | static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) |
2330 | Serge | 61 | { |
3243 | Serge | 62 | return container_of(encoder, struct intel_lvds_encoder, base.base); |
2330 | Serge | 63 | } |
64 | |||
3243 | Serge | 65 | static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector) |
2330 | Serge | 66 | { |
3243 | Serge | 67 | return container_of(connector, struct intel_lvds_connector, base.base); |
2330 | Serge | 68 | } |
69 | |||
3031 | serge | 70 | static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, |
71 | enum pipe *pipe) |
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72 | { |
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73 | struct drm_device *dev = encoder->base.dev; |
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74 | struct drm_i915_private *dev_priv = dev->dev_private; |
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3480 | Serge | 75 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
5060 | serge | 76 | enum intel_display_power_domain power_domain; |
3480 | Serge | 77 | u32 tmp; |
6937 | serge | 78 | bool ret; |
3031 | serge | 79 | |
5060 | serge | 80 | power_domain = intel_display_port_power_domain(encoder); |
6937 | serge | 81 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
5060 | serge | 82 | return false; |
83 | |||
6937 | serge | 84 | ret = false; |
85 | |||
3480 | Serge | 86 | tmp = I915_READ(lvds_encoder->reg); |
3031 | serge | 87 | |
88 | if (!(tmp & LVDS_PORT_EN)) |
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6937 | serge | 89 | goto out; |
3031 | serge | 90 | |
91 | if (HAS_PCH_CPT(dev)) |
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92 | *pipe = PORT_TO_PIPE_CPT(tmp); |
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93 | else |
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94 | *pipe = PORT_TO_PIPE(tmp); |
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95 | |||
6937 | serge | 96 | ret = true; |
97 | |||
98 | out: |
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99 | intel_display_power_put(dev_priv, power_domain); |
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100 | |||
101 | return ret; |
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3031 | serge | 102 | } |
103 | |||
4104 | Serge | 104 | static void intel_lvds_get_config(struct intel_encoder *encoder, |
6084 | serge | 105 | struct intel_crtc_state *pipe_config) |
4104 | Serge | 106 | { |
107 | struct drm_device *dev = encoder->base.dev; |
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108 | struct drm_i915_private *dev_priv = dev->dev_private; |
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6084 | serge | 109 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
110 | u32 tmp, flags = 0; |
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4560 | Serge | 111 | int dotclock; |
4104 | Serge | 112 | |
6084 | serge | 113 | tmp = I915_READ(lvds_encoder->reg); |
4104 | Serge | 114 | if (tmp & LVDS_HSYNC_POLARITY) |
115 | flags |= DRM_MODE_FLAG_NHSYNC; |
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116 | else |
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117 | flags |= DRM_MODE_FLAG_PHSYNC; |
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118 | if (tmp & LVDS_VSYNC_POLARITY) |
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119 | flags |= DRM_MODE_FLAG_NVSYNC; |
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120 | else |
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121 | flags |= DRM_MODE_FLAG_PVSYNC; |
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122 | |||
6084 | serge | 123 | pipe_config->base.adjusted_mode.flags |= flags; |
4104 | Serge | 124 | |
125 | /* gen2/3 store dither state in pfit control, needs to match */ |
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126 | if (INTEL_INFO(dev)->gen < 4) { |
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127 | tmp = I915_READ(PFIT_CONTROL); |
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128 | |||
129 | pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; |
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130 | } |
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4560 | Serge | 131 | |
132 | dotclock = pipe_config->port_clock; |
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133 | |||
134 | if (HAS_PCH_SPLIT(dev_priv->dev)) |
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135 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
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136 | |||
6084 | serge | 137 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
4104 | Serge | 138 | } |
139 | |||
140 | static void intel_pre_enable_lvds(struct intel_encoder *encoder) |
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3480 | Serge | 141 | { |
142 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
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143 | struct drm_device *dev = encoder->base.dev; |
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144 | struct drm_i915_private *dev_priv = dev->dev_private; |
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4104 | Serge | 145 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
6084 | serge | 146 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
4104 | Serge | 147 | int pipe = crtc->pipe; |
3480 | Serge | 148 | u32 temp; |
149 | |||
4104 | Serge | 150 | if (HAS_PCH_SPLIT(dev)) { |
151 | assert_fdi_rx_pll_disabled(dev_priv, pipe); |
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152 | assert_shared_dpll_disabled(dev_priv, |
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153 | intel_crtc_to_shared_dpll(crtc)); |
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154 | } else { |
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155 | assert_pll_disabled(dev_priv, pipe); |
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156 | } |
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157 | |||
3480 | Serge | 158 | temp = I915_READ(lvds_encoder->reg); |
159 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
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160 | |||
161 | if (HAS_PCH_CPT(dev)) { |
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162 | temp &= ~PORT_TRANS_SEL_MASK; |
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163 | temp |= PORT_TRANS_SEL_CPT(pipe); |
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164 | } else { |
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165 | if (pipe == 1) { |
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166 | temp |= LVDS_PIPEB_SELECT; |
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167 | } else { |
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168 | temp &= ~LVDS_PIPEB_SELECT; |
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169 | } |
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170 | } |
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171 | |||
172 | /* set the corresponsding LVDS_BORDER bit */ |
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4104 | Serge | 173 | temp &= ~LVDS_BORDER_ENABLE; |
6084 | serge | 174 | temp |= crtc->config->gmch_pfit.lvds_border_bits; |
3480 | Serge | 175 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
176 | * set the DPLLs for dual-channel mode or not. |
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177 | */ |
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178 | if (lvds_encoder->is_dual_link) |
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179 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
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180 | else |
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181 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
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182 | |||
183 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) |
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184 | * appropriately here, but we need to look more thoroughly into how |
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5060 | serge | 185 | * panels behave in the two modes. For now, let's just maintain the |
186 | * value we got from the BIOS. |
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3480 | Serge | 187 | */ |
5060 | serge | 188 | temp &= ~LVDS_A3_POWER_MASK; |
189 | temp |= lvds_encoder->a3_power; |
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3480 | Serge | 190 | |
191 | /* Set the dithering flag on LVDS as needed, note that there is no |
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192 | * special lvds dither control bit on pch-split platforms, dithering is |
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193 | * only controlled through the PIPECONF reg. */ |
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194 | if (INTEL_INFO(dev)->gen == 4) { |
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4104 | Serge | 195 | /* Bspec wording suggests that LVDS port dithering only exists |
196 | * for 18bpp panels. */ |
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6084 | serge | 197 | if (crtc->config->dither && crtc->config->pipe_bpp == 18) |
3480 | Serge | 198 | temp |= LVDS_ENABLE_DITHER; |
199 | else |
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200 | temp &= ~LVDS_ENABLE_DITHER; |
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201 | } |
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202 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); |
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4104 | Serge | 203 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
3480 | Serge | 204 | temp |= LVDS_HSYNC_POLARITY; |
4104 | Serge | 205 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
3480 | Serge | 206 | temp |= LVDS_VSYNC_POLARITY; |
207 | |||
208 | I915_WRITE(lvds_encoder->reg, temp); |
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209 | } |
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210 | |||
2330 | Serge | 211 | /** |
212 | * Sets the power state for the panel. |
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213 | */ |
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3031 | serge | 214 | static void intel_enable_lvds(struct intel_encoder *encoder) |
2330 | Serge | 215 | { |
3031 | serge | 216 | struct drm_device *dev = encoder->base.dev; |
3243 | Serge | 217 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
4560 | Serge | 218 | struct intel_connector *intel_connector = |
219 | &lvds_encoder->attached_connector->base; |
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2330 | Serge | 220 | struct drm_i915_private *dev_priv = dev->dev_private; |
6937 | serge | 221 | i915_reg_t ctl_reg, stat_reg; |
2330 | Serge | 222 | |
223 | if (HAS_PCH_SPLIT(dev)) { |
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224 | ctl_reg = PCH_PP_CONTROL; |
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225 | stat_reg = PCH_PP_STATUS; |
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226 | } else { |
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227 | ctl_reg = PP_CONTROL; |
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228 | stat_reg = PP_STATUS; |
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229 | } |
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230 | |||
3480 | Serge | 231 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); |
2330 | Serge | 232 | |
233 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); |
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3480 | Serge | 234 | POSTING_READ(lvds_encoder->reg); |
2330 | Serge | 235 | if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) |
236 | DRM_ERROR("timed out waiting for panel to power on\n"); |
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237 | |||
4560 | Serge | 238 | intel_panel_enable_backlight(intel_connector); |
2330 | Serge | 239 | } |
240 | |||
3031 | serge | 241 | static void intel_disable_lvds(struct intel_encoder *encoder) |
2330 | Serge | 242 | { |
3031 | serge | 243 | struct drm_device *dev = encoder->base.dev; |
3243 | Serge | 244 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
2330 | Serge | 245 | struct drm_i915_private *dev_priv = dev->dev_private; |
6937 | serge | 246 | i915_reg_t ctl_reg, stat_reg; |
2330 | Serge | 247 | |
248 | if (HAS_PCH_SPLIT(dev)) { |
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249 | ctl_reg = PCH_PP_CONTROL; |
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250 | stat_reg = PCH_PP_STATUS; |
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251 | } else { |
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252 | ctl_reg = PP_CONTROL; |
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253 | stat_reg = PP_STATUS; |
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254 | } |
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255 | |||
256 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); |
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257 | if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) |
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258 | DRM_ERROR("timed out waiting for panel to power off\n"); |
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259 | |||
3480 | Serge | 260 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); |
261 | POSTING_READ(lvds_encoder->reg); |
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2330 | Serge | 262 | } |
263 | |||
6084 | serge | 264 | static void gmch_disable_lvds(struct intel_encoder *encoder) |
265 | { |
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266 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
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267 | struct intel_connector *intel_connector = |
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268 | &lvds_encoder->attached_connector->base; |
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269 | |||
270 | intel_panel_disable_backlight(intel_connector); |
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271 | |||
272 | intel_disable_lvds(encoder); |
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273 | } |
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274 | |||
275 | static void pch_disable_lvds(struct intel_encoder *encoder) |
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276 | { |
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277 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
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278 | struct intel_connector *intel_connector = |
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279 | &lvds_encoder->attached_connector->base; |
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280 | |||
281 | intel_panel_disable_backlight(intel_connector); |
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282 | } |
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283 | |||
284 | static void pch_post_disable_lvds(struct intel_encoder *encoder) |
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285 | { |
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286 | intel_disable_lvds(encoder); |
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287 | } |
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288 | |||
4560 | Serge | 289 | static enum drm_mode_status |
290 | intel_lvds_mode_valid(struct drm_connector *connector, |
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6084 | serge | 291 | struct drm_display_mode *mode) |
2330 | Serge | 292 | { |
3243 | Serge | 293 | struct intel_connector *intel_connector = to_intel_connector(connector); |
294 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
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6084 | serge | 295 | int max_pixclk = to_i915(connector->dev)->max_dotclk_freq; |
2330 | Serge | 296 | |
297 | if (mode->hdisplay > fixed_mode->hdisplay) |
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298 | return MODE_PANEL; |
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299 | if (mode->vdisplay > fixed_mode->vdisplay) |
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300 | return MODE_PANEL; |
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6084 | serge | 301 | if (fixed_mode->clock > max_pixclk) |
302 | return MODE_CLOCK_HIGH; |
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2330 | Serge | 303 | |
304 | return MODE_OK; |
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305 | } |
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306 | |||
3746 | Serge | 307 | static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, |
6084 | serge | 308 | struct intel_crtc_state *pipe_config) |
2330 | Serge | 309 | { |
3746 | Serge | 310 | struct drm_device *dev = intel_encoder->base.dev; |
311 | struct intel_lvds_encoder *lvds_encoder = |
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312 | to_lvds_encoder(&intel_encoder->base); |
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3243 | Serge | 313 | struct intel_connector *intel_connector = |
314 | &lvds_encoder->attached_connector->base; |
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6084 | serge | 315 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
316 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
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3746 | Serge | 317 | unsigned int lvds_bpp; |
2330 | Serge | 318 | |
319 | /* Should never happen!! */ |
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320 | if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { |
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321 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
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322 | return false; |
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323 | } |
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324 | |||
5060 | serge | 325 | if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) |
3746 | Serge | 326 | lvds_bpp = 8*3; |
327 | else |
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328 | lvds_bpp = 6*3; |
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329 | |||
4104 | Serge | 330 | if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { |
3746 | Serge | 331 | DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n", |
332 | pipe_config->pipe_bpp, lvds_bpp); |
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333 | pipe_config->pipe_bpp = lvds_bpp; |
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334 | } |
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4104 | Serge | 335 | |
2330 | Serge | 336 | /* |
337 | * We have timings from the BIOS for the panel, put them in |
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338 | * to the adjusted mode. The CRTC will be set up for this mode, |
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339 | * with the panel scaling set up to source from the H/VDisplay |
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340 | * of the original mode. |
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341 | */ |
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3243 | Serge | 342 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
343 | adjusted_mode); |
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2330 | Serge | 344 | |
345 | if (HAS_PCH_SPLIT(dev)) { |
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3746 | Serge | 346 | pipe_config->has_pch_encoder = true; |
347 | |||
4104 | Serge | 348 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
349 | intel_connector->panel.fitting_mode); |
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350 | } else { |
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351 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
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352 | intel_connector->panel.fitting_mode); |
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2330 | Serge | 353 | |
354 | } |
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355 | |||
356 | /* |
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357 | * XXX: It would be nice to support lower refresh rates on the |
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358 | * panels to reduce power consumption, and perhaps match the |
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359 | * user's requested refresh rate. |
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360 | */ |
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361 | |||
362 | return true; |
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363 | } |
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364 | |||
365 | /** |
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366 | * Detect the LVDS connection. |
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367 | * |
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368 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
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369 | * connected and closed means disconnected. We also send hotplug events as |
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370 | * needed, using lid status notification from the input layer. |
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371 | */ |
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372 | static enum drm_connector_status |
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373 | intel_lvds_detect(struct drm_connector *connector, bool force) |
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374 | { |
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375 | struct drm_device *dev = connector->dev; |
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376 | enum drm_connector_status status; |
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377 | |||
4104 | Serge | 378 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
5060 | serge | 379 | connector->base.id, connector->name); |
4104 | Serge | 380 | |
2330 | Serge | 381 | status = intel_panel_detect(dev); |
382 | if (status != connector_status_unknown) |
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383 | return status; |
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384 | |||
385 | return connector_status_connected; |
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386 | } |
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387 | |||
388 | /** |
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389 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. |
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390 | */ |
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391 | static int intel_lvds_get_modes(struct drm_connector *connector) |
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392 | { |
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3243 | Serge | 393 | struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector); |
2330 | Serge | 394 | struct drm_device *dev = connector->dev; |
395 | struct drm_display_mode *mode; |
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396 | |||
3243 | Serge | 397 | /* use cached edid if we have one */ |
398 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
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399 | return drm_add_edid_modes(connector, lvds_connector->base.edid); |
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2330 | Serge | 400 | |
3243 | Serge | 401 | mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode); |
2330 | Serge | 402 | if (mode == NULL) |
403 | return 0; |
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404 | |||
405 | drm_mode_probed_add(connector, mode); |
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406 | return 1; |
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407 | } |
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408 | |||
409 | static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) |
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410 | { |
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3031 | serge | 411 | DRM_INFO("Skipping forced modeset for %s\n", id->ident); |
2330 | Serge | 412 | return 1; |
413 | } |
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414 | |||
415 | /* The GPU hangs up on these systems if modeset is performed on LID open */ |
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416 | static const struct dmi_system_id intel_no_modeset_on_lid[] = { |
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417 | { |
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418 | .callback = intel_no_modeset_on_lid_dmi_callback, |
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419 | .ident = "Toshiba Tecra A11", |
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420 | .matches = { |
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421 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
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422 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), |
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423 | }, |
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424 | }, |
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425 | |||
426 | { } /* terminating entry */ |
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427 | }; |
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428 | |||
429 | #if 0 |
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430 | /* |
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3480 | Serge | 431 | * Lid events. Note the use of 'modeset': |
432 | * - we set it to MODESET_ON_LID_OPEN on lid close, |
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433 | * and set it to MODESET_DONE on open |
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2330 | Serge | 434 | * - we use it as a "only once" bit (ie we ignore |
3480 | Serge | 435 | * duplicate events where it was already properly set) |
436 | * - the suspend/resume paths will set it to |
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437 | * MODESET_SUSPENDED and ignore the lid open event, |
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438 | * because they restore the mode ("lid open"). |
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2330 | Serge | 439 | */ |
440 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
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441 | void *unused) |
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442 | { |
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3243 | Serge | 443 | struct intel_lvds_connector *lvds_connector = |
444 | container_of(nb, struct intel_lvds_connector, lid_notifier); |
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445 | struct drm_connector *connector = &lvds_connector->base.base; |
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446 | struct drm_device *dev = connector->dev; |
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447 | struct drm_i915_private *dev_priv = dev->dev_private; |
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2330 | Serge | 448 | |
449 | if (dev->switch_power_state != DRM_SWITCH_POWER_ON) |
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450 | return NOTIFY_OK; |
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451 | |||
3480 | Serge | 452 | mutex_lock(&dev_priv->modeset_restore_lock); |
453 | if (dev_priv->modeset_restore == MODESET_SUSPENDED) |
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454 | goto exit; |
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2330 | Serge | 455 | /* |
456 | * check and update the status of LVDS connector after receiving |
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457 | * the LID nofication event. |
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458 | */ |
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3243 | Serge | 459 | connector->status = connector->funcs->detect(connector, false); |
2330 | Serge | 460 | |
461 | /* Don't force modeset on machines where it causes a GPU lockup */ |
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462 | if (dmi_check_system(intel_no_modeset_on_lid)) |
||
3480 | Serge | 463 | goto exit; |
2330 | Serge | 464 | if (!acpi_lid_open()) { |
3480 | Serge | 465 | /* do modeset on next lid open event */ |
466 | dev_priv->modeset_restore = MODESET_ON_LID_OPEN; |
||
467 | goto exit; |
||
2330 | Serge | 468 | } |
469 | |||
3480 | Serge | 470 | if (dev_priv->modeset_restore == MODESET_DONE) |
471 | goto exit; |
||
2330 | Serge | 472 | |
4560 | Serge | 473 | /* |
474 | * Some old platform's BIOS love to wreak havoc while the lid is closed. |
||
475 | * We try to detect this here and undo any damage. The split for PCH |
||
476 | * platforms is rather conservative and a bit arbitrary expect that on |
||
477 | * those platforms VGA disabling requires actual legacy VGA I/O access, |
||
478 | * and as part of the cleanup in the hw state restore we also redisable |
||
479 | * the vga plane. |
||
480 | */ |
||
481 | if (!HAS_PCH_SPLIT(dev)) { |
||
6084 | serge | 482 | drm_modeset_lock_all(dev); |
483 | intel_display_resume(dev); |
||
484 | drm_modeset_unlock_all(dev); |
||
4560 | Serge | 485 | } |
2330 | Serge | 486 | |
3480 | Serge | 487 | dev_priv->modeset_restore = MODESET_DONE; |
488 | |||
489 | exit: |
||
490 | mutex_unlock(&dev_priv->modeset_restore_lock); |
||
2330 | Serge | 491 | return NOTIFY_OK; |
492 | } |
||
493 | #endif |
||
494 | |||
495 | /** |
||
496 | * intel_lvds_destroy - unregister and free LVDS structures |
||
497 | * @connector: connector to free |
||
498 | * |
||
499 | * Unregister the DDC bus for this connector then free the driver private |
||
500 | * structure. |
||
501 | */ |
||
502 | static void intel_lvds_destroy(struct drm_connector *connector) |
||
503 | { |
||
3243 | Serge | 504 | struct intel_lvds_connector *lvds_connector = |
505 | to_lvds_connector(connector); |
||
2330 | Serge | 506 | |
507 | |||
3243 | Serge | 508 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
509 | kfree(lvds_connector->base.edid); |
||
510 | |||
511 | intel_panel_fini(&lvds_connector->base.panel); |
||
512 | |||
2330 | Serge | 513 | drm_connector_cleanup(connector); |
514 | kfree(connector); |
||
515 | } |
||
516 | |||
517 | static int intel_lvds_set_property(struct drm_connector *connector, |
||
518 | struct drm_property *property, |
||
519 | uint64_t value) |
||
520 | { |
||
3243 | Serge | 521 | struct intel_connector *intel_connector = to_intel_connector(connector); |
2330 | Serge | 522 | struct drm_device *dev = connector->dev; |
523 | |||
524 | if (property == dev->mode_config.scaling_mode_property) { |
||
3243 | Serge | 525 | struct drm_crtc *crtc; |
2330 | Serge | 526 | |
527 | if (value == DRM_MODE_SCALE_NONE) { |
||
528 | DRM_DEBUG_KMS("no scaling not supported\n"); |
||
529 | return -EINVAL; |
||
530 | } |
||
531 | |||
3243 | Serge | 532 | if (intel_connector->panel.fitting_mode == value) { |
2330 | Serge | 533 | /* the LVDS scaling property is not changed */ |
534 | return 0; |
||
535 | } |
||
3243 | Serge | 536 | intel_connector->panel.fitting_mode = value; |
537 | |||
538 | crtc = intel_attached_encoder(connector)->base.crtc; |
||
6084 | serge | 539 | if (crtc && crtc->state->enable) { |
2330 | Serge | 540 | /* |
541 | * If the CRTC is enabled, the display will be changed |
||
542 | * according to the new panel fitting mode. |
||
543 | */ |
||
3480 | Serge | 544 | intel_crtc_restore_mode(crtc); |
2330 | Serge | 545 | } |
546 | } |
||
547 | |||
548 | return 0; |
||
549 | } |
||
550 | |||
551 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { |
||
552 | .get_modes = intel_lvds_get_modes, |
||
553 | .mode_valid = intel_lvds_mode_valid, |
||
554 | .best_encoder = intel_best_encoder, |
||
555 | }; |
||
556 | |||
557 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { |
||
6084 | serge | 558 | .dpms = drm_atomic_helper_connector_dpms, |
2330 | Serge | 559 | .detect = intel_lvds_detect, |
560 | .fill_modes = drm_helper_probe_single_connector_modes, |
||
561 | .set_property = intel_lvds_set_property, |
||
6084 | serge | 562 | .atomic_get_property = intel_connector_atomic_get_property, |
2330 | Serge | 563 | .destroy = intel_lvds_destroy, |
6084 | serge | 564 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
565 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
||
2330 | Serge | 566 | }; |
567 | |||
568 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { |
||
569 | .destroy = intel_encoder_destroy, |
||
570 | }; |
||
571 | |||
5097 | serge | 572 | static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
2330 | Serge | 573 | { |
3031 | serge | 574 | DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); |
2330 | Serge | 575 | return 1; |
576 | } |
||
577 | |||
578 | /* These systems claim to have LVDS, but really don't */ |
||
579 | static const struct dmi_system_id intel_no_lvds[] = { |
||
580 | { |
||
581 | .callback = intel_no_lvds_dmi_callback, |
||
582 | .ident = "Apple Mac Mini (Core series)", |
||
583 | .matches = { |
||
584 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
||
585 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
||
586 | }, |
||
587 | }, |
||
588 | { |
||
589 | .callback = intel_no_lvds_dmi_callback, |
||
590 | .ident = "Apple Mac Mini (Core 2 series)", |
||
591 | .matches = { |
||
592 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
||
593 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
||
594 | }, |
||
595 | }, |
||
596 | { |
||
597 | .callback = intel_no_lvds_dmi_callback, |
||
598 | .ident = "MSI IM-945GSE-A", |
||
599 | .matches = { |
||
600 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), |
||
601 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), |
||
602 | }, |
||
603 | }, |
||
604 | { |
||
605 | .callback = intel_no_lvds_dmi_callback, |
||
606 | .ident = "Dell Studio Hybrid", |
||
607 | .matches = { |
||
608 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), |
||
609 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), |
||
610 | }, |
||
611 | }, |
||
612 | { |
||
613 | .callback = intel_no_lvds_dmi_callback, |
||
614 | .ident = "Dell OptiPlex FX170", |
||
615 | .matches = { |
||
616 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), |
||
617 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), |
||
618 | }, |
||
619 | }, |
||
620 | { |
||
621 | .callback = intel_no_lvds_dmi_callback, |
||
622 | .ident = "AOpen Mini PC", |
||
623 | .matches = { |
||
624 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), |
||
625 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), |
||
626 | }, |
||
627 | }, |
||
628 | { |
||
629 | .callback = intel_no_lvds_dmi_callback, |
||
630 | .ident = "AOpen Mini PC MP915", |
||
631 | .matches = { |
||
632 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), |
||
633 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), |
||
634 | }, |
||
635 | }, |
||
636 | { |
||
637 | .callback = intel_no_lvds_dmi_callback, |
||
638 | .ident = "AOpen i915GMm-HFS", |
||
639 | .matches = { |
||
640 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), |
||
641 | DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), |
||
642 | }, |
||
643 | }, |
||
644 | { |
||
645 | .callback = intel_no_lvds_dmi_callback, |
||
2351 | Serge | 646 | .ident = "AOpen i45GMx-I", |
647 | .matches = { |
||
648 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), |
||
649 | DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), |
||
650 | }, |
||
651 | }, |
||
652 | { |
||
653 | .callback = intel_no_lvds_dmi_callback, |
||
2330 | Serge | 654 | .ident = "Aopen i945GTt-VFA", |
655 | .matches = { |
||
656 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), |
||
657 | }, |
||
658 | }, |
||
659 | { |
||
660 | .callback = intel_no_lvds_dmi_callback, |
||
661 | .ident = "Clientron U800", |
||
662 | .matches = { |
||
663 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), |
||
664 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), |
||
665 | }, |
||
666 | }, |
||
667 | { |
||
6084 | serge | 668 | .callback = intel_no_lvds_dmi_callback, |
2342 | Serge | 669 | .ident = "Clientron E830", |
670 | .matches = { |
||
671 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), |
||
672 | DMI_MATCH(DMI_PRODUCT_NAME, "E830"), |
||
673 | }, |
||
674 | }, |
||
675 | { |
||
676 | .callback = intel_no_lvds_dmi_callback, |
||
2330 | Serge | 677 | .ident = "Asus EeeBox PC EB1007", |
678 | .matches = { |
||
679 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), |
||
680 | DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), |
||
681 | }, |
||
682 | }, |
||
2342 | Serge | 683 | { |
684 | .callback = intel_no_lvds_dmi_callback, |
||
685 | .ident = "Asus AT5NM10T-I", |
||
686 | .matches = { |
||
687 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), |
||
688 | DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), |
||
689 | }, |
||
690 | }, |
||
3031 | serge | 691 | { |
692 | .callback = intel_no_lvds_dmi_callback, |
||
3746 | Serge | 693 | .ident = "Hewlett-Packard HP t5740", |
3031 | serge | 694 | .matches = { |
695 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), |
||
3746 | Serge | 696 | DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), |
3031 | serge | 697 | }, |
698 | }, |
||
699 | { |
||
700 | .callback = intel_no_lvds_dmi_callback, |
||
701 | .ident = "Hewlett-Packard t5745", |
||
702 | .matches = { |
||
703 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), |
||
704 | DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), |
||
705 | }, |
||
706 | }, |
||
707 | { |
||
708 | .callback = intel_no_lvds_dmi_callback, |
||
709 | .ident = "Hewlett-Packard st5747", |
||
710 | .matches = { |
||
711 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), |
||
712 | DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), |
||
713 | }, |
||
714 | }, |
||
715 | { |
||
716 | .callback = intel_no_lvds_dmi_callback, |
||
717 | .ident = "MSI Wind Box DC500", |
||
718 | .matches = { |
||
719 | DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), |
||
720 | DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), |
||
721 | }, |
||
722 | }, |
||
723 | { |
||
724 | .callback = intel_no_lvds_dmi_callback, |
||
725 | .ident = "Gigabyte GA-D525TUD", |
||
726 | .matches = { |
||
727 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), |
||
728 | DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), |
||
729 | }, |
||
730 | }, |
||
731 | { |
||
732 | .callback = intel_no_lvds_dmi_callback, |
||
733 | .ident = "Supermicro X7SPA-H", |
||
734 | .matches = { |
||
735 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), |
||
736 | DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), |
||
737 | }, |
||
738 | }, |
||
3746 | Serge | 739 | { |
740 | .callback = intel_no_lvds_dmi_callback, |
||
741 | .ident = "Fujitsu Esprimo Q900", |
||
742 | .matches = { |
||
743 | DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), |
||
744 | DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), |
||
745 | }, |
||
746 | }, |
||
4104 | Serge | 747 | { |
748 | .callback = intel_no_lvds_dmi_callback, |
||
4280 | Serge | 749 | .ident = "Intel D410PT", |
750 | .matches = { |
||
751 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), |
||
752 | DMI_MATCH(DMI_BOARD_NAME, "D410PT"), |
||
753 | }, |
||
754 | }, |
||
755 | { |
||
756 | .callback = intel_no_lvds_dmi_callback, |
||
757 | .ident = "Intel D425KT", |
||
758 | .matches = { |
||
759 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), |
||
760 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), |
||
761 | }, |
||
762 | }, |
||
763 | { |
||
764 | .callback = intel_no_lvds_dmi_callback, |
||
4104 | Serge | 765 | .ident = "Intel D510MO", |
766 | .matches = { |
||
767 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), |
||
768 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), |
||
769 | }, |
||
770 | }, |
||
771 | { |
||
772 | .callback = intel_no_lvds_dmi_callback, |
||
773 | .ident = "Intel D525MW", |
||
774 | .matches = { |
||
775 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), |
||
776 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), |
||
777 | }, |
||
778 | }, |
||
2330 | Serge | 779 | |
780 | { } /* terminating entry */ |
||
781 | }; |
||
782 | |||
783 | /* |
||
784 | * Enumerate the child dev array parsed from VBT to check whether |
||
785 | * the LVDS is present. |
||
786 | * If it is present, return 1. |
||
787 | * If it is not present, return false. |
||
788 | * If no child dev is parsed from VBT, it assumes that the LVDS is present. |
||
789 | */ |
||
790 | static bool lvds_is_present_in_vbt(struct drm_device *dev, |
||
791 | u8 *i2c_pin) |
||
792 | { |
||
793 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
794 | int i; |
||
795 | |||
4104 | Serge | 796 | if (!dev_priv->vbt.child_dev_num) |
2330 | Serge | 797 | return true; |
798 | |||
4104 | Serge | 799 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
4560 | Serge | 800 | union child_device_config *uchild = dev_priv->vbt.child_dev + i; |
801 | struct old_child_dev_config *child = &uchild->old; |
||
2330 | Serge | 802 | |
803 | /* If the device type is not LFP, continue. |
||
804 | * We have to check both the new identifiers as well as the |
||
805 | * old for compatibility with some BIOSes. |
||
806 | */ |
||
807 | if (child->device_type != DEVICE_TYPE_INT_LFP && |
||
808 | child->device_type != DEVICE_TYPE_LFP) |
||
809 | continue; |
||
810 | |||
6084 | serge | 811 | if (intel_gmbus_is_valid_pin(dev_priv, child->i2c_pin)) |
812 | *i2c_pin = child->i2c_pin; |
||
2330 | Serge | 813 | |
814 | /* However, we cannot trust the BIOS writers to populate |
||
815 | * the VBT correctly. Since LVDS requires additional |
||
816 | * information from AIM blocks, a non-zero addin offset is |
||
817 | * a good indicator that the LVDS is actually present. |
||
818 | */ |
||
819 | if (child->addin_offset) |
||
820 | return true; |
||
821 | |||
822 | /* But even then some BIOS writers perform some black magic |
||
823 | * and instantiate the device without reference to any |
||
824 | * additional data. Trust that if the VBT was written into |
||
825 | * the OpRegion then they have validated the LVDS's existence. |
||
826 | */ |
||
827 | if (dev_priv->opregion.vbt) |
||
828 | return true; |
||
829 | } |
||
830 | |||
831 | return false; |
||
832 | } |
||
833 | |||
3480 | Serge | 834 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
835 | { |
||
836 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); |
||
837 | return 1; |
||
838 | } |
||
4104 | Serge | 839 | |
840 | static const struct dmi_system_id intel_dual_link_lvds[] = { |
||
841 | { |
||
842 | .callback = intel_dual_link_lvds_callback, |
||
6084 | serge | 843 | .ident = "Apple MacBook Pro 15\" (2010)", |
4104 | Serge | 844 | .matches = { |
845 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), |
||
6084 | serge | 846 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"), |
847 | }, |
||
848 | }, |
||
849 | { |
||
850 | .callback = intel_dual_link_lvds_callback, |
||
851 | .ident = "Apple MacBook Pro 15\" (2011)", |
||
852 | .matches = { |
||
853 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), |
||
4104 | Serge | 854 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), |
855 | }, |
||
856 | }, |
||
6084 | serge | 857 | { |
858 | .callback = intel_dual_link_lvds_callback, |
||
859 | .ident = "Apple MacBook Pro 15\" (2012)", |
||
860 | .matches = { |
||
861 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), |
||
862 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"), |
||
863 | }, |
||
864 | }, |
||
4104 | Serge | 865 | { } /* terminating entry */ |
866 | }; |
||
867 | |||
3480 | Serge | 868 | bool intel_is_dual_link_lvds(struct drm_device *dev) |
869 | { |
||
870 | struct intel_encoder *encoder; |
||
871 | struct intel_lvds_encoder *lvds_encoder; |
||
872 | |||
5354 | serge | 873 | for_each_intel_encoder(dev, encoder) { |
3480 | Serge | 874 | if (encoder->type == INTEL_OUTPUT_LVDS) { |
875 | lvds_encoder = to_lvds_encoder(&encoder->base); |
||
876 | |||
877 | return lvds_encoder->is_dual_link; |
||
878 | } |
||
879 | } |
||
880 | |||
881 | return false; |
||
882 | } |
||
883 | |||
884 | static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) |
||
885 | { |
||
886 | struct drm_device *dev = lvds_encoder->base.base.dev; |
||
887 | unsigned int val; |
||
888 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
889 | |||
890 | /* use the module option value if specified */ |
||
5060 | serge | 891 | if (i915.lvds_channel_mode > 0) |
892 | return i915.lvds_channel_mode == 2; |
||
3480 | Serge | 893 | |
6084 | serge | 894 | /* single channel LVDS is limited to 112 MHz */ |
895 | if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock |
||
896 | > 112999) |
||
897 | return true; |
||
898 | |||
5097 | serge | 899 | if (dmi_check_system(intel_dual_link_lvds)) |
900 | return true; |
||
3480 | Serge | 901 | |
902 | /* BIOS should set the proper LVDS register value at boot, but |
||
903 | * in reality, it doesn't set the value when the lid is closed; |
||
904 | * we need to check "the value to be set" in VBT when LVDS |
||
905 | * register is uninitialized. |
||
906 | */ |
||
907 | val = I915_READ(lvds_encoder->reg); |
||
908 | if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) |
||
4104 | Serge | 909 | val = dev_priv->vbt.bios_lvds_val; |
3480 | Serge | 910 | |
911 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; |
||
912 | } |
||
913 | |||
3031 | serge | 914 | static bool intel_lvds_supported(struct drm_device *dev) |
915 | { |
||
916 | /* With the introduction of the PCH we gained a dedicated |
||
917 | * LVDS presence pin, use it. */ |
||
3746 | Serge | 918 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
3031 | serge | 919 | return true; |
920 | |||
921 | /* Otherwise LVDS was only attached to mobile products, |
||
922 | * except for the inglorious 830gm */ |
||
3746 | Serge | 923 | if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) |
924 | return true; |
||
925 | |||
926 | return false; |
||
3031 | serge | 927 | } |
928 | |||
2330 | Serge | 929 | /** |
930 | * intel_lvds_init - setup LVDS connectors on this device |
||
931 | * @dev: drm device |
||
932 | * |
||
933 | * Create the connector, register the LVDS DDC bus, and try to figure out what |
||
934 | * modes we can display on the LVDS panel (if present). |
||
935 | */ |
||
4104 | Serge | 936 | void intel_lvds_init(struct drm_device *dev) |
2330 | Serge | 937 | { |
938 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3243 | Serge | 939 | struct intel_lvds_encoder *lvds_encoder; |
2330 | Serge | 940 | struct intel_encoder *intel_encoder; |
3243 | Serge | 941 | struct intel_lvds_connector *lvds_connector; |
2330 | Serge | 942 | struct intel_connector *intel_connector; |
943 | struct drm_connector *connector; |
||
944 | struct drm_encoder *encoder; |
||
945 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ |
||
3243 | Serge | 946 | struct drm_display_mode *fixed_mode = NULL; |
5060 | serge | 947 | struct drm_display_mode *downclock_mode = NULL; |
3243 | Serge | 948 | struct edid *edid; |
2330 | Serge | 949 | struct drm_crtc *crtc; |
6937 | serge | 950 | i915_reg_t lvds_reg; |
2330 | Serge | 951 | u32 lvds; |
952 | int pipe; |
||
953 | u8 pin; |
||
954 | |||
5354 | serge | 955 | /* |
956 | * Unlock registers and just leave them unlocked. Do this before |
||
957 | * checking quirk lists to avoid bogus WARNINGs. |
||
958 | */ |
||
959 | if (HAS_PCH_SPLIT(dev)) { |
||
960 | I915_WRITE(PCH_PP_CONTROL, |
||
961 | I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); |
||
6084 | serge | 962 | } else if (INTEL_INFO(dev_priv)->gen < 5) { |
5354 | serge | 963 | I915_WRITE(PP_CONTROL, |
964 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); |
||
965 | } |
||
3031 | serge | 966 | if (!intel_lvds_supported(dev)) |
4104 | Serge | 967 | return; |
3031 | serge | 968 | |
2330 | Serge | 969 | /* Skip init on machines we know falsely report LVDS */ |
5097 | serge | 970 | if (dmi_check_system(intel_no_lvds)) |
971 | return; |
||
2330 | Serge | 972 | |
6084 | serge | 973 | if (HAS_PCH_SPLIT(dev)) |
974 | lvds_reg = PCH_LVDS; |
||
975 | else |
||
976 | lvds_reg = LVDS; |
||
2330 | Serge | 977 | |
6084 | serge | 978 | lvds = I915_READ(lvds_reg); |
979 | |||
2330 | Serge | 980 | if (HAS_PCH_SPLIT(dev)) { |
6084 | serge | 981 | if ((lvds & LVDS_DETECTED) == 0) |
4104 | Serge | 982 | return; |
983 | if (dev_priv->vbt.edp_support) { |
||
2330 | Serge | 984 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
4104 | Serge | 985 | return; |
2330 | Serge | 986 | } |
987 | } |
||
988 | |||
6084 | serge | 989 | pin = GMBUS_PIN_PANEL; |
990 | if (!lvds_is_present_in_vbt(dev, &pin)) { |
||
991 | if ((lvds & LVDS_PORT_EN) == 0) { |
||
992 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); |
||
993 | return; |
||
994 | } |
||
995 | DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n"); |
||
996 | } |
||
997 | |||
998 | /* Set the Panel Power On/Off timings if uninitialized. */ |
||
999 | if (INTEL_INFO(dev_priv)->gen < 5 && |
||
1000 | I915_READ(PP_ON_DELAYS) == 0 && I915_READ(PP_OFF_DELAYS) == 0) { |
||
1001 | /* Set T2 to 40ms and T5 to 200ms */ |
||
1002 | I915_WRITE(PP_ON_DELAYS, 0x019007d0); |
||
1003 | |||
1004 | /* Set T3 to 35ms and Tx to 200ms */ |
||
1005 | I915_WRITE(PP_OFF_DELAYS, 0x015e07d0); |
||
1006 | |||
1007 | DRM_DEBUG_KMS("Panel power timings uninitialized, setting defaults\n"); |
||
1008 | } |
||
1009 | |||
4560 | Serge | 1010 | lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); |
3243 | Serge | 1011 | if (!lvds_encoder) |
4104 | Serge | 1012 | return; |
2330 | Serge | 1013 | |
4560 | Serge | 1014 | lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL); |
3243 | Serge | 1015 | if (!lvds_connector) { |
1016 | kfree(lvds_encoder); |
||
4104 | Serge | 1017 | return; |
2330 | Serge | 1018 | } |
1019 | |||
6084 | serge | 1020 | if (intel_connector_init(&lvds_connector->base) < 0) { |
1021 | kfree(lvds_connector); |
||
1022 | kfree(lvds_encoder); |
||
1023 | return; |
||
1024 | } |
||
1025 | |||
3243 | Serge | 1026 | lvds_encoder->attached_connector = lvds_connector; |
1027 | |||
1028 | intel_encoder = &lvds_encoder->base; |
||
2330 | Serge | 1029 | encoder = &intel_encoder->base; |
3243 | Serge | 1030 | intel_connector = &lvds_connector->base; |
2330 | Serge | 1031 | connector = &intel_connector->base; |
1032 | drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, |
||
1033 | DRM_MODE_CONNECTOR_LVDS); |
||
1034 | |||
1035 | drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, |
||
6937 | serge | 1036 | DRM_MODE_ENCODER_LVDS, NULL); |
2330 | Serge | 1037 | |
3031 | serge | 1038 | intel_encoder->enable = intel_enable_lvds; |
3480 | Serge | 1039 | intel_encoder->pre_enable = intel_pre_enable_lvds; |
3746 | Serge | 1040 | intel_encoder->compute_config = intel_lvds_compute_config; |
6084 | serge | 1041 | if (HAS_PCH_SPLIT(dev_priv)) { |
1042 | intel_encoder->disable = pch_disable_lvds; |
||
1043 | intel_encoder->post_disable = pch_post_disable_lvds; |
||
1044 | } else { |
||
1045 | intel_encoder->disable = gmch_disable_lvds; |
||
1046 | } |
||
3031 | serge | 1047 | intel_encoder->get_hw_state = intel_lvds_get_hw_state; |
4104 | Serge | 1048 | intel_encoder->get_config = intel_lvds_get_config; |
3031 | serge | 1049 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
5060 | serge | 1050 | intel_connector->unregister = intel_connector_unregister; |
3031 | serge | 1051 | |
2330 | Serge | 1052 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
1053 | intel_encoder->type = INTEL_OUTPUT_LVDS; |
||
1054 | |||
5060 | serge | 1055 | intel_encoder->cloneable = 0; |
2342 | Serge | 1056 | if (HAS_PCH_SPLIT(dev)) |
1057 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
||
3031 | serge | 1058 | else if (IS_GEN4(dev)) |
1059 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
||
2342 | Serge | 1060 | else |
6084 | serge | 1061 | intel_encoder->crtc_mask = (1 << 1); |
2342 | Serge | 1062 | |
2330 | Serge | 1063 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); |
1064 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; |
||
1065 | connector->interlace_allowed = false; |
||
1066 | connector->doublescan_allowed = false; |
||
1067 | |||
6084 | serge | 1068 | lvds_encoder->reg = lvds_reg; |
3480 | Serge | 1069 | |
2330 | Serge | 1070 | /* create the scaling mode property */ |
1071 | drm_mode_create_scaling_mode_property(dev); |
||
3243 | Serge | 1072 | drm_object_attach_property(&connector->base, |
2330 | Serge | 1073 | dev->mode_config.scaling_mode_property, |
1074 | DRM_MODE_SCALE_ASPECT); |
||
3243 | Serge | 1075 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
2330 | Serge | 1076 | /* |
1077 | * LVDS discovery: |
||
1078 | * 1) check for EDID on DDC |
||
1079 | * 2) check for VBT data |
||
1080 | * 3) check to see if LVDS is already on |
||
1081 | * if none of the above, no panel |
||
1082 | * 4) make sure lid is open |
||
1083 | * if closed, act like it's not there for now |
||
1084 | */ |
||
1085 | |||
1086 | /* |
||
1087 | * Attempt to get the fixed panel mode from DDC. Assume that the |
||
1088 | * preferred mode is the right one. |
||
1089 | */ |
||
5060 | serge | 1090 | mutex_lock(&dev->mode_config.mutex); |
3243 | Serge | 1091 | edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin)); |
1092 | if (edid) { |
||
1093 | if (drm_add_edid_modes(connector, edid)) { |
||
2330 | Serge | 1094 | drm_mode_connector_update_edid_property(connector, |
3243 | Serge | 1095 | edid); |
2330 | Serge | 1096 | } else { |
3243 | Serge | 1097 | kfree(edid); |
1098 | edid = ERR_PTR(-EINVAL); |
||
2330 | Serge | 1099 | } |
3243 | Serge | 1100 | } else { |
1101 | edid = ERR_PTR(-ENOENT); |
||
2330 | Serge | 1102 | } |
3243 | Serge | 1103 | lvds_connector->base.edid = edid; |
1104 | |||
1105 | if (IS_ERR_OR_NULL(edid)) { |
||
2330 | Serge | 1106 | /* Didn't get an EDID, so |
1107 | * Set wide sync ranges so we get all modes |
||
1108 | * handed to valid_mode for checking |
||
1109 | */ |
||
1110 | connector->display_info.min_vfreq = 0; |
||
1111 | connector->display_info.max_vfreq = 200; |
||
1112 | connector->display_info.min_hfreq = 0; |
||
1113 | connector->display_info.max_hfreq = 200; |
||
1114 | } |
||
1115 | |||
1116 | list_for_each_entry(scan, &connector->probed_modes, head) { |
||
1117 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { |
||
3243 | Serge | 1118 | DRM_DEBUG_KMS("using preferred mode from EDID: "); |
1119 | drm_mode_debug_printmodeline(scan); |
||
1120 | |||
1121 | fixed_mode = drm_mode_duplicate(dev, scan); |
||
6084 | serge | 1122 | if (fixed_mode) |
1123 | goto out; |
||
2330 | Serge | 1124 | } |
1125 | } |
||
1126 | |||
1127 | /* Failed to get EDID, what about VBT? */ |
||
4104 | Serge | 1128 | if (dev_priv->vbt.lfp_lvds_vbt_mode) { |
3243 | Serge | 1129 | DRM_DEBUG_KMS("using mode from VBT: "); |
4104 | Serge | 1130 | drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode); |
3243 | Serge | 1131 | |
4104 | Serge | 1132 | fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode); |
3243 | Serge | 1133 | if (fixed_mode) { |
1134 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
||
2330 | Serge | 1135 | goto out; |
1136 | } |
||
1137 | } |
||
1138 | |||
1139 | /* |
||
1140 | * If we didn't get EDID, try checking if the panel is already turned |
||
1141 | * on. If so, assume that whatever is currently programmed is the |
||
1142 | * correct mode. |
||
1143 | */ |
||
1144 | |||
1145 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
||
1146 | if (HAS_PCH_SPLIT(dev)) |
||
1147 | goto failed; |
||
1148 | |||
1149 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; |
||
1150 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
||
1151 | |||
1152 | if (crtc && (lvds & LVDS_PORT_EN)) { |
||
3243 | Serge | 1153 | fixed_mode = intel_crtc_mode_get(dev, crtc); |
1154 | if (fixed_mode) { |
||
1155 | DRM_DEBUG_KMS("using current (BIOS) mode: "); |
||
1156 | drm_mode_debug_printmodeline(fixed_mode); |
||
1157 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
||
2330 | Serge | 1158 | goto out; |
1159 | } |
||
1160 | } |
||
1161 | |||
1162 | /* If we still don't have a mode after all that, give up. */ |
||
3243 | Serge | 1163 | if (!fixed_mode) |
2330 | Serge | 1164 | goto failed; |
1165 | |||
1166 | out: |
||
5060 | serge | 1167 | mutex_unlock(&dev->mode_config.mutex); |
1168 | |||
6084 | serge | 1169 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
1170 | |||
3480 | Serge | 1171 | lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); |
1172 | DRM_DEBUG_KMS("detected %s-link lvds configuration\n", |
||
1173 | lvds_encoder->is_dual_link ? "dual" : "single"); |
||
1174 | |||
6937 | serge | 1175 | lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; |
5060 | serge | 1176 | |
1177 | drm_connector_register(connector); |
||
2330 | Serge | 1178 | |
5354 | serge | 1179 | intel_panel_setup_backlight(connector, INVALID_PIPE); |
2330 | Serge | 1180 | |
4104 | Serge | 1181 | return; |
2330 | Serge | 1182 | |
1183 | failed: |
||
5060 | serge | 1184 | mutex_unlock(&dev->mode_config.mutex); |
1185 | |||
2330 | Serge | 1186 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
1187 | drm_connector_cleanup(connector); |
||
1188 | drm_encoder_cleanup(encoder); |
||
3243 | Serge | 1189 | kfree(lvds_encoder); |
1190 | kfree(lvds_connector); |
||
4104 | Serge | 1191 | return; |
2330 | Serge | 1192 | }><>><>><>><>><>><>>>>=>>>> |