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/*

 * Copyright © 2006-2007 Intel Corporation

 * Copyright (c) 2006 Dave Airlie 

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice (including the next

 * paragraph) shall be included in all copies or substantial portions of the

 * Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

 * DEALINGS IN THE SOFTWARE.

 *

 * Authors:

 *	Eric Anholt 

 *      Dave Airlie 

 *      Jesse Barnes 

 */

//#include 

//#include 

#include 

#include 

#include 

#include 

#include 

#include "intel_drv.h"

#include 

#include "i915_drv.h"

//#include 

/* Private structure for the integrated LVDS support */

struct intel_lvds_connector {

	struct intel_connector base;

//	struct notifier_block lid_notifier;

};

struct intel_lvds_encoder {

	struct intel_encoder base;

	u32 pfit_control;

	u32 pfit_pgm_ratios;

	bool is_dual_link;

	u32 reg;

	struct intel_lvds_connector *attached_connector;

};

static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)

{

	return container_of(encoder, struct intel_lvds_encoder, base.base);

}

static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)

{

	return container_of(connector, struct intel_lvds_connector, base.base);

}

static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,

				    enum pipe *pipe)

{

	struct drm_device *dev = encoder->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);

	u32 tmp;

	tmp = I915_READ(lvds_encoder->reg);

	if (!(tmp & LVDS_PORT_EN))

		return false;

	if (HAS_PCH_CPT(dev))

		*pipe = PORT_TO_PIPE_CPT(tmp);

	else

		*pipe = PORT_TO_PIPE(tmp);

	return true;

}

/* The LVDS pin pair needs to be on before the DPLLs are enabled.

 * This is an exception to the general rule that mode_set doesn't turn

 * things on.

 */

static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder)

{

	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);

	struct drm_device *dev = encoder->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);

	struct drm_display_mode *fixed_mode =

		lvds_encoder->attached_connector->base.panel.fixed_mode;

	int pipe = intel_crtc->pipe;

	u32 temp;

	temp = I915_READ(lvds_encoder->reg);

	temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;

	if (HAS_PCH_CPT(dev)) {

		temp &= ~PORT_TRANS_SEL_MASK;

		temp |= PORT_TRANS_SEL_CPT(pipe);

	} else {

		if (pipe == 1) {

			temp |= LVDS_PIPEB_SELECT;

		} else {

			temp &= ~LVDS_PIPEB_SELECT;

		}

	}

	/* set the corresponsding LVDS_BORDER bit */

	temp |= dev_priv->lvds_border_bits;

	/* Set the B0-B3 data pairs corresponding to whether we're going to

	 * set the DPLLs for dual-channel mode or not.

	 */

	if (lvds_encoder->is_dual_link)

		temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;

	else

		temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);

	/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)

	 * appropriately here, but we need to look more thoroughly into how

	 * panels behave in the two modes.

	 */

	/* Set the dithering flag on LVDS as needed, note that there is no

	 * special lvds dither control bit on pch-split platforms, dithering is

	 * only controlled through the PIPECONF reg. */

	if (INTEL_INFO(dev)->gen == 4) {

		if (dev_priv->lvds_dither)

			temp |= LVDS_ENABLE_DITHER;

		else

			temp &= ~LVDS_ENABLE_DITHER;

	}

	temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);

	if (fixed_mode->flags & DRM_MODE_FLAG_NHSYNC)

		temp |= LVDS_HSYNC_POLARITY;

	if (fixed_mode->flags & DRM_MODE_FLAG_NVSYNC)

		temp |= LVDS_VSYNC_POLARITY;

	I915_WRITE(lvds_encoder->reg, temp);

}

static void intel_pre_enable_lvds(struct intel_encoder *encoder)

{

	struct drm_device *dev = encoder->base.dev;

	struct intel_lvds_encoder *enc = to_lvds_encoder(&encoder->base);

	struct drm_i915_private *dev_priv = dev->dev_private;

	if (HAS_PCH_SPLIT(dev) || !enc->pfit_control)

		return;

	/*

	 * Enable automatic panel scaling so that non-native modes

	 * fill the screen.  The panel fitter should only be

	 * adjusted whilst the pipe is disabled, according to

	 * register description and PRM.

	 */

	DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",

		      enc->pfit_control,

		      enc->pfit_pgm_ratios);

	I915_WRITE(PFIT_PGM_RATIOS, enc->pfit_pgm_ratios);

	I915_WRITE(PFIT_CONTROL, enc->pfit_control);

}

/**

 * Sets the power state for the panel.

 */

static void intel_enable_lvds(struct intel_encoder *encoder)

{

	struct drm_device *dev = encoder->base.dev;

	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);

	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 ctl_reg, stat_reg;

	if (HAS_PCH_SPLIT(dev)) {

		ctl_reg = PCH_PP_CONTROL;

		stat_reg = PCH_PP_STATUS;

	} else {

		ctl_reg = PP_CONTROL;

		stat_reg = PP_STATUS;

	}

	I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);

	I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);

	POSTING_READ(lvds_encoder->reg);

	if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))

		DRM_ERROR("timed out waiting for panel to power on\n");

	intel_panel_enable_backlight(dev, intel_crtc->pipe);

}

static void intel_disable_lvds(struct intel_encoder *encoder)

{

	struct drm_device *dev = encoder->base.dev;

	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 ctl_reg, stat_reg;

	if (HAS_PCH_SPLIT(dev)) {

		ctl_reg = PCH_PP_CONTROL;

		stat_reg = PCH_PP_STATUS;

	} else {

		ctl_reg = PP_CONTROL;

		stat_reg = PP_STATUS;

	}

	intel_panel_disable_backlight(dev);

	I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);

	if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))

		DRM_ERROR("timed out waiting for panel to power off\n");

	I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);

	POSTING_READ(lvds_encoder->reg);

}

static int intel_lvds_mode_valid(struct drm_connector *connector,

				 struct drm_display_mode *mode)

{

	struct intel_connector *intel_connector = to_intel_connector(connector);

	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;

	if (mode->hdisplay > fixed_mode->hdisplay)

		return MODE_PANEL;

	if (mode->vdisplay > fixed_mode->vdisplay)

		return MODE_PANEL;

	return MODE_OK;

}

static void

centre_horizontally(struct drm_display_mode *mode,

		    int width)

{

	u32 border, sync_pos, blank_width, sync_width;

	/* keep the hsync and hblank widths constant */

	sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;

	blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;

	sync_pos = (blank_width - sync_width + 1) / 2;

	border = (mode->hdisplay - width + 1) / 2;

	border += border & 1; /* make the border even */

	mode->crtc_hdisplay = width;

	mode->crtc_hblank_start = width + border;

	mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;

	mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;

	mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;

}

static void

centre_vertically(struct drm_display_mode *mode,

		  int height)

{

	u32 border, sync_pos, blank_width, sync_width;

	/* keep the vsync and vblank widths constant */

	sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;

	blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;

	sync_pos = (blank_width - sync_width + 1) / 2;

	border = (mode->vdisplay - height + 1) / 2;

	mode->crtc_vdisplay = height;

	mode->crtc_vblank_start = height + border;

	mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;

	mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;

	mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;

}

static inline u32 panel_fitter_scaling(u32 source, u32 target)

{

	/*

	 * Floating point operation is not supported. So the FACTOR

	 * is defined, which can avoid the floating point computation

	 * when calculating the panel ratio.

	 */

#define ACCURACY 12

#define FACTOR (1 << ACCURACY)

	u32 ratio = source * FACTOR / target;

	return (FACTOR * ratio + FACTOR/2) / FACTOR;

}

static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,

				      struct intel_crtc_config *pipe_config)

{

	struct drm_device *dev = intel_encoder->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_lvds_encoder *lvds_encoder =

		to_lvds_encoder(&intel_encoder->base);

	struct intel_connector *intel_connector =

		&lvds_encoder->attached_connector->base;

	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;

	struct drm_display_mode *mode = &pipe_config->requested_mode;

	struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;

	u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;

	unsigned int lvds_bpp;

	int pipe;

	/* Should never happen!! */

	if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {

		DRM_ERROR("Can't support LVDS on pipe A\n");

		return false;

	}

	if (intel_encoder_check_is_cloned(&lvds_encoder->base))

			return false;

	if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) ==

	    LVDS_A3_POWER_UP)

		lvds_bpp = 8*3;

	else

		lvds_bpp = 6*3;

	if (lvds_bpp != pipe_config->pipe_bpp) {

		DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",

			      pipe_config->pipe_bpp, lvds_bpp);

		pipe_config->pipe_bpp = lvds_bpp;

	}

	/*

	 * We have timings from the BIOS for the panel, put them in

	 * to the adjusted mode.  The CRTC will be set up for this mode,

	 * with the panel scaling set up to source from the H/VDisplay

	 * of the original mode.

	 */

	intel_fixed_panel_mode(intel_connector->panel.fixed_mode,

			       adjusted_mode);

	if (HAS_PCH_SPLIT(dev)) {

		pipe_config->has_pch_encoder = true;

		intel_pch_panel_fitting(dev,

					intel_connector->panel.fitting_mode,

					mode, adjusted_mode);

		return true;

	}

	/* Native modes don't need fitting */

	if (adjusted_mode->hdisplay == mode->hdisplay &&

	    adjusted_mode->vdisplay == mode->vdisplay)

		goto out;

	/* 965+ wants fuzzy fitting */

	if (INTEL_INFO(dev)->gen >= 4)

		pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |

				 PFIT_FILTER_FUZZY);

	/*

	 * Enable automatic panel scaling for non-native modes so that they fill

	 * the screen.  Should be enabled before the pipe is enabled, according

	 * to register description and PRM.

	 * Change the value here to see the borders for debugging

	 */

	for_each_pipe(pipe)

		I915_WRITE(BCLRPAT(pipe), 0);

	drm_mode_set_crtcinfo(adjusted_mode, 0);

	pipe_config->timings_set = true;

	switch (intel_connector->panel.fitting_mode) {

	case DRM_MODE_SCALE_CENTER:

		/*

		 * For centered modes, we have to calculate border widths &

		 * heights and modify the values programmed into the CRTC.

		 */

		centre_horizontally(adjusted_mode, mode->hdisplay);

		centre_vertically(adjusted_mode, mode->vdisplay);

		border = LVDS_BORDER_ENABLE;

		break;

	case DRM_MODE_SCALE_ASPECT:

		/* Scale but preserve the aspect ratio */

		if (INTEL_INFO(dev)->gen >= 4) {

			u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;

			u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;

			/* 965+ is easy, it does everything in hw */

			if (scaled_width > scaled_height)

				pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR;

			else if (scaled_width < scaled_height)

				pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER;

			else if (adjusted_mode->hdisplay != mode->hdisplay)

				pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;

		} else {

			u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;

			u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;

			/*

			 * For earlier chips we have to calculate the scaling

			 * ratio by hand and program it into the

			 * PFIT_PGM_RATIO register

			 */

			if (scaled_width > scaled_height) { /* pillar */

				centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay);

				border = LVDS_BORDER_ENABLE;

				if (mode->vdisplay != adjusted_mode->vdisplay) {

					u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay);

					pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |

							    bits << PFIT_VERT_SCALE_SHIFT);

					pfit_control |= (PFIT_ENABLE |

							 VERT_INTERP_BILINEAR |

							 HORIZ_INTERP_BILINEAR);

				}

			} else if (scaled_width < scaled_height) { /* letter */

				centre_vertically(adjusted_mode, scaled_width / mode->hdisplay);

				border = LVDS_BORDER_ENABLE;

				if (mode->hdisplay != adjusted_mode->hdisplay) {

					u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay);

					pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |

							    bits << PFIT_VERT_SCALE_SHIFT);

					pfit_control |= (PFIT_ENABLE |

							 VERT_INTERP_BILINEAR |

							 HORIZ_INTERP_BILINEAR);

				}

			} else

				/* Aspects match, Let hw scale both directions */

				pfit_control |= (PFIT_ENABLE |

						 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |

						 VERT_INTERP_BILINEAR |

						 HORIZ_INTERP_BILINEAR);

		}

		break;

	case DRM_MODE_SCALE_FULLSCREEN:

		/*

		 * Full scaling, even if it changes the aspect ratio.

		 * Fortunately this is all done for us in hw.

		 */

		if (mode->vdisplay != adjusted_mode->vdisplay ||

		    mode->hdisplay != adjusted_mode->hdisplay) {

			pfit_control |= PFIT_ENABLE;

			if (INTEL_INFO(dev)->gen >= 4)

				pfit_control |= PFIT_SCALING_AUTO;

			else

				pfit_control |= (VERT_AUTO_SCALE |

						 VERT_INTERP_BILINEAR |

						 HORIZ_AUTO_SCALE |

						 HORIZ_INTERP_BILINEAR);

		}

		break;

	default:

		break;

	}

out:

	/* If not enabling scaling, be consistent and always use 0. */

	if ((pfit_control & PFIT_ENABLE) == 0) {

		pfit_control = 0;

		pfit_pgm_ratios = 0;

	}

	/* Make sure pre-965 set dither correctly */

	if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither)

		pfit_control |= PANEL_8TO6_DITHER_ENABLE;

	if (pfit_control != lvds_encoder->pfit_control ||

	    pfit_pgm_ratios != lvds_encoder->pfit_pgm_ratios) {

		lvds_encoder->pfit_control = pfit_control;

		lvds_encoder->pfit_pgm_ratios = pfit_pgm_ratios;

	}

	dev_priv->lvds_border_bits = border;

	/*

	 * XXX: It would be nice to support lower refresh rates on the

	 * panels to reduce power consumption, and perhaps match the

	 * user's requested refresh rate.

	 */

	return true;

}

static void intel_lvds_mode_set(struct drm_encoder *encoder,

				struct drm_display_mode *mode,

				struct drm_display_mode *adjusted_mode)

{

	/*

	 * The LVDS pin pair will already have been turned on in the

	 * intel_crtc_mode_set since it has a large impact on the DPLL

	 * settings.

	 */

}

/**

 * Detect the LVDS connection.

 *

 * Since LVDS doesn't have hotlug, we use the lid as a proxy.  Open means

 * connected and closed means disconnected.  We also send hotplug events as

 * needed, using lid status notification from the input layer.

 */

static enum drm_connector_status

intel_lvds_detect(struct drm_connector *connector, bool force)

{

	struct drm_device *dev = connector->dev;

	enum drm_connector_status status;

	status = intel_panel_detect(dev);

	if (status != connector_status_unknown)

		return status;

	return connector_status_connected;

}

/**

 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.

 */

static int intel_lvds_get_modes(struct drm_connector *connector)

{

	struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);

	struct drm_device *dev = connector->dev;

	struct drm_display_mode *mode;

	/* use cached edid if we have one */

	if (!IS_ERR_OR_NULL(lvds_connector->base.edid))

		return drm_add_edid_modes(connector, lvds_connector->base.edid);

	mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);

	if (mode == NULL)

		return 0;

	drm_mode_probed_add(connector, mode);

	return 1;

}

static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)

{

	DRM_INFO("Skipping forced modeset for %s\n", id->ident);

	return 1;

}

/* The GPU hangs up on these systems if modeset is performed on LID open */

static const struct dmi_system_id intel_no_modeset_on_lid[] = {

	{

		.callback = intel_no_modeset_on_lid_dmi_callback,

		.ident = "Toshiba Tecra A11",

		.matches = {

			DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),

			DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),

		},

	},

	{ }	/* terminating entry */

};

#if 0

/*

 * Lid events. Note the use of 'modeset':

 *  - we set it to MODESET_ON_LID_OPEN on lid close,

 *    and set it to MODESET_DONE on open

 *  - we use it as a "only once" bit (ie we ignore

 *    duplicate events where it was already properly set)

 *  - the suspend/resume paths will set it to

 *    MODESET_SUSPENDED and ignore the lid open event,

 *    because they restore the mode ("lid open").

 */

static int intel_lid_notify(struct notifier_block *nb, unsigned long val,

			    void *unused)

{

	struct intel_lvds_connector *lvds_connector =

		container_of(nb, struct intel_lvds_connector, lid_notifier);

	struct drm_connector *connector = &lvds_connector->base.base;

	struct drm_device *dev = connector->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	if (dev->switch_power_state != DRM_SWITCH_POWER_ON)

		return NOTIFY_OK;

	mutex_lock(&dev_priv->modeset_restore_lock);

	if (dev_priv->modeset_restore == MODESET_SUSPENDED)

		goto exit;

	/*

	 * check and update the status of LVDS connector after receiving

	 * the LID nofication event.

	 */

	connector->status = connector->funcs->detect(connector, false);

	/* Don't force modeset on machines where it causes a GPU lockup */

	if (dmi_check_system(intel_no_modeset_on_lid))

		goto exit;

	if (!acpi_lid_open()) {

		/* do modeset on next lid open event */

		dev_priv->modeset_restore = MODESET_ON_LID_OPEN;

		goto exit;

	}

	if (dev_priv->modeset_restore == MODESET_DONE)

		goto exit;

	drm_modeset_lock_all(dev);

	intel_modeset_setup_hw_state(dev, true);

	drm_modeset_unlock_all(dev);

	dev_priv->modeset_restore = MODESET_DONE;

exit:

	mutex_unlock(&dev_priv->modeset_restore_lock);

	return NOTIFY_OK;

}

#endif

/**

 * intel_lvds_destroy - unregister and free LVDS structures

 * @connector: connector to free

 *

 * Unregister the DDC bus for this connector then free the driver private

 * structure.

 */

static void intel_lvds_destroy(struct drm_connector *connector)

{

	struct intel_lvds_connector *lvds_connector =

		to_lvds_connector(connector);

	if (!IS_ERR_OR_NULL(lvds_connector->base.edid))

		kfree(lvds_connector->base.edid);

	intel_panel_fini(&lvds_connector->base.panel);

	drm_sysfs_connector_remove(connector);

	drm_connector_cleanup(connector);

	kfree(connector);

}

static int intel_lvds_set_property(struct drm_connector *connector,

				   struct drm_property *property,

				   uint64_t value)

{

	struct intel_connector *intel_connector = to_intel_connector(connector);

	struct drm_device *dev = connector->dev;

	if (property == dev->mode_config.scaling_mode_property) {

		struct drm_crtc *crtc;

		if (value == DRM_MODE_SCALE_NONE) {

			DRM_DEBUG_KMS("no scaling not supported\n");

			return -EINVAL;

		}

		if (intel_connector->panel.fitting_mode == value) {

			/* the LVDS scaling property is not changed */

			return 0;

		}

		intel_connector->panel.fitting_mode = value;

		crtc = intel_attached_encoder(connector)->base.crtc;

		if (crtc && crtc->enabled) {

			/*

			 * If the CRTC is enabled, the display will be changed

			 * according to the new panel fitting mode.

			 */

			intel_crtc_restore_mode(crtc);

		}

	}

	return 0;

}

static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {

	.mode_set = intel_lvds_mode_set,

};

static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {

	.get_modes = intel_lvds_get_modes,

	.mode_valid = intel_lvds_mode_valid,

	.best_encoder = intel_best_encoder,

};

static const struct drm_connector_funcs intel_lvds_connector_funcs = {

	.dpms = intel_connector_dpms,

	.detect = intel_lvds_detect,

	.fill_modes = drm_helper_probe_single_connector_modes,

	.set_property = intel_lvds_set_property,

	.destroy = intel_lvds_destroy,

};

static const struct drm_encoder_funcs intel_lvds_enc_funcs = {

	.destroy = intel_encoder_destroy,

};

static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)

{

	DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);

	return 1;

}

/* These systems claim to have LVDS, but really don't */

static const struct dmi_system_id intel_no_lvds[] = {

	{

		.callback = intel_no_lvds_dmi_callback,

		.ident = "Apple Mac Mini (Core series)",

		.matches = {

			DMI_MATCH(DMI_SYS_VENDOR, "Apple"),

			DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),

		},

	},

	{

		.callback = intel_no_lvds_dmi_callback,

		.ident = "Apple Mac Mini (Core 2 series)",

		.matches = {

			DMI_MATCH(DMI_SYS_VENDOR, "Apple"),

			DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),

		},

	},

	{

		.callback = intel_no_lvds_dmi_callback,

		.ident = "MSI IM-945GSE-A",

		.matches = {

			DMI_MATCH(DMI_SYS_VENDOR, "MSI"),

			DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),

		},

	},

	{

		.callback = intel_no_lvds_dmi_callback,

		.ident = "Dell Studio Hybrid",

		.matches = {

			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),

			DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),

		},

	},

	{

		.callback = intel_no_lvds_dmi_callback,

		.ident = "Dell OptiPlex FX170",

		.matches = {

			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),

			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),

		},

	},

	{

		.callback = intel_no_lvds_dmi_callback,

		.ident = "AOpen Mini PC",

		.matches = {

			DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),

			DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),

		},

	},

	{

		.callback = intel_no_lvds_dmi_callback,

		.ident = "AOpen Mini PC MP915",

		.matches = {

			DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),

			DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),

		},

	},

	{

		.callback = intel_no_lvds_dmi_callback,

		.ident = "AOpen i915GMm-HFS",

		.matches = {

			DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),

			DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),

		},

	},

	{

		.callback = intel_no_lvds_dmi_callback,

                .ident = "AOpen i45GMx-I",

                .matches = {

                        DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),

                        DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),

                },

        },

	{

		.callback = intel_no_lvds_dmi_callback,

		.ident = "Aopen i945GTt-VFA",

		.matches = {

			DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),

		},

	},

	{

		.callback = intel_no_lvds_dmi_callback,

		.ident = "Clientron U800",

		.matches = {

			DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),

			DMI_MATCH(DMI_PRODUCT_NAME, "U800"),

		},

	},

	{

		.callback = intel_no_lvds_dmi_callback,

                .ident = "Clientron E830",

                .matches = {

                        DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),

                        DMI_MATCH(DMI_PRODUCT_NAME, "E830"),

                },

        },

        {

		.callback = intel_no_lvds_dmi_callback,

		.ident = "Asus EeeBox PC EB1007",

		.matches = {

			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),

			DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),

		},

	},

	{

		.callback = intel_no_lvds_dmi_callback,

		.ident = "Asus AT5NM10T-I",

		.matches = {

			DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),

			DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),

		},

	},

	{

		.callback = intel_no_lvds_dmi_callback,

		.ident = "Hewlett-Packard HP t5740",

		.matches = {

			DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),

			DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),

		},

	},

	{

		.callback = intel_no_lvds_dmi_callback,

		.ident = "Hewlett-Packard t5745",

		.matches = {

			DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),

			DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),

		},

	},

	{

		.callback = intel_no_lvds_dmi_callback,

		.ident = "Hewlett-Packard st5747",

		.matches = {

			DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),

			DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),

		},

	},

	{

		.callback = intel_no_lvds_dmi_callback,

		.ident = "MSI Wind Box DC500",

		.matches = {

			DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),

			DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),

		},

	},

	{

		.callback = intel_no_lvds_dmi_callback,

		.ident = "Gigabyte GA-D525TUD",

		.matches = {

			DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),

			DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),

		},

	},

	{

		.callback = intel_no_lvds_dmi_callback,

		.ident = "Supermicro X7SPA-H",

		.matches = {

			DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),

			DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),

		},

	},

	{

		.callback = intel_no_lvds_dmi_callback,

		.ident = "Fujitsu Esprimo Q900",

		.matches = {

			DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),

			DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),

		},

	},

	{ }	/* terminating entry */

};

/**

 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID

 * @dev: drm device

 * @connector: LVDS connector

 *

 * Find the reduced downclock for LVDS in EDID.

 */

static void intel_find_lvds_downclock(struct drm_device *dev,

				      struct drm_display_mode *fixed_mode,

				      struct drm_connector *connector)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_display_mode *scan;

	int temp_downclock;

	temp_downclock = fixed_mode->clock;

	list_for_each_entry(scan, &connector->probed_modes, head) {

		/*

		 * If one mode has the same resolution with the fixed_panel

		 * mode while they have the different refresh rate, it means

		 * that the reduced downclock is found for the LVDS. In such

		 * case we can set the different FPx0/1 to dynamically select

		 * between low and high frequency.

		 */

		if (scan->hdisplay == fixed_mode->hdisplay &&

		    scan->hsync_start == fixed_mode->hsync_start &&

		    scan->hsync_end == fixed_mode->hsync_end &&

		    scan->htotal == fixed_mode->htotal &&

		    scan->vdisplay == fixed_mode->vdisplay &&

		    scan->vsync_start == fixed_mode->vsync_start &&

		    scan->vsync_end == fixed_mode->vsync_end &&

		    scan->vtotal == fixed_mode->vtotal) {

			if (scan->clock < temp_downclock) {

				/*

				 * The downclock is already found. But we

				 * expect to find the lower downclock.

				 */

				temp_downclock = scan->clock;

			}

		}

	}

	if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) {

		/* We found the downclock for LVDS. */

		dev_priv->lvds_downclock_avail = 1;

		dev_priv->lvds_downclock = temp_downclock;

		DRM_DEBUG_KMS("LVDS downclock is found in EDID. "

			      "Normal clock %dKhz, downclock %dKhz\n",

			      fixed_mode->clock, temp_downclock);

	}

}

/*

 * Enumerate the child dev array parsed from VBT to check whether

 * the LVDS is present.

 * If it is present, return 1.

 * If it is not present, return false.

 * If no child dev is parsed from VBT, it assumes that the LVDS is present.

 */

static bool lvds_is_present_in_vbt(struct drm_device *dev,

				   u8 *i2c_pin)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int i;

	if (!dev_priv->child_dev_num)

		return true;

	for (i = 0; i < dev_priv->child_dev_num; i++) {

		struct child_device_config *child = dev_priv->child_dev + i;

		/* If the device type is not LFP, continue.

		 * We have to check both the new identifiers as well as the

		 * old for compatibility with some BIOSes.

		 */

		if (child->device_type != DEVICE_TYPE_INT_LFP &&

		    child->device_type != DEVICE_TYPE_LFP)

			continue;

		if (intel_gmbus_is_port_valid(child->i2c_pin))

		    *i2c_pin = child->i2c_pin;

		/* However, we cannot trust the BIOS writers to populate

		 * the VBT correctly.  Since LVDS requires additional

		 * information from AIM blocks, a non-zero addin offset is

		 * a good indicator that the LVDS is actually present.

		 */

		if (child->addin_offset)

			return true;

		/* But even then some BIOS writers perform some black magic

		 * and instantiate the device without reference to any

		 * additional data.  Trust that if the VBT was written into

		 * the OpRegion then they have validated the LVDS's existence.

		 */

		if (dev_priv->opregion.vbt)

			return true;

	}

	return false;

}

static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)

{

	DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);

	return 1;

}

bool intel_is_dual_link_lvds(struct drm_device *dev)

{

	struct intel_encoder *encoder;

	struct intel_lvds_encoder *lvds_encoder;

	list_for_each_entry(encoder, &dev->mode_config.encoder_list,

			    base.head) {

		if (encoder->type == INTEL_OUTPUT_LVDS) {

			lvds_encoder = to_lvds_encoder(&encoder->base);

			return lvds_encoder->is_dual_link;

		}

	}

	return false;

}

static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)

{

	struct drm_device *dev = lvds_encoder->base.base.dev;

	unsigned int val;

	struct drm_i915_private *dev_priv = dev->dev_private;

	/* use the module option value if specified */

	if (i915_lvds_channel_mode > 0)

		return i915_lvds_channel_mode == 2;

//	if (dmi_check_system(intel_dual_link_lvds))

//		return true;

	/* BIOS should set the proper LVDS register value at boot, but

	 * in reality, it doesn't set the value when the lid is closed;

	 * we need to check "the value to be set" in VBT when LVDS

	 * register is uninitialized.

	 */

	val = I915_READ(lvds_encoder->reg);

	if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))

		val = dev_priv->bios_lvds_val;

	return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;

}

static bool intel_lvds_supported(struct drm_device *dev)

{

	/* With the introduction of the PCH we gained a dedicated

	 * LVDS presence pin, use it. */

	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))

		return true;

	/* Otherwise LVDS was only attached to mobile products,

	 * except for the inglorious 830gm */

	if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))

		return true;

	return false;

}

/**

 * intel_lvds_init - setup LVDS connectors on this device

 * @dev: drm device

 *

 * Create the connector, register the LVDS DDC bus, and try to figure out what

 * modes we can display on the LVDS panel (if present).

 */

bool intel_lvds_init(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_lvds_encoder *lvds_encoder;

	struct intel_encoder *intel_encoder;

	struct intel_lvds_connector *lvds_connector;

	struct intel_connector *intel_connector;

	struct drm_connector *connector;

	struct drm_encoder *encoder;

	struct drm_display_mode *scan; /* *modes, *bios_mode; */

	struct drm_display_mode *fixed_mode = NULL;

	struct edid *edid;

	struct drm_crtc *crtc;

	u32 lvds;

	int pipe;

	u8 pin;

	if (!intel_lvds_supported(dev))

		return false;

	/* Skip init on machines we know falsely report LVDS */

//   if (dmi_check_system(intel_no_lvds))

//       return false;

	pin = GMBUS_PORT_PANEL;

	if (!lvds_is_present_in_vbt(dev, &pin)) {

		DRM_DEBUG_KMS("LVDS is not present in VBT\n");

		return false;

	}

	if (HAS_PCH_SPLIT(dev)) {

		if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)

			return false;

		if (dev_priv->edp.support) {

			DRM_DEBUG_KMS("disable LVDS for eDP support\n");

			return false;

		}

	}

	lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL);

	if (!lvds_encoder)

		return false;

	lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL);

	if (!lvds_connector) {

		kfree(lvds_encoder);

		return false;

	}

	lvds_encoder->attached_connector = lvds_connector;

	if (!HAS_PCH_SPLIT(dev)) {

		lvds_encoder->pfit_control = I915_READ(PFIT_CONTROL);

	}

	intel_encoder = &lvds_encoder->base;

	encoder = &intel_encoder->base;

	intel_connector = &lvds_connector->base;