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| 5354 | serge | 1 | /* |
| 2 | * Copyright © 2014 Intel Corporation |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice (including the next |
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| 12 | * paragraph) shall be included in all copies or substantial portions of the |
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| 13 | * Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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| 21 | * DEALINGS IN THE SOFTWARE. |
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| 22 | */ |
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| 23 | |||
| 24 | #ifndef _INTEL_LRC_H_ |
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| 25 | #define _INTEL_LRC_H_ |
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| 26 | |||
| 27 | #define GEN8_LR_CONTEXT_ALIGN 4096 |
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| 6084 | serge | 28 | #define GEN8_CSB_ENTRIES 6 |
| 29 | #define GEN8_CSB_PTR_MASK 0x07 |
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| 5354 | serge | 30 | |
| 31 | /* Execlists regs */ |
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| 32 | #define RING_ELSP(ring) ((ring)->mmio_base+0x230) |
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| 6084 | serge | 33 | #define RING_EXECLIST_STATUS_LO(ring) ((ring)->mmio_base+0x234) |
| 34 | #define RING_EXECLIST_STATUS_HI(ring) ((ring)->mmio_base+0x234 + 4) |
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| 5354 | serge | 35 | #define RING_CONTEXT_CONTROL(ring) ((ring)->mmio_base+0x244) |
| 6084 | serge | 36 | #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3) |
| 37 | #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0) |
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| 38 | #define CTX_CTRL_RS_CTX_ENABLE (1 << 1) |
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| 39 | #define RING_CONTEXT_STATUS_BUF_LO(ring, i) ((ring)->mmio_base+0x370 + (i) * 8) |
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| 40 | #define RING_CONTEXT_STATUS_BUF_HI(ring, i) ((ring)->mmio_base+0x370 + (i) * 8 + 4) |
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| 5354 | serge | 41 | #define RING_CONTEXT_STATUS_PTR(ring) ((ring)->mmio_base+0x3a0) |
| 42 | |||
| 43 | /* Logical Rings */ |
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| 6084 | serge | 44 | int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request); |
| 45 | int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request); |
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| 5354 | serge | 46 | void intel_logical_ring_stop(struct intel_engine_cs *ring); |
| 47 | void intel_logical_ring_cleanup(struct intel_engine_cs *ring); |
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| 48 | int intel_logical_rings_init(struct drm_device *dev); |
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| 6084 | serge | 49 | int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords); |
| 5354 | serge | 50 | |
| 6084 | serge | 51 | int logical_ring_flush_all_caches(struct drm_i915_gem_request *req); |
| 5354 | serge | 52 | /** |
| 53 | * intel_logical_ring_advance() - advance the ringbuffer tail |
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| 54 | * @ringbuf: Ringbuffer to advance. |
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| 55 | * |
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| 56 | * The tail is only updated in our logical ringbuffer struct. |
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| 57 | */ |
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| 58 | static inline void intel_logical_ring_advance(struct intel_ringbuffer *ringbuf) |
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| 59 | { |
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| 60 | ringbuf->tail &= ringbuf->size - 1; |
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| 61 | } |
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| 62 | /** |
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| 63 | * intel_logical_ring_emit() - write a DWORD to the ringbuffer. |
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| 64 | * @ringbuf: Ringbuffer to write to. |
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| 65 | * @data: DWORD to write. |
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| 66 | */ |
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| 67 | static inline void intel_logical_ring_emit(struct intel_ringbuffer *ringbuf, |
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| 68 | u32 data) |
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| 69 | { |
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| 70 | iowrite32(data, ringbuf->virtual_start + ringbuf->tail); |
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| 71 | ringbuf->tail += 4; |
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| 72 | } |
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| 73 | |||
| 74 | /* Logical Ring Contexts */ |
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| 6084 | serge | 75 | |
| 76 | /* One extra page is added before LRC for GuC as shared data */ |
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| 77 | #define LRC_GUCSHR_PN (0) |
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| 78 | #define LRC_PPHWSP_PN (LRC_GUCSHR_PN + 1) |
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| 79 | #define LRC_STATE_PN (LRC_PPHWSP_PN + 1) |
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| 80 | |||
| 5354 | serge | 81 | void intel_lr_context_free(struct intel_context *ctx); |
| 6084 | serge | 82 | int intel_lr_context_deferred_alloc(struct intel_context *ctx, |
| 83 | struct intel_engine_cs *ring); |
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| 84 | void intel_lr_context_unpin(struct drm_i915_gem_request *req); |
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| 85 | void intel_lr_context_reset(struct drm_device *dev, |
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| 86 | struct intel_context *ctx); |
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| 87 | uint64_t intel_lr_context_descriptor(struct intel_context *ctx, |
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| 5354 | serge | 88 | struct intel_engine_cs *ring); |
| 89 | |||
| 90 | /* Execlists */ |
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| 91 | int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists); |
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| 6084 | serge | 92 | struct i915_execbuffer_params; |
| 93 | int intel_execlists_submission(struct i915_execbuffer_params *params, |
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| 5354 | serge | 94 | struct drm_i915_gem_execbuffer2 *args, |
| 6084 | serge | 95 | struct list_head *vmas); |
| 5354 | serge | 96 | u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj); |
| 97 | |||
| 6084 | serge | 98 | void intel_lrc_irq_handler(struct intel_engine_cs *ring); |
| 5354 | serge | 99 | void intel_execlists_retire_requests(struct intel_engine_cs *ring); |
| 100 | |||
| 101 | #endif /* _INTEL_LRC_H_ */ |