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Rev | Author | Line No. | Line |
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3243 | Serge | 1 | /* |
2 | * Copyright (c) 2006 Dave Airlie |
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3 | * Copyright © 2006-2008,2010 Intel Corporation |
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4 | * Jesse Barnes |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice (including the next |
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14 | * paragraph) shall be included in all copies or substantial portions of the |
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15 | * Software. |
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16 | * |
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17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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23 | * DEALINGS IN THE SOFTWARE. |
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24 | * |
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25 | * Authors: |
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26 | * Eric Anholt |
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27 | * Chris Wilson |
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28 | */ |
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29 | #include |
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30 | #include |
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31 | #include |
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32 | #include |
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33 | #include "intel_drv.h" |
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34 | #include |
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35 | #include "i915_drv.h" |
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36 | |||
6084 | serge | 37 | struct gmbus_pin { |
3243 | Serge | 38 | const char *name; |
39 | int reg; |
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40 | }; |
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41 | |||
6084 | serge | 42 | /* Map gmbus pin pairs to names and registers. */ |
43 | static const struct gmbus_pin gmbus_pins[] = { |
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44 | [GMBUS_PIN_SSC] = { "ssc", GPIOB }, |
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45 | [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, |
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46 | [GMBUS_PIN_PANEL] = { "panel", GPIOC }, |
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47 | [GMBUS_PIN_DPC] = { "dpc", GPIOD }, |
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48 | [GMBUS_PIN_DPB] = { "dpb", GPIOE }, |
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49 | [GMBUS_PIN_DPD] = { "dpd", GPIOF }, |
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3243 | Serge | 50 | }; |
51 | |||
6084 | serge | 52 | static const struct gmbus_pin gmbus_pins_bdw[] = { |
53 | [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, |
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54 | [GMBUS_PIN_DPC] = { "dpc", GPIOD }, |
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55 | [GMBUS_PIN_DPB] = { "dpb", GPIOE }, |
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56 | [GMBUS_PIN_DPD] = { "dpd", GPIOF }, |
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57 | }; |
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58 | |||
59 | static const struct gmbus_pin gmbus_pins_skl[] = { |
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60 | [GMBUS_PIN_DPC] = { "dpc", GPIOD }, |
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61 | [GMBUS_PIN_DPB] = { "dpb", GPIOE }, |
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62 | [GMBUS_PIN_DPD] = { "dpd", GPIOF }, |
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63 | }; |
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64 | |||
65 | static const struct gmbus_pin gmbus_pins_bxt[] = { |
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66 | [GMBUS_PIN_1_BXT] = { "dpb", PCH_GPIOB }, |
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67 | [GMBUS_PIN_2_BXT] = { "dpc", PCH_GPIOC }, |
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68 | [GMBUS_PIN_3_BXT] = { "misc", PCH_GPIOD }, |
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69 | }; |
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70 | |||
71 | /* pin is expected to be valid */ |
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72 | static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, |
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73 | unsigned int pin) |
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74 | { |
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75 | if (IS_BROXTON(dev_priv)) |
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76 | return &gmbus_pins_bxt[pin]; |
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77 | else if (IS_SKYLAKE(dev_priv)) |
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78 | return &gmbus_pins_skl[pin]; |
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79 | else if (IS_BROADWELL(dev_priv)) |
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80 | return &gmbus_pins_bdw[pin]; |
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81 | else |
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82 | return &gmbus_pins[pin]; |
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83 | } |
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84 | |||
85 | bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
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86 | unsigned int pin) |
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87 | { |
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88 | unsigned int size; |
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89 | |||
90 | if (IS_BROXTON(dev_priv)) |
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91 | size = ARRAY_SIZE(gmbus_pins_bxt); |
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92 | else if (IS_SKYLAKE(dev_priv)) |
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93 | size = ARRAY_SIZE(gmbus_pins_skl); |
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94 | else if (IS_BROADWELL(dev_priv)) |
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95 | size = ARRAY_SIZE(gmbus_pins_bdw); |
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96 | else |
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97 | size = ARRAY_SIZE(gmbus_pins); |
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98 | |||
99 | return pin < size && get_gmbus_pin(dev_priv, pin)->reg; |
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100 | } |
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101 | |||
3243 | Serge | 102 | /* Intel GPIO access functions */ |
103 | |||
104 | #define I2C_RISEFALL_TIME 10 |
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105 | |||
106 | static inline struct intel_gmbus * |
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107 | to_intel_gmbus(struct i2c_adapter *i2c) |
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108 | { |
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109 | return container_of(i2c, struct intel_gmbus, adapter); |
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110 | } |
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111 | |||
112 | void |
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113 | intel_i2c_reset(struct drm_device *dev) |
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114 | { |
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115 | struct drm_i915_private *dev_priv = dev->dev_private; |
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4560 | Serge | 116 | |
6084 | serge | 117 | I915_WRITE(GMBUS0, 0); |
118 | I915_WRITE(GMBUS4, 0); |
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3243 | Serge | 119 | } |
120 | |||
121 | static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) |
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122 | { |
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123 | u32 val; |
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124 | |||
125 | /* When using bit bashing for I2C, this bit needs to be set to 1 */ |
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126 | if (!IS_PINEVIEW(dev_priv->dev)) |
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127 | return; |
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128 | |||
129 | val = I915_READ(DSPCLK_GATE_D); |
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130 | if (enable) |
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131 | val |= DPCUNIT_CLOCK_GATE_DISABLE; |
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132 | else |
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133 | val &= ~DPCUNIT_CLOCK_GATE_DISABLE; |
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134 | I915_WRITE(DSPCLK_GATE_D, val); |
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135 | } |
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136 | |||
137 | static u32 get_reserved(struct intel_gmbus *bus) |
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138 | { |
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139 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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140 | struct drm_device *dev = dev_priv->dev; |
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141 | u32 reserved = 0; |
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142 | |||
143 | /* On most chips, these bits must be preserved in software. */ |
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144 | if (!IS_I830(dev) && !IS_845G(dev)) |
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145 | reserved = I915_READ_NOTRACE(bus->gpio_reg) & |
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146 | (GPIO_DATA_PULLUP_DISABLE | |
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147 | GPIO_CLOCK_PULLUP_DISABLE); |
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148 | |||
149 | return reserved; |
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150 | } |
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151 | |||
152 | static int get_clock(void *data) |
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153 | { |
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154 | struct intel_gmbus *bus = data; |
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155 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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156 | u32 reserved = get_reserved(bus); |
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157 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); |
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158 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved); |
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159 | return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; |
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160 | } |
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161 | |||
162 | static int get_data(void *data) |
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163 | { |
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164 | struct intel_gmbus *bus = data; |
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165 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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166 | u32 reserved = get_reserved(bus); |
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167 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); |
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168 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved); |
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169 | return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; |
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170 | } |
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171 | |||
172 | static void set_clock(void *data, int state_high) |
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173 | { |
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174 | struct intel_gmbus *bus = data; |
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175 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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176 | u32 reserved = get_reserved(bus); |
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177 | u32 clock_bits; |
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178 | |||
179 | if (state_high) |
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180 | clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; |
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181 | else |
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182 | clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | |
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183 | GPIO_CLOCK_VAL_MASK; |
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184 | |||
185 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits); |
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186 | POSTING_READ(bus->gpio_reg); |
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187 | } |
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188 | |||
189 | static void set_data(void *data, int state_high) |
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190 | { |
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191 | struct intel_gmbus *bus = data; |
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192 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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193 | u32 reserved = get_reserved(bus); |
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194 | u32 data_bits; |
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195 | |||
196 | if (state_high) |
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197 | data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; |
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198 | else |
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199 | data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | |
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200 | GPIO_DATA_VAL_MASK; |
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201 | |||
202 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits); |
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203 | POSTING_READ(bus->gpio_reg); |
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204 | } |
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205 | |||
206 | static int |
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207 | intel_gpio_pre_xfer(struct i2c_adapter *adapter) |
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208 | { |
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209 | struct intel_gmbus *bus = container_of(adapter, |
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210 | struct intel_gmbus, |
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211 | adapter); |
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212 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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213 | |||
214 | intel_i2c_reset(dev_priv->dev); |
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215 | intel_i2c_quirk_set(dev_priv, true); |
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216 | set_data(bus, 1); |
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217 | set_clock(bus, 1); |
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218 | udelay(I2C_RISEFALL_TIME); |
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219 | return 0; |
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220 | } |
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221 | |||
222 | static void |
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223 | intel_gpio_post_xfer(struct i2c_adapter *adapter) |
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224 | { |
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225 | struct intel_gmbus *bus = container_of(adapter, |
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226 | struct intel_gmbus, |
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227 | adapter); |
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228 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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229 | |||
230 | set_data(bus, 1); |
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231 | set_clock(bus, 1); |
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232 | intel_i2c_quirk_set(dev_priv, false); |
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233 | } |
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234 | |||
235 | static void |
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6084 | serge | 236 | intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) |
3243 | Serge | 237 | { |
238 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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239 | struct i2c_algo_bit_data *algo; |
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240 | |||
241 | algo = &bus->bit_algo; |
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242 | |||
6084 | serge | 243 | bus->gpio_reg = dev_priv->gpio_mmio_base + |
244 | get_gmbus_pin(dev_priv, pin)->reg; |
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3243 | Serge | 245 | |
246 | bus->adapter.algo_data = algo; |
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247 | algo->setsda = set_data; |
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248 | algo->setscl = set_clock; |
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249 | algo->getsda = get_data; |
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250 | algo->getscl = get_clock; |
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251 | algo->pre_xfer = intel_gpio_pre_xfer; |
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252 | algo->post_xfer = intel_gpio_post_xfer; |
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253 | algo->udelay = I2C_RISEFALL_TIME; |
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254 | algo->timeout = usecs_to_jiffies(2200); |
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255 | algo->data = bus; |
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256 | } |
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257 | |||
258 | static int |
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3480 | Serge | 259 | gmbus_wait_hw_status(struct drm_i915_private *dev_priv, |
260 | u32 gmbus2_status, |
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261 | u32 gmbus4_irq_en) |
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262 | { |
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263 | int i; |
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264 | u32 gmbus2 = 0; |
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265 | DEFINE_WAIT(wait); |
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266 | |||
267 | if (!HAS_GMBUS_IRQ(dev_priv->dev)) |
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268 | gmbus4_irq_en = 0; |
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269 | |||
270 | /* Important: The hw handles only the first bit, so set only one! Since |
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271 | * we also need to check for NAKs besides the hw ready/idle signal, we |
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272 | * need to wake up periodically and check that ourselves. */ |
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6084 | serge | 273 | I915_WRITE(GMBUS4, gmbus4_irq_en); |
3480 | Serge | 274 | |
3746 | Serge | 275 | for (i = 0; i < msecs_to_jiffies_timeout(50); i++) { |
3480 | Serge | 276 | prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait, |
277 | TASK_UNINTERRUPTIBLE); |
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278 | |||
6084 | serge | 279 | gmbus2 = I915_READ_NOTRACE(GMBUS2); |
3480 | Serge | 280 | if (gmbus2 & (GMBUS_SATOER | gmbus2_status)) |
281 | break; |
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282 | |||
283 | schedule_timeout(1); |
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284 | } |
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285 | finish_wait(&dev_priv->gmbus_wait_queue, &wait); |
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286 | |||
6084 | serge | 287 | I915_WRITE(GMBUS4, 0); |
3480 | Serge | 288 | |
289 | if (gmbus2 & GMBUS_SATOER) |
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290 | return -ENXIO; |
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291 | if (gmbus2 & gmbus2_status) |
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292 | return 0; |
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293 | return -ETIMEDOUT; |
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294 | } |
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295 | |||
296 | static int |
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297 | gmbus_wait_idle(struct drm_i915_private *dev_priv) |
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298 | { |
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299 | int ret; |
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300 | |||
6084 | serge | 301 | #define C ((I915_READ_NOTRACE(GMBUS2) & GMBUS_ACTIVE) == 0) |
3480 | Serge | 302 | |
303 | if (!HAS_GMBUS_IRQ(dev_priv->dev)) |
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304 | return wait_for(C, 10); |
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305 | |||
306 | /* Important: The hw handles only the first bit, so set only one! */ |
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6084 | serge | 307 | I915_WRITE(GMBUS4, GMBUS_IDLE_EN); |
3480 | Serge | 308 | |
3746 | Serge | 309 | ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
310 | msecs_to_jiffies_timeout(10)); |
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3480 | Serge | 311 | |
6084 | serge | 312 | I915_WRITE(GMBUS4, 0); |
3480 | Serge | 313 | |
314 | if (ret) |
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315 | return 0; |
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316 | else |
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317 | return -ETIMEDOUT; |
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318 | #undef C |
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319 | } |
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320 | |||
321 | static int |
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6084 | serge | 322 | gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, |
323 | unsigned short addr, u8 *buf, unsigned int len, |
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324 | u32 gmbus1_index) |
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3243 | Serge | 325 | { |
6084 | serge | 326 | I915_WRITE(GMBUS1, |
3243 | Serge | 327 | gmbus1_index | |
328 | GMBUS_CYCLE_WAIT | |
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329 | (len << GMBUS_BYTE_COUNT_SHIFT) | |
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6084 | serge | 330 | (addr << GMBUS_SLAVE_ADDR_SHIFT) | |
3243 | Serge | 331 | GMBUS_SLAVE_READ | GMBUS_SW_RDY); |
332 | while (len) { |
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333 | int ret; |
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334 | u32 val, loop = 0; |
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335 | |||
3480 | Serge | 336 | ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, |
337 | GMBUS_HW_RDY_EN); |
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3243 | Serge | 338 | if (ret) |
3480 | Serge | 339 | return ret; |
3243 | Serge | 340 | |
6084 | serge | 341 | val = I915_READ(GMBUS3); |
3243 | Serge | 342 | do { |
343 | *buf++ = val & 0xff; |
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344 | val >>= 8; |
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345 | } while (--len && ++loop < 4); |
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346 | } |
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347 | |||
348 | return 0; |
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349 | } |
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350 | |||
351 | static int |
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6084 | serge | 352 | gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, |
353 | u32 gmbus1_index) |
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3243 | Serge | 354 | { |
355 | u8 *buf = msg->buf; |
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6084 | serge | 356 | unsigned int rx_size = msg->len; |
357 | unsigned int len; |
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358 | int ret; |
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359 | |||
360 | do { |
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361 | len = min(rx_size, GMBUS_BYTE_COUNT_MAX); |
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362 | |||
363 | ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, |
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364 | buf, len, gmbus1_index); |
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365 | if (ret) |
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366 | return ret; |
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367 | |||
368 | rx_size -= len; |
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369 | buf += len; |
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370 | } while (rx_size != 0); |
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371 | |||
372 | return 0; |
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373 | } |
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374 | |||
375 | static int |
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376 | gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, |
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377 | unsigned short addr, u8 *buf, unsigned int len) |
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378 | { |
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379 | unsigned int chunk_size = len; |
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3243 | Serge | 380 | u32 val, loop; |
381 | |||
382 | val = loop = 0; |
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383 | while (len && loop < 4) { |
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384 | val |= *buf++ << (8 * loop++); |
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385 | len -= 1; |
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386 | } |
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387 | |||
6084 | serge | 388 | I915_WRITE(GMBUS3, val); |
389 | I915_WRITE(GMBUS1, |
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3243 | Serge | 390 | GMBUS_CYCLE_WAIT | |
6084 | serge | 391 | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | |
392 | (addr << GMBUS_SLAVE_ADDR_SHIFT) | |
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3243 | Serge | 393 | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); |
394 | while (len) { |
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395 | int ret; |
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396 | |||
397 | val = loop = 0; |
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398 | do { |
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399 | val |= *buf++ << (8 * loop); |
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400 | } while (--len && ++loop < 4); |
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401 | |||
6084 | serge | 402 | I915_WRITE(GMBUS3, val); |
3243 | Serge | 403 | |
3480 | Serge | 404 | ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, |
405 | GMBUS_HW_RDY_EN); |
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3243 | Serge | 406 | if (ret) |
3480 | Serge | 407 | return ret; |
3243 | Serge | 408 | } |
6084 | serge | 409 | |
3243 | Serge | 410 | return 0; |
411 | } |
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412 | |||
6084 | serge | 413 | static int |
414 | gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) |
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415 | { |
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416 | u8 *buf = msg->buf; |
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417 | unsigned int tx_size = msg->len; |
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418 | unsigned int len; |
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419 | int ret; |
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420 | |||
421 | do { |
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422 | len = min(tx_size, GMBUS_BYTE_COUNT_MAX); |
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423 | |||
424 | ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len); |
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425 | if (ret) |
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426 | return ret; |
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427 | |||
428 | buf += len; |
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429 | tx_size -= len; |
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430 | } while (tx_size != 0); |
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431 | |||
432 | return 0; |
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433 | } |
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434 | |||
3243 | Serge | 435 | /* |
436 | * The gmbus controller can combine a 1 or 2 byte write with a read that |
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437 | * immediately follows it by using an "INDEX" cycle. |
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438 | */ |
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439 | static bool |
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440 | gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) |
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441 | { |
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442 | return (i + 1 < num && |
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443 | !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 && |
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444 | (msgs[i + 1].flags & I2C_M_RD)); |
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445 | } |
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446 | |||
447 | static int |
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448 | gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) |
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449 | { |
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450 | u32 gmbus1_index = 0; |
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451 | u32 gmbus5 = 0; |
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452 | int ret; |
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453 | |||
454 | if (msgs[0].len == 2) |
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455 | gmbus5 = GMBUS_2BYTE_INDEX_EN | |
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456 | msgs[0].buf[1] | (msgs[0].buf[0] << 8); |
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457 | if (msgs[0].len == 1) |
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458 | gmbus1_index = GMBUS_CYCLE_INDEX | |
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459 | (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); |
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460 | |||
461 | /* GMBUS5 holds 16-bit index */ |
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462 | if (gmbus5) |
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6084 | serge | 463 | I915_WRITE(GMBUS5, gmbus5); |
3243 | Serge | 464 | |
465 | ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index); |
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466 | |||
467 | /* Clear GMBUS5 after each index transfer */ |
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468 | if (gmbus5) |
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6084 | serge | 469 | I915_WRITE(GMBUS5, 0); |
3243 | Serge | 470 | |
471 | return ret; |
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472 | } |
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473 | |||
474 | static int |
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475 | gmbus_xfer(struct i2c_adapter *adapter, |
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476 | struct i2c_msg *msgs, |
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477 | int num) |
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478 | { |
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479 | struct intel_gmbus *bus = container_of(adapter, |
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480 | struct intel_gmbus, |
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481 | adapter); |
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482 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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6084 | serge | 483 | int i = 0, inc, try = 0; |
3243 | Serge | 484 | int ret = 0; |
485 | |||
6084 | serge | 486 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
3243 | Serge | 487 | mutex_lock(&dev_priv->gmbus_mutex); |
488 | |||
489 | if (bus->force_bit) { |
||
490 | ret = i2c_bit_algo.master_xfer(adapter, msgs, num); |
||
491 | goto out; |
||
492 | } |
||
493 | |||
6084 | serge | 494 | retry: |
495 | I915_WRITE(GMBUS0, bus->reg0); |
||
3243 | Serge | 496 | |
6084 | serge | 497 | for (; i < num; i += inc) { |
498 | inc = 1; |
||
3243 | Serge | 499 | if (gmbus_is_index_read(msgs, i, num)) { |
500 | ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); |
||
6084 | serge | 501 | inc = 2; /* an index read is two msgs */ |
3243 | Serge | 502 | } else if (msgs[i].flags & I2C_M_RD) { |
503 | ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); |
||
504 | } else { |
||
505 | ret = gmbus_xfer_write(dev_priv, &msgs[i]); |
||
506 | } |
||
507 | |||
508 | if (ret == -ETIMEDOUT) |
||
509 | goto timeout; |
||
510 | if (ret == -ENXIO) |
||
511 | goto clear_err; |
||
512 | |||
3480 | Serge | 513 | ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE, |
514 | GMBUS_HW_WAIT_EN); |
||
515 | if (ret == -ENXIO) |
||
516 | goto clear_err; |
||
3243 | Serge | 517 | if (ret) |
518 | goto timeout; |
||
519 | } |
||
520 | |||
521 | /* Generate a STOP condition on the bus. Note that gmbus can't generata |
||
522 | * a STOP on the very first cycle. To simplify the code we |
||
523 | * unconditionally generate the STOP condition with an additional gmbus |
||
524 | * cycle. */ |
||
6084 | serge | 525 | I915_WRITE(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); |
3243 | Serge | 526 | |
527 | /* Mark the GMBUS interface as disabled after waiting for idle. |
||
528 | * We will re-enable it at the start of the next xfer, |
||
529 | * till then let it sleep. |
||
530 | */ |
||
3480 | Serge | 531 | if (gmbus_wait_idle(dev_priv)) { |
3243 | Serge | 532 | DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", |
533 | adapter->name); |
||
534 | ret = -ETIMEDOUT; |
||
535 | } |
||
6084 | serge | 536 | I915_WRITE(GMBUS0, 0); |
3243 | Serge | 537 | ret = ret ?: i; |
538 | goto out; |
||
539 | |||
540 | clear_err: |
||
541 | /* |
||
542 | * Wait for bus to IDLE before clearing NAK. |
||
543 | * If we clear the NAK while bus is still active, then it will stay |
||
544 | * active and the next transaction may fail. |
||
545 | * |
||
546 | * If no ACK is received during the address phase of a transaction, the |
||
547 | * adapter must report -ENXIO. It is not clear what to return if no ACK |
||
548 | * is received at other times. But we have to be careful to not return |
||
549 | * spurious -ENXIO because that will prevent i2c and drm edid functions |
||
550 | * from retrying. So return -ENXIO only when gmbus properly quiescents - |
||
551 | * timing out seems to happen when there _is_ a ddc chip present, but |
||
552 | * it's slow responding and only answers on the 2nd retry. |
||
553 | */ |
||
554 | ret = -ENXIO; |
||
3480 | Serge | 555 | if (gmbus_wait_idle(dev_priv)) { |
3243 | Serge | 556 | DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", |
557 | adapter->name); |
||
558 | ret = -ETIMEDOUT; |
||
559 | } |
||
560 | |||
561 | /* Toggle the Software Clear Interrupt bit. This has the effect |
||
562 | * of resetting the GMBUS controller and so clearing the |
||
563 | * BUS_ERROR raised by the slave's NAK. |
||
564 | */ |
||
6084 | serge | 565 | I915_WRITE(GMBUS1, GMBUS_SW_CLR_INT); |
566 | I915_WRITE(GMBUS1, 0); |
||
567 | I915_WRITE(GMBUS0, 0); |
||
3243 | Serge | 568 | |
569 | DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", |
||
570 | adapter->name, msgs[i].addr, |
||
571 | (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); |
||
572 | |||
6084 | serge | 573 | /* |
574 | * Passive adapters sometimes NAK the first probe. Retry the first |
||
575 | * message once on -ENXIO for GMBUS transfers; the bit banging algorithm |
||
576 | * has retries internally. See also the retry loop in |
||
577 | * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. |
||
578 | */ |
||
579 | if (ret == -ENXIO && i == 0 && try++ == 0) { |
||
580 | DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n", |
||
581 | adapter->name); |
||
582 | goto retry; |
||
583 | } |
||
584 | |||
3243 | Serge | 585 | goto out; |
586 | |||
587 | timeout: |
||
588 | DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", |
||
589 | bus->adapter.name, bus->reg0 & 0xff); |
||
6084 | serge | 590 | I915_WRITE(GMBUS0, 0); |
3243 | Serge | 591 | |
592 | /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */ |
||
593 | bus->force_bit = 1; |
||
594 | ret = i2c_bit_algo.master_xfer(adapter, msgs, num); |
||
595 | |||
596 | out: |
||
597 | mutex_unlock(&dev_priv->gmbus_mutex); |
||
6084 | serge | 598 | |
599 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
||
600 | |||
3243 | Serge | 601 | return ret; |
602 | } |
||
603 | |||
604 | static u32 gmbus_func(struct i2c_adapter *adapter) |
||
605 | { |
||
606 | return i2c_bit_algo.functionality(adapter) & |
||
607 | (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | |
||
608 | /* I2C_FUNC_10BIT_ADDR | */ |
||
609 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | |
||
610 | I2C_FUNC_SMBUS_BLOCK_PROC_CALL); |
||
611 | } |
||
612 | |||
613 | static const struct i2c_algorithm gmbus_algorithm = { |
||
614 | .master_xfer = gmbus_xfer, |
||
615 | .functionality = gmbus_func |
||
616 | }; |
||
617 | |||
618 | /** |
||
619 | * intel_gmbus_setup - instantiate all Intel i2c GMBuses |
||
620 | * @dev: DRM device |
||
621 | */ |
||
622 | int intel_setup_gmbus(struct drm_device *dev) |
||
623 | { |
||
624 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
6084 | serge | 625 | struct intel_gmbus *bus; |
626 | unsigned int pin; |
||
627 | int ret; |
||
3243 | Serge | 628 | |
3746 | Serge | 629 | if (HAS_PCH_NOP(dev)) |
630 | return 0; |
||
631 | else if (HAS_PCH_SPLIT(dev)) |
||
3243 | Serge | 632 | dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA; |
3480 | Serge | 633 | else if (IS_VALLEYVIEW(dev)) |
634 | dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; |
||
3243 | Serge | 635 | else |
636 | dev_priv->gpio_mmio_base = 0; |
||
637 | |||
638 | mutex_init(&dev_priv->gmbus_mutex); |
||
3480 | Serge | 639 | init_waitqueue_head(&dev_priv->gmbus_wait_queue); |
3243 | Serge | 640 | |
6084 | serge | 641 | for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { |
642 | if (!intel_gmbus_is_valid_pin(dev_priv, pin)) |
||
643 | continue; |
||
3243 | Serge | 644 | |
6084 | serge | 645 | bus = &dev_priv->gmbus[pin]; |
646 | |||
3243 | Serge | 647 | bus->adapter.owner = THIS_MODULE; |
648 | bus->adapter.class = I2C_CLASS_DDC; |
||
649 | snprintf(bus->adapter.name, |
||
650 | sizeof(bus->adapter.name), |
||
651 | "i915 gmbus %s", |
||
6084 | serge | 652 | get_gmbus_pin(dev_priv, pin)->name); |
3243 | Serge | 653 | |
654 | bus->adapter.dev.parent = &dev->pdev->dev; |
||
655 | bus->dev_priv = dev_priv; |
||
656 | |||
657 | bus->adapter.algo = &gmbus_algorithm; |
||
658 | |||
659 | /* By default use a conservative clock rate */ |
||
6084 | serge | 660 | bus->reg0 = pin | GMBUS_RATE_100KHZ; |
3243 | Serge | 661 | |
662 | /* gmbus seems to be broken on i830 */ |
||
663 | if (IS_I830(dev)) |
||
664 | bus->force_bit = 1; |
||
665 | |||
6084 | serge | 666 | intel_gpio_setup(bus, pin); |
3243 | Serge | 667 | |
668 | ret = i2c_add_adapter(&bus->adapter); |
||
669 | if (ret) |
||
670 | goto err; |
||
671 | } |
||
672 | |||
673 | intel_i2c_reset(dev_priv->dev); |
||
674 | |||
675 | return 0; |
||
676 | |||
677 | err: |
||
6320 | serge | 678 | while (pin--) { |
6084 | serge | 679 | if (!intel_gmbus_is_valid_pin(dev_priv, pin)) |
680 | continue; |
||
681 | |||
682 | bus = &dev_priv->gmbus[pin]; |
||
3243 | Serge | 683 | i2c_del_adapter(&bus->adapter); |
684 | } |
||
685 | return ret; |
||
686 | } |
||
687 | |||
688 | struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, |
||
6084 | serge | 689 | unsigned int pin) |
3243 | Serge | 690 | { |
6084 | serge | 691 | if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin))) |
692 | return NULL; |
||
693 | |||
694 | return &dev_priv->gmbus[pin].adapter; |
||
3243 | Serge | 695 | } |
696 | |||
697 | void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) |
||
698 | { |
||
699 | struct intel_gmbus *bus = to_intel_gmbus(adapter); |
||
700 | |||
701 | bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed; |
||
702 | } |
||
703 | |||
704 | void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) |
||
705 | { |
||
706 | struct intel_gmbus *bus = to_intel_gmbus(adapter); |
||
707 | |||
708 | bus->force_bit += force_bit ? 1 : -1; |
||
709 | DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n", |
||
710 | force_bit ? "en" : "dis", adapter->name, |
||
711 | bus->force_bit); |
||
712 | } |
||
713 | |||
714 | void intel_teardown_gmbus(struct drm_device *dev) |
||
715 | { |
||
716 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
6084 | serge | 717 | struct intel_gmbus *bus; |
718 | unsigned int pin; |
||
3243 | Serge | 719 | |
6084 | serge | 720 | for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { |
721 | if (!intel_gmbus_is_valid_pin(dev_priv, pin)) |
||
722 | continue; |
||
723 | |||
724 | bus = &dev_priv->gmbus[pin]; |
||
3243 | Serge | 725 | i2c_del_adapter(&bus->adapter); |
726 | } |
||
727 | }>><>>>><>><>=>>>><>><>><>><>>>><>><>>> |