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Rev | Author | Line No. | Line |
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3243 | Serge | 1 | /* |
2 | * Copyright (c) 2006 Dave Airlie |
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3 | * Copyright © 2006-2008,2010 Intel Corporation |
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4 | * Jesse Barnes |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice (including the next |
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14 | * paragraph) shall be included in all copies or substantial portions of the |
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15 | * Software. |
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16 | * |
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17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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23 | * DEALINGS IN THE SOFTWARE. |
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24 | * |
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25 | * Authors: |
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26 | * Eric Anholt |
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27 | * Chris Wilson |
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28 | */ |
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29 | #include |
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30 | #include |
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31 | #include |
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32 | #include |
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33 | #include "intel_drv.h" |
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34 | #include |
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35 | #include "i915_drv.h" |
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36 | |||
37 | struct gmbus_port { |
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38 | const char *name; |
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39 | int reg; |
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40 | }; |
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41 | |||
42 | static const struct gmbus_port gmbus_ports[] = { |
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43 | { "ssc", GPIOB }, |
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44 | { "vga", GPIOA }, |
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45 | { "panel", GPIOC }, |
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46 | { "dpc", GPIOD }, |
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47 | { "dpb", GPIOE }, |
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48 | { "dpd", GPIOF }, |
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49 | }; |
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50 | |||
51 | /* Intel GPIO access functions */ |
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52 | |||
53 | #define I2C_RISEFALL_TIME 10 |
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54 | |||
55 | static inline struct intel_gmbus * |
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56 | to_intel_gmbus(struct i2c_adapter *i2c) |
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57 | { |
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58 | return container_of(i2c, struct intel_gmbus, adapter); |
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59 | } |
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60 | |||
61 | void |
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62 | intel_i2c_reset(struct drm_device *dev) |
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63 | { |
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64 | struct drm_i915_private *dev_priv = dev->dev_private; |
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65 | I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0); |
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3480 | Serge | 66 | I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0); |
3243 | Serge | 67 | } |
68 | |||
69 | static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) |
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70 | { |
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71 | u32 val; |
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72 | |||
73 | /* When using bit bashing for I2C, this bit needs to be set to 1 */ |
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74 | if (!IS_PINEVIEW(dev_priv->dev)) |
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75 | return; |
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76 | |||
77 | val = I915_READ(DSPCLK_GATE_D); |
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78 | if (enable) |
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79 | val |= DPCUNIT_CLOCK_GATE_DISABLE; |
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80 | else |
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81 | val &= ~DPCUNIT_CLOCK_GATE_DISABLE; |
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82 | I915_WRITE(DSPCLK_GATE_D, val); |
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83 | } |
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84 | |||
85 | static u32 get_reserved(struct intel_gmbus *bus) |
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86 | { |
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87 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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88 | struct drm_device *dev = dev_priv->dev; |
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89 | u32 reserved = 0; |
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90 | |||
91 | /* On most chips, these bits must be preserved in software. */ |
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92 | if (!IS_I830(dev) && !IS_845G(dev)) |
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93 | reserved = I915_READ_NOTRACE(bus->gpio_reg) & |
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94 | (GPIO_DATA_PULLUP_DISABLE | |
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95 | GPIO_CLOCK_PULLUP_DISABLE); |
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96 | |||
97 | return reserved; |
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98 | } |
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99 | |||
100 | static int get_clock(void *data) |
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101 | { |
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102 | struct intel_gmbus *bus = data; |
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103 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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104 | u32 reserved = get_reserved(bus); |
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105 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); |
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106 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved); |
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107 | return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; |
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108 | } |
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109 | |||
110 | static int get_data(void *data) |
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111 | { |
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112 | struct intel_gmbus *bus = data; |
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113 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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114 | u32 reserved = get_reserved(bus); |
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115 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); |
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116 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved); |
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117 | return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; |
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118 | } |
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119 | |||
120 | static void set_clock(void *data, int state_high) |
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121 | { |
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122 | struct intel_gmbus *bus = data; |
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123 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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124 | u32 reserved = get_reserved(bus); |
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125 | u32 clock_bits; |
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126 | |||
127 | if (state_high) |
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128 | clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; |
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129 | else |
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130 | clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | |
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131 | GPIO_CLOCK_VAL_MASK; |
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132 | |||
133 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits); |
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134 | POSTING_READ(bus->gpio_reg); |
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135 | } |
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136 | |||
137 | static void set_data(void *data, int state_high) |
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138 | { |
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139 | struct intel_gmbus *bus = data; |
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140 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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141 | u32 reserved = get_reserved(bus); |
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142 | u32 data_bits; |
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143 | |||
144 | if (state_high) |
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145 | data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; |
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146 | else |
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147 | data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | |
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148 | GPIO_DATA_VAL_MASK; |
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149 | |||
150 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits); |
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151 | POSTING_READ(bus->gpio_reg); |
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152 | } |
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153 | |||
154 | static int |
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155 | intel_gpio_pre_xfer(struct i2c_adapter *adapter) |
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156 | { |
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157 | struct intel_gmbus *bus = container_of(adapter, |
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158 | struct intel_gmbus, |
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159 | adapter); |
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160 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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161 | |||
162 | intel_i2c_reset(dev_priv->dev); |
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163 | intel_i2c_quirk_set(dev_priv, true); |
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164 | set_data(bus, 1); |
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165 | set_clock(bus, 1); |
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166 | udelay(I2C_RISEFALL_TIME); |
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167 | return 0; |
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168 | } |
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169 | |||
170 | static void |
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171 | intel_gpio_post_xfer(struct i2c_adapter *adapter) |
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172 | { |
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173 | struct intel_gmbus *bus = container_of(adapter, |
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174 | struct intel_gmbus, |
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175 | adapter); |
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176 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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177 | |||
178 | set_data(bus, 1); |
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179 | set_clock(bus, 1); |
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180 | intel_i2c_quirk_set(dev_priv, false); |
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181 | } |
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182 | |||
183 | static void |
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184 | intel_gpio_setup(struct intel_gmbus *bus, u32 pin) |
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185 | { |
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186 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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187 | struct i2c_algo_bit_data *algo; |
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188 | |||
189 | algo = &bus->bit_algo; |
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190 | |||
191 | /* -1 to map pin pair to gmbus index */ |
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192 | bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg; |
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193 | |||
194 | bus->adapter.algo_data = algo; |
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195 | algo->setsda = set_data; |
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196 | algo->setscl = set_clock; |
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197 | algo->getsda = get_data; |
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198 | algo->getscl = get_clock; |
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199 | algo->pre_xfer = intel_gpio_pre_xfer; |
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200 | algo->post_xfer = intel_gpio_post_xfer; |
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201 | algo->udelay = I2C_RISEFALL_TIME; |
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202 | algo->timeout = usecs_to_jiffies(2200); |
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203 | algo->data = bus; |
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204 | } |
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205 | |||
3480 | Serge | 206 | /* |
207 | * gmbus on gen4 seems to be able to generate legacy interrupts even when in MSI |
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208 | * mode. This results in spurious interrupt warnings if the legacy irq no. is |
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209 | * shared with another device. The kernel then disables that interrupt source |
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210 | * and so prevents the other device from working properly. |
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211 | */ |
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212 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) |
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3243 | Serge | 213 | static int |
3480 | Serge | 214 | gmbus_wait_hw_status(struct drm_i915_private *dev_priv, |
215 | u32 gmbus2_status, |
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216 | u32 gmbus4_irq_en) |
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217 | { |
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218 | int i; |
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219 | int reg_offset = dev_priv->gpio_mmio_base; |
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220 | u32 gmbus2 = 0; |
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221 | DEFINE_WAIT(wait); |
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222 | |||
223 | if (!HAS_GMBUS_IRQ(dev_priv->dev)) |
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224 | gmbus4_irq_en = 0; |
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225 | |||
226 | /* Important: The hw handles only the first bit, so set only one! Since |
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227 | * we also need to check for NAKs besides the hw ready/idle signal, we |
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228 | * need to wake up periodically and check that ourselves. */ |
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229 | I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en); |
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230 | |||
3746 | Serge | 231 | for (i = 0; i < msecs_to_jiffies_timeout(50); i++) { |
3480 | Serge | 232 | prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait, |
233 | TASK_UNINTERRUPTIBLE); |
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234 | |||
235 | gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset); |
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236 | if (gmbus2 & (GMBUS_SATOER | gmbus2_status)) |
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237 | break; |
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238 | |||
239 | schedule_timeout(1); |
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240 | } |
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241 | finish_wait(&dev_priv->gmbus_wait_queue, &wait); |
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242 | |||
243 | I915_WRITE(GMBUS4 + reg_offset, 0); |
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244 | |||
245 | if (gmbus2 & GMBUS_SATOER) |
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246 | return -ENXIO; |
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247 | if (gmbus2 & gmbus2_status) |
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248 | return 0; |
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249 | return -ETIMEDOUT; |
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250 | } |
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251 | |||
252 | static int |
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253 | gmbus_wait_idle(struct drm_i915_private *dev_priv) |
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254 | { |
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255 | int ret; |
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256 | int reg_offset = dev_priv->gpio_mmio_base; |
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257 | |||
258 | #define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0) |
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259 | |||
260 | if (!HAS_GMBUS_IRQ(dev_priv->dev)) |
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261 | return wait_for(C, 10); |
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262 | |||
263 | /* Important: The hw handles only the first bit, so set only one! */ |
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264 | I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN); |
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265 | |||
3746 | Serge | 266 | ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
267 | msecs_to_jiffies_timeout(10)); |
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3480 | Serge | 268 | |
269 | I915_WRITE(GMBUS4 + reg_offset, 0); |
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270 | |||
271 | if (ret) |
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272 | return 0; |
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273 | else |
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274 | return -ETIMEDOUT; |
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275 | #undef C |
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276 | } |
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277 | |||
278 | static int |
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3243 | Serge | 279 | gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, |
280 | u32 gmbus1_index) |
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281 | { |
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282 | int reg_offset = dev_priv->gpio_mmio_base; |
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283 | u16 len = msg->len; |
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284 | u8 *buf = msg->buf; |
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285 | |||
286 | I915_WRITE(GMBUS1 + reg_offset, |
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287 | gmbus1_index | |
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288 | GMBUS_CYCLE_WAIT | |
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289 | (len << GMBUS_BYTE_COUNT_SHIFT) | |
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290 | (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) | |
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291 | GMBUS_SLAVE_READ | GMBUS_SW_RDY); |
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292 | while (len) { |
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293 | int ret; |
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294 | u32 val, loop = 0; |
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295 | |||
3480 | Serge | 296 | ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, |
297 | GMBUS_HW_RDY_EN); |
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3243 | Serge | 298 | if (ret) |
3480 | Serge | 299 | return ret; |
3243 | Serge | 300 | |
301 | val = I915_READ(GMBUS3 + reg_offset); |
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302 | do { |
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303 | *buf++ = val & 0xff; |
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304 | val >>= 8; |
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305 | } while (--len && ++loop < 4); |
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306 | } |
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307 | |||
308 | return 0; |
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309 | } |
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310 | |||
311 | static int |
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312 | gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) |
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313 | { |
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314 | int reg_offset = dev_priv->gpio_mmio_base; |
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315 | u16 len = msg->len; |
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316 | u8 *buf = msg->buf; |
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317 | u32 val, loop; |
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318 | |||
319 | val = loop = 0; |
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320 | while (len && loop < 4) { |
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321 | val |= *buf++ << (8 * loop++); |
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322 | len -= 1; |
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323 | } |
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324 | |||
325 | I915_WRITE(GMBUS3 + reg_offset, val); |
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326 | I915_WRITE(GMBUS1 + reg_offset, |
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327 | GMBUS_CYCLE_WAIT | |
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328 | (msg->len << GMBUS_BYTE_COUNT_SHIFT) | |
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329 | (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) | |
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330 | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); |
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331 | while (len) { |
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332 | int ret; |
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333 | |||
334 | val = loop = 0; |
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335 | do { |
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336 | val |= *buf++ << (8 * loop); |
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337 | } while (--len && ++loop < 4); |
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338 | |||
339 | I915_WRITE(GMBUS3 + reg_offset, val); |
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340 | |||
3480 | Serge | 341 | ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, |
342 | GMBUS_HW_RDY_EN); |
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3243 | Serge | 343 | if (ret) |
3480 | Serge | 344 | return ret; |
3243 | Serge | 345 | } |
346 | return 0; |
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347 | } |
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348 | |||
349 | /* |
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350 | * The gmbus controller can combine a 1 or 2 byte write with a read that |
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351 | * immediately follows it by using an "INDEX" cycle. |
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352 | */ |
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353 | static bool |
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354 | gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) |
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355 | { |
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356 | return (i + 1 < num && |
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357 | !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 && |
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358 | (msgs[i + 1].flags & I2C_M_RD)); |
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359 | } |
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360 | |||
361 | static int |
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362 | gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) |
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363 | { |
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364 | int reg_offset = dev_priv->gpio_mmio_base; |
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365 | u32 gmbus1_index = 0; |
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366 | u32 gmbus5 = 0; |
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367 | int ret; |
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368 | |||
369 | if (msgs[0].len == 2) |
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370 | gmbus5 = GMBUS_2BYTE_INDEX_EN | |
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371 | msgs[0].buf[1] | (msgs[0].buf[0] << 8); |
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372 | if (msgs[0].len == 1) |
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373 | gmbus1_index = GMBUS_CYCLE_INDEX | |
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374 | (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); |
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375 | |||
376 | /* GMBUS5 holds 16-bit index */ |
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377 | if (gmbus5) |
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378 | I915_WRITE(GMBUS5 + reg_offset, gmbus5); |
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379 | |||
380 | ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index); |
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381 | |||
382 | /* Clear GMBUS5 after each index transfer */ |
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383 | if (gmbus5) |
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384 | I915_WRITE(GMBUS5 + reg_offset, 0); |
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385 | |||
386 | return ret; |
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387 | } |
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388 | |||
389 | static int |
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390 | gmbus_xfer(struct i2c_adapter *adapter, |
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391 | struct i2c_msg *msgs, |
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392 | int num) |
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393 | { |
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394 | struct intel_gmbus *bus = container_of(adapter, |
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395 | struct intel_gmbus, |
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396 | adapter); |
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397 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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398 | int i, reg_offset; |
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399 | int ret = 0; |
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400 | |||
401 | mutex_lock(&dev_priv->gmbus_mutex); |
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402 | |||
403 | if (bus->force_bit) { |
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404 | ret = i2c_bit_algo.master_xfer(adapter, msgs, num); |
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405 | goto out; |
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406 | } |
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407 | |||
408 | reg_offset = dev_priv->gpio_mmio_base; |
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409 | |||
410 | I915_WRITE(GMBUS0 + reg_offset, bus->reg0); |
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411 | |||
412 | for (i = 0; i < num; i++) { |
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413 | if (gmbus_is_index_read(msgs, i, num)) { |
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414 | ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); |
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415 | i += 1; /* set i to the index of the read xfer */ |
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416 | } else if (msgs[i].flags & I2C_M_RD) { |
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417 | ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); |
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418 | } else { |
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419 | ret = gmbus_xfer_write(dev_priv, &msgs[i]); |
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420 | } |
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421 | |||
422 | if (ret == -ETIMEDOUT) |
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423 | goto timeout; |
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424 | if (ret == -ENXIO) |
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425 | goto clear_err; |
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426 | |||
3480 | Serge | 427 | ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE, |
428 | GMBUS_HW_WAIT_EN); |
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429 | if (ret == -ENXIO) |
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430 | goto clear_err; |
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3243 | Serge | 431 | if (ret) |
432 | goto timeout; |
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433 | } |
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434 | |||
435 | /* Generate a STOP condition on the bus. Note that gmbus can't generata |
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436 | * a STOP on the very first cycle. To simplify the code we |
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437 | * unconditionally generate the STOP condition with an additional gmbus |
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438 | * cycle. */ |
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439 | I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); |
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440 | |||
441 | /* Mark the GMBUS interface as disabled after waiting for idle. |
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442 | * We will re-enable it at the start of the next xfer, |
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443 | * till then let it sleep. |
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444 | */ |
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3480 | Serge | 445 | if (gmbus_wait_idle(dev_priv)) { |
3243 | Serge | 446 | DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", |
447 | adapter->name); |
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448 | ret = -ETIMEDOUT; |
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449 | } |
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450 | I915_WRITE(GMBUS0 + reg_offset, 0); |
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451 | ret = ret ?: i; |
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452 | goto out; |
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453 | |||
454 | clear_err: |
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455 | /* |
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456 | * Wait for bus to IDLE before clearing NAK. |
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457 | * If we clear the NAK while bus is still active, then it will stay |
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458 | * active and the next transaction may fail. |
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459 | * |
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460 | * If no ACK is received during the address phase of a transaction, the |
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461 | * adapter must report -ENXIO. It is not clear what to return if no ACK |
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462 | * is received at other times. But we have to be careful to not return |
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463 | * spurious -ENXIO because that will prevent i2c and drm edid functions |
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464 | * from retrying. So return -ENXIO only when gmbus properly quiescents - |
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465 | * timing out seems to happen when there _is_ a ddc chip present, but |
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466 | * it's slow responding and only answers on the 2nd retry. |
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467 | */ |
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468 | ret = -ENXIO; |
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3480 | Serge | 469 | if (gmbus_wait_idle(dev_priv)) { |
3243 | Serge | 470 | DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", |
471 | adapter->name); |
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472 | ret = -ETIMEDOUT; |
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473 | } |
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474 | |||
475 | /* Toggle the Software Clear Interrupt bit. This has the effect |
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476 | * of resetting the GMBUS controller and so clearing the |
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477 | * BUS_ERROR raised by the slave's NAK. |
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478 | */ |
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479 | I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); |
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480 | I915_WRITE(GMBUS1 + reg_offset, 0); |
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481 | I915_WRITE(GMBUS0 + reg_offset, 0); |
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482 | |||
483 | DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", |
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484 | adapter->name, msgs[i].addr, |
||
485 | (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); |
||
486 | |||
487 | goto out; |
||
488 | |||
489 | timeout: |
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490 | DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", |
||
491 | bus->adapter.name, bus->reg0 & 0xff); |
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492 | I915_WRITE(GMBUS0 + reg_offset, 0); |
||
493 | |||
494 | /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */ |
||
495 | bus->force_bit = 1; |
||
496 | ret = i2c_bit_algo.master_xfer(adapter, msgs, num); |
||
497 | |||
498 | out: |
||
499 | mutex_unlock(&dev_priv->gmbus_mutex); |
||
500 | return ret; |
||
501 | } |
||
502 | |||
503 | static u32 gmbus_func(struct i2c_adapter *adapter) |
||
504 | { |
||
505 | return i2c_bit_algo.functionality(adapter) & |
||
506 | (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | |
||
507 | /* I2C_FUNC_10BIT_ADDR | */ |
||
508 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | |
||
509 | I2C_FUNC_SMBUS_BLOCK_PROC_CALL); |
||
510 | } |
||
511 | |||
512 | static const struct i2c_algorithm gmbus_algorithm = { |
||
513 | .master_xfer = gmbus_xfer, |
||
514 | .functionality = gmbus_func |
||
515 | }; |
||
516 | |||
517 | /** |
||
518 | * intel_gmbus_setup - instantiate all Intel i2c GMBuses |
||
519 | * @dev: DRM device |
||
520 | */ |
||
521 | int intel_setup_gmbus(struct drm_device *dev) |
||
522 | { |
||
523 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
524 | int ret, i; |
||
525 | |||
3746 | Serge | 526 | if (HAS_PCH_NOP(dev)) |
527 | return 0; |
||
528 | else if (HAS_PCH_SPLIT(dev)) |
||
3243 | Serge | 529 | dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA; |
3480 | Serge | 530 | else if (IS_VALLEYVIEW(dev)) |
531 | dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; |
||
3243 | Serge | 532 | else |
533 | dev_priv->gpio_mmio_base = 0; |
||
534 | |||
535 | mutex_init(&dev_priv->gmbus_mutex); |
||
3480 | Serge | 536 | init_waitqueue_head(&dev_priv->gmbus_wait_queue); |
3243 | Serge | 537 | |
538 | for (i = 0; i < GMBUS_NUM_PORTS; i++) { |
||
539 | struct intel_gmbus *bus = &dev_priv->gmbus[i]; |
||
540 | u32 port = i + 1; /* +1 to map gmbus index to pin pair */ |
||
541 | |||
542 | bus->adapter.owner = THIS_MODULE; |
||
543 | bus->adapter.class = I2C_CLASS_DDC; |
||
544 | snprintf(bus->adapter.name, |
||
545 | sizeof(bus->adapter.name), |
||
546 | "i915 gmbus %s", |
||
547 | gmbus_ports[i].name); |
||
548 | |||
549 | bus->adapter.dev.parent = &dev->pdev->dev; |
||
550 | bus->dev_priv = dev_priv; |
||
551 | |||
552 | bus->adapter.algo = &gmbus_algorithm; |
||
553 | |||
554 | /* By default use a conservative clock rate */ |
||
555 | bus->reg0 = port | GMBUS_RATE_100KHZ; |
||
556 | |||
557 | /* gmbus seems to be broken on i830 */ |
||
558 | if (IS_I830(dev)) |
||
559 | bus->force_bit = 1; |
||
560 | |||
561 | intel_gpio_setup(bus, port); |
||
562 | |||
563 | ret = i2c_add_adapter(&bus->adapter); |
||
564 | if (ret) |
||
565 | goto err; |
||
566 | } |
||
567 | |||
568 | intel_i2c_reset(dev_priv->dev); |
||
569 | |||
570 | return 0; |
||
571 | |||
572 | err: |
||
573 | while (--i) { |
||
574 | struct intel_gmbus *bus = &dev_priv->gmbus[i]; |
||
575 | i2c_del_adapter(&bus->adapter); |
||
576 | } |
||
577 | return ret; |
||
578 | } |
||
579 | |||
580 | struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, |
||
581 | unsigned port) |
||
582 | { |
||
583 | WARN_ON(!intel_gmbus_is_port_valid(port)); |
||
584 | /* -1 to map pin pair to gmbus index */ |
||
585 | return (intel_gmbus_is_port_valid(port)) ? |
||
586 | &dev_priv->gmbus[port - 1].adapter : NULL; |
||
587 | } |
||
588 | |||
589 | void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) |
||
590 | { |
||
591 | struct intel_gmbus *bus = to_intel_gmbus(adapter); |
||
592 | |||
593 | bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed; |
||
594 | } |
||
595 | |||
596 | void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) |
||
597 | { |
||
598 | struct intel_gmbus *bus = to_intel_gmbus(adapter); |
||
599 | |||
600 | bus->force_bit += force_bit ? 1 : -1; |
||
601 | DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n", |
||
602 | force_bit ? "en" : "dis", adapter->name, |
||
603 | bus->force_bit); |
||
604 | } |
||
605 | |||
606 | void intel_teardown_gmbus(struct drm_device *dev) |
||
607 | { |
||
608 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
609 | int i; |
||
610 | |||
611 | for (i = 0; i < GMBUS_NUM_PORTS; i++) { |
||
612 | struct intel_gmbus *bus = &dev_priv->gmbus[i]; |
||
613 | i2c_del_adapter(&bus->adapter); |
||
614 | } |
||
615 | }>><>>>><>><>=>>>><>><>><>><>>>><>><>> |