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Rev | Author | Line No. | Line |
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2330 | Serge | 1 | /* |
2326 | Serge | 2 | * Copyright (c) 2006 Dave Airlie |
3 | * Copyright © 2006-2008,2010 Intel Corporation |
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4 | * Jesse Barnes |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice (including the next |
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14 | * paragraph) shall be included in all copies or substantial portions of the |
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15 | * Software. |
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16 | * |
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17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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23 | * DEALINGS IN THE SOFTWARE. |
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24 | * |
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25 | * Authors: |
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26 | * Eric Anholt |
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27 | * Chris Wilson |
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28 | */ |
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29 | #include |
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30 | #include |
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31 | #include "drmP.h" |
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32 | #include "drm.h" |
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33 | #include "intel_drv.h" |
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2330 | Serge | 34 | #include "i915_drm.h" |
2326 | Serge | 35 | #include "i915_drv.h" |
36 | |||
37 | #define MSEC_PER_SEC 1000L |
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38 | #define USEC_PER_MSEC 1000L |
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39 | #define NSEC_PER_USEC 1000L |
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40 | #define NSEC_PER_MSEC 1000000L |
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41 | #define USEC_PER_SEC 1000000L |
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42 | #define NSEC_PER_SEC 1000000000L |
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43 | #define FSEC_PER_SEC 1000000000000000L |
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44 | |||
45 | #define HZ_TO_MSEC_MUL32 0xA0000000 |
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46 | #define HZ_TO_MSEC_ADJ32 0x0 |
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47 | #define HZ_TO_MSEC_SHR32 28 |
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48 | #define HZ_TO_MSEC_MUL64 0xA000000000000000 |
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49 | #define HZ_TO_MSEC_ADJ64 0x0 |
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50 | #define HZ_TO_MSEC_SHR64 60 |
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51 | #define MSEC_TO_HZ_MUL32 0xCCCCCCCD |
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52 | #define MSEC_TO_HZ_ADJ32 0x733333333 |
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53 | #define MSEC_TO_HZ_SHR32 35 |
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54 | #define MSEC_TO_HZ_MUL64 0xCCCCCCCCCCCCCCCD |
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55 | #define MSEC_TO_HZ_ADJ64 0x73333333333333333 |
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56 | #define MSEC_TO_HZ_SHR64 67 |
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57 | #define HZ_TO_MSEC_NUM 10 |
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58 | #define HZ_TO_MSEC_DEN 1 |
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59 | #define MSEC_TO_HZ_NUM 1 |
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60 | #define MSEC_TO_HZ_DEN 10 |
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61 | |||
62 | #define HZ_TO_USEC_MUL32 0x9C400000 |
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63 | #define HZ_TO_USEC_ADJ32 0x0 |
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64 | #define HZ_TO_USEC_SHR32 18 |
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65 | #define HZ_TO_USEC_MUL64 0x9C40000000000000 |
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66 | #define HZ_TO_USEC_ADJ64 0x0 |
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67 | #define HZ_TO_USEC_SHR64 50 |
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68 | #define USEC_TO_HZ_MUL32 0xD1B71759 |
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69 | #define USEC_TO_HZ_ADJ32 0x1FFF2E48E8A7 |
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70 | #define USEC_TO_HZ_SHR32 45 |
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71 | #define USEC_TO_HZ_MUL64 0xD1B71758E219652C |
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72 | #define USEC_TO_HZ_ADJ64 0x1FFF2E48E8A71DE69AD4 |
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73 | #define USEC_TO_HZ_SHR64 77 |
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74 | #define HZ_TO_USEC_NUM 10000 |
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75 | #define HZ_TO_USEC_DEN 1 |
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76 | #define USEC_TO_HZ_NUM 1 |
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77 | #define USEC_TO_HZ_DEN 10000 |
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78 | |||
79 | unsigned int inline jiffies_to_usecs(const unsigned long j) |
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80 | { |
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81 | #if HZ <= USEC_PER_SEC && !(USEC_PER_SEC % HZ) |
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82 | return (USEC_PER_SEC / HZ) * j; |
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83 | #elif HZ > USEC_PER_SEC && !(HZ % USEC_PER_SEC) |
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84 | return (j + (HZ / USEC_PER_SEC) - 1)/(HZ / USEC_PER_SEC); |
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85 | #else |
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86 | # if BITS_PER_LONG == 32 |
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87 | return (HZ_TO_USEC_MUL32 * j) >> HZ_TO_USEC_SHR32; |
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88 | # else |
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89 | return (j * HZ_TO_USEC_NUM) / HZ_TO_USEC_DEN; |
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90 | # endif |
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91 | #endif |
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92 | } |
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93 | |||
94 | /* |
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95 | * When we convert to jiffies then we interpret incoming values |
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96 | * the following way: |
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97 | * |
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98 | * - negative values mean 'infinite timeout' (MAX_JIFFY_OFFSET) |
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99 | * |
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100 | * - 'too large' values [that would result in larger than |
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101 | * MAX_JIFFY_OFFSET values] mean 'infinite timeout' too. |
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102 | * |
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103 | * - all other values are converted to jiffies by either multiplying |
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104 | * the input value by a factor or dividing it with a factor |
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105 | * |
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106 | * We must also be careful about 32-bit overflows. |
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107 | */ |
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108 | unsigned long msecs_to_jiffies(const unsigned int m) |
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109 | { |
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110 | /* |
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111 | * Negative value, means infinite timeout: |
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112 | */ |
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113 | if ((int)m < 0) |
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114 | return MAX_JIFFY_OFFSET; |
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115 | |||
116 | #if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ) |
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117 | /* |
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118 | * HZ is equal to or smaller than 1000, and 1000 is a nice |
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119 | * round multiple of HZ, divide with the factor between them, |
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120 | * but round upwards: |
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121 | */ |
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122 | return (m + (MSEC_PER_SEC / HZ) - 1) / (MSEC_PER_SEC / HZ); |
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123 | #elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC) |
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124 | /* |
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125 | * HZ is larger than 1000, and HZ is a nice round multiple of |
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126 | * 1000 - simply multiply with the factor between them. |
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127 | * |
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128 | * But first make sure the multiplication result cannot |
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129 | * overflow: |
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130 | */ |
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131 | if (m > jiffies_to_msecs(MAX_JIFFY_OFFSET)) |
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132 | return MAX_JIFFY_OFFSET; |
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133 | |||
134 | return m * (HZ / MSEC_PER_SEC); |
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135 | #else |
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136 | /* |
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137 | * Generic case - multiply, round and divide. But first |
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138 | * check that if we are doing a net multiplication, that |
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139 | * we wouldn't overflow: |
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140 | */ |
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141 | if (HZ > MSEC_PER_SEC && m > jiffies_to_msecs(MAX_JIFFY_OFFSET)) |
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142 | return MAX_JIFFY_OFFSET; |
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143 | |||
144 | return (MSEC_TO_HZ_MUL32 * m + MSEC_TO_HZ_ADJ32) |
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145 | >> MSEC_TO_HZ_SHR32; |
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146 | #endif |
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147 | } |
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148 | |||
149 | unsigned long usecs_to_jiffies(const unsigned int u) |
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150 | { |
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151 | if (u > jiffies_to_usecs(MAX_JIFFY_OFFSET)) |
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152 | return MAX_JIFFY_OFFSET; |
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153 | #if HZ <= USEC_PER_SEC && !(USEC_PER_SEC % HZ) |
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154 | return (u + (USEC_PER_SEC / HZ) - 1) / (USEC_PER_SEC / HZ); |
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155 | #elif HZ > USEC_PER_SEC && !(HZ % USEC_PER_SEC) |
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156 | return u * (HZ / USEC_PER_SEC); |
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157 | #else |
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158 | return (USEC_TO_HZ_MUL32 * u + USEC_TO_HZ_ADJ32) |
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159 | >> USEC_TO_HZ_SHR32; |
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160 | #endif |
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161 | } |
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162 | |||
163 | |||
164 | |||
165 | /* Intel GPIO access functions */ |
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166 | |||
167 | #define I2C_RISEFALL_TIME 20 |
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168 | |||
169 | static inline struct intel_gmbus * |
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170 | to_intel_gmbus(struct i2c_adapter *i2c) |
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171 | { |
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172 | return container_of(i2c, struct intel_gmbus, adapter); |
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173 | } |
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174 | |||
175 | struct intel_gpio { |
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176 | struct i2c_adapter adapter; |
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177 | struct i2c_algo_bit_data algo; |
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178 | struct drm_i915_private *dev_priv; |
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179 | u32 reg; |
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180 | }; |
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181 | |||
182 | void |
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183 | intel_i2c_reset(struct drm_device *dev) |
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184 | { |
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185 | struct drm_i915_private *dev_priv = dev->dev_private; |
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186 | if (HAS_PCH_SPLIT(dev)) |
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187 | I915_WRITE(PCH_GMBUS0, 0); |
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188 | else |
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189 | I915_WRITE(GMBUS0, 0); |
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190 | } |
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191 | |||
192 | static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) |
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193 | { |
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194 | u32 val; |
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195 | |||
196 | /* When using bit bashing for I2C, this bit needs to be set to 1 */ |
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197 | if (!IS_PINEVIEW(dev_priv->dev)) |
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198 | return; |
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199 | |||
200 | val = I915_READ(DSPCLK_GATE_D); |
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201 | if (enable) |
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202 | val |= DPCUNIT_CLOCK_GATE_DISABLE; |
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203 | else |
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204 | val &= ~DPCUNIT_CLOCK_GATE_DISABLE; |
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205 | I915_WRITE(DSPCLK_GATE_D, val); |
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206 | } |
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207 | |||
208 | static u32 get_reserved(struct intel_gpio *gpio) |
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209 | { |
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210 | struct drm_i915_private *dev_priv = gpio->dev_priv; |
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211 | struct drm_device *dev = dev_priv->dev; |
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212 | u32 reserved = 0; |
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213 | |||
214 | /* On most chips, these bits must be preserved in software. */ |
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215 | if (!IS_I830(dev) && !IS_845G(dev)) |
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216 | reserved = I915_READ_NOTRACE(gpio->reg) & |
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217 | (GPIO_DATA_PULLUP_DISABLE | |
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218 | GPIO_CLOCK_PULLUP_DISABLE); |
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219 | |||
220 | return reserved; |
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221 | } |
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222 | |||
223 | static int get_clock(void *data) |
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224 | { |
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225 | struct intel_gpio *gpio = data; |
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226 | struct drm_i915_private *dev_priv = gpio->dev_priv; |
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227 | u32 reserved = get_reserved(gpio); |
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228 | I915_WRITE_NOTRACE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK); |
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229 | I915_WRITE_NOTRACE(gpio->reg, reserved); |
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230 | return (I915_READ_NOTRACE(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0; |
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231 | } |
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232 | |||
233 | static int get_data(void *data) |
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234 | { |
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235 | struct intel_gpio *gpio = data; |
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236 | struct drm_i915_private *dev_priv = gpio->dev_priv; |
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237 | u32 reserved = get_reserved(gpio); |
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238 | I915_WRITE_NOTRACE(gpio->reg, reserved | GPIO_DATA_DIR_MASK); |
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239 | I915_WRITE_NOTRACE(gpio->reg, reserved); |
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240 | return (I915_READ_NOTRACE(gpio->reg) & GPIO_DATA_VAL_IN) != 0; |
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241 | } |
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242 | |||
243 | static void set_clock(void *data, int state_high) |
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244 | { |
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245 | struct intel_gpio *gpio = data; |
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246 | struct drm_i915_private *dev_priv = gpio->dev_priv; |
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247 | u32 reserved = get_reserved(gpio); |
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248 | u32 clock_bits; |
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249 | |||
250 | if (state_high) |
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251 | clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; |
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252 | else |
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253 | clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | |
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254 | GPIO_CLOCK_VAL_MASK; |
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255 | |||
256 | I915_WRITE_NOTRACE(gpio->reg, reserved | clock_bits); |
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257 | POSTING_READ(gpio->reg); |
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258 | } |
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259 | |||
260 | static void set_data(void *data, int state_high) |
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261 | { |
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262 | struct intel_gpio *gpio = data; |
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263 | struct drm_i915_private *dev_priv = gpio->dev_priv; |
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264 | u32 reserved = get_reserved(gpio); |
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265 | u32 data_bits; |
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266 | |||
267 | if (state_high) |
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268 | data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; |
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269 | else |
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270 | data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | |
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271 | GPIO_DATA_VAL_MASK; |
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272 | |||
273 | I915_WRITE_NOTRACE(gpio->reg, reserved | data_bits); |
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274 | POSTING_READ(gpio->reg); |
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275 | } |
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276 | |||
277 | static struct i2c_adapter * |
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278 | intel_gpio_create(struct drm_i915_private *dev_priv, u32 pin) |
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279 | { |
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280 | static const int map_pin_to_reg[] = { |
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281 | 0, |
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282 | GPIOB, |
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283 | GPIOA, |
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284 | GPIOC, |
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285 | GPIOD, |
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286 | GPIOE, |
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287 | 0, |
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288 | GPIOF, |
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289 | }; |
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290 | struct intel_gpio *gpio; |
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2327 | Serge | 291 | |
2326 | Serge | 292 | if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin]) |
293 | return NULL; |
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294 | |||
295 | gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL); |
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296 | if (gpio == NULL) |
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297 | return NULL; |
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298 | |||
299 | gpio->reg = map_pin_to_reg[pin]; |
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300 | if (HAS_PCH_SPLIT(dev_priv->dev)) |
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301 | gpio->reg += PCH_GPIOA - GPIOA; |
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302 | gpio->dev_priv = dev_priv; |
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303 | |||
304 | snprintf(gpio->adapter.name, sizeof(gpio->adapter.name), |
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305 | "i915 GPIO%c", "?BACDE?F"[pin]); |
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306 | // gpio->adapter.owner = THIS_MODULE; |
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307 | gpio->adapter.algo_data = &gpio->algo; |
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308 | gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev; |
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309 | gpio->algo.setsda = set_data; |
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310 | gpio->algo.setscl = set_clock; |
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311 | gpio->algo.getsda = get_data; |
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312 | gpio->algo.getscl = get_clock; |
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313 | gpio->algo.udelay = I2C_RISEFALL_TIME; |
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314 | gpio->algo.timeout = usecs_to_jiffies(2200); |
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315 | gpio->algo.data = gpio; |
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316 | |||
317 | if (i2c_bit_add_bus(&gpio->adapter)) |
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318 | goto out_free; |
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2327 | Serge | 319 | |
2326 | Serge | 320 | return &gpio->adapter; |
321 | |||
322 | out_free: |
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323 | kfree(gpio); |
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324 | return NULL; |
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325 | } |
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326 | |||
327 | static int |
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328 | intel_i2c_quirk_xfer(struct drm_i915_private *dev_priv, |
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329 | struct i2c_adapter *adapter, |
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330 | struct i2c_msg *msgs, |
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331 | int num) |
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332 | { |
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333 | struct intel_gpio *gpio = container_of(adapter, |
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334 | struct intel_gpio, |
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335 | adapter); |
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336 | int ret; |
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337 | |||
338 | intel_i2c_reset(dev_priv->dev); |
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339 | |||
340 | intel_i2c_quirk_set(dev_priv, true); |
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341 | set_data(gpio, 1); |
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342 | set_clock(gpio, 1); |
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343 | udelay(I2C_RISEFALL_TIME); |
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344 | |||
345 | ret = adapter->algo->master_xfer(adapter, msgs, num); |
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346 | |||
347 | set_data(gpio, 1); |
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348 | set_clock(gpio, 1); |
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349 | intel_i2c_quirk_set(dev_priv, false); |
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350 | |||
351 | return ret; |
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352 | } |
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353 | |||
354 | static int |
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355 | gmbus_xfer(struct i2c_adapter *adapter, |
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356 | struct i2c_msg *msgs, |
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357 | int num) |
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358 | { |
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359 | struct intel_gmbus *bus = container_of(adapter, |
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360 | struct intel_gmbus, |
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361 | adapter); |
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362 | struct drm_i915_private *dev_priv = adapter->algo_data; |
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363 | int i, reg_offset; |
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364 | |||
365 | if (bus->force_bit) |
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366 | return intel_i2c_quirk_xfer(dev_priv, |
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367 | bus->force_bit, msgs, num); |
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368 | |||
369 | reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0; |
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370 | |||
371 | I915_WRITE(GMBUS0 + reg_offset, bus->reg0); |
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372 | |||
373 | for (i = 0; i < num; i++) { |
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374 | u16 len = msgs[i].len; |
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375 | u8 *buf = msgs[i].buf; |
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376 | |||
377 | if (msgs[i].flags & I2C_M_RD) { |
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378 | I915_WRITE(GMBUS1 + reg_offset, |
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379 | GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0) | |
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380 | (len << GMBUS_BYTE_COUNT_SHIFT) | |
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381 | (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) | |
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382 | GMBUS_SLAVE_READ | GMBUS_SW_RDY); |
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383 | POSTING_READ(GMBUS2+reg_offset); |
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384 | do { |
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385 | u32 val, loop = 0; |
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386 | |||
387 | if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50)) |
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388 | goto timeout; |
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389 | if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) |
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390 | goto clear_err; |
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391 | |||
392 | val = I915_READ(GMBUS3 + reg_offset); |
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393 | do { |
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394 | *buf++ = val & 0xff; |
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395 | val >>= 8; |
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396 | } while (--len && ++loop < 4); |
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397 | } while (len); |
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398 | } else { |
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399 | u32 val, loop; |
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400 | |||
401 | val = loop = 0; |
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402 | do { |
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403 | val |= *buf++ << (8 * loop); |
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404 | } while (--len && ++loop < 4); |
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405 | |||
406 | I915_WRITE(GMBUS3 + reg_offset, val); |
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407 | I915_WRITE(GMBUS1 + reg_offset, |
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408 | (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) | |
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409 | (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) | |
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410 | (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) | |
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411 | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); |
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412 | POSTING_READ(GMBUS2+reg_offset); |
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413 | |||
414 | while (len) { |
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415 | if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50)) |
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416 | goto timeout; |
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417 | if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) |
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418 | goto clear_err; |
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419 | |||
420 | val = loop = 0; |
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421 | do { |
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422 | val |= *buf++ << (8 * loop); |
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423 | } while (--len && ++loop < 4); |
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424 | |||
425 | I915_WRITE(GMBUS3 + reg_offset, val); |
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426 | POSTING_READ(GMBUS2+reg_offset); |
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427 | } |
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428 | } |
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429 | |||
430 | if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50)) |
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431 | goto timeout; |
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432 | if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) |
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433 | goto clear_err; |
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434 | } |
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435 | |||
436 | goto done; |
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437 | |||
438 | clear_err: |
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439 | /* Toggle the Software Clear Interrupt bit. This has the effect |
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440 | * of resetting the GMBUS controller and so clearing the |
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441 | * BUS_ERROR raised by the slave's NAK. |
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442 | */ |
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443 | I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); |
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444 | I915_WRITE(GMBUS1 + reg_offset, 0); |
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445 | |||
446 | done: |
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447 | /* Mark the GMBUS interface as disabled. We will re-enable it at the |
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448 | * start of the next xfer, till then let it sleep. |
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449 | */ |
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450 | I915_WRITE(GMBUS0 + reg_offset, 0); |
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451 | return i; |
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452 | |||
453 | timeout: |
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454 | DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n", |
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455 | bus->reg0 & 0xff, bus->adapter.name); |
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456 | I915_WRITE(GMBUS0 + reg_offset, 0); |
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457 | |||
458 | /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */ |
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459 | bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff); |
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460 | if (!bus->force_bit) |
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461 | return -ENOMEM; |
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462 | |||
463 | return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num); |
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464 | } |
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465 | |||
466 | static u32 gmbus_func(struct i2c_adapter *adapter) |
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467 | { |
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468 | struct intel_gmbus *bus = container_of(adapter, |
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469 | struct intel_gmbus, |
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470 | adapter); |
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471 | |||
472 | if (bus->force_bit) |
||
473 | bus->force_bit->algo->functionality(bus->force_bit); |
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474 | |||
475 | return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | |
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476 | /* I2C_FUNC_10BIT_ADDR | */ |
||
477 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | |
||
478 | I2C_FUNC_SMBUS_BLOCK_PROC_CALL); |
||
479 | } |
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480 | |||
481 | static const struct i2c_algorithm gmbus_algorithm = { |
||
482 | .master_xfer = gmbus_xfer, |
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483 | .functionality = gmbus_func |
||
484 | }; |
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485 | |||
486 | /** |
||
487 | * intel_gmbus_setup - instantiate all Intel i2c GMBuses |
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488 | * @dev: DRM device |
||
489 | */ |
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490 | int intel_setup_gmbus(struct drm_device *dev) |
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491 | { |
||
492 | static const char *names[GMBUS_NUM_PORTS] = { |
||
493 | "disabled", |
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494 | "ssc", |
||
495 | "vga", |
||
496 | "panel", |
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497 | "dpc", |
||
498 | "dpb", |
||
499 | "reserved", |
||
500 | "dpd", |
||
501 | }; |
||
502 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
503 | int ret, i; |
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2327 | Serge | 504 | |
2326 | Serge | 505 | dev_priv->gmbus = kcalloc(sizeof(struct intel_gmbus), GMBUS_NUM_PORTS, |
506 | GFP_KERNEL); |
||
507 | if (dev_priv->gmbus == NULL) |
||
508 | return -ENOMEM; |
||
509 | |||
510 | for (i = 0; i < GMBUS_NUM_PORTS; i++) { |
||
511 | struct intel_gmbus *bus = &dev_priv->gmbus[i]; |
||
512 | |||
513 | // bus->adapter.owner = THIS_MODULE; |
||
514 | bus->adapter.class = I2C_CLASS_DDC; |
||
515 | snprintf(bus->adapter.name, |
||
516 | sizeof(bus->adapter.name), |
||
517 | "i915 gmbus %s", |
||
518 | names[i]); |
||
519 | |||
520 | bus->adapter.dev.parent = &dev->pdev->dev; |
||
521 | bus->adapter.algo_data = dev_priv; |
||
522 | |||
523 | bus->adapter.algo = &gmbus_algorithm; |
||
524 | // ret = i2c_add_adapter(&bus->adapter); |
||
525 | // if (ret) |
||
526 | // goto err; |
||
527 | |||
528 | /* By default use a conservative clock rate */ |
||
529 | bus->reg0 = i | GMBUS_RATE_100KHZ; |
||
530 | |||
531 | /* XXX force bit banging until GMBUS is fully debugged */ |
||
532 | bus->force_bit = intel_gpio_create(dev_priv, i); |
||
533 | } |
||
534 | |||
535 | intel_i2c_reset(dev_priv->dev); |
||
2327 | Serge | 536 | |
2326 | Serge | 537 | return 0; |
538 | |||
539 | err: |
||
540 | // while (--i) { |
||
541 | // struct intel_gmbus *bus = &dev_priv->gmbus[i]; |
||
542 | // i2c_del_adapter(&bus->adapter); |
||
543 | // } |
||
544 | kfree(dev_priv->gmbus); |
||
545 | dev_priv->gmbus = NULL; |
||
546 | return ret; |
||
547 | } |
||
548 | |||
549 | void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) |
||
550 | { |
||
551 | struct intel_gmbus *bus = to_intel_gmbus(adapter); |
||
552 | |||
553 | /* speed: |
||
554 | * 0x0 = 100 KHz |
||
555 | * 0x1 = 50 KHz |
||
556 | * 0x2 = 400 KHz |
||
557 | * 0x3 = 1000 Khz |
||
558 | */ |
||
559 | bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | (speed << 8); |
||
560 | } |
||
561 | |||
562 | void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) |
||
563 | { |
||
564 | struct intel_gmbus *bus = to_intel_gmbus(adapter); |
||
565 | |||
566 | if (force_bit) { |
||
567 | if (bus->force_bit == NULL) { |
||
568 | struct drm_i915_private *dev_priv = adapter->algo_data; |
||
569 | bus->force_bit = intel_gpio_create(dev_priv, |
||
570 | bus->reg0 & 0xff); |
||
571 | } |
||
572 | } else { |
||
573 | if (bus->force_bit) { |
||
574 | // i2c_del_adapter(bus->force_bit); |
||
575 | kfree(bus->force_bit); |
||
576 | bus->force_bit = NULL; |
||
577 | } |
||
578 | } |
||
579 | } |
||
580 | |||
581 | void intel_teardown_gmbus(struct drm_device *dev) |
||
582 | { |
||
583 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
584 | int i; |
||
585 | |||
586 | if (dev_priv->gmbus == NULL) |
||
587 | return; |
||
588 | |||
589 | for (i = 0; i < GMBUS_NUM_PORTS; i++) { |
||
590 | struct intel_gmbus *bus = &dev_priv->gmbus[i]; |
||
591 | if (bus->force_bit) { |
||
592 | // i2c_del_adapter(bus->force_bit); |
||
593 | kfree(bus->force_bit); |
||
594 | } |
||
595 | // i2c_del_adapter(&bus->adapter); |
||
596 | } |
||
597 | |||
598 | kfree(dev_priv->gmbus); |
||
599 | dev_priv->gmbus = NULL; |
||
600 | }>><>><>>>>><>><>><>>><>>><>><>>=>=>>=> |