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2330 | Serge | 1 | /* |
2 | * Copyright 2006 Dave Airlie |
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3 | * Copyright © 2006-2009 Intel Corporation |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice (including the next |
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13 | * paragraph) shall be included in all copies or substantial portions of the |
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14 | * Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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22 | * DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: |
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25 | * Eric Anholt |
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26 | * Jesse Barnes |
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27 | */ |
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28 | |||
29 | #include |
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30 | #include |
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3031 | serge | 31 | #include |
4104 | Serge | 32 | #include |
3031 | serge | 33 | #include |
6084 | serge | 34 | #include |
3031 | serge | 35 | #include |
36 | #include |
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2330 | Serge | 37 | #include "intel_drv.h" |
3031 | serge | 38 | #include |
2330 | Serge | 39 | #include "i915_drv.h" |
40 | |||
3243 | Serge | 41 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
42 | { |
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43 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
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44 | } |
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45 | |||
3031 | serge | 46 | static void |
47 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) |
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48 | { |
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3243 | Serge | 49 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
3031 | serge | 50 | struct drm_i915_private *dev_priv = dev->dev_private; |
51 | uint32_t enabled_bits; |
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2330 | Serge | 52 | |
3480 | Serge | 53 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
3031 | serge | 54 | |
3746 | Serge | 55 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
3031 | serge | 56 | "HDMI port enabled, expecting disabled\n"); |
57 | } |
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58 | |||
59 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
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2330 | Serge | 60 | { |
3243 | Serge | 61 | struct intel_digital_port *intel_dig_port = |
62 | container_of(encoder, struct intel_digital_port, base.base); |
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63 | return &intel_dig_port->hdmi; |
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2330 | Serge | 64 | } |
65 | |||
66 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
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67 | { |
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3243 | Serge | 68 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
2330 | Serge | 69 | } |
70 | |||
4104 | Serge | 71 | static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) |
2330 | Serge | 72 | { |
4104 | Serge | 73 | switch (type) { |
74 | case HDMI_INFOFRAME_TYPE_AVI: |
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3031 | serge | 75 | return VIDEO_DIP_SELECT_AVI; |
4104 | Serge | 76 | case HDMI_INFOFRAME_TYPE_SPD: |
3031 | serge | 77 | return VIDEO_DIP_SELECT_SPD; |
4104 | Serge | 78 | case HDMI_INFOFRAME_TYPE_VENDOR: |
79 | return VIDEO_DIP_SELECT_VENDOR; |
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3031 | serge | 80 | default: |
4104 | Serge | 81 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
3031 | serge | 82 | return 0; |
83 | } |
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84 | } |
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2330 | Serge | 85 | |
4104 | Serge | 86 | static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) |
3031 | serge | 87 | { |
4104 | Serge | 88 | switch (type) { |
89 | case HDMI_INFOFRAME_TYPE_AVI: |
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3031 | serge | 90 | return VIDEO_DIP_ENABLE_AVI; |
4104 | Serge | 91 | case HDMI_INFOFRAME_TYPE_SPD: |
3031 | serge | 92 | return VIDEO_DIP_ENABLE_SPD; |
4104 | Serge | 93 | case HDMI_INFOFRAME_TYPE_VENDOR: |
94 | return VIDEO_DIP_ENABLE_VENDOR; |
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2330 | Serge | 95 | default: |
4104 | Serge | 96 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
3031 | serge | 97 | return 0; |
2330 | Serge | 98 | } |
3031 | serge | 99 | } |
2330 | Serge | 100 | |
4104 | Serge | 101 | static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) |
3031 | serge | 102 | { |
4104 | Serge | 103 | switch (type) { |
104 | case HDMI_INFOFRAME_TYPE_AVI: |
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3031 | serge | 105 | return VIDEO_DIP_ENABLE_AVI_HSW; |
4104 | Serge | 106 | case HDMI_INFOFRAME_TYPE_SPD: |
3031 | serge | 107 | return VIDEO_DIP_ENABLE_SPD_HSW; |
4104 | Serge | 108 | case HDMI_INFOFRAME_TYPE_VENDOR: |
109 | return VIDEO_DIP_ENABLE_VS_HSW; |
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3031 | serge | 110 | default: |
4104 | Serge | 111 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
3031 | serge | 112 | return 0; |
113 | } |
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2330 | Serge | 114 | } |
115 | |||
6084 | serge | 116 | static u32 hsw_dip_data_reg(struct drm_i915_private *dev_priv, |
117 | enum transcoder cpu_transcoder, |
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118 | enum hdmi_infoframe_type type, |
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119 | int i) |
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2330 | Serge | 120 | { |
4104 | Serge | 121 | switch (type) { |
122 | case HDMI_INFOFRAME_TYPE_AVI: |
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6084 | serge | 123 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); |
4104 | Serge | 124 | case HDMI_INFOFRAME_TYPE_SPD: |
6084 | serge | 125 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); |
4104 | Serge | 126 | case HDMI_INFOFRAME_TYPE_VENDOR: |
6084 | serge | 127 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); |
2330 | Serge | 128 | default: |
4104 | Serge | 129 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
3031 | serge | 130 | return 0; |
2330 | Serge | 131 | } |
132 | } |
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133 | |||
3031 | serge | 134 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
4104 | Serge | 135 | enum hdmi_infoframe_type type, |
4560 | Serge | 136 | const void *frame, ssize_t len) |
2330 | Serge | 137 | { |
4560 | Serge | 138 | const uint32_t *data = frame; |
2330 | Serge | 139 | struct drm_device *dev = encoder->dev; |
140 | struct drm_i915_private *dev_priv = dev->dev_private; |
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3031 | serge | 141 | u32 val = I915_READ(VIDEO_DIP_CTL); |
4104 | Serge | 142 | int i; |
2330 | Serge | 143 | |
3031 | serge | 144 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
2330 | Serge | 145 | |
3031 | serge | 146 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
4104 | Serge | 147 | val |= g4x_infoframe_index(type); |
2330 | Serge | 148 | |
4104 | Serge | 149 | val &= ~g4x_infoframe_enable(type); |
2330 | Serge | 150 | |
3031 | serge | 151 | I915_WRITE(VIDEO_DIP_CTL, val); |
2330 | Serge | 152 | |
3031 | serge | 153 | mmiowb(); |
2330 | Serge | 154 | for (i = 0; i < len; i += 4) { |
155 | I915_WRITE(VIDEO_DIP_DATA, *data); |
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156 | data++; |
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157 | } |
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3031 | serge | 158 | /* Write every possible data byte to force correct ECC calculation. */ |
159 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
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160 | I915_WRITE(VIDEO_DIP_DATA, 0); |
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161 | mmiowb(); |
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2330 | Serge | 162 | |
4104 | Serge | 163 | val |= g4x_infoframe_enable(type); |
3031 | serge | 164 | val &= ~VIDEO_DIP_FREQ_MASK; |
165 | val |= VIDEO_DIP_FREQ_VSYNC; |
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2330 | Serge | 166 | |
3031 | serge | 167 | I915_WRITE(VIDEO_DIP_CTL, val); |
168 | POSTING_READ(VIDEO_DIP_CTL); |
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2330 | Serge | 169 | } |
170 | |||
5354 | serge | 171 | static bool g4x_infoframe_enabled(struct drm_encoder *encoder) |
172 | { |
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173 | struct drm_device *dev = encoder->dev; |
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174 | struct drm_i915_private *dev_priv = dev->dev_private; |
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175 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
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176 | u32 val = I915_READ(VIDEO_DIP_CTL); |
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177 | |||
6084 | serge | 178 | if ((val & VIDEO_DIP_ENABLE) == 0) |
179 | return false; |
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5354 | serge | 180 | |
6084 | serge | 181 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) |
182 | return false; |
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183 | |||
184 | return val & (VIDEO_DIP_ENABLE_AVI | |
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185 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); |
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5354 | serge | 186 | } |
187 | |||
3031 | serge | 188 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
4104 | Serge | 189 | enum hdmi_infoframe_type type, |
4560 | Serge | 190 | const void *frame, ssize_t len) |
2330 | Serge | 191 | { |
4560 | Serge | 192 | const uint32_t *data = frame; |
2330 | Serge | 193 | struct drm_device *dev = encoder->dev; |
194 | struct drm_i915_private *dev_priv = dev->dev_private; |
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3031 | serge | 195 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
4104 | Serge | 196 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
3031 | serge | 197 | u32 val = I915_READ(reg); |
2330 | Serge | 198 | |
3031 | serge | 199 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
2330 | Serge | 200 | |
3031 | serge | 201 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
4104 | Serge | 202 | val |= g4x_infoframe_index(type); |
2330 | Serge | 203 | |
4104 | Serge | 204 | val &= ~g4x_infoframe_enable(type); |
3031 | serge | 205 | |
206 | I915_WRITE(reg, val); |
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207 | |||
208 | mmiowb(); |
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209 | for (i = 0; i < len; i += 4) { |
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210 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
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211 | data++; |
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212 | } |
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213 | /* Write every possible data byte to force correct ECC calculation. */ |
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214 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
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215 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); |
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216 | mmiowb(); |
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217 | |||
4104 | Serge | 218 | val |= g4x_infoframe_enable(type); |
3031 | serge | 219 | val &= ~VIDEO_DIP_FREQ_MASK; |
220 | val |= VIDEO_DIP_FREQ_VSYNC; |
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221 | |||
222 | I915_WRITE(reg, val); |
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223 | POSTING_READ(reg); |
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224 | } |
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225 | |||
5354 | serge | 226 | static bool ibx_infoframe_enabled(struct drm_encoder *encoder) |
227 | { |
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228 | struct drm_device *dev = encoder->dev; |
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229 | struct drm_i915_private *dev_priv = dev->dev_private; |
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230 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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6084 | serge | 231 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
5354 | serge | 232 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
233 | u32 val = I915_READ(reg); |
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234 | |||
6084 | serge | 235 | if ((val & VIDEO_DIP_ENABLE) == 0) |
236 | return false; |
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237 | |||
238 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) |
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239 | return false; |
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240 | |||
241 | return val & (VIDEO_DIP_ENABLE_AVI | |
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242 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
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243 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
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5354 | serge | 244 | } |
245 | |||
3031 | serge | 246 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
4104 | Serge | 247 | enum hdmi_infoframe_type type, |
4560 | Serge | 248 | const void *frame, ssize_t len) |
3031 | serge | 249 | { |
4560 | Serge | 250 | const uint32_t *data = frame; |
3031 | serge | 251 | struct drm_device *dev = encoder->dev; |
252 | struct drm_i915_private *dev_priv = dev->dev_private; |
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253 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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4104 | Serge | 254 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
3031 | serge | 255 | u32 val = I915_READ(reg); |
256 | |||
257 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
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258 | |||
2342 | Serge | 259 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
4104 | Serge | 260 | val |= g4x_infoframe_index(type); |
2330 | Serge | 261 | |
3031 | serge | 262 | /* The DIP control register spec says that we need to update the AVI |
263 | * infoframe without clearing its enable bit */ |
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4104 | Serge | 264 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
265 | val &= ~g4x_infoframe_enable(type); |
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2330 | Serge | 266 | |
3031 | serge | 267 | I915_WRITE(reg, val); |
268 | |||
269 | mmiowb(); |
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2330 | Serge | 270 | for (i = 0; i < len; i += 4) { |
271 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
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272 | data++; |
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273 | } |
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3031 | serge | 274 | /* Write every possible data byte to force correct ECC calculation. */ |
275 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
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276 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); |
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277 | mmiowb(); |
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2330 | Serge | 278 | |
4104 | Serge | 279 | val |= g4x_infoframe_enable(type); |
3031 | serge | 280 | val &= ~VIDEO_DIP_FREQ_MASK; |
281 | val |= VIDEO_DIP_FREQ_VSYNC; |
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2330 | Serge | 282 | |
3031 | serge | 283 | I915_WRITE(reg, val); |
284 | POSTING_READ(reg); |
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2330 | Serge | 285 | } |
3031 | serge | 286 | |
5354 | serge | 287 | static bool cpt_infoframe_enabled(struct drm_encoder *encoder) |
288 | { |
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289 | struct drm_device *dev = encoder->dev; |
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290 | struct drm_i915_private *dev_priv = dev->dev_private; |
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291 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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292 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
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293 | u32 val = I915_READ(reg); |
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294 | |||
6084 | serge | 295 | if ((val & VIDEO_DIP_ENABLE) == 0) |
296 | return false; |
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297 | |||
298 | return val & (VIDEO_DIP_ENABLE_AVI | |
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299 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
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300 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
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5354 | serge | 301 | } |
302 | |||
3031 | serge | 303 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
4104 | Serge | 304 | enum hdmi_infoframe_type type, |
4560 | Serge | 305 | const void *frame, ssize_t len) |
3031 | serge | 306 | { |
4560 | Serge | 307 | const uint32_t *data = frame; |
3031 | serge | 308 | struct drm_device *dev = encoder->dev; |
309 | struct drm_i915_private *dev_priv = dev->dev_private; |
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310 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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4104 | Serge | 311 | int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
3031 | serge | 312 | u32 val = I915_READ(reg); |
313 | |||
314 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
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315 | |||
316 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
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4104 | Serge | 317 | val |= g4x_infoframe_index(type); |
3031 | serge | 318 | |
4104 | Serge | 319 | val &= ~g4x_infoframe_enable(type); |
3031 | serge | 320 | |
321 | I915_WRITE(reg, val); |
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322 | |||
323 | mmiowb(); |
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324 | for (i = 0; i < len; i += 4) { |
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325 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
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326 | data++; |
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327 | } |
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328 | /* Write every possible data byte to force correct ECC calculation. */ |
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329 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
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330 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); |
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331 | mmiowb(); |
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332 | |||
4104 | Serge | 333 | val |= g4x_infoframe_enable(type); |
3031 | serge | 334 | val &= ~VIDEO_DIP_FREQ_MASK; |
335 | val |= VIDEO_DIP_FREQ_VSYNC; |
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336 | |||
337 | I915_WRITE(reg, val); |
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338 | POSTING_READ(reg); |
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339 | } |
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340 | |||
5354 | serge | 341 | static bool vlv_infoframe_enabled(struct drm_encoder *encoder) |
342 | { |
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343 | struct drm_device *dev = encoder->dev; |
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344 | struct drm_i915_private *dev_priv = dev->dev_private; |
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345 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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6084 | serge | 346 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
5354 | serge | 347 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
348 | u32 val = I915_READ(reg); |
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349 | |||
6084 | serge | 350 | if ((val & VIDEO_DIP_ENABLE) == 0) |
351 | return false; |
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352 | |||
353 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) |
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354 | return false; |
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355 | |||
356 | return val & (VIDEO_DIP_ENABLE_AVI | |
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357 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
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358 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
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5354 | serge | 359 | } |
360 | |||
3031 | serge | 361 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
4104 | Serge | 362 | enum hdmi_infoframe_type type, |
4560 | Serge | 363 | const void *frame, ssize_t len) |
3031 | serge | 364 | { |
4560 | Serge | 365 | const uint32_t *data = frame; |
3031 | serge | 366 | struct drm_device *dev = encoder->dev; |
367 | struct drm_i915_private *dev_priv = dev->dev_private; |
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368 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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6084 | serge | 369 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
370 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); |
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4104 | Serge | 371 | u32 data_reg; |
372 | int i; |
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3031 | serge | 373 | u32 val = I915_READ(ctl_reg); |
374 | |||
6084 | serge | 375 | data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0); |
3031 | serge | 376 | if (data_reg == 0) |
377 | return; |
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378 | |||
4104 | Serge | 379 | val &= ~hsw_infoframe_enable(type); |
3031 | serge | 380 | I915_WRITE(ctl_reg, val); |
381 | |||
382 | mmiowb(); |
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383 | for (i = 0; i < len; i += 4) { |
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6084 | serge | 384 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
385 | type, i >> 2), *data); |
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3031 | serge | 386 | data++; |
387 | } |
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388 | /* Write every possible data byte to force correct ECC calculation. */ |
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389 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
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6084 | serge | 390 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
391 | type, i >> 2), 0); |
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3031 | serge | 392 | mmiowb(); |
393 | |||
4104 | Serge | 394 | val |= hsw_infoframe_enable(type); |
3031 | serge | 395 | I915_WRITE(ctl_reg, val); |
396 | POSTING_READ(ctl_reg); |
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397 | } |
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398 | |||
5354 | serge | 399 | static bool hsw_infoframe_enabled(struct drm_encoder *encoder) |
400 | { |
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401 | struct drm_device *dev = encoder->dev; |
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402 | struct drm_i915_private *dev_priv = dev->dev_private; |
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403 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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6084 | serge | 404 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
5354 | serge | 405 | u32 val = I915_READ(ctl_reg); |
406 | |||
6084 | serge | 407 | return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
408 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | |
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409 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); |
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5354 | serge | 410 | } |
411 | |||
4104 | Serge | 412 | /* |
413 | * The data we write to the DIP data buffer registers is 1 byte bigger than the |
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414 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting |
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415 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be |
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416 | * used for both technologies. |
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417 | * |
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418 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 |
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419 | * DW1: DB3 | DB2 | DB1 | DB0 |
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420 | * DW2: DB7 | DB6 | DB5 | DB4 |
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421 | * DW3: ... |
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422 | * |
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423 | * (HB is Header Byte, DB is Data Byte) |
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424 | * |
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425 | * The hdmi pack() functions don't know about that hardware specific hole so we |
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426 | * trick them by giving an offset into the buffer and moving back the header |
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427 | * bytes by one. |
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428 | */ |
||
429 | static void intel_write_infoframe(struct drm_encoder *encoder, |
||
430 | union hdmi_infoframe *frame) |
||
2330 | Serge | 431 | { |
432 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
||
4104 | Serge | 433 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
434 | ssize_t len; |
||
2330 | Serge | 435 | |
4104 | Serge | 436 | /* see comment above for the reason for this offset */ |
437 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); |
||
438 | if (len < 0) |
||
439 | return; |
||
440 | |||
441 | /* Insert the 'hole' (see big comment above) at position 3 */ |
||
442 | buffer[0] = buffer[1]; |
||
443 | buffer[1] = buffer[2]; |
||
444 | buffer[2] = buffer[3]; |
||
445 | buffer[3] = 0; |
||
446 | len++; |
||
447 | |||
448 | intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); |
||
2330 | Serge | 449 | } |
450 | |||
3031 | serge | 451 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
6084 | serge | 452 | const struct drm_display_mode *adjusted_mode) |
2330 | Serge | 453 | { |
3480 | Serge | 454 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
3746 | Serge | 455 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
4104 | Serge | 456 | union hdmi_infoframe frame; |
457 | int ret; |
||
2330 | Serge | 458 | |
4104 | Serge | 459 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
460 | adjusted_mode); |
||
461 | if (ret < 0) { |
||
462 | DRM_ERROR("couldn't fill AVI infoframe\n"); |
||
463 | return; |
||
464 | } |
||
3031 | serge | 465 | |
3480 | Serge | 466 | if (intel_hdmi->rgb_quant_range_selectable) { |
6084 | serge | 467 | if (intel_crtc->config->limited_color_range) |
4104 | Serge | 468 | frame.avi.quantization_range = |
469 | HDMI_QUANTIZATION_RANGE_LIMITED; |
||
3480 | Serge | 470 | else |
4104 | Serge | 471 | frame.avi.quantization_range = |
472 | HDMI_QUANTIZATION_RANGE_FULL; |
||
3480 | Serge | 473 | } |
3243 | Serge | 474 | |
4104 | Serge | 475 | intel_write_infoframe(encoder, &frame); |
2330 | Serge | 476 | } |
477 | |||
478 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
||
479 | { |
||
4104 | Serge | 480 | union hdmi_infoframe frame; |
481 | int ret; |
||
2330 | Serge | 482 | |
4104 | Serge | 483 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); |
484 | if (ret < 0) { |
||
485 | DRM_ERROR("couldn't fill SPD infoframe\n"); |
||
486 | return; |
||
487 | } |
||
2330 | Serge | 488 | |
4104 | Serge | 489 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
490 | |||
491 | intel_write_infoframe(encoder, &frame); |
||
2330 | Serge | 492 | } |
493 | |||
4104 | Serge | 494 | static void |
495 | intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, |
||
6084 | serge | 496 | const struct drm_display_mode *adjusted_mode) |
4104 | Serge | 497 | { |
498 | union hdmi_infoframe frame; |
||
499 | int ret; |
||
500 | |||
501 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, |
||
502 | adjusted_mode); |
||
503 | if (ret < 0) |
||
504 | return; |
||
505 | |||
506 | intel_write_infoframe(encoder, &frame); |
||
507 | } |
||
508 | |||
3031 | serge | 509 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
5060 | serge | 510 | bool enable, |
6084 | serge | 511 | const struct drm_display_mode *adjusted_mode) |
3031 | serge | 512 | { |
513 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
||
3480 | Serge | 514 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
515 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
||
3031 | serge | 516 | u32 reg = VIDEO_DIP_CTL; |
517 | u32 val = I915_READ(reg); |
||
5060 | serge | 518 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
3031 | serge | 519 | |
520 | assert_hdmi_port_disabled(intel_hdmi); |
||
521 | |||
522 | /* If the registers were not initialized yet, they might be zeroes, |
||
523 | * which means we're selecting the AVI DIP and we're setting its |
||
524 | * frequency to once. This seems to really confuse the HW and make |
||
525 | * things stop working (the register spec says the AVI always needs to |
||
526 | * be sent every VSync). So here we avoid writing to the register more |
||
527 | * than we need and also explicitly select the AVI DIP and explicitly |
||
528 | * set its frequency to every VSync. Avoiding to write it twice seems to |
||
529 | * be enough to solve the problem, but being defensive shouldn't hurt us |
||
530 | * either. */ |
||
531 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
||
532 | |||
5060 | serge | 533 | if (!enable) { |
3031 | serge | 534 | if (!(val & VIDEO_DIP_ENABLE)) |
535 | return; |
||
6084 | serge | 536 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
537 | DRM_DEBUG_KMS("video DIP still enabled on port %c\n", |
||
538 | (val & VIDEO_DIP_PORT_MASK) >> 29); |
||
539 | return; |
||
540 | } |
||
541 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
||
542 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); |
||
3031 | serge | 543 | I915_WRITE(reg, val); |
544 | POSTING_READ(reg); |
||
545 | return; |
||
546 | } |
||
547 | |||
548 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
||
549 | if (val & VIDEO_DIP_ENABLE) { |
||
6084 | serge | 550 | DRM_DEBUG_KMS("video DIP already enabled on port %c\n", |
551 | (val & VIDEO_DIP_PORT_MASK) >> 29); |
||
552 | return; |
||
3031 | serge | 553 | } |
554 | val &= ~VIDEO_DIP_PORT_MASK; |
||
555 | val |= port; |
||
556 | } |
||
557 | |||
558 | val |= VIDEO_DIP_ENABLE; |
||
6084 | serge | 559 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
560 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); |
||
3031 | serge | 561 | |
562 | I915_WRITE(reg, val); |
||
563 | POSTING_READ(reg); |
||
564 | |||
565 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
||
566 | intel_hdmi_set_spd_infoframe(encoder); |
||
4104 | Serge | 567 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
3031 | serge | 568 | } |
569 | |||
6084 | serge | 570 | static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder) |
571 | { |
||
572 | struct drm_device *dev = encoder->dev; |
||
573 | struct drm_connector *connector; |
||
574 | |||
575 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
||
576 | |||
577 | /* |
||
578 | * HDMI cloning is only supported on g4x which doesn't |
||
579 | * support deep color or GCP infoframes anyway so no |
||
580 | * need to worry about multiple HDMI sinks here. |
||
581 | */ |
||
582 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) |
||
583 | if (connector->encoder == encoder) |
||
584 | return connector->display_info.bpc > 8; |
||
585 | |||
586 | return false; |
||
587 | } |
||
588 | |||
589 | /* |
||
590 | * Determine if default_phase=1 can be indicated in the GCP infoframe. |
||
591 | * |
||
592 | * From HDMI specification 1.4a: |
||
593 | * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 |
||
594 | * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 |
||
595 | * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase |
||
596 | * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing |
||
597 | * phase of 0 |
||
598 | */ |
||
599 | static bool gcp_default_phase_possible(int pipe_bpp, |
||
600 | const struct drm_display_mode *mode) |
||
601 | { |
||
602 | unsigned int pixels_per_group; |
||
603 | |||
604 | switch (pipe_bpp) { |
||
605 | case 30: |
||
606 | /* 4 pixels in 5 clocks */ |
||
607 | pixels_per_group = 4; |
||
608 | break; |
||
609 | case 36: |
||
610 | /* 2 pixels in 3 clocks */ |
||
611 | pixels_per_group = 2; |
||
612 | break; |
||
613 | case 48: |
||
614 | /* 1 pixel in 2 clocks */ |
||
615 | pixels_per_group = 1; |
||
616 | break; |
||
617 | default: |
||
618 | /* phase information not relevant for 8bpc */ |
||
619 | return false; |
||
620 | } |
||
621 | |||
622 | return mode->crtc_hdisplay % pixels_per_group == 0 && |
||
623 | mode->crtc_htotal % pixels_per_group == 0 && |
||
624 | mode->crtc_hblank_start % pixels_per_group == 0 && |
||
625 | mode->crtc_hblank_end % pixels_per_group == 0 && |
||
626 | mode->crtc_hsync_start % pixels_per_group == 0 && |
||
627 | mode->crtc_hsync_end % pixels_per_group == 0 && |
||
628 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || |
||
629 | mode->crtc_htotal/2 % pixels_per_group == 0); |
||
630 | } |
||
631 | |||
632 | static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder) |
||
633 | { |
||
634 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
||
635 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
||
636 | u32 reg, val = 0; |
||
637 | |||
638 | if (HAS_DDI(dev_priv)) |
||
639 | reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder); |
||
640 | else if (IS_VALLEYVIEW(dev_priv)) |
||
641 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); |
||
642 | else if (HAS_PCH_SPLIT(dev_priv->dev)) |
||
643 | reg = TVIDEO_DIP_GCP(crtc->pipe); |
||
644 | else |
||
645 | return false; |
||
646 | |||
647 | /* Indicate color depth whenever the sink supports deep color */ |
||
648 | if (hdmi_sink_is_deep_color(encoder)) |
||
649 | val |= GCP_COLOR_INDICATION; |
||
650 | |||
651 | /* Enable default_phase whenever the display mode is suitably aligned */ |
||
652 | if (gcp_default_phase_possible(crtc->config->pipe_bpp, |
||
653 | &crtc->config->base.adjusted_mode)) |
||
654 | val |= GCP_DEFAULT_PHASE_ENABLE; |
||
655 | |||
656 | I915_WRITE(reg, val); |
||
657 | |||
658 | return val != 0; |
||
659 | } |
||
660 | |||
3031 | serge | 661 | static void ibx_set_infoframes(struct drm_encoder *encoder, |
5060 | serge | 662 | bool enable, |
6084 | serge | 663 | const struct drm_display_mode *adjusted_mode) |
3031 | serge | 664 | { |
665 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
||
666 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
||
3480 | Serge | 667 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
668 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
||
3031 | serge | 669 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
670 | u32 val = I915_READ(reg); |
||
5060 | serge | 671 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
3031 | serge | 672 | |
673 | assert_hdmi_port_disabled(intel_hdmi); |
||
674 | |||
675 | /* See the big comment in g4x_set_infoframes() */ |
||
676 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
||
677 | |||
5060 | serge | 678 | if (!enable) { |
3031 | serge | 679 | if (!(val & VIDEO_DIP_ENABLE)) |
680 | return; |
||
6084 | serge | 681 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
682 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
||
683 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
||
3031 | serge | 684 | I915_WRITE(reg, val); |
685 | POSTING_READ(reg); |
||
686 | return; |
||
687 | } |
||
688 | |||
689 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
||
6084 | serge | 690 | WARN(val & VIDEO_DIP_ENABLE, |
691 | "DIP already enabled on port %c\n", |
||
692 | (val & VIDEO_DIP_PORT_MASK) >> 29); |
||
3031 | serge | 693 | val &= ~VIDEO_DIP_PORT_MASK; |
694 | val |= port; |
||
695 | } |
||
696 | |||
697 | val |= VIDEO_DIP_ENABLE; |
||
6084 | serge | 698 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
699 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
||
700 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
||
3031 | serge | 701 | |
6084 | serge | 702 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
703 | val |= VIDEO_DIP_ENABLE_GCP; |
||
704 | |||
3031 | serge | 705 | I915_WRITE(reg, val); |
706 | POSTING_READ(reg); |
||
707 | |||
708 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
||
709 | intel_hdmi_set_spd_infoframe(encoder); |
||
4104 | Serge | 710 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
3031 | serge | 711 | } |
712 | |||
713 | static void cpt_set_infoframes(struct drm_encoder *encoder, |
||
5060 | serge | 714 | bool enable, |
6084 | serge | 715 | const struct drm_display_mode *adjusted_mode) |
3031 | serge | 716 | { |
717 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
||
718 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
||
719 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
||
720 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
||
721 | u32 val = I915_READ(reg); |
||
722 | |||
723 | assert_hdmi_port_disabled(intel_hdmi); |
||
724 | |||
725 | /* See the big comment in g4x_set_infoframes() */ |
||
726 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
||
727 | |||
5060 | serge | 728 | if (!enable) { |
3031 | serge | 729 | if (!(val & VIDEO_DIP_ENABLE)) |
730 | return; |
||
6084 | serge | 731 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
732 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
||
733 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
||
3031 | serge | 734 | I915_WRITE(reg, val); |
735 | POSTING_READ(reg); |
||
736 | return; |
||
737 | } |
||
738 | |||
739 | /* Set both together, unset both together: see the spec. */ |
||
740 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; |
||
741 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
||
6084 | serge | 742 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
3031 | serge | 743 | |
6084 | serge | 744 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
745 | val |= VIDEO_DIP_ENABLE_GCP; |
||
746 | |||
3031 | serge | 747 | I915_WRITE(reg, val); |
748 | POSTING_READ(reg); |
||
749 | |||
750 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
||
751 | intel_hdmi_set_spd_infoframe(encoder); |
||
4104 | Serge | 752 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
3031 | serge | 753 | } |
754 | |||
755 | static void vlv_set_infoframes(struct drm_encoder *encoder, |
||
5060 | serge | 756 | bool enable, |
6084 | serge | 757 | const struct drm_display_mode *adjusted_mode) |
3031 | serge | 758 | { |
759 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
||
5060 | serge | 760 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
3031 | serge | 761 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
762 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
||
763 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
||
764 | u32 val = I915_READ(reg); |
||
5060 | serge | 765 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
3031 | serge | 766 | |
767 | assert_hdmi_port_disabled(intel_hdmi); |
||
768 | |||
769 | /* See the big comment in g4x_set_infoframes() */ |
||
770 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
||
771 | |||
5060 | serge | 772 | if (!enable) { |
3031 | serge | 773 | if (!(val & VIDEO_DIP_ENABLE)) |
774 | return; |
||
6084 | serge | 775 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
776 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
||
777 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
||
3031 | serge | 778 | I915_WRITE(reg, val); |
779 | POSTING_READ(reg); |
||
780 | return; |
||
781 | } |
||
782 | |||
5060 | serge | 783 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
6084 | serge | 784 | WARN(val & VIDEO_DIP_ENABLE, |
785 | "DIP already enabled on port %c\n", |
||
786 | (val & VIDEO_DIP_PORT_MASK) >> 29); |
||
5060 | serge | 787 | val &= ~VIDEO_DIP_PORT_MASK; |
788 | val |= port; |
||
789 | } |
||
790 | |||
3031 | serge | 791 | val |= VIDEO_DIP_ENABLE; |
6084 | serge | 792 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
793 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
||
794 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
||
3031 | serge | 795 | |
6084 | serge | 796 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
797 | val |= VIDEO_DIP_ENABLE_GCP; |
||
798 | |||
3031 | serge | 799 | I915_WRITE(reg, val); |
800 | POSTING_READ(reg); |
||
801 | |||
802 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
||
803 | intel_hdmi_set_spd_infoframe(encoder); |
||
4104 | Serge | 804 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
3031 | serge | 805 | } |
806 | |||
807 | static void hsw_set_infoframes(struct drm_encoder *encoder, |
||
5060 | serge | 808 | bool enable, |
6084 | serge | 809 | const struct drm_display_mode *adjusted_mode) |
3031 | serge | 810 | { |
811 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
||
812 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
||
813 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
||
6084 | serge | 814 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
3031 | serge | 815 | u32 val = I915_READ(reg); |
816 | |||
817 | assert_hdmi_port_disabled(intel_hdmi); |
||
818 | |||
6084 | serge | 819 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
820 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | |
||
821 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); |
||
822 | |||
5060 | serge | 823 | if (!enable) { |
6084 | serge | 824 | I915_WRITE(reg, val); |
3031 | serge | 825 | POSTING_READ(reg); |
826 | return; |
||
827 | } |
||
828 | |||
6084 | serge | 829 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
830 | val |= VIDEO_DIP_ENABLE_GCP_HSW; |
||
3031 | serge | 831 | |
832 | I915_WRITE(reg, val); |
||
833 | POSTING_READ(reg); |
||
834 | |||
835 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
||
836 | intel_hdmi_set_spd_infoframe(encoder); |
||
4104 | Serge | 837 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
3031 | serge | 838 | } |
839 | |||
5060 | serge | 840 | static void intel_hdmi_prepare(struct intel_encoder *encoder) |
2330 | Serge | 841 | { |
4104 | Serge | 842 | struct drm_device *dev = encoder->base.dev; |
2330 | Serge | 843 | struct drm_i915_private *dev_priv = dev->dev_private; |
4104 | Serge | 844 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
845 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
||
6084 | serge | 846 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
3746 | Serge | 847 | u32 hdmi_val; |
2330 | Serge | 848 | |
3746 | Serge | 849 | hdmi_val = SDVO_ENCODING_HDMI; |
6084 | serge | 850 | if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) |
851 | hdmi_val |= HDMI_COLOR_RANGE_16_235; |
||
2330 | Serge | 852 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
3746 | Serge | 853 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
2330 | Serge | 854 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
3746 | Serge | 855 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
2330 | Serge | 856 | |
6084 | serge | 857 | if (crtc->config->pipe_bpp > 24) |
3746 | Serge | 858 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
2330 | Serge | 859 | else |
3746 | Serge | 860 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
2330 | Serge | 861 | |
6084 | serge | 862 | if (crtc->config->has_hdmi_sink) |
3746 | Serge | 863 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2330 | Serge | 864 | |
6084 | serge | 865 | if (HAS_PCH_CPT(dev)) |
4104 | Serge | 866 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
5060 | serge | 867 | else if (IS_CHERRYVIEW(dev)) |
868 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); |
||
3746 | Serge | 869 | else |
4104 | Serge | 870 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
2330 | Serge | 871 | |
3746 | Serge | 872 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
873 | POSTING_READ(intel_hdmi->hdmi_reg); |
||
2330 | Serge | 874 | } |
875 | |||
3031 | serge | 876 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
877 | enum pipe *pipe) |
||
2330 | Serge | 878 | { |
3031 | serge | 879 | struct drm_device *dev = encoder->base.dev; |
2330 | Serge | 880 | struct drm_i915_private *dev_priv = dev->dev_private; |
3031 | serge | 881 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
5060 | serge | 882 | enum intel_display_power_domain power_domain; |
3031 | serge | 883 | u32 tmp; |
884 | |||
5060 | serge | 885 | power_domain = intel_display_port_power_domain(encoder); |
5354 | serge | 886 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
5060 | serge | 887 | return false; |
888 | |||
3746 | Serge | 889 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
3031 | serge | 890 | |
891 | if (!(tmp & SDVO_ENABLE)) |
||
892 | return false; |
||
893 | |||
894 | if (HAS_PCH_CPT(dev)) |
||
895 | *pipe = PORT_TO_PIPE_CPT(tmp); |
||
5060 | serge | 896 | else if (IS_CHERRYVIEW(dev)) |
897 | *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); |
||
3031 | serge | 898 | else |
899 | *pipe = PORT_TO_PIPE(tmp); |
||
900 | |||
901 | return true; |
||
902 | } |
||
903 | |||
4104 | Serge | 904 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
6084 | serge | 905 | struct intel_crtc_state *pipe_config) |
4104 | Serge | 906 | { |
907 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
||
5139 | serge | 908 | struct drm_device *dev = encoder->base.dev; |
909 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4104 | Serge | 910 | u32 tmp, flags = 0; |
4560 | Serge | 911 | int dotclock; |
4104 | Serge | 912 | |
913 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
||
914 | |||
915 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) |
||
916 | flags |= DRM_MODE_FLAG_PHSYNC; |
||
917 | else |
||
918 | flags |= DRM_MODE_FLAG_NHSYNC; |
||
919 | |||
920 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) |
||
921 | flags |= DRM_MODE_FLAG_PVSYNC; |
||
922 | else |
||
923 | flags |= DRM_MODE_FLAG_NVSYNC; |
||
924 | |||
5060 | serge | 925 | if (tmp & HDMI_MODE_SELECT_HDMI) |
926 | pipe_config->has_hdmi_sink = true; |
||
927 | |||
5354 | serge | 928 | if (intel_hdmi->infoframe_enabled(&encoder->base)) |
929 | pipe_config->has_infoframe = true; |
||
930 | |||
931 | if (tmp & SDVO_AUDIO_ENABLE) |
||
5060 | serge | 932 | pipe_config->has_audio = true; |
933 | |||
5139 | serge | 934 | if (!HAS_PCH_SPLIT(dev) && |
935 | tmp & HDMI_COLOR_RANGE_16_235) |
||
936 | pipe_config->limited_color_range = true; |
||
937 | |||
6084 | serge | 938 | pipe_config->base.adjusted_mode.flags |= flags; |
4560 | Serge | 939 | |
940 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) |
||
941 | dotclock = pipe_config->port_clock * 2 / 3; |
||
942 | else |
||
943 | dotclock = pipe_config->port_clock; |
||
944 | |||
6084 | serge | 945 | if (pipe_config->pixel_multiplier) |
946 | dotclock /= pipe_config->pixel_multiplier; |
||
947 | |||
4560 | Serge | 948 | if (HAS_PCH_SPLIT(dev_priv->dev)) |
949 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
||
950 | |||
6084 | serge | 951 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
4104 | Serge | 952 | } |
953 | |||
6084 | serge | 954 | static void intel_enable_hdmi_audio(struct intel_encoder *encoder) |
3031 | serge | 955 | { |
6084 | serge | 956 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
957 | |||
958 | WARN_ON(!crtc->config->has_hdmi_sink); |
||
959 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
||
960 | pipe_name(crtc->pipe)); |
||
961 | intel_audio_codec_enable(encoder); |
||
962 | } |
||
963 | |||
964 | static void g4x_enable_hdmi(struct intel_encoder *encoder) |
||
965 | { |
||
3031 | serge | 966 | struct drm_device *dev = encoder->base.dev; |
967 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
6084 | serge | 968 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
3031 | serge | 969 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
2330 | Serge | 970 | u32 temp; |
971 | |||
6084 | serge | 972 | temp = I915_READ(intel_hdmi->hdmi_reg); |
2342 | Serge | 973 | |
6084 | serge | 974 | temp |= SDVO_ENABLE; |
975 | if (crtc->config->has_audio) |
||
976 | temp |= SDVO_AUDIO_ENABLE; |
||
977 | |||
978 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
||
979 | POSTING_READ(intel_hdmi->hdmi_reg); |
||
980 | |||
981 | if (crtc->config->has_audio) |
||
982 | intel_enable_hdmi_audio(encoder); |
||
983 | } |
||
984 | |||
985 | static void ibx_enable_hdmi(struct intel_encoder *encoder) |
||
986 | { |
||
987 | struct drm_device *dev = encoder->base.dev; |
||
988 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
989 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
||
990 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
||
991 | u32 temp; |
||
992 | |||
3746 | Serge | 993 | temp = I915_READ(intel_hdmi->hdmi_reg); |
2330 | Serge | 994 | |
6084 | serge | 995 | temp |= SDVO_ENABLE; |
996 | if (crtc->config->has_audio) |
||
997 | temp |= SDVO_AUDIO_ENABLE; |
||
3031 | serge | 998 | |
6084 | serge | 999 | /* |
1000 | * HW workaround, need to write this twice for issue |
||
1001 | * that may result in first write getting masked. |
||
2330 | Serge | 1002 | */ |
6084 | serge | 1003 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1004 | POSTING_READ(intel_hdmi->hdmi_reg); |
||
1005 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
||
1006 | POSTING_READ(intel_hdmi->hdmi_reg); |
||
1007 | |||
1008 | /* |
||
1009 | * HW workaround, need to toggle enable bit off and on |
||
1010 | * for 12bpc with pixel repeat. |
||
1011 | * |
||
1012 | * FIXME: BSpec says this should be done at the end of |
||
1013 | * of the modeset sequence, so not sure if this isn't too soon. |
||
1014 | */ |
||
1015 | if (crtc->config->pipe_bpp > 24 && |
||
1016 | crtc->config->pixel_multiplier > 1) { |
||
3746 | Serge | 1017 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
1018 | POSTING_READ(intel_hdmi->hdmi_reg); |
||
6084 | serge | 1019 | |
1020 | /* |
||
1021 | * HW workaround, need to write this twice for issue |
||
1022 | * that may result in first write getting masked. |
||
1023 | */ |
||
1024 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
||
1025 | POSTING_READ(intel_hdmi->hdmi_reg); |
||
1026 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
||
1027 | POSTING_READ(intel_hdmi->hdmi_reg); |
||
2330 | Serge | 1028 | } |
1029 | |||
6084 | serge | 1030 | if (crtc->config->has_audio) |
1031 | intel_enable_hdmi_audio(encoder); |
||
1032 | } |
||
3031 | serge | 1033 | |
6084 | serge | 1034 | static void cpt_enable_hdmi(struct intel_encoder *encoder) |
1035 | { |
||
1036 | struct drm_device *dev = encoder->base.dev; |
||
1037 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1038 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
||
1039 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
||
1040 | enum pipe pipe = crtc->pipe; |
||
1041 | u32 temp; |
||
1042 | |||
1043 | temp = I915_READ(intel_hdmi->hdmi_reg); |
||
1044 | |||
1045 | temp |= SDVO_ENABLE; |
||
1046 | if (crtc->config->has_audio) |
||
1047 | temp |= SDVO_AUDIO_ENABLE; |
||
1048 | |||
1049 | /* |
||
1050 | * WaEnableHDMI8bpcBefore12bpc:snb,ivb |
||
1051 | * |
||
1052 | * The procedure for 12bpc is as follows: |
||
1053 | * 1. disable HDMI clock gating |
||
1054 | * 2. enable HDMI with 8bpc |
||
1055 | * 3. enable HDMI with 12bpc |
||
1056 | * 4. enable HDMI clock gating |
||
1057 | */ |
||
1058 | |||
1059 | if (crtc->config->pipe_bpp > 24) { |
||
1060 | I915_WRITE(TRANS_CHICKEN1(pipe), |
||
1061 | I915_READ(TRANS_CHICKEN1(pipe)) | |
||
1062 | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); |
||
1063 | |||
1064 | temp &= ~SDVO_COLOR_FORMAT_MASK; |
||
1065 | temp |= SDVO_COLOR_FORMAT_8bpc; |
||
1066 | } |
||
1067 | |||
3746 | Serge | 1068 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1069 | POSTING_READ(intel_hdmi->hdmi_reg); |
||
3031 | serge | 1070 | |
6084 | serge | 1071 | if (crtc->config->pipe_bpp > 24) { |
1072 | temp &= ~SDVO_COLOR_FORMAT_MASK; |
||
1073 | temp |= HDMI_COLOR_FORMAT_12bpc; |
||
1074 | |||
3746 | Serge | 1075 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1076 | POSTING_READ(intel_hdmi->hdmi_reg); |
||
6084 | serge | 1077 | |
1078 | I915_WRITE(TRANS_CHICKEN1(pipe), |
||
1079 | I915_READ(TRANS_CHICKEN1(pipe)) & |
||
1080 | ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); |
||
2330 | Serge | 1081 | } |
5354 | serge | 1082 | |
6084 | serge | 1083 | if (crtc->config->has_audio) |
1084 | intel_enable_hdmi_audio(encoder); |
||
3031 | serge | 1085 | } |
2330 | Serge | 1086 | |
4104 | Serge | 1087 | static void vlv_enable_hdmi(struct intel_encoder *encoder) |
1088 | { |
||
1089 | } |
||
1090 | |||
3031 | serge | 1091 | static void intel_disable_hdmi(struct intel_encoder *encoder) |
1092 | { |
||
1093 | struct drm_device *dev = encoder->base.dev; |
||
1094 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1095 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
||
5354 | serge | 1096 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
3031 | serge | 1097 | u32 temp; |
1098 | |||
3746 | Serge | 1099 | temp = I915_READ(intel_hdmi->hdmi_reg); |
3031 | serge | 1100 | |
6084 | serge | 1101 | temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); |
3746 | Serge | 1102 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1103 | POSTING_READ(intel_hdmi->hdmi_reg); |
||
2330 | Serge | 1104 | |
6084 | serge | 1105 | /* |
1106 | * HW workaround for IBX, we need to move the port |
||
1107 | * to transcoder A after disabling it to allow the |
||
1108 | * matching DP port to be enabled on transcoder A. |
||
2330 | Serge | 1109 | */ |
6084 | serge | 1110 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) { |
1111 | temp &= ~SDVO_PIPE_B_SELECT; |
||
1112 | temp |= SDVO_ENABLE; |
||
1113 | /* |
||
1114 | * HW workaround, need to write this twice for issue |
||
1115 | * that may result in first write getting masked. |
||
1116 | */ |
||
3746 | Serge | 1117 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1118 | POSTING_READ(intel_hdmi->hdmi_reg); |
||
6084 | serge | 1119 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1120 | POSTING_READ(intel_hdmi->hdmi_reg); |
||
1121 | |||
1122 | temp &= ~SDVO_ENABLE; |
||
1123 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
||
1124 | POSTING_READ(intel_hdmi->hdmi_reg); |
||
2330 | Serge | 1125 | } |
6084 | serge | 1126 | |
1127 | intel_hdmi->set_infoframes(&encoder->base, false, NULL); |
||
2330 | Serge | 1128 | } |
1129 | |||
6084 | serge | 1130 | static void g4x_disable_hdmi(struct intel_encoder *encoder) |
4104 | Serge | 1131 | { |
6084 | serge | 1132 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1133 | |||
1134 | if (crtc->config->has_audio) |
||
1135 | intel_audio_codec_disable(encoder); |
||
1136 | |||
1137 | intel_disable_hdmi(encoder); |
||
1138 | } |
||
1139 | |||
1140 | static void pch_disable_hdmi(struct intel_encoder *encoder) |
||
1141 | { |
||
1142 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
||
1143 | |||
1144 | if (crtc->config->has_audio) |
||
1145 | intel_audio_codec_disable(encoder); |
||
1146 | } |
||
1147 | |||
1148 | static void pch_post_disable_hdmi(struct intel_encoder *encoder) |
||
1149 | { |
||
1150 | intel_disable_hdmi(encoder); |
||
1151 | } |
||
1152 | |||
1153 | static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) |
||
1154 | { |
||
4104 | Serge | 1155 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); |
1156 | |||
5060 | serge | 1157 | if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) |
4104 | Serge | 1158 | return 165000; |
4560 | Serge | 1159 | else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) |
4104 | Serge | 1160 | return 300000; |
1161 | else |
||
1162 | return 225000; |
||
1163 | } |
||
1164 | |||
4560 | Serge | 1165 | static enum drm_mode_status |
6084 | serge | 1166 | hdmi_port_clock_valid(struct intel_hdmi *hdmi, |
1167 | int clock, bool respect_dvi_limit) |
||
1168 | { |
||
1169 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); |
||
1170 | |||
1171 | if (clock < 25000) |
||
1172 | return MODE_CLOCK_LOW; |
||
1173 | if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit)) |
||
1174 | return MODE_CLOCK_HIGH; |
||
1175 | |||
1176 | /* BXT DPLL can't generate 223-240 MHz */ |
||
1177 | if (IS_BROXTON(dev) && clock > 223333 && clock < 240000) |
||
1178 | return MODE_CLOCK_RANGE; |
||
1179 | |||
1180 | /* CHV DPLL can't generate 216-240 MHz */ |
||
1181 | if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000) |
||
1182 | return MODE_CLOCK_RANGE; |
||
1183 | |||
1184 | return MODE_OK; |
||
1185 | } |
||
1186 | |||
1187 | static enum drm_mode_status |
||
4560 | Serge | 1188 | intel_hdmi_mode_valid(struct drm_connector *connector, |
6084 | serge | 1189 | struct drm_display_mode *mode) |
2330 | Serge | 1190 | { |
6084 | serge | 1191 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); |
1192 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); |
||
1193 | enum drm_mode_status status; |
||
1194 | int clock; |
||
5354 | serge | 1195 | |
6084 | serge | 1196 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
1197 | return MODE_NO_DBLESCAN; |
||
1198 | |||
1199 | clock = mode->clock; |
||
5354 | serge | 1200 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
1201 | clock *= 2; |
||
1202 | |||
6084 | serge | 1203 | /* check if we can do 8bpc */ |
1204 | status = hdmi_port_clock_valid(hdmi, clock, true); |
||
2330 | Serge | 1205 | |
6084 | serge | 1206 | /* if we can't do 8bpc we may still be able to do 12bpc */ |
1207 | if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK) |
||
1208 | status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true); |
||
2330 | Serge | 1209 | |
6084 | serge | 1210 | return status; |
2330 | Serge | 1211 | } |
1212 | |||
6084 | serge | 1213 | static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) |
5060 | serge | 1214 | { |
6084 | serge | 1215 | struct drm_device *dev = crtc_state->base.crtc->dev; |
1216 | struct drm_atomic_state *state; |
||
5060 | serge | 1217 | struct intel_encoder *encoder; |
6084 | serge | 1218 | struct drm_connector *connector; |
1219 | struct drm_connector_state *connector_state; |
||
5060 | serge | 1220 | int count = 0, count_hdmi = 0; |
6084 | serge | 1221 | int i; |
5060 | serge | 1222 | |
1223 | if (HAS_GMCH_DISPLAY(dev)) |
||
1224 | return false; |
||
1225 | |||
6084 | serge | 1226 | state = crtc_state->base.state; |
1227 | |||
1228 | for_each_connector_in_state(state, connector, connector_state, i) { |
||
1229 | if (connector_state->crtc != crtc_state->base.crtc) |
||
5060 | serge | 1230 | continue; |
1231 | |||
6084 | serge | 1232 | encoder = to_intel_encoder(connector_state->best_encoder); |
1233 | |||
5060 | serge | 1234 | count_hdmi += encoder->type == INTEL_OUTPUT_HDMI; |
1235 | count++; |
||
1236 | } |
||
1237 | |||
1238 | /* |
||
1239 | * HDMI 12bpc affects the clocks, so it's only possible |
||
1240 | * when not cloning with other encoder types. |
||
1241 | */ |
||
1242 | return count_hdmi > 0 && count_hdmi == count; |
||
1243 | } |
||
1244 | |||
3746 | Serge | 1245 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
6084 | serge | 1246 | struct intel_crtc_state *pipe_config) |
2330 | Serge | 1247 | { |
3746 | Serge | 1248 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1249 | struct drm_device *dev = encoder->base.dev; |
||
6084 | serge | 1250 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
1251 | int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; |
||
1252 | int clock_12bpc = clock_8bpc * 3 / 2; |
||
4104 | Serge | 1253 | int desired_bpp; |
2330 | Serge | 1254 | |
5060 | serge | 1255 | pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; |
1256 | |||
5354 | serge | 1257 | if (pipe_config->has_hdmi_sink) |
1258 | pipe_config->has_infoframe = true; |
||
1259 | |||
3480 | Serge | 1260 | if (intel_hdmi->color_range_auto) { |
1261 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ |
||
6084 | serge | 1262 | pipe_config->limited_color_range = |
1263 | pipe_config->has_hdmi_sink && |
||
1264 | drm_match_cea_mode(adjusted_mode) > 1; |
||
1265 | } else { |
||
1266 | pipe_config->limited_color_range = |
||
1267 | intel_hdmi->limited_color_range; |
||
3031 | serge | 1268 | } |
1269 | |||
5354 | serge | 1270 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { |
1271 | pipe_config->pixel_multiplier = 2; |
||
6084 | serge | 1272 | clock_8bpc *= 2; |
1273 | clock_12bpc *= 2; |
||
5354 | serge | 1274 | } |
1275 | |||
3746 | Serge | 1276 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) |
1277 | pipe_config->has_pch_encoder = true; |
||
1278 | |||
5060 | serge | 1279 | if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) |
1280 | pipe_config->has_audio = true; |
||
1281 | |||
3746 | Serge | 1282 | /* |
1283 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak |
||
1284 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi |
||
4104 | Serge | 1285 | * outputs. We also need to check that the higher clock still fits |
1286 | * within limits. |
||
3746 | Serge | 1287 | */ |
5060 | serge | 1288 | if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && |
6084 | serge | 1289 | hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK && |
1290 | hdmi_12bpc_possible(pipe_config)) { |
||
4104 | Serge | 1291 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
1292 | desired_bpp = 12*3; |
||
1293 | |||
1294 | /* Need to adjust the port link by 1.5x for 12bpc. */ |
||
1295 | pipe_config->port_clock = clock_12bpc; |
||
3746 | Serge | 1296 | } else { |
4104 | Serge | 1297 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
1298 | desired_bpp = 8*3; |
||
6084 | serge | 1299 | |
1300 | pipe_config->port_clock = clock_8bpc; |
||
3746 | Serge | 1301 | } |
1302 | |||
4104 | Serge | 1303 | if (!pipe_config->bw_constrained) { |
1304 | DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); |
||
1305 | pipe_config->pipe_bpp = desired_bpp; |
||
1306 | } |
||
1307 | |||
6084 | serge | 1308 | if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, |
1309 | false) != MODE_OK) { |
||
1310 | DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); |
||
4104 | Serge | 1311 | return false; |
1312 | } |
||
1313 | |||
6084 | serge | 1314 | /* Set user selected PAR to incoming mode's member */ |
1315 | adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio; |
||
1316 | |||
3480 | Serge | 1317 | return true; |
3031 | serge | 1318 | } |
1319 | |||
5354 | serge | 1320 | static void |
1321 | intel_hdmi_unset_edid(struct drm_connector *connector) |
||
2330 | Serge | 1322 | { |
1323 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
||
5354 | serge | 1324 | |
1325 | intel_hdmi->has_hdmi_sink = false; |
||
1326 | intel_hdmi->has_audio = false; |
||
1327 | intel_hdmi->rgb_quant_range_selectable = false; |
||
1328 | |||
1329 | kfree(to_intel_connector(connector)->detect_edid); |
||
1330 | to_intel_connector(connector)->detect_edid = NULL; |
||
1331 | } |
||
1332 | |||
1333 | static bool |
||
6084 | serge | 1334 | intel_hdmi_set_edid(struct drm_connector *connector, bool force) |
5354 | serge | 1335 | { |
1336 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
||
1337 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
||
6084 | serge | 1338 | struct edid *edid = NULL; |
5354 | serge | 1339 | bool connected = false; |
2330 | Serge | 1340 | |
6084 | serge | 1341 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
5060 | serge | 1342 | |
6084 | serge | 1343 | if (force) |
1344 | edid = drm_get_edid(connector, |
||
1345 | intel_gmbus_get_adapter(dev_priv, |
||
1346 | intel_hdmi->ddc_bus)); |
||
2330 | Serge | 1347 | |
6084 | serge | 1348 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
5354 | serge | 1349 | |
1350 | to_intel_connector(connector)->detect_edid = edid; |
||
1351 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { |
||
6084 | serge | 1352 | intel_hdmi->rgb_quant_range_selectable = |
1353 | drm_rgb_quant_range_selectable(edid); |
||
2330 | Serge | 1354 | |
5354 | serge | 1355 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
3031 | serge | 1356 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
1357 | intel_hdmi->has_audio = |
||
5354 | serge | 1358 | intel_hdmi->force_audio == HDMI_AUDIO_ON; |
1359 | |||
1360 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
||
1361 | intel_hdmi->has_hdmi_sink = |
||
1362 | drm_detect_hdmi_monitor(edid); |
||
1363 | |||
1364 | connected = true; |
||
2330 | Serge | 1365 | } |
1366 | |||
5354 | serge | 1367 | return connected; |
1368 | } |
||
5060 | serge | 1369 | |
5354 | serge | 1370 | static enum drm_connector_status |
1371 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
||
1372 | { |
||
1373 | enum drm_connector_status status; |
||
6084 | serge | 1374 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
1375 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
||
1376 | bool live_status = false; |
||
1377 | unsigned int try; |
||
5354 | serge | 1378 | |
1379 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
||
1380 | connector->base.id, connector->name); |
||
1381 | |||
6084 | serge | 1382 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
1383 | |||
1384 | for (try = 0; !live_status && try < 9; try++) { |
||
1385 | if (try) |
||
1386 | msleep(10); |
||
1387 | live_status = intel_digital_port_connected(dev_priv, |
||
1388 | hdmi_to_dig_port(intel_hdmi)); |
||
1389 | } |
||
1390 | |||
6660 | serge | 1391 | if (!live_status) { |
1392 | DRM_DEBUG_KMS("HDMI live status down\n"); |
||
1393 | /* |
||
1394 | * Live status register is not reliable on all intel platforms. |
||
1395 | * So consider live_status only for certain platforms, for |
||
1396 | * others, read EDID to determine presence of sink. |
||
1397 | */ |
||
1398 | if (INTEL_INFO(dev_priv)->gen < 7 || IS_IVYBRIDGE(dev_priv)) |
||
1399 | live_status = true; |
||
1400 | } |
||
6084 | serge | 1401 | |
5354 | serge | 1402 | intel_hdmi_unset_edid(connector); |
1403 | |||
6084 | serge | 1404 | if (intel_hdmi_set_edid(connector, live_status)) { |
5354 | serge | 1405 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
1406 | |||
1407 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; |
||
1408 | status = connector_status_connected; |
||
1409 | } else |
||
1410 | status = connector_status_disconnected; |
||
1411 | |||
6084 | serge | 1412 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
1413 | |||
2330 | Serge | 1414 | return status; |
1415 | } |
||
1416 | |||
5354 | serge | 1417 | static void |
1418 | intel_hdmi_force(struct drm_connector *connector) |
||
2330 | Serge | 1419 | { |
5354 | serge | 1420 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
2330 | Serge | 1421 | |
5354 | serge | 1422 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1423 | connector->base.id, connector->name); |
||
2330 | Serge | 1424 | |
5354 | serge | 1425 | intel_hdmi_unset_edid(connector); |
5060 | serge | 1426 | |
5354 | serge | 1427 | if (connector->status != connector_status_connected) |
1428 | return; |
||
5060 | serge | 1429 | |
6084 | serge | 1430 | intel_hdmi_set_edid(connector, true); |
5354 | serge | 1431 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; |
1432 | } |
||
5060 | serge | 1433 | |
5354 | serge | 1434 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
1435 | { |
||
1436 | struct edid *edid; |
||
1437 | |||
1438 | edid = to_intel_connector(connector)->detect_edid; |
||
1439 | if (edid == NULL) |
||
1440 | return 0; |
||
1441 | |||
1442 | return intel_connector_update_modes(connector, edid); |
||
2330 | Serge | 1443 | } |
1444 | |||
1445 | static bool |
||
1446 | intel_hdmi_detect_audio(struct drm_connector *connector) |
||
1447 | { |
||
5354 | serge | 1448 | bool has_audio = false; |
2330 | Serge | 1449 | struct edid *edid; |
1450 | |||
5354 | serge | 1451 | edid = to_intel_connector(connector)->detect_edid; |
1452 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) |
||
6084 | serge | 1453 | has_audio = drm_detect_monitor_audio(edid); |
2330 | Serge | 1454 | |
1455 | return has_audio; |
||
1456 | } |
||
1457 | |||
1458 | static int |
||
1459 | intel_hdmi_set_property(struct drm_connector *connector, |
||
6084 | serge | 1460 | struct drm_property *property, |
1461 | uint64_t val) |
||
2330 | Serge | 1462 | { |
1463 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
||
3243 | Serge | 1464 | struct intel_digital_port *intel_dig_port = |
1465 | hdmi_to_dig_port(intel_hdmi); |
||
2330 | Serge | 1466 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
1467 | int ret; |
||
1468 | |||
3243 | Serge | 1469 | ret = drm_object_property_set_value(&connector->base, property, val); |
2330 | Serge | 1470 | if (ret) |
1471 | return ret; |
||
3480 | Serge | 1472 | |
2330 | Serge | 1473 | if (property == dev_priv->force_audio_property) { |
3031 | serge | 1474 | enum hdmi_force_audio i = val; |
2330 | Serge | 1475 | bool has_audio; |
1476 | |||
1477 | if (i == intel_hdmi->force_audio) |
||
1478 | return 0; |
||
1479 | |||
1480 | intel_hdmi->force_audio = i; |
||
1481 | |||
3031 | serge | 1482 | if (i == HDMI_AUDIO_AUTO) |
2330 | Serge | 1483 | has_audio = intel_hdmi_detect_audio(connector); |
1484 | else |
||
3031 | serge | 1485 | has_audio = (i == HDMI_AUDIO_ON); |
2330 | Serge | 1486 | |
3031 | serge | 1487 | if (i == HDMI_AUDIO_OFF_DVI) |
1488 | intel_hdmi->has_hdmi_sink = 0; |
||
2330 | Serge | 1489 | |
1490 | intel_hdmi->has_audio = has_audio; |
||
1491 | goto done; |
||
1492 | } |
||
1493 | |||
1494 | if (property == dev_priv->broadcast_rgb_property) { |
||
3746 | Serge | 1495 | bool old_auto = intel_hdmi->color_range_auto; |
6084 | serge | 1496 | bool old_range = intel_hdmi->limited_color_range; |
3746 | Serge | 1497 | |
3480 | Serge | 1498 | switch (val) { |
1499 | case INTEL_BROADCAST_RGB_AUTO: |
||
1500 | intel_hdmi->color_range_auto = true; |
||
1501 | break; |
||
1502 | case INTEL_BROADCAST_RGB_FULL: |
||
1503 | intel_hdmi->color_range_auto = false; |
||
6084 | serge | 1504 | intel_hdmi->limited_color_range = false; |
3480 | Serge | 1505 | break; |
1506 | case INTEL_BROADCAST_RGB_LIMITED: |
||
1507 | intel_hdmi->color_range_auto = false; |
||
6084 | serge | 1508 | intel_hdmi->limited_color_range = true; |
3480 | Serge | 1509 | break; |
1510 | default: |
||
1511 | return -EINVAL; |
||
1512 | } |
||
3746 | Serge | 1513 | |
1514 | if (old_auto == intel_hdmi->color_range_auto && |
||
6084 | serge | 1515 | old_range == intel_hdmi->limited_color_range) |
3746 | Serge | 1516 | return 0; |
1517 | |||
2330 | Serge | 1518 | goto done; |
1519 | } |
||
3031 | serge | 1520 | |
5060 | serge | 1521 | if (property == connector->dev->mode_config.aspect_ratio_property) { |
1522 | switch (val) { |
||
1523 | case DRM_MODE_PICTURE_ASPECT_NONE: |
||
1524 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; |
||
1525 | break; |
||
1526 | case DRM_MODE_PICTURE_ASPECT_4_3: |
||
1527 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; |
||
1528 | break; |
||
1529 | case DRM_MODE_PICTURE_ASPECT_16_9: |
||
1530 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; |
||
1531 | break; |
||
1532 | default: |
||
1533 | return -EINVAL; |
||
1534 | } |
||
1535 | goto done; |
||
1536 | } |
||
1537 | |||
2330 | Serge | 1538 | return -EINVAL; |
1539 | |||
1540 | done: |
||
3480 | Serge | 1541 | if (intel_dig_port->base.base.crtc) |
1542 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); |
||
2330 | Serge | 1543 | |
1544 | return 0; |
||
1545 | } |
||
1546 | |||
5060 | serge | 1547 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder) |
1548 | { |
||
1549 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
||
1550 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
||
6084 | serge | 1551 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
5060 | serge | 1552 | |
1553 | intel_hdmi_prepare(encoder); |
||
1554 | |||
1555 | intel_hdmi->set_infoframes(&encoder->base, |
||
6084 | serge | 1556 | intel_crtc->config->has_hdmi_sink, |
5060 | serge | 1557 | adjusted_mode); |
1558 | } |
||
1559 | |||
4560 | Serge | 1560 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) |
4104 | Serge | 1561 | { |
1562 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
||
5060 | serge | 1563 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
4104 | Serge | 1564 | struct drm_device *dev = encoder->base.dev; |
1565 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1566 | struct intel_crtc *intel_crtc = |
||
1567 | to_intel_crtc(encoder->base.crtc); |
||
6084 | serge | 1568 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
4560 | Serge | 1569 | enum dpio_channel port = vlv_dport_to_channel(dport); |
4104 | Serge | 1570 | int pipe = intel_crtc->pipe; |
1571 | u32 val; |
||
1572 | |||
1573 | /* Enable clock channels for this port */ |
||
6084 | serge | 1574 | mutex_lock(&dev_priv->sb_lock); |
4560 | Serge | 1575 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
4104 | Serge | 1576 | val = 0; |
1577 | if (pipe) |
||
1578 | val |= (1<<21); |
||
1579 | else |
||
1580 | val &= ~(1<<21); |
||
1581 | val |= 0x001000c4; |
||
4560 | Serge | 1582 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
4104 | Serge | 1583 | |
1584 | /* HDMI 1.0V-2dB */ |
||
4560 | Serge | 1585 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); |
1586 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); |
||
1587 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); |
||
1588 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); |
||
1589 | vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); |
||
1590 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); |
||
1591 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); |
||
1592 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); |
||
4104 | Serge | 1593 | |
1594 | /* Program lane clock */ |
||
4560 | Serge | 1595 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
1596 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); |
||
6084 | serge | 1597 | mutex_unlock(&dev_priv->sb_lock); |
4104 | Serge | 1598 | |
5060 | serge | 1599 | intel_hdmi->set_infoframes(&encoder->base, |
6084 | serge | 1600 | intel_crtc->config->has_hdmi_sink, |
5060 | serge | 1601 | adjusted_mode); |
1602 | |||
6084 | serge | 1603 | g4x_enable_hdmi(encoder); |
4104 | Serge | 1604 | |
6084 | serge | 1605 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
4104 | Serge | 1606 | } |
1607 | |||
4560 | Serge | 1608 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
4104 | Serge | 1609 | { |
1610 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
||
1611 | struct drm_device *dev = encoder->base.dev; |
||
1612 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4560 | Serge | 1613 | struct intel_crtc *intel_crtc = |
1614 | to_intel_crtc(encoder->base.crtc); |
||
1615 | enum dpio_channel port = vlv_dport_to_channel(dport); |
||
1616 | int pipe = intel_crtc->pipe; |
||
4104 | Serge | 1617 | |
5060 | serge | 1618 | intel_hdmi_prepare(encoder); |
4104 | Serge | 1619 | |
1620 | /* Program Tx lane resets to default */ |
||
6084 | serge | 1621 | mutex_lock(&dev_priv->sb_lock); |
4560 | Serge | 1622 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
4104 | Serge | 1623 | DPIO_PCS_TX_LANE2_RESET | |
1624 | DPIO_PCS_TX_LANE1_RESET); |
||
4560 | Serge | 1625 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
4104 | Serge | 1626 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1627 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | |
||
1628 | (1< |
||
1629 | DPIO_PCS_CLK_SOFT_RESET); |
||
1630 | |||
1631 | /* Fix up inter-pair skew failure */ |
||
4560 | Serge | 1632 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
1633 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); |
||
1634 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); |
||
4104 | Serge | 1635 | |
4560 | Serge | 1636 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); |
1637 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); |
||
6084 | serge | 1638 | mutex_unlock(&dev_priv->sb_lock); |
4104 | Serge | 1639 | } |
1640 | |||
6084 | serge | 1641 | static void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
1642 | bool reset) |
||
1643 | { |
||
1644 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
||
1645 | enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); |
||
1646 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
||
1647 | enum pipe pipe = crtc->pipe; |
||
1648 | uint32_t val; |
||
1649 | |||
1650 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); |
||
1651 | if (reset) |
||
1652 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
||
1653 | else |
||
1654 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; |
||
1655 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); |
||
1656 | |||
1657 | if (crtc->config->lane_count > 2) { |
||
1658 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
||
1659 | if (reset) |
||
1660 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
||
1661 | else |
||
1662 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; |
||
1663 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
||
1664 | } |
||
1665 | |||
1666 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
||
1667 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
||
1668 | if (reset) |
||
1669 | val &= ~DPIO_PCS_CLK_SOFT_RESET; |
||
1670 | else |
||
1671 | val |= DPIO_PCS_CLK_SOFT_RESET; |
||
1672 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
||
1673 | |||
1674 | if (crtc->config->lane_count > 2) { |
||
1675 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
||
1676 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
||
1677 | if (reset) |
||
1678 | val &= ~DPIO_PCS_CLK_SOFT_RESET; |
||
1679 | else |
||
1680 | val |= DPIO_PCS_CLK_SOFT_RESET; |
||
1681 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); |
||
1682 | } |
||
1683 | } |
||
1684 | |||
5060 | serge | 1685 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
1686 | { |
||
1687 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
||
1688 | struct drm_device *dev = encoder->base.dev; |
||
1689 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1690 | struct intel_crtc *intel_crtc = |
||
1691 | to_intel_crtc(encoder->base.crtc); |
||
1692 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
||
1693 | enum pipe pipe = intel_crtc->pipe; |
||
1694 | u32 val; |
||
1695 | |||
5354 | serge | 1696 | intel_hdmi_prepare(encoder); |
1697 | |||
6084 | serge | 1698 | /* |
1699 | * Must trick the second common lane into life. |
||
1700 | * Otherwise we can't even access the PLL. |
||
1701 | */ |
||
1702 | if (ch == DPIO_CH0 && pipe == PIPE_B) |
||
1703 | dport->release_cl2_override = |
||
1704 | !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); |
||
5060 | serge | 1705 | |
6084 | serge | 1706 | chv_phy_powergate_lanes(encoder, true, 0x0); |
1707 | |||
1708 | mutex_lock(&dev_priv->sb_lock); |
||
1709 | |||
1710 | /* Assert data lane reset */ |
||
1711 | chv_data_lane_soft_reset(encoder, true); |
||
1712 | |||
5060 | serge | 1713 | /* program left/right clock distribution */ |
1714 | if (pipe != PIPE_B) { |
||
1715 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
||
1716 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
||
1717 | if (ch == DPIO_CH0) |
||
1718 | val |= CHV_BUFLEFTENA1_FORCE; |
||
1719 | if (ch == DPIO_CH1) |
||
1720 | val |= CHV_BUFRIGHTENA1_FORCE; |
||
1721 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
||
1722 | } else { |
||
1723 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
||
1724 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
||
1725 | if (ch == DPIO_CH0) |
||
1726 | val |= CHV_BUFLEFTENA2_FORCE; |
||
1727 | if (ch == DPIO_CH1) |
||
1728 | val |= CHV_BUFRIGHTENA2_FORCE; |
||
1729 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
||
1730 | } |
||
1731 | |||
1732 | /* program clock channel usage */ |
||
1733 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); |
||
1734 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
||
1735 | if (pipe != PIPE_B) |
||
1736 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
||
1737 | else |
||
1738 | val |= CHV_PCS_USEDCLKCHANNEL; |
||
1739 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); |
||
1740 | |||
1741 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); |
||
1742 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
||
1743 | if (pipe != PIPE_B) |
||
1744 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
||
1745 | else |
||
1746 | val |= CHV_PCS_USEDCLKCHANNEL; |
||
1747 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); |
||
1748 | |||
1749 | /* |
||
1750 | * This a a bit weird since generally CL |
||
1751 | * matches the pipe, but here we need to |
||
1752 | * pick the CL based on the port. |
||
1753 | */ |
||
1754 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); |
||
1755 | if (pipe != PIPE_B) |
||
1756 | val &= ~CHV_CMN_USEDCLKCHANNEL; |
||
1757 | else |
||
1758 | val |= CHV_CMN_USEDCLKCHANNEL; |
||
1759 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); |
||
1760 | |||
6084 | serge | 1761 | mutex_unlock(&dev_priv->sb_lock); |
5060 | serge | 1762 | } |
1763 | |||
6084 | serge | 1764 | static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder) |
1765 | { |
||
1766 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
||
1767 | enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
||
1768 | u32 val; |
||
1769 | |||
1770 | mutex_lock(&dev_priv->sb_lock); |
||
1771 | |||
1772 | /* disable left/right clock distribution */ |
||
1773 | if (pipe != PIPE_B) { |
||
1774 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
||
1775 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
||
1776 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
||
1777 | } else { |
||
1778 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
||
1779 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
||
1780 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
||
1781 | } |
||
1782 | |||
1783 | mutex_unlock(&dev_priv->sb_lock); |
||
1784 | |||
1785 | /* |
||
1786 | * Leave the power down bit cleared for at least one |
||
1787 | * lane so that chv_powergate_phy_ch() will power |
||
1788 | * on something when the channel is otherwise unused. |
||
1789 | * When the port is off and the override is removed |
||
1790 | * the lanes power down anyway, so otherwise it doesn't |
||
1791 | * really matter what the state of power down bits is |
||
1792 | * after this. |
||
1793 | */ |
||
1794 | chv_phy_powergate_lanes(encoder, false, 0x0); |
||
1795 | } |
||
1796 | |||
4560 | Serge | 1797 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder) |
4104 | Serge | 1798 | { |
1799 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
||
1800 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
||
4560 | Serge | 1801 | struct intel_crtc *intel_crtc = |
1802 | to_intel_crtc(encoder->base.crtc); |
||
1803 | enum dpio_channel port = vlv_dport_to_channel(dport); |
||
1804 | int pipe = intel_crtc->pipe; |
||
4104 | Serge | 1805 | |
1806 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ |
||
6084 | serge | 1807 | mutex_lock(&dev_priv->sb_lock); |
4560 | Serge | 1808 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); |
1809 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); |
||
6084 | serge | 1810 | mutex_unlock(&dev_priv->sb_lock); |
4104 | Serge | 1811 | } |
1812 | |||
5060 | serge | 1813 | static void chv_hdmi_post_disable(struct intel_encoder *encoder) |
1814 | { |
||
1815 | struct drm_device *dev = encoder->base.dev; |
||
1816 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1817 | |||
6084 | serge | 1818 | mutex_lock(&dev_priv->sb_lock); |
5060 | serge | 1819 | |
6084 | serge | 1820 | /* Assert data lane reset */ |
1821 | chv_data_lane_soft_reset(encoder, true); |
||
5060 | serge | 1822 | |
6084 | serge | 1823 | mutex_unlock(&dev_priv->sb_lock); |
5060 | serge | 1824 | } |
1825 | |||
1826 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder) |
||
1827 | { |
||
1828 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
||
5354 | serge | 1829 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
5060 | serge | 1830 | struct drm_device *dev = encoder->base.dev; |
1831 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1832 | struct intel_crtc *intel_crtc = |
||
1833 | to_intel_crtc(encoder->base.crtc); |
||
6084 | serge | 1834 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
5060 | serge | 1835 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
1836 | int pipe = intel_crtc->pipe; |
||
6084 | serge | 1837 | int data, i, stagger; |
5060 | serge | 1838 | u32 val; |
1839 | |||
6084 | serge | 1840 | mutex_lock(&dev_priv->sb_lock); |
5060 | serge | 1841 | |
5354 | serge | 1842 | /* allow hardware to manage TX FIFO reset source */ |
1843 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
||
1844 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
||
1845 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
||
1846 | |||
1847 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
||
1848 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
||
1849 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
||
1850 | |||
5060 | serge | 1851 | /* Program Tx latency optimal setting */ |
1852 | for (i = 0; i < 4; i++) { |
||
1853 | /* Set the upar bit */ |
||
1854 | data = (i == 1) ? 0x0 : 0x1; |
||
1855 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), |
||
1856 | data << DPIO_UPAR_SHIFT); |
||
1857 | } |
||
1858 | |||
1859 | /* Data lane stagger programming */ |
||
6084 | serge | 1860 | if (intel_crtc->config->port_clock > 270000) |
1861 | stagger = 0x18; |
||
1862 | else if (intel_crtc->config->port_clock > 135000) |
||
1863 | stagger = 0xd; |
||
1864 | else if (intel_crtc->config->port_clock > 67500) |
||
1865 | stagger = 0x7; |
||
1866 | else if (intel_crtc->config->port_clock > 33750) |
||
1867 | stagger = 0x4; |
||
1868 | else |
||
1869 | stagger = 0x2; |
||
5060 | serge | 1870 | |
6084 | serge | 1871 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
1872 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
||
1873 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
||
1874 | |||
1875 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
||
1876 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
||
1877 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
||
1878 | |||
1879 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), |
||
1880 | DPIO_LANESTAGGER_STRAP(stagger) | |
||
1881 | DPIO_LANESTAGGER_STRAP_OVRD | |
||
1882 | DPIO_TX1_STAGGER_MASK(0x1f) | |
||
1883 | DPIO_TX1_STAGGER_MULT(6) | |
||
1884 | DPIO_TX2_STAGGER_MULT(0)); |
||
1885 | |||
1886 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), |
||
1887 | DPIO_LANESTAGGER_STRAP(stagger) | |
||
1888 | DPIO_LANESTAGGER_STRAP_OVRD | |
||
1889 | DPIO_TX1_STAGGER_MASK(0x1f) | |
||
1890 | DPIO_TX1_STAGGER_MULT(7) | |
||
1891 | DPIO_TX2_STAGGER_MULT(5)); |
||
1892 | |||
1893 | /* Deassert data lane reset */ |
||
1894 | chv_data_lane_soft_reset(encoder, false); |
||
1895 | |||
5060 | serge | 1896 | /* Clear calc init */ |
1897 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
||
1898 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
||
5354 | serge | 1899 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
1900 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
||
5060 | serge | 1901 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
1902 | |||
1903 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
||
1904 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
||
5354 | serge | 1905 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
1906 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
||
5060 | serge | 1907 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
1908 | |||
5354 | serge | 1909 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
1910 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
||
1911 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
||
1912 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); |
||
1913 | |||
1914 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); |
||
1915 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
||
1916 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
||
1917 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); |
||
1918 | |||
5060 | serge | 1919 | /* FIXME: Program the support xxx V-dB */ |
1920 | /* Use 800mV-0dB */ |
||
1921 | for (i = 0; i < 4; i++) { |
||
1922 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); |
||
1923 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; |
||
1924 | val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT; |
||
1925 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); |
||
1926 | } |
||
1927 | |||
1928 | for (i = 0; i < 4; i++) { |
||
1929 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); |
||
6084 | serge | 1930 | |
5354 | serge | 1931 | val &= ~DPIO_SWING_MARGIN000_MASK; |
1932 | val |= 102 << DPIO_SWING_MARGIN000_SHIFT; |
||
6084 | serge | 1933 | |
1934 | /* |
||
1935 | * Supposedly this value shouldn't matter when unique transition |
||
1936 | * scale is disabled, but in fact it does matter. Let's just |
||
1937 | * always program the same value and hope it's OK. |
||
1938 | */ |
||
1939 | val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); |
||
1940 | val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; |
||
1941 | |||
5060 | serge | 1942 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
1943 | } |
||
1944 | |||
6084 | serge | 1945 | /* |
1946 | * The document said it needs to set bit 27 for ch0 and bit 26 |
||
1947 | * for ch1. Might be a typo in the doc. |
||
1948 | * For now, for this unique transition scale selection, set bit |
||
1949 | * 27 for ch0 and ch1. |
||
1950 | */ |
||
5060 | serge | 1951 | for (i = 0; i < 4; i++) { |
1952 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); |
||
1953 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; |
||
1954 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); |
||
1955 | } |
||
1956 | |||
1957 | /* Start swing calculation */ |
||
1958 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
||
1959 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
||
1960 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
||
1961 | |||
1962 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
||
1963 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
||
1964 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
||
1965 | |||
6084 | serge | 1966 | mutex_unlock(&dev_priv->sb_lock); |
5060 | serge | 1967 | |
5354 | serge | 1968 | intel_hdmi->set_infoframes(&encoder->base, |
6084 | serge | 1969 | intel_crtc->config->has_hdmi_sink, |
5354 | serge | 1970 | adjusted_mode); |
1971 | |||
6084 | serge | 1972 | g4x_enable_hdmi(encoder); |
5060 | serge | 1973 | |
6084 | serge | 1974 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
1975 | |||
1976 | /* Second common lane will stay alive on its own now */ |
||
1977 | if (dport->release_cl2_override) { |
||
1978 | chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); |
||
1979 | dport->release_cl2_override = false; |
||
1980 | } |
||
5060 | serge | 1981 | } |
1982 | |||
2330 | Serge | 1983 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1984 | { |
||
5354 | serge | 1985 | kfree(to_intel_connector(connector)->detect_edid); |
2330 | Serge | 1986 | drm_connector_cleanup(connector); |
1987 | kfree(connector); |
||
1988 | } |
||
1989 | |||
1990 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
||
6084 | serge | 1991 | .dpms = drm_atomic_helper_connector_dpms, |
2330 | Serge | 1992 | .detect = intel_hdmi_detect, |
5354 | serge | 1993 | .force = intel_hdmi_force, |
2330 | Serge | 1994 | .fill_modes = drm_helper_probe_single_connector_modes, |
1995 | .set_property = intel_hdmi_set_property, |
||
6084 | serge | 1996 | .atomic_get_property = intel_connector_atomic_get_property, |
2330 | Serge | 1997 | .destroy = intel_hdmi_destroy, |
6084 | serge | 1998 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
1999 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
||
2330 | Serge | 2000 | }; |
2001 | |||
2002 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { |
||
2003 | .get_modes = intel_hdmi_get_modes, |
||
2004 | .mode_valid = intel_hdmi_mode_valid, |
||
2005 | .best_encoder = intel_best_encoder, |
||
2006 | }; |
||
2007 | |||
2008 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
||
2009 | .destroy = intel_encoder_destroy, |
||
2010 | }; |
||
2011 | |||
2012 | static void |
||
2013 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) |
||
2014 | { |
||
2015 | intel_attach_force_audio_property(connector); |
||
2016 | intel_attach_broadcast_rgb_property(connector); |
||
3480 | Serge | 2017 | intel_hdmi->color_range_auto = true; |
5060 | serge | 2018 | intel_attach_aspect_ratio_property(connector); |
2019 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; |
||
2330 | Serge | 2020 | } |
2021 | |||
3243 | Serge | 2022 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
2023 | struct intel_connector *intel_connector) |
||
2330 | Serge | 2024 | { |
3243 | Serge | 2025 | struct drm_connector *connector = &intel_connector->base; |
2026 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
||
2027 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
||
2028 | struct drm_device *dev = intel_encoder->base.dev; |
||
2330 | Serge | 2029 | struct drm_i915_private *dev_priv = dev->dev_private; |
3243 | Serge | 2030 | enum port port = intel_dig_port->port; |
6084 | serge | 2031 | uint8_t alternate_ddc_pin; |
2330 | Serge | 2032 | |
6660 | serge | 2033 | DRM_DEBUG_KMS("Adding HDMI connector on port %c\n", |
2034 | port_name(port)); |
||
2035 | |||
2330 | Serge | 2036 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
2037 | DRM_MODE_CONNECTOR_HDMIA); |
||
2038 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
||
2039 | |||
3031 | serge | 2040 | connector->interlace_allowed = 1; |
2330 | Serge | 2041 | connector->doublescan_allowed = 0; |
4560 | Serge | 2042 | connector->stereo_allowed = 1; |
2330 | Serge | 2043 | |
3031 | serge | 2044 | switch (port) { |
2045 | case PORT_B: |
||
6084 | serge | 2046 | if (IS_BROXTON(dev_priv)) |
2047 | intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT; |
||
2048 | else |
||
2049 | intel_hdmi->ddc_bus = GMBUS_PIN_DPB; |
||
2050 | /* |
||
2051 | * On BXT A0/A1, sw needs to activate DDIA HPD logic and |
||
2052 | * interrupts to check the external panel connection. |
||
2053 | */ |
||
2054 | if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) |
||
2055 | intel_encoder->hpd_pin = HPD_PORT_A; |
||
2056 | else |
||
2057 | intel_encoder->hpd_pin = HPD_PORT_B; |
||
3031 | serge | 2058 | break; |
2059 | case PORT_C: |
||
6084 | serge | 2060 | if (IS_BROXTON(dev_priv)) |
2061 | intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT; |
||
2062 | else |
||
2063 | intel_hdmi->ddc_bus = GMBUS_PIN_DPC; |
||
3746 | Serge | 2064 | intel_encoder->hpd_pin = HPD_PORT_C; |
3031 | serge | 2065 | break; |
2066 | case PORT_D: |
||
6084 | serge | 2067 | if (WARN_ON(IS_BROXTON(dev_priv))) |
2068 | intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED; |
||
2069 | else if (IS_CHERRYVIEW(dev_priv)) |
||
2070 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV; |
||
5060 | serge | 2071 | else |
6084 | serge | 2072 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD; |
3746 | Serge | 2073 | intel_encoder->hpd_pin = HPD_PORT_D; |
3031 | serge | 2074 | break; |
6084 | serge | 2075 | case PORT_E: |
2076 | /* On SKL PORT E doesn't have seperate GMBUS pin |
||
2077 | * We rely on VBT to set a proper alternate GMBUS pin. */ |
||
2078 | alternate_ddc_pin = |
||
2079 | dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin; |
||
2080 | switch (alternate_ddc_pin) { |
||
2081 | case DDC_PIN_B: |
||
2082 | intel_hdmi->ddc_bus = GMBUS_PIN_DPB; |
||
2083 | break; |
||
2084 | case DDC_PIN_C: |
||
2085 | intel_hdmi->ddc_bus = GMBUS_PIN_DPC; |
||
2086 | break; |
||
2087 | case DDC_PIN_D: |
||
2088 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD; |
||
2089 | break; |
||
2090 | default: |
||
2091 | MISSING_CASE(alternate_ddc_pin); |
||
2092 | } |
||
2093 | intel_encoder->hpd_pin = HPD_PORT_E; |
||
2094 | break; |
||
3031 | serge | 2095 | case PORT_A: |
3746 | Serge | 2096 | intel_encoder->hpd_pin = HPD_PORT_A; |
3031 | serge | 2097 | /* Internal port only for eDP. */ |
2098 | default: |
||
2099 | BUG(); |
||
2330 | Serge | 2100 | } |
2101 | |||
3746 | Serge | 2102 | if (IS_VALLEYVIEW(dev)) { |
2103 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
||
2104 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
||
5354 | serge | 2105 | intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; |
5060 | serge | 2106 | } else if (IS_G4X(dev)) { |
3031 | serge | 2107 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
2108 | intel_hdmi->set_infoframes = g4x_set_infoframes; |
||
5354 | serge | 2109 | intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; |
3746 | Serge | 2110 | } else if (HAS_DDI(dev)) { |
3031 | serge | 2111 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
2112 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
||
5354 | serge | 2113 | intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; |
3031 | serge | 2114 | } else if (HAS_PCH_IBX(dev)) { |
2115 | intel_hdmi->write_infoframe = ibx_write_infoframe; |
||
2116 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
||
5354 | serge | 2117 | intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; |
2342 | Serge | 2118 | } else { |
3031 | serge | 2119 | intel_hdmi->write_infoframe = cpt_write_infoframe; |
2120 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
||
5354 | serge | 2121 | intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; |
2342 | Serge | 2122 | } |
2330 | Serge | 2123 | |
3480 | Serge | 2124 | if (HAS_DDI(dev)) |
3243 | Serge | 2125 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
2126 | else |
||
6084 | serge | 2127 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
5060 | serge | 2128 | intel_connector->unregister = intel_connector_unregister; |
2330 | Serge | 2129 | |
2130 | intel_hdmi_add_properties(intel_hdmi, connector); |
||
2131 | |||
2132 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
||
5060 | serge | 2133 | drm_connector_register(connector); |
6084 | serge | 2134 | intel_hdmi->attached_connector = intel_connector; |
2330 | Serge | 2135 | |
2136 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
||
2137 | * 0xd. Failure to do so will result in spurious interrupts being |
||
2138 | * generated on the port when a cable is not attached. |
||
2139 | */ |
||
2140 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
||
2141 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
||
2142 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
||
2143 | } |
||
2144 | } |
||
3243 | Serge | 2145 | |
3746 | Serge | 2146 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) |
3243 | Serge | 2147 | { |
2148 | struct intel_digital_port *intel_dig_port; |
||
2149 | struct intel_encoder *intel_encoder; |
||
2150 | struct intel_connector *intel_connector; |
||
2151 | |||
4560 | Serge | 2152 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
3243 | Serge | 2153 | if (!intel_dig_port) |
2154 | return; |
||
2155 | |||
6084 | serge | 2156 | intel_connector = intel_connector_alloc(); |
3243 | Serge | 2157 | if (!intel_connector) { |
2158 | kfree(intel_dig_port); |
||
2159 | return; |
||
2160 | } |
||
2161 | |||
2162 | intel_encoder = &intel_dig_port->base; |
||
2163 | |||
2164 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
||
2165 | DRM_MODE_ENCODER_TMDS); |
||
2166 | |||
3746 | Serge | 2167 | intel_encoder->compute_config = intel_hdmi_compute_config; |
6084 | serge | 2168 | if (HAS_PCH_SPLIT(dev)) { |
2169 | intel_encoder->disable = pch_disable_hdmi; |
||
2170 | intel_encoder->post_disable = pch_post_disable_hdmi; |
||
2171 | } else { |
||
2172 | intel_encoder->disable = g4x_disable_hdmi; |
||
2173 | } |
||
3243 | Serge | 2174 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
4104 | Serge | 2175 | intel_encoder->get_config = intel_hdmi_get_config; |
5060 | serge | 2176 | if (IS_CHERRYVIEW(dev)) { |
2177 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
||
2178 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
||
2179 | intel_encoder->enable = vlv_enable_hdmi; |
||
2180 | intel_encoder->post_disable = chv_hdmi_post_disable; |
||
6084 | serge | 2181 | intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; |
5060 | serge | 2182 | } else if (IS_VALLEYVIEW(dev)) { |
4560 | Serge | 2183 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
2184 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; |
||
4104 | Serge | 2185 | intel_encoder->enable = vlv_enable_hdmi; |
4560 | Serge | 2186 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
4104 | Serge | 2187 | } else { |
5060 | serge | 2188 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
6084 | serge | 2189 | if (HAS_PCH_CPT(dev)) |
2190 | intel_encoder->enable = cpt_enable_hdmi; |
||
2191 | else if (HAS_PCH_IBX(dev)) |
||
2192 | intel_encoder->enable = ibx_enable_hdmi; |
||
2193 | else |
||
2194 | intel_encoder->enable = g4x_enable_hdmi; |
||
4104 | Serge | 2195 | } |
3243 | Serge | 2196 | |
2197 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
||
5060 | serge | 2198 | if (IS_CHERRYVIEW(dev)) { |
2199 | if (port == PORT_D) |
||
2200 | intel_encoder->crtc_mask = 1 << 2; |
||
2201 | else |
||
2202 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
||
2203 | } else { |
||
6084 | serge | 2204 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
5060 | serge | 2205 | } |
2206 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
||
2207 | /* |
||
2208 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems |
||
2209 | * to work on real hardware. And since g4x can send infoframes to |
||
2210 | * only one port anyway, nothing is lost by allowing it. |
||
2211 | */ |
||
2212 | if (IS_G4X(dev)) |
||
2213 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; |
||
3243 | Serge | 2214 | |
2215 | intel_dig_port->port = port; |
||
3746 | Serge | 2216 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
3243 | Serge | 2217 | intel_dig_port->dp.output_reg = 0; |
2218 | |||
2219 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
||
2220 | }><>><>><>><>><>><>><>><>>>><>><>><>>><>>><>> |