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Rev | Author | Line No. | Line |
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2330 | Serge | 1 | /* |
2 | * Copyright 2006 Dave Airlie |
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3 | * Copyright © 2006-2009 Intel Corporation |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice (including the next |
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13 | * paragraph) shall be included in all copies or substantial portions of the |
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14 | * Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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22 | * DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: |
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25 | * Eric Anholt |
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26 | * Jesse Barnes |
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27 | */ |
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28 | |||
29 | #include |
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30 | #include |
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3031 | serge | 31 | #include |
32 | #include |
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33 | #include |
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34 | #include |
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2330 | Serge | 35 | #include "intel_drv.h" |
3031 | serge | 36 | #include |
2330 | Serge | 37 | #include "i915_drv.h" |
38 | |||
3243 | Serge | 39 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
40 | { |
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41 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
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42 | } |
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43 | |||
3031 | serge | 44 | static void |
45 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) |
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46 | { |
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3243 | Serge | 47 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
3031 | serge | 48 | struct drm_i915_private *dev_priv = dev->dev_private; |
49 | uint32_t enabled_bits; |
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2330 | Serge | 50 | |
3480 | Serge | 51 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
3031 | serge | 52 | |
53 | WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits, |
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54 | "HDMI port enabled, expecting disabled\n"); |
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55 | } |
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56 | |||
57 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
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2330 | Serge | 58 | { |
3243 | Serge | 59 | struct intel_digital_port *intel_dig_port = |
60 | container_of(encoder, struct intel_digital_port, base.base); |
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61 | return &intel_dig_port->hdmi; |
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2330 | Serge | 62 | } |
63 | |||
64 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
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65 | { |
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3243 | Serge | 66 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
2330 | Serge | 67 | } |
68 | |||
69 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
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70 | { |
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71 | uint8_t *data = (uint8_t *)frame; |
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72 | uint8_t sum = 0; |
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73 | unsigned i; |
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74 | |||
75 | frame->checksum = 0; |
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76 | frame->ecc = 0; |
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77 | |||
2342 | Serge | 78 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
2330 | Serge | 79 | sum += data[i]; |
80 | |||
81 | frame->checksum = 0x100 - sum; |
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82 | } |
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83 | |||
3031 | serge | 84 | static u32 g4x_infoframe_index(struct dip_infoframe *frame) |
2330 | Serge | 85 | { |
3031 | serge | 86 | switch (frame->type) { |
87 | case DIP_TYPE_AVI: |
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88 | return VIDEO_DIP_SELECT_AVI; |
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89 | case DIP_TYPE_SPD: |
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90 | return VIDEO_DIP_SELECT_SPD; |
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91 | default: |
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92 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
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93 | return 0; |
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94 | } |
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95 | } |
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2330 | Serge | 96 | |
3031 | serge | 97 | static u32 g4x_infoframe_enable(struct dip_infoframe *frame) |
98 | { |
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2330 | Serge | 99 | switch (frame->type) { |
100 | case DIP_TYPE_AVI: |
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3031 | serge | 101 | return VIDEO_DIP_ENABLE_AVI; |
2330 | Serge | 102 | case DIP_TYPE_SPD: |
3031 | serge | 103 | return VIDEO_DIP_ENABLE_SPD; |
2330 | Serge | 104 | default: |
105 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
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3031 | serge | 106 | return 0; |
2330 | Serge | 107 | } |
3031 | serge | 108 | } |
2330 | Serge | 109 | |
3031 | serge | 110 | static u32 hsw_infoframe_enable(struct dip_infoframe *frame) |
111 | { |
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112 | switch (frame->type) { |
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113 | case DIP_TYPE_AVI: |
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114 | return VIDEO_DIP_ENABLE_AVI_HSW; |
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115 | case DIP_TYPE_SPD: |
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116 | return VIDEO_DIP_ENABLE_SPD_HSW; |
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117 | default: |
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118 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
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119 | return 0; |
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120 | } |
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2330 | Serge | 121 | } |
122 | |||
3031 | serge | 123 | static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe) |
2330 | Serge | 124 | { |
125 | switch (frame->type) { |
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126 | case DIP_TYPE_AVI: |
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3031 | serge | 127 | return HSW_TVIDEO_DIP_AVI_DATA(pipe); |
2330 | Serge | 128 | case DIP_TYPE_SPD: |
3031 | serge | 129 | return HSW_TVIDEO_DIP_SPD_DATA(pipe); |
2330 | Serge | 130 | default: |
131 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
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3031 | serge | 132 | return 0; |
2330 | Serge | 133 | } |
134 | } |
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135 | |||
3031 | serge | 136 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
2330 | Serge | 137 | struct dip_infoframe *frame) |
138 | { |
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139 | uint32_t *data = (uint32_t *)frame; |
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140 | struct drm_device *dev = encoder->dev; |
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141 | struct drm_i915_private *dev_priv = dev->dev_private; |
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3031 | serge | 142 | u32 val = I915_READ(VIDEO_DIP_CTL); |
2330 | Serge | 143 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
144 | |||
3031 | serge | 145 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
2330 | Serge | 146 | |
3031 | serge | 147 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
148 | val |= g4x_infoframe_index(frame); |
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2330 | Serge | 149 | |
3031 | serge | 150 | val &= ~g4x_infoframe_enable(frame); |
2330 | Serge | 151 | |
3031 | serge | 152 | I915_WRITE(VIDEO_DIP_CTL, val); |
2330 | Serge | 153 | |
3031 | serge | 154 | mmiowb(); |
2330 | Serge | 155 | for (i = 0; i < len; i += 4) { |
156 | I915_WRITE(VIDEO_DIP_DATA, *data); |
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157 | data++; |
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158 | } |
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3031 | serge | 159 | /* Write every possible data byte to force correct ECC calculation. */ |
160 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
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161 | I915_WRITE(VIDEO_DIP_DATA, 0); |
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162 | mmiowb(); |
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2330 | Serge | 163 | |
3031 | serge | 164 | val |= g4x_infoframe_enable(frame); |
165 | val &= ~VIDEO_DIP_FREQ_MASK; |
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166 | val |= VIDEO_DIP_FREQ_VSYNC; |
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2330 | Serge | 167 | |
3031 | serge | 168 | I915_WRITE(VIDEO_DIP_CTL, val); |
169 | POSTING_READ(VIDEO_DIP_CTL); |
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2330 | Serge | 170 | } |
171 | |||
3031 | serge | 172 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
2330 | Serge | 173 | struct dip_infoframe *frame) |
174 | { |
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175 | uint32_t *data = (uint32_t *)frame; |
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176 | struct drm_device *dev = encoder->dev; |
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177 | struct drm_i915_private *dev_priv = dev->dev_private; |
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3031 | serge | 178 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
2330 | Serge | 179 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
180 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
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3031 | serge | 181 | u32 val = I915_READ(reg); |
2330 | Serge | 182 | |
3031 | serge | 183 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
2330 | Serge | 184 | |
3031 | serge | 185 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
186 | val |= g4x_infoframe_index(frame); |
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2330 | Serge | 187 | |
3031 | serge | 188 | val &= ~g4x_infoframe_enable(frame); |
189 | |||
190 | I915_WRITE(reg, val); |
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191 | |||
192 | mmiowb(); |
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193 | for (i = 0; i < len; i += 4) { |
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194 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
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195 | data++; |
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196 | } |
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197 | /* Write every possible data byte to force correct ECC calculation. */ |
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198 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
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199 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); |
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200 | mmiowb(); |
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201 | |||
202 | val |= g4x_infoframe_enable(frame); |
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203 | val &= ~VIDEO_DIP_FREQ_MASK; |
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204 | val |= VIDEO_DIP_FREQ_VSYNC; |
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205 | |||
206 | I915_WRITE(reg, val); |
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207 | POSTING_READ(reg); |
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208 | } |
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209 | |||
210 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
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211 | struct dip_infoframe *frame) |
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212 | { |
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213 | uint32_t *data = (uint32_t *)frame; |
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214 | struct drm_device *dev = encoder->dev; |
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215 | struct drm_i915_private *dev_priv = dev->dev_private; |
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216 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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217 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
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218 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
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219 | u32 val = I915_READ(reg); |
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220 | |||
221 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
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222 | |||
2342 | Serge | 223 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
3031 | serge | 224 | val |= g4x_infoframe_index(frame); |
2330 | Serge | 225 | |
3031 | serge | 226 | /* The DIP control register spec says that we need to update the AVI |
227 | * infoframe without clearing its enable bit */ |
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228 | if (frame->type != DIP_TYPE_AVI) |
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229 | val &= ~g4x_infoframe_enable(frame); |
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2330 | Serge | 230 | |
3031 | serge | 231 | I915_WRITE(reg, val); |
232 | |||
233 | mmiowb(); |
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2330 | Serge | 234 | for (i = 0; i < len; i += 4) { |
235 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
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236 | data++; |
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237 | } |
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3031 | serge | 238 | /* Write every possible data byte to force correct ECC calculation. */ |
239 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
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240 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); |
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241 | mmiowb(); |
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2330 | Serge | 242 | |
3031 | serge | 243 | val |= g4x_infoframe_enable(frame); |
244 | val &= ~VIDEO_DIP_FREQ_MASK; |
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245 | val |= VIDEO_DIP_FREQ_VSYNC; |
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2330 | Serge | 246 | |
3031 | serge | 247 | I915_WRITE(reg, val); |
248 | POSTING_READ(reg); |
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2330 | Serge | 249 | } |
3031 | serge | 250 | |
251 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
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252 | struct dip_infoframe *frame) |
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253 | { |
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254 | uint32_t *data = (uint32_t *)frame; |
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255 | struct drm_device *dev = encoder->dev; |
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256 | struct drm_i915_private *dev_priv = dev->dev_private; |
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257 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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258 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
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259 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
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260 | u32 val = I915_READ(reg); |
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261 | |||
262 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
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263 | |||
264 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
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265 | val |= g4x_infoframe_index(frame); |
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266 | |||
267 | val &= ~g4x_infoframe_enable(frame); |
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268 | |||
269 | I915_WRITE(reg, val); |
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270 | |||
271 | mmiowb(); |
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272 | for (i = 0; i < len; i += 4) { |
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273 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
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274 | data++; |
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275 | } |
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276 | /* Write every possible data byte to force correct ECC calculation. */ |
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277 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
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278 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); |
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279 | mmiowb(); |
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280 | |||
281 | val |= g4x_infoframe_enable(frame); |
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282 | val &= ~VIDEO_DIP_FREQ_MASK; |
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283 | val |= VIDEO_DIP_FREQ_VSYNC; |
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284 | |||
285 | I915_WRITE(reg, val); |
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286 | POSTING_READ(reg); |
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287 | } |
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288 | |||
289 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
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290 | struct dip_infoframe *frame) |
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291 | { |
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292 | uint32_t *data = (uint32_t *)frame; |
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293 | struct drm_device *dev = encoder->dev; |
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294 | struct drm_i915_private *dev_priv = dev->dev_private; |
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295 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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296 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); |
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297 | u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe); |
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298 | unsigned int i, len = DIP_HEADER_SIZE + frame->len; |
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299 | u32 val = I915_READ(ctl_reg); |
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300 | |||
301 | if (data_reg == 0) |
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302 | return; |
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303 | |||
304 | val &= ~hsw_infoframe_enable(frame); |
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305 | I915_WRITE(ctl_reg, val); |
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306 | |||
307 | mmiowb(); |
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308 | for (i = 0; i < len; i += 4) { |
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309 | I915_WRITE(data_reg + i, *data); |
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310 | data++; |
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311 | } |
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312 | /* Write every possible data byte to force correct ECC calculation. */ |
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313 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
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314 | I915_WRITE(data_reg + i, 0); |
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315 | mmiowb(); |
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316 | |||
317 | val |= hsw_infoframe_enable(frame); |
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318 | I915_WRITE(ctl_reg, val); |
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319 | POSTING_READ(ctl_reg); |
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320 | } |
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321 | |||
2330 | Serge | 322 | static void intel_set_infoframe(struct drm_encoder *encoder, |
323 | struct dip_infoframe *frame) |
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324 | { |
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325 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
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326 | |||
327 | intel_dip_infoframe_csum(frame); |
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328 | intel_hdmi->write_infoframe(encoder, frame); |
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329 | } |
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330 | |||
3031 | serge | 331 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
332 | struct drm_display_mode *adjusted_mode) |
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2330 | Serge | 333 | { |
3480 | Serge | 334 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
2330 | Serge | 335 | struct dip_infoframe avi_if = { |
336 | .type = DIP_TYPE_AVI, |
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337 | .ver = DIP_VERSION_AVI, |
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338 | .len = DIP_LEN_AVI, |
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339 | }; |
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340 | |||
3031 | serge | 341 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
342 | avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; |
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343 | |||
3480 | Serge | 344 | if (intel_hdmi->rgb_quant_range_selectable) { |
345 | if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) |
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346 | avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED; |
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347 | else |
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348 | avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL; |
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349 | } |
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3243 | Serge | 350 | |
3480 | Serge | 351 | avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode); |
352 | |||
2330 | Serge | 353 | intel_set_infoframe(encoder, &avi_if); |
354 | } |
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355 | |||
356 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
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357 | { |
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358 | struct dip_infoframe spd_if; |
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359 | |||
360 | memset(&spd_if, 0, sizeof(spd_if)); |
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361 | spd_if.type = DIP_TYPE_SPD; |
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362 | spd_if.ver = DIP_VERSION_SPD; |
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363 | spd_if.len = DIP_LEN_SPD; |
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364 | strcpy(spd_if.body.spd.vn, "Intel"); |
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365 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); |
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366 | spd_if.body.spd.sdi = DIP_SPD_PC; |
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367 | |||
368 | intel_set_infoframe(encoder, &spd_if); |
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369 | } |
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370 | |||
3031 | serge | 371 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
372 | struct drm_display_mode *adjusted_mode) |
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373 | { |
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374 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
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3480 | Serge | 375 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
376 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
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3031 | serge | 377 | u32 reg = VIDEO_DIP_CTL; |
378 | u32 val = I915_READ(reg); |
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379 | u32 port; |
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380 | |||
381 | assert_hdmi_port_disabled(intel_hdmi); |
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382 | |||
383 | /* If the registers were not initialized yet, they might be zeroes, |
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384 | * which means we're selecting the AVI DIP and we're setting its |
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385 | * frequency to once. This seems to really confuse the HW and make |
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386 | * things stop working (the register spec says the AVI always needs to |
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387 | * be sent every VSync). So here we avoid writing to the register more |
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388 | * than we need and also explicitly select the AVI DIP and explicitly |
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389 | * set its frequency to every VSync. Avoiding to write it twice seems to |
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390 | * be enough to solve the problem, but being defensive shouldn't hurt us |
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391 | * either. */ |
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392 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
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393 | |||
394 | if (!intel_hdmi->has_hdmi_sink) { |
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395 | if (!(val & VIDEO_DIP_ENABLE)) |
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396 | return; |
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397 | val &= ~VIDEO_DIP_ENABLE; |
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398 | I915_WRITE(reg, val); |
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399 | POSTING_READ(reg); |
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400 | return; |
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401 | } |
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402 | |||
3480 | Serge | 403 | switch (intel_dig_port->port) { |
404 | case PORT_B: |
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3031 | serge | 405 | port = VIDEO_DIP_PORT_B; |
406 | break; |
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3480 | Serge | 407 | case PORT_C: |
3031 | serge | 408 | port = VIDEO_DIP_PORT_C; |
409 | break; |
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410 | default: |
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411 | BUG(); |
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412 | return; |
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413 | } |
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414 | |||
415 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
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416 | if (val & VIDEO_DIP_ENABLE) { |
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417 | val &= ~VIDEO_DIP_ENABLE; |
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418 | I915_WRITE(reg, val); |
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419 | POSTING_READ(reg); |
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420 | } |
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421 | val &= ~VIDEO_DIP_PORT_MASK; |
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422 | val |= port; |
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423 | } |
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424 | |||
425 | val |= VIDEO_DIP_ENABLE; |
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426 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
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427 | |||
428 | I915_WRITE(reg, val); |
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429 | POSTING_READ(reg); |
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430 | |||
431 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
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432 | intel_hdmi_set_spd_infoframe(encoder); |
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433 | } |
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434 | |||
435 | static void ibx_set_infoframes(struct drm_encoder *encoder, |
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436 | struct drm_display_mode *adjusted_mode) |
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437 | { |
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438 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
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439 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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3480 | Serge | 440 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
441 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
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3031 | serge | 442 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
443 | u32 val = I915_READ(reg); |
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444 | u32 port; |
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445 | |||
446 | assert_hdmi_port_disabled(intel_hdmi); |
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447 | |||
448 | /* See the big comment in g4x_set_infoframes() */ |
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449 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
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450 | |||
451 | if (!intel_hdmi->has_hdmi_sink) { |
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452 | if (!(val & VIDEO_DIP_ENABLE)) |
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453 | return; |
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454 | val &= ~VIDEO_DIP_ENABLE; |
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455 | I915_WRITE(reg, val); |
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456 | POSTING_READ(reg); |
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457 | return; |
||
458 | } |
||
459 | |||
3480 | Serge | 460 | switch (intel_dig_port->port) { |
461 | case PORT_B: |
||
3031 | serge | 462 | port = VIDEO_DIP_PORT_B; |
463 | break; |
||
3480 | Serge | 464 | case PORT_C: |
3031 | serge | 465 | port = VIDEO_DIP_PORT_C; |
466 | break; |
||
3480 | Serge | 467 | case PORT_D: |
3031 | serge | 468 | port = VIDEO_DIP_PORT_D; |
469 | break; |
||
470 | default: |
||
471 | BUG(); |
||
472 | return; |
||
473 | } |
||
474 | |||
475 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
||
476 | if (val & VIDEO_DIP_ENABLE) { |
||
477 | val &= ~VIDEO_DIP_ENABLE; |
||
478 | I915_WRITE(reg, val); |
||
479 | POSTING_READ(reg); |
||
480 | } |
||
481 | val &= ~VIDEO_DIP_PORT_MASK; |
||
482 | val |= port; |
||
483 | } |
||
484 | |||
485 | val |= VIDEO_DIP_ENABLE; |
||
486 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
||
487 | VIDEO_DIP_ENABLE_GCP); |
||
488 | |||
489 | I915_WRITE(reg, val); |
||
490 | POSTING_READ(reg); |
||
491 | |||
492 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
||
493 | intel_hdmi_set_spd_infoframe(encoder); |
||
494 | } |
||
495 | |||
496 | static void cpt_set_infoframes(struct drm_encoder *encoder, |
||
497 | struct drm_display_mode *adjusted_mode) |
||
498 | { |
||
499 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
||
500 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
||
501 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
||
502 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
||
503 | u32 val = I915_READ(reg); |
||
504 | |||
505 | assert_hdmi_port_disabled(intel_hdmi); |
||
506 | |||
507 | /* See the big comment in g4x_set_infoframes() */ |
||
508 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
||
509 | |||
510 | if (!intel_hdmi->has_hdmi_sink) { |
||
511 | if (!(val & VIDEO_DIP_ENABLE)) |
||
512 | return; |
||
513 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); |
||
514 | I915_WRITE(reg, val); |
||
515 | POSTING_READ(reg); |
||
516 | return; |
||
517 | } |
||
518 | |||
519 | /* Set both together, unset both together: see the spec. */ |
||
520 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; |
||
521 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
||
522 | VIDEO_DIP_ENABLE_GCP); |
||
523 | |||
524 | I915_WRITE(reg, val); |
||
525 | POSTING_READ(reg); |
||
526 | |||
527 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
||
528 | intel_hdmi_set_spd_infoframe(encoder); |
||
529 | } |
||
530 | |||
531 | static void vlv_set_infoframes(struct drm_encoder *encoder, |
||
532 | struct drm_display_mode *adjusted_mode) |
||
533 | { |
||
534 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
||
535 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
||
536 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
||
537 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
||
538 | u32 val = I915_READ(reg); |
||
539 | |||
540 | assert_hdmi_port_disabled(intel_hdmi); |
||
541 | |||
542 | /* See the big comment in g4x_set_infoframes() */ |
||
543 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
||
544 | |||
545 | if (!intel_hdmi->has_hdmi_sink) { |
||
546 | if (!(val & VIDEO_DIP_ENABLE)) |
||
547 | return; |
||
548 | val &= ~VIDEO_DIP_ENABLE; |
||
549 | I915_WRITE(reg, val); |
||
550 | POSTING_READ(reg); |
||
551 | return; |
||
552 | } |
||
553 | |||
554 | val |= VIDEO_DIP_ENABLE; |
||
555 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
||
556 | VIDEO_DIP_ENABLE_GCP); |
||
557 | |||
558 | I915_WRITE(reg, val); |
||
559 | POSTING_READ(reg); |
||
560 | |||
561 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
||
562 | intel_hdmi_set_spd_infoframe(encoder); |
||
563 | } |
||
564 | |||
565 | static void hsw_set_infoframes(struct drm_encoder *encoder, |
||
566 | struct drm_display_mode *adjusted_mode) |
||
567 | { |
||
568 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
||
569 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
||
570 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
||
571 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); |
||
572 | u32 val = I915_READ(reg); |
||
573 | |||
574 | assert_hdmi_port_disabled(intel_hdmi); |
||
575 | |||
576 | if (!intel_hdmi->has_hdmi_sink) { |
||
577 | I915_WRITE(reg, 0); |
||
578 | POSTING_READ(reg); |
||
579 | return; |
||
580 | } |
||
581 | |||
582 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
||
583 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); |
||
584 | |||
585 | I915_WRITE(reg, val); |
||
586 | POSTING_READ(reg); |
||
587 | |||
588 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
||
589 | intel_hdmi_set_spd_infoframe(encoder); |
||
590 | } |
||
591 | |||
2330 | Serge | 592 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
593 | struct drm_display_mode *mode, |
||
594 | struct drm_display_mode *adjusted_mode) |
||
595 | { |
||
596 | struct drm_device *dev = encoder->dev; |
||
597 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3031 | serge | 598 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
2330 | Serge | 599 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
600 | u32 sdvox; |
||
601 | |||
3031 | serge | 602 | sdvox = SDVO_ENCODING_HDMI; |
2330 | Serge | 603 | if (!HAS_PCH_SPLIT(dev)) |
604 | sdvox |= intel_hdmi->color_range; |
||
605 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
||
606 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; |
||
607 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
||
608 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; |
||
609 | |||
610 | if (intel_crtc->bpp > 24) |
||
611 | sdvox |= COLOR_FORMAT_12bpc; |
||
612 | else |
||
613 | sdvox |= COLOR_FORMAT_8bpc; |
||
614 | |||
615 | /* Required on CPT */ |
||
616 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) |
||
617 | sdvox |= HDMI_MODE_SELECT; |
||
618 | |||
619 | if (intel_hdmi->has_audio) { |
||
2342 | Serge | 620 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
621 | pipe_name(intel_crtc->pipe)); |
||
2330 | Serge | 622 | sdvox |= SDVO_AUDIO_ENABLE; |
623 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
||
2342 | Serge | 624 | intel_write_eld(encoder, adjusted_mode); |
2330 | Serge | 625 | } |
626 | |||
627 | if (HAS_PCH_CPT(dev)) |
||
2342 | Serge | 628 | sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); |
3031 | serge | 629 | else if (intel_crtc->pipe == PIPE_B) |
2330 | Serge | 630 | sdvox |= SDVO_PIPE_B_SELECT; |
631 | |||
632 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
||
633 | POSTING_READ(intel_hdmi->sdvox_reg); |
||
634 | |||
3031 | serge | 635 | intel_hdmi->set_infoframes(encoder, adjusted_mode); |
2330 | Serge | 636 | } |
637 | |||
3031 | serge | 638 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
639 | enum pipe *pipe) |
||
2330 | Serge | 640 | { |
3031 | serge | 641 | struct drm_device *dev = encoder->base.dev; |
2330 | Serge | 642 | struct drm_i915_private *dev_priv = dev->dev_private; |
3031 | serge | 643 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
644 | u32 tmp; |
||
645 | |||
646 | tmp = I915_READ(intel_hdmi->sdvox_reg); |
||
647 | |||
648 | if (!(tmp & SDVO_ENABLE)) |
||
649 | return false; |
||
650 | |||
651 | if (HAS_PCH_CPT(dev)) |
||
652 | *pipe = PORT_TO_PIPE_CPT(tmp); |
||
653 | else |
||
654 | *pipe = PORT_TO_PIPE(tmp); |
||
655 | |||
656 | return true; |
||
657 | } |
||
658 | |||
659 | static void intel_enable_hdmi(struct intel_encoder *encoder) |
||
660 | { |
||
661 | struct drm_device *dev = encoder->base.dev; |
||
662 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
663 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
||
2330 | Serge | 664 | u32 temp; |
2342 | Serge | 665 | u32 enable_bits = SDVO_ENABLE; |
2330 | Serge | 666 | |
2342 | Serge | 667 | if (intel_hdmi->has_audio) |
668 | enable_bits |= SDVO_AUDIO_ENABLE; |
||
669 | |||
2330 | Serge | 670 | temp = I915_READ(intel_hdmi->sdvox_reg); |
671 | |||
3031 | serge | 672 | /* HW workaround for IBX, we need to move the port to transcoder A |
673 | * before disabling it. */ |
||
674 | if (HAS_PCH_IBX(dev)) { |
||
675 | struct drm_crtc *crtc = encoder->base.crtc; |
||
676 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; |
||
677 | |||
678 | /* Restore the transcoder select bit. */ |
||
679 | if (pipe == PIPE_B) |
||
680 | enable_bits |= SDVO_PIPE_B_SELECT; |
||
681 | } |
||
682 | |||
2330 | Serge | 683 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
684 | * we do this anyway which shows more stable in testing. |
||
685 | */ |
||
686 | if (HAS_PCH_SPLIT(dev)) { |
||
687 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
||
688 | POSTING_READ(intel_hdmi->sdvox_reg); |
||
689 | } |
||
690 | |||
3031 | serge | 691 | temp |= enable_bits; |
692 | |||
693 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
||
694 | POSTING_READ(intel_hdmi->sdvox_reg); |
||
695 | |||
696 | /* HW workaround, need to write this twice for issue that may result |
||
697 | * in first write getting masked. |
||
698 | */ |
||
699 | if (HAS_PCH_SPLIT(dev)) { |
||
700 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
||
701 | POSTING_READ(intel_hdmi->sdvox_reg); |
||
2330 | Serge | 702 | } |
3031 | serge | 703 | } |
2330 | Serge | 704 | |
3031 | serge | 705 | static void intel_disable_hdmi(struct intel_encoder *encoder) |
706 | { |
||
707 | struct drm_device *dev = encoder->base.dev; |
||
708 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
709 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
||
710 | u32 temp; |
||
711 | u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; |
||
712 | |||
713 | temp = I915_READ(intel_hdmi->sdvox_reg); |
||
714 | |||
715 | /* HW workaround for IBX, we need to move the port to transcoder A |
||
716 | * before disabling it. */ |
||
717 | if (HAS_PCH_IBX(dev)) { |
||
718 | struct drm_crtc *crtc = encoder->base.crtc; |
||
719 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; |
||
720 | |||
721 | if (temp & SDVO_PIPE_B_SELECT) { |
||
722 | temp &= ~SDVO_PIPE_B_SELECT; |
||
723 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
||
724 | POSTING_READ(intel_hdmi->sdvox_reg); |
||
725 | |||
726 | /* Again we need to write this twice. */ |
||
727 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
||
728 | POSTING_READ(intel_hdmi->sdvox_reg); |
||
729 | |||
730 | /* Transcoder selection bits only update |
||
731 | * effectively on vblank. */ |
||
732 | if (crtc) |
||
733 | intel_wait_for_vblank(dev, pipe); |
||
734 | else |
||
735 | msleep(50); |
||
736 | } |
||
737 | } |
||
738 | |||
739 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
||
740 | * we do this anyway which shows more stable in testing. |
||
741 | */ |
||
742 | if (HAS_PCH_SPLIT(dev)) { |
||
743 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
||
744 | POSTING_READ(intel_hdmi->sdvox_reg); |
||
745 | } |
||
746 | |||
747 | temp &= ~enable_bits; |
||
748 | |||
2330 | Serge | 749 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
750 | POSTING_READ(intel_hdmi->sdvox_reg); |
||
751 | |||
752 | /* HW workaround, need to write this twice for issue that may result |
||
753 | * in first write getting masked. |
||
754 | */ |
||
755 | if (HAS_PCH_SPLIT(dev)) { |
||
756 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
||
757 | POSTING_READ(intel_hdmi->sdvox_reg); |
||
758 | } |
||
759 | } |
||
760 | |||
761 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
||
762 | struct drm_display_mode *mode) |
||
763 | { |
||
764 | if (mode->clock > 165000) |
||
765 | return MODE_CLOCK_HIGH; |
||
766 | if (mode->clock < 20000) |
||
767 | return MODE_CLOCK_LOW; |
||
768 | |||
769 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
||
770 | return MODE_NO_DBLESCAN; |
||
771 | |||
772 | return MODE_OK; |
||
773 | } |
||
774 | |||
3243 | Serge | 775 | bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, |
3031 | serge | 776 | const struct drm_display_mode *mode, |
2330 | Serge | 777 | struct drm_display_mode *adjusted_mode) |
778 | { |
||
3480 | Serge | 779 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
2330 | Serge | 780 | |
3480 | Serge | 781 | if (intel_hdmi->color_range_auto) { |
782 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ |
||
783 | if (intel_hdmi->has_hdmi_sink && |
||
784 | drm_match_cea_mode(adjusted_mode) > 1) |
||
785 | intel_hdmi->color_range = SDVO_COLOR_RANGE_16_235; |
||
786 | else |
||
787 | intel_hdmi->color_range = 0; |
||
3031 | serge | 788 | } |
789 | |||
3480 | Serge | 790 | if (intel_hdmi->color_range) |
791 | adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE; |
||
792 | |||
793 | return true; |
||
3031 | serge | 794 | } |
795 | |||
2330 | Serge | 796 | static enum drm_connector_status |
797 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
||
798 | { |
||
3480 | Serge | 799 | struct drm_device *dev = connector->dev; |
2330 | Serge | 800 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
3243 | Serge | 801 | struct intel_digital_port *intel_dig_port = |
802 | hdmi_to_dig_port(intel_hdmi); |
||
803 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
||
3480 | Serge | 804 | struct drm_i915_private *dev_priv = dev->dev_private; |
2330 | Serge | 805 | struct edid *edid; |
806 | enum drm_connector_status status = connector_status_disconnected; |
||
807 | |||
808 | intel_hdmi->has_hdmi_sink = false; |
||
809 | intel_hdmi->has_audio = false; |
||
3480 | Serge | 810 | intel_hdmi->rgb_quant_range_selectable = false; |
2330 | Serge | 811 | edid = drm_get_edid(connector, |
3031 | serge | 812 | intel_gmbus_get_adapter(dev_priv, |
813 | intel_hdmi->ddc_bus)); |
||
2330 | Serge | 814 | |
815 | if (edid) { |
||
816 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
||
817 | status = connector_status_connected; |
||
3031 | serge | 818 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
819 | intel_hdmi->has_hdmi_sink = |
||
820 | drm_detect_hdmi_monitor(edid); |
||
2330 | Serge | 821 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
3480 | Serge | 822 | intel_hdmi->rgb_quant_range_selectable = |
823 | drm_rgb_quant_range_selectable(edid); |
||
2330 | Serge | 824 | } |
825 | kfree(edid); |
||
826 | } |
||
827 | |||
828 | if (status == connector_status_connected) { |
||
3031 | serge | 829 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
830 | intel_hdmi->has_audio = |
||
831 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); |
||
3243 | Serge | 832 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
2330 | Serge | 833 | } |
834 | |||
835 | return status; |
||
836 | } |
||
837 | |||
838 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
||
839 | { |
||
840 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
||
841 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
||
842 | |||
843 | /* We should parse the EDID data and find out if it's an HDMI sink so |
||
844 | * we can send audio to it. |
||
845 | */ |
||
846 | |||
847 | return intel_ddc_get_modes(connector, |
||
3031 | serge | 848 | intel_gmbus_get_adapter(dev_priv, |
849 | intel_hdmi->ddc_bus)); |
||
2330 | Serge | 850 | } |
851 | |||
852 | static bool |
||
853 | intel_hdmi_detect_audio(struct drm_connector *connector) |
||
854 | { |
||
855 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
||
856 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
||
857 | struct edid *edid; |
||
858 | bool has_audio = false; |
||
859 | |||
860 | edid = drm_get_edid(connector, |
||
3031 | serge | 861 | intel_gmbus_get_adapter(dev_priv, |
862 | intel_hdmi->ddc_bus)); |
||
2330 | Serge | 863 | if (edid) { |
864 | if (edid->input & DRM_EDID_INPUT_DIGITAL) |
||
865 | has_audio = drm_detect_monitor_audio(edid); |
||
866 | kfree(edid); |
||
867 | } |
||
868 | |||
869 | return has_audio; |
||
870 | } |
||
871 | |||
872 | static int |
||
873 | intel_hdmi_set_property(struct drm_connector *connector, |
||
874 | struct drm_property *property, |
||
875 | uint64_t val) |
||
876 | { |
||
877 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
||
3243 | Serge | 878 | struct intel_digital_port *intel_dig_port = |
879 | hdmi_to_dig_port(intel_hdmi); |
||
2330 | Serge | 880 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
881 | int ret; |
||
882 | |||
3243 | Serge | 883 | ret = drm_object_property_set_value(&connector->base, property, val); |
2330 | Serge | 884 | if (ret) |
885 | return ret; |
||
3480 | Serge | 886 | |
2330 | Serge | 887 | if (property == dev_priv->force_audio_property) { |
3031 | serge | 888 | enum hdmi_force_audio i = val; |
2330 | Serge | 889 | bool has_audio; |
890 | |||
891 | if (i == intel_hdmi->force_audio) |
||
892 | return 0; |
||
893 | |||
894 | intel_hdmi->force_audio = i; |
||
895 | |||
3031 | serge | 896 | if (i == HDMI_AUDIO_AUTO) |
2330 | Serge | 897 | has_audio = intel_hdmi_detect_audio(connector); |
898 | else |
||
3031 | serge | 899 | has_audio = (i == HDMI_AUDIO_ON); |
2330 | Serge | 900 | |
3031 | serge | 901 | if (i == HDMI_AUDIO_OFF_DVI) |
902 | intel_hdmi->has_hdmi_sink = 0; |
||
2330 | Serge | 903 | |
904 | intel_hdmi->has_audio = has_audio; |
||
905 | goto done; |
||
906 | } |
||
907 | |||
908 | if (property == dev_priv->broadcast_rgb_property) { |
||
3480 | Serge | 909 | switch (val) { |
910 | case INTEL_BROADCAST_RGB_AUTO: |
||
911 | intel_hdmi->color_range_auto = true; |
||
912 | break; |
||
913 | case INTEL_BROADCAST_RGB_FULL: |
||
914 | intel_hdmi->color_range_auto = false; |
||
915 | intel_hdmi->color_range = 0; |
||
916 | break; |
||
917 | case INTEL_BROADCAST_RGB_LIMITED: |
||
918 | intel_hdmi->color_range_auto = false; |
||
919 | intel_hdmi->color_range = SDVO_COLOR_RANGE_16_235; |
||
920 | break; |
||
921 | default: |
||
922 | return -EINVAL; |
||
923 | } |
||
2330 | Serge | 924 | goto done; |
925 | } |
||
3031 | serge | 926 | |
2330 | Serge | 927 | return -EINVAL; |
928 | |||
929 | done: |
||
3480 | Serge | 930 | if (intel_dig_port->base.base.crtc) |
931 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); |
||
2330 | Serge | 932 | |
933 | return 0; |
||
934 | } |
||
935 | |||
936 | static void intel_hdmi_destroy(struct drm_connector *connector) |
||
937 | { |
||
938 | drm_sysfs_connector_remove(connector); |
||
939 | drm_connector_cleanup(connector); |
||
940 | kfree(connector); |
||
941 | } |
||
942 | |||
943 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { |
||
944 | .mode_fixup = intel_hdmi_mode_fixup, |
||
945 | .mode_set = intel_hdmi_mode_set, |
||
946 | }; |
||
947 | |||
948 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
||
3031 | serge | 949 | .dpms = intel_connector_dpms, |
2330 | Serge | 950 | .detect = intel_hdmi_detect, |
951 | .fill_modes = drm_helper_probe_single_connector_modes, |
||
952 | .set_property = intel_hdmi_set_property, |
||
953 | .destroy = intel_hdmi_destroy, |
||
954 | }; |
||
955 | |||
956 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { |
||
957 | .get_modes = intel_hdmi_get_modes, |
||
958 | .mode_valid = intel_hdmi_mode_valid, |
||
959 | .best_encoder = intel_best_encoder, |
||
960 | }; |
||
961 | |||
962 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
||
963 | .destroy = intel_encoder_destroy, |
||
964 | }; |
||
965 | |||
966 | static void |
||
967 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) |
||
968 | { |
||
969 | intel_attach_force_audio_property(connector); |
||
970 | intel_attach_broadcast_rgb_property(connector); |
||
3480 | Serge | 971 | intel_hdmi->color_range_auto = true; |
2330 | Serge | 972 | } |
973 | |||
3243 | Serge | 974 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
975 | struct intel_connector *intel_connector) |
||
2330 | Serge | 976 | { |
3243 | Serge | 977 | struct drm_connector *connector = &intel_connector->base; |
978 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
||
979 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
||
980 | struct drm_device *dev = intel_encoder->base.dev; |
||
2330 | Serge | 981 | struct drm_i915_private *dev_priv = dev->dev_private; |
3243 | Serge | 982 | enum port port = intel_dig_port->port; |
2330 | Serge | 983 | |
984 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
||
985 | DRM_MODE_CONNECTOR_HDMIA); |
||
986 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
||
987 | |||
988 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
||
3031 | serge | 989 | connector->interlace_allowed = 1; |
2330 | Serge | 990 | connector->doublescan_allowed = 0; |
991 | |||
3031 | serge | 992 | switch (port) { |
993 | case PORT_B: |
||
2330 | Serge | 994 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
3480 | Serge | 995 | dev_priv->hotplug_supported_mask |= PORTB_HOTPLUG_INT_STATUS; |
3031 | serge | 996 | break; |
997 | case PORT_C: |
||
2330 | Serge | 998 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
3480 | Serge | 999 | dev_priv->hotplug_supported_mask |= PORTC_HOTPLUG_INT_STATUS; |
3031 | serge | 1000 | break; |
1001 | case PORT_D: |
||
2330 | Serge | 1002 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
3480 | Serge | 1003 | dev_priv->hotplug_supported_mask |= PORTD_HOTPLUG_INT_STATUS; |
3031 | serge | 1004 | break; |
1005 | case PORT_A: |
||
1006 | /* Internal port only for eDP. */ |
||
1007 | default: |
||
1008 | BUG(); |
||
2330 | Serge | 1009 | } |
1010 | |||
2342 | Serge | 1011 | if (!HAS_PCH_SPLIT(dev)) { |
3031 | serge | 1012 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
1013 | intel_hdmi->set_infoframes = g4x_set_infoframes; |
||
1014 | } else if (IS_VALLEYVIEW(dev)) { |
||
1015 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
||
1016 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
||
1017 | } else if (IS_HASWELL(dev)) { |
||
1018 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
||
1019 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
||
1020 | } else if (HAS_PCH_IBX(dev)) { |
||
1021 | intel_hdmi->write_infoframe = ibx_write_infoframe; |
||
1022 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
||
2342 | Serge | 1023 | } else { |
3031 | serge | 1024 | intel_hdmi->write_infoframe = cpt_write_infoframe; |
1025 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
||
2342 | Serge | 1026 | } |
2330 | Serge | 1027 | |
3480 | Serge | 1028 | if (HAS_DDI(dev)) |
3243 | Serge | 1029 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
1030 | else |
||
3031 | serge | 1031 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
2330 | Serge | 1032 | |
1033 | intel_hdmi_add_properties(intel_hdmi, connector); |
||
1034 | |||
1035 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
||
1036 | drm_sysfs_connector_add(connector); |
||
1037 | |||
1038 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
||
1039 | * 0xd. Failure to do so will result in spurious interrupts being |
||
1040 | * generated on the port when a cable is not attached. |
||
1041 | */ |
||
1042 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
||
1043 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
||
1044 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
||
1045 | } |
||
1046 | } |
||
3243 | Serge | 1047 | |
1048 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg, enum port port) |
||
1049 | { |
||
1050 | struct intel_digital_port *intel_dig_port; |
||
1051 | struct intel_encoder *intel_encoder; |
||
1052 | struct drm_encoder *encoder; |
||
1053 | struct intel_connector *intel_connector; |
||
1054 | |||
1055 | intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL); |
||
1056 | if (!intel_dig_port) |
||
1057 | return; |
||
1058 | |||
1059 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
||
1060 | if (!intel_connector) { |
||
1061 | kfree(intel_dig_port); |
||
1062 | return; |
||
1063 | } |
||
1064 | |||
1065 | intel_encoder = &intel_dig_port->base; |
||
1066 | encoder = &intel_encoder->base; |
||
1067 | |||
1068 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
||
1069 | DRM_MODE_ENCODER_TMDS); |
||
1070 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); |
||
1071 | |||
1072 | intel_encoder->enable = intel_enable_hdmi; |
||
1073 | intel_encoder->disable = intel_disable_hdmi; |
||
1074 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
||
1075 | |||
1076 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
||
1077 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
||
1078 | intel_encoder->cloneable = false; |
||
1079 | |||
1080 | intel_dig_port->port = port; |
||
1081 | intel_dig_port->hdmi.sdvox_reg = sdvox_reg; |
||
1082 | intel_dig_port->dp.output_reg = 0; |
||
1083 | |||
1084 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
||
1085 | }><>><>><>>>>>>>>>>>>> |