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Rev | Author | Line No. | Line |
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2330 | Serge | 1 | /* |
2 | * Copyright 2006 Dave Airlie |
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3 | * Copyright © 2006-2009 Intel Corporation |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice (including the next |
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13 | * paragraph) shall be included in all copies or substantial portions of the |
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14 | * Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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22 | * DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: |
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25 | * Eric Anholt |
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26 | * Jesse Barnes |
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27 | */ |
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28 | |||
29 | #include |
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30 | #include |
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3031 | serge | 31 | #include |
32 | #include |
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33 | #include |
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34 | #include |
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2330 | Serge | 35 | #include "intel_drv.h" |
3031 | serge | 36 | #include |
2330 | Serge | 37 | #include "i915_drv.h" |
38 | |||
3031 | serge | 39 | static void |
40 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) |
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41 | { |
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42 | struct drm_device *dev = intel_hdmi->base.base.dev; |
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43 | struct drm_i915_private *dev_priv = dev->dev_private; |
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44 | uint32_t enabled_bits; |
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2330 | Serge | 45 | |
3031 | serge | 46 | enabled_bits = IS_HASWELL(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
47 | |||
48 | WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits, |
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49 | "HDMI port enabled, expecting disabled\n"); |
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50 | } |
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51 | |||
52 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
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2330 | Serge | 53 | { |
54 | return container_of(encoder, struct intel_hdmi, base.base); |
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55 | } |
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56 | |||
57 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
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58 | { |
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59 | return container_of(intel_attached_encoder(connector), |
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60 | struct intel_hdmi, base); |
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61 | } |
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62 | |||
63 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
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64 | { |
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65 | uint8_t *data = (uint8_t *)frame; |
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66 | uint8_t sum = 0; |
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67 | unsigned i; |
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68 | |||
69 | frame->checksum = 0; |
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70 | frame->ecc = 0; |
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71 | |||
2342 | Serge | 72 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
2330 | Serge | 73 | sum += data[i]; |
74 | |||
75 | frame->checksum = 0x100 - sum; |
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76 | } |
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77 | |||
3031 | serge | 78 | static u32 g4x_infoframe_index(struct dip_infoframe *frame) |
2330 | Serge | 79 | { |
3031 | serge | 80 | switch (frame->type) { |
81 | case DIP_TYPE_AVI: |
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82 | return VIDEO_DIP_SELECT_AVI; |
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83 | case DIP_TYPE_SPD: |
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84 | return VIDEO_DIP_SELECT_SPD; |
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85 | default: |
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86 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
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87 | return 0; |
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88 | } |
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89 | } |
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2330 | Serge | 90 | |
3031 | serge | 91 | static u32 g4x_infoframe_enable(struct dip_infoframe *frame) |
92 | { |
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2330 | Serge | 93 | switch (frame->type) { |
94 | case DIP_TYPE_AVI: |
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3031 | serge | 95 | return VIDEO_DIP_ENABLE_AVI; |
2330 | Serge | 96 | case DIP_TYPE_SPD: |
3031 | serge | 97 | return VIDEO_DIP_ENABLE_SPD; |
2330 | Serge | 98 | default: |
99 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
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3031 | serge | 100 | return 0; |
2330 | Serge | 101 | } |
3031 | serge | 102 | } |
2330 | Serge | 103 | |
3031 | serge | 104 | static u32 hsw_infoframe_enable(struct dip_infoframe *frame) |
105 | { |
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106 | switch (frame->type) { |
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107 | case DIP_TYPE_AVI: |
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108 | return VIDEO_DIP_ENABLE_AVI_HSW; |
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109 | case DIP_TYPE_SPD: |
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110 | return VIDEO_DIP_ENABLE_SPD_HSW; |
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111 | default: |
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112 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
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113 | return 0; |
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114 | } |
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2330 | Serge | 115 | } |
116 | |||
3031 | serge | 117 | static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe) |
2330 | Serge | 118 | { |
119 | switch (frame->type) { |
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120 | case DIP_TYPE_AVI: |
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3031 | serge | 121 | return HSW_TVIDEO_DIP_AVI_DATA(pipe); |
2330 | Serge | 122 | case DIP_TYPE_SPD: |
3031 | serge | 123 | return HSW_TVIDEO_DIP_SPD_DATA(pipe); |
2330 | Serge | 124 | default: |
125 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
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3031 | serge | 126 | return 0; |
2330 | Serge | 127 | } |
128 | } |
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129 | |||
3031 | serge | 130 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
2330 | Serge | 131 | struct dip_infoframe *frame) |
132 | { |
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133 | uint32_t *data = (uint32_t *)frame; |
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134 | struct drm_device *dev = encoder->dev; |
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135 | struct drm_i915_private *dev_priv = dev->dev_private; |
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3031 | serge | 136 | u32 val = I915_READ(VIDEO_DIP_CTL); |
2330 | Serge | 137 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
138 | |||
3031 | serge | 139 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
2330 | Serge | 140 | |
3031 | serge | 141 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
142 | val |= g4x_infoframe_index(frame); |
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2330 | Serge | 143 | |
3031 | serge | 144 | val &= ~g4x_infoframe_enable(frame); |
2330 | Serge | 145 | |
3031 | serge | 146 | I915_WRITE(VIDEO_DIP_CTL, val); |
2330 | Serge | 147 | |
3031 | serge | 148 | mmiowb(); |
2330 | Serge | 149 | for (i = 0; i < len; i += 4) { |
150 | I915_WRITE(VIDEO_DIP_DATA, *data); |
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151 | data++; |
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152 | } |
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3031 | serge | 153 | /* Write every possible data byte to force correct ECC calculation. */ |
154 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
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155 | I915_WRITE(VIDEO_DIP_DATA, 0); |
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156 | mmiowb(); |
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2330 | Serge | 157 | |
3031 | serge | 158 | val |= g4x_infoframe_enable(frame); |
159 | val &= ~VIDEO_DIP_FREQ_MASK; |
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160 | val |= VIDEO_DIP_FREQ_VSYNC; |
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2330 | Serge | 161 | |
3031 | serge | 162 | I915_WRITE(VIDEO_DIP_CTL, val); |
163 | POSTING_READ(VIDEO_DIP_CTL); |
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2330 | Serge | 164 | } |
165 | |||
3031 | serge | 166 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
2330 | Serge | 167 | struct dip_infoframe *frame) |
168 | { |
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169 | uint32_t *data = (uint32_t *)frame; |
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170 | struct drm_device *dev = encoder->dev; |
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171 | struct drm_i915_private *dev_priv = dev->dev_private; |
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3031 | serge | 172 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
2330 | Serge | 173 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
174 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
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3031 | serge | 175 | u32 val = I915_READ(reg); |
2330 | Serge | 176 | |
3031 | serge | 177 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
2330 | Serge | 178 | |
3031 | serge | 179 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
180 | val |= g4x_infoframe_index(frame); |
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2330 | Serge | 181 | |
3031 | serge | 182 | val &= ~g4x_infoframe_enable(frame); |
183 | |||
184 | I915_WRITE(reg, val); |
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185 | |||
186 | mmiowb(); |
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187 | for (i = 0; i < len; i += 4) { |
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188 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
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189 | data++; |
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190 | } |
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191 | /* Write every possible data byte to force correct ECC calculation. */ |
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192 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
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193 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); |
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194 | mmiowb(); |
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195 | |||
196 | val |= g4x_infoframe_enable(frame); |
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197 | val &= ~VIDEO_DIP_FREQ_MASK; |
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198 | val |= VIDEO_DIP_FREQ_VSYNC; |
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199 | |||
200 | I915_WRITE(reg, val); |
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201 | POSTING_READ(reg); |
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202 | } |
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203 | |||
204 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
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205 | struct dip_infoframe *frame) |
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206 | { |
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207 | uint32_t *data = (uint32_t *)frame; |
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208 | struct drm_device *dev = encoder->dev; |
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209 | struct drm_i915_private *dev_priv = dev->dev_private; |
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210 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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211 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
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212 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
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213 | u32 val = I915_READ(reg); |
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214 | |||
215 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
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216 | |||
2342 | Serge | 217 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
3031 | serge | 218 | val |= g4x_infoframe_index(frame); |
2330 | Serge | 219 | |
3031 | serge | 220 | /* The DIP control register spec says that we need to update the AVI |
221 | * infoframe without clearing its enable bit */ |
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222 | if (frame->type != DIP_TYPE_AVI) |
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223 | val &= ~g4x_infoframe_enable(frame); |
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2330 | Serge | 224 | |
3031 | serge | 225 | I915_WRITE(reg, val); |
226 | |||
227 | mmiowb(); |
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2330 | Serge | 228 | for (i = 0; i < len; i += 4) { |
229 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
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230 | data++; |
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231 | } |
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3031 | serge | 232 | /* Write every possible data byte to force correct ECC calculation. */ |
233 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
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234 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); |
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235 | mmiowb(); |
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2330 | Serge | 236 | |
3031 | serge | 237 | val |= g4x_infoframe_enable(frame); |
238 | val &= ~VIDEO_DIP_FREQ_MASK; |
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239 | val |= VIDEO_DIP_FREQ_VSYNC; |
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2330 | Serge | 240 | |
3031 | serge | 241 | I915_WRITE(reg, val); |
242 | POSTING_READ(reg); |
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2330 | Serge | 243 | } |
3031 | serge | 244 | |
245 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
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246 | struct dip_infoframe *frame) |
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247 | { |
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248 | uint32_t *data = (uint32_t *)frame; |
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249 | struct drm_device *dev = encoder->dev; |
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250 | struct drm_i915_private *dev_priv = dev->dev_private; |
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251 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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252 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
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253 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
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254 | u32 val = I915_READ(reg); |
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255 | |||
256 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
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257 | |||
258 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
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259 | val |= g4x_infoframe_index(frame); |
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260 | |||
261 | val &= ~g4x_infoframe_enable(frame); |
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262 | |||
263 | I915_WRITE(reg, val); |
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264 | |||
265 | mmiowb(); |
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266 | for (i = 0; i < len; i += 4) { |
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267 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
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268 | data++; |
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269 | } |
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270 | /* Write every possible data byte to force correct ECC calculation. */ |
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271 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
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272 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); |
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273 | mmiowb(); |
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274 | |||
275 | val |= g4x_infoframe_enable(frame); |
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276 | val &= ~VIDEO_DIP_FREQ_MASK; |
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277 | val |= VIDEO_DIP_FREQ_VSYNC; |
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278 | |||
279 | I915_WRITE(reg, val); |
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280 | POSTING_READ(reg); |
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281 | } |
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282 | |||
283 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
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284 | struct dip_infoframe *frame) |
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285 | { |
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286 | uint32_t *data = (uint32_t *)frame; |
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287 | struct drm_device *dev = encoder->dev; |
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288 | struct drm_i915_private *dev_priv = dev->dev_private; |
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289 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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290 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); |
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291 | u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe); |
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292 | unsigned int i, len = DIP_HEADER_SIZE + frame->len; |
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293 | u32 val = I915_READ(ctl_reg); |
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294 | |||
295 | if (data_reg == 0) |
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296 | return; |
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297 | |||
298 | val &= ~hsw_infoframe_enable(frame); |
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299 | I915_WRITE(ctl_reg, val); |
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300 | |||
301 | mmiowb(); |
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302 | for (i = 0; i < len; i += 4) { |
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303 | I915_WRITE(data_reg + i, *data); |
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304 | data++; |
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305 | } |
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306 | /* Write every possible data byte to force correct ECC calculation. */ |
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307 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
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308 | I915_WRITE(data_reg + i, 0); |
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309 | mmiowb(); |
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310 | |||
311 | val |= hsw_infoframe_enable(frame); |
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312 | I915_WRITE(ctl_reg, val); |
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313 | POSTING_READ(ctl_reg); |
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314 | } |
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315 | |||
2330 | Serge | 316 | static void intel_set_infoframe(struct drm_encoder *encoder, |
317 | struct dip_infoframe *frame) |
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318 | { |
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319 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
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320 | |||
321 | intel_dip_infoframe_csum(frame); |
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322 | intel_hdmi->write_infoframe(encoder, frame); |
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323 | } |
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324 | |||
3031 | serge | 325 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
326 | struct drm_display_mode *adjusted_mode) |
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2330 | Serge | 327 | { |
328 | struct dip_infoframe avi_if = { |
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329 | .type = DIP_TYPE_AVI, |
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330 | .ver = DIP_VERSION_AVI, |
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331 | .len = DIP_LEN_AVI, |
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332 | }; |
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333 | |||
3031 | serge | 334 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
335 | avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; |
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336 | |||
2330 | Serge | 337 | intel_set_infoframe(encoder, &avi_if); |
338 | } |
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339 | |||
340 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
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341 | { |
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342 | struct dip_infoframe spd_if; |
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343 | |||
344 | memset(&spd_if, 0, sizeof(spd_if)); |
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345 | spd_if.type = DIP_TYPE_SPD; |
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346 | spd_if.ver = DIP_VERSION_SPD; |
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347 | spd_if.len = DIP_LEN_SPD; |
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348 | strcpy(spd_if.body.spd.vn, "Intel"); |
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349 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); |
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350 | spd_if.body.spd.sdi = DIP_SPD_PC; |
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351 | |||
352 | intel_set_infoframe(encoder, &spd_if); |
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353 | } |
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354 | |||
3031 | serge | 355 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
356 | struct drm_display_mode *adjusted_mode) |
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357 | { |
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358 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
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359 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
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360 | u32 reg = VIDEO_DIP_CTL; |
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361 | u32 val = I915_READ(reg); |
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362 | u32 port; |
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363 | |||
364 | assert_hdmi_port_disabled(intel_hdmi); |
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365 | |||
366 | /* If the registers were not initialized yet, they might be zeroes, |
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367 | * which means we're selecting the AVI DIP and we're setting its |
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368 | * frequency to once. This seems to really confuse the HW and make |
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369 | * things stop working (the register spec says the AVI always needs to |
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370 | * be sent every VSync). So here we avoid writing to the register more |
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371 | * than we need and also explicitly select the AVI DIP and explicitly |
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372 | * set its frequency to every VSync. Avoiding to write it twice seems to |
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373 | * be enough to solve the problem, but being defensive shouldn't hurt us |
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374 | * either. */ |
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375 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
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376 | |||
377 | if (!intel_hdmi->has_hdmi_sink) { |
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378 | if (!(val & VIDEO_DIP_ENABLE)) |
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379 | return; |
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380 | val &= ~VIDEO_DIP_ENABLE; |
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381 | I915_WRITE(reg, val); |
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382 | POSTING_READ(reg); |
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383 | return; |
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384 | } |
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385 | |||
386 | switch (intel_hdmi->sdvox_reg) { |
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387 | case SDVOB: |
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388 | port = VIDEO_DIP_PORT_B; |
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389 | break; |
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390 | case SDVOC: |
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391 | port = VIDEO_DIP_PORT_C; |
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392 | break; |
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393 | default: |
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394 | BUG(); |
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395 | return; |
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396 | } |
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397 | |||
398 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
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399 | if (val & VIDEO_DIP_ENABLE) { |
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400 | val &= ~VIDEO_DIP_ENABLE; |
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401 | I915_WRITE(reg, val); |
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402 | POSTING_READ(reg); |
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403 | } |
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404 | val &= ~VIDEO_DIP_PORT_MASK; |
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405 | val |= port; |
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406 | } |
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407 | |||
408 | val |= VIDEO_DIP_ENABLE; |
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409 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
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410 | |||
411 | I915_WRITE(reg, val); |
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412 | POSTING_READ(reg); |
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413 | |||
414 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
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415 | intel_hdmi_set_spd_infoframe(encoder); |
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416 | } |
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417 | |||
418 | static void ibx_set_infoframes(struct drm_encoder *encoder, |
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419 | struct drm_display_mode *adjusted_mode) |
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420 | { |
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421 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
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422 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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423 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
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424 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
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425 | u32 val = I915_READ(reg); |
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426 | u32 port; |
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427 | |||
428 | assert_hdmi_port_disabled(intel_hdmi); |
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429 | |||
430 | /* See the big comment in g4x_set_infoframes() */ |
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431 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
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432 | |||
433 | if (!intel_hdmi->has_hdmi_sink) { |
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434 | if (!(val & VIDEO_DIP_ENABLE)) |
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435 | return; |
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436 | val &= ~VIDEO_DIP_ENABLE; |
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437 | I915_WRITE(reg, val); |
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438 | POSTING_READ(reg); |
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439 | return; |
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440 | } |
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441 | |||
442 | switch (intel_hdmi->sdvox_reg) { |
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443 | case HDMIB: |
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444 | port = VIDEO_DIP_PORT_B; |
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445 | break; |
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446 | case HDMIC: |
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447 | port = VIDEO_DIP_PORT_C; |
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448 | break; |
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449 | case HDMID: |
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450 | port = VIDEO_DIP_PORT_D; |
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451 | break; |
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452 | default: |
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453 | BUG(); |
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454 | return; |
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455 | } |
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456 | |||
457 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
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458 | if (val & VIDEO_DIP_ENABLE) { |
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459 | val &= ~VIDEO_DIP_ENABLE; |
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460 | I915_WRITE(reg, val); |
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461 | POSTING_READ(reg); |
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462 | } |
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463 | val &= ~VIDEO_DIP_PORT_MASK; |
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464 | val |= port; |
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465 | } |
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466 | |||
467 | val |= VIDEO_DIP_ENABLE; |
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468 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
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469 | VIDEO_DIP_ENABLE_GCP); |
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470 | |||
471 | I915_WRITE(reg, val); |
||
472 | POSTING_READ(reg); |
||
473 | |||
474 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
||
475 | intel_hdmi_set_spd_infoframe(encoder); |
||
476 | } |
||
477 | |||
478 | static void cpt_set_infoframes(struct drm_encoder *encoder, |
||
479 | struct drm_display_mode *adjusted_mode) |
||
480 | { |
||
481 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
||
482 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
||
483 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
||
484 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
||
485 | u32 val = I915_READ(reg); |
||
486 | |||
487 | assert_hdmi_port_disabled(intel_hdmi); |
||
488 | |||
489 | /* See the big comment in g4x_set_infoframes() */ |
||
490 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
||
491 | |||
492 | if (!intel_hdmi->has_hdmi_sink) { |
||
493 | if (!(val & VIDEO_DIP_ENABLE)) |
||
494 | return; |
||
495 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); |
||
496 | I915_WRITE(reg, val); |
||
497 | POSTING_READ(reg); |
||
498 | return; |
||
499 | } |
||
500 | |||
501 | /* Set both together, unset both together: see the spec. */ |
||
502 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; |
||
503 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
||
504 | VIDEO_DIP_ENABLE_GCP); |
||
505 | |||
506 | I915_WRITE(reg, val); |
||
507 | POSTING_READ(reg); |
||
508 | |||
509 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
||
510 | intel_hdmi_set_spd_infoframe(encoder); |
||
511 | } |
||
512 | |||
513 | static void vlv_set_infoframes(struct drm_encoder *encoder, |
||
514 | struct drm_display_mode *adjusted_mode) |
||
515 | { |
||
516 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
||
517 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
||
518 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
||
519 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
||
520 | u32 val = I915_READ(reg); |
||
521 | |||
522 | assert_hdmi_port_disabled(intel_hdmi); |
||
523 | |||
524 | /* See the big comment in g4x_set_infoframes() */ |
||
525 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
||
526 | |||
527 | if (!intel_hdmi->has_hdmi_sink) { |
||
528 | if (!(val & VIDEO_DIP_ENABLE)) |
||
529 | return; |
||
530 | val &= ~VIDEO_DIP_ENABLE; |
||
531 | I915_WRITE(reg, val); |
||
532 | POSTING_READ(reg); |
||
533 | return; |
||
534 | } |
||
535 | |||
536 | val |= VIDEO_DIP_ENABLE; |
||
537 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
||
538 | VIDEO_DIP_ENABLE_GCP); |
||
539 | |||
540 | I915_WRITE(reg, val); |
||
541 | POSTING_READ(reg); |
||
542 | |||
543 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
||
544 | intel_hdmi_set_spd_infoframe(encoder); |
||
545 | } |
||
546 | |||
547 | static void hsw_set_infoframes(struct drm_encoder *encoder, |
||
548 | struct drm_display_mode *adjusted_mode) |
||
549 | { |
||
550 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
||
551 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
||
552 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
||
553 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); |
||
554 | u32 val = I915_READ(reg); |
||
555 | |||
556 | assert_hdmi_port_disabled(intel_hdmi); |
||
557 | |||
558 | if (!intel_hdmi->has_hdmi_sink) { |
||
559 | I915_WRITE(reg, 0); |
||
560 | POSTING_READ(reg); |
||
561 | return; |
||
562 | } |
||
563 | |||
564 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
||
565 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); |
||
566 | |||
567 | I915_WRITE(reg, val); |
||
568 | POSTING_READ(reg); |
||
569 | |||
570 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
||
571 | intel_hdmi_set_spd_infoframe(encoder); |
||
572 | } |
||
573 | |||
2330 | Serge | 574 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
575 | struct drm_display_mode *mode, |
||
576 | struct drm_display_mode *adjusted_mode) |
||
577 | { |
||
578 | struct drm_device *dev = encoder->dev; |
||
579 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3031 | serge | 580 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
2330 | Serge | 581 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
582 | u32 sdvox; |
||
583 | |||
3031 | serge | 584 | sdvox = SDVO_ENCODING_HDMI; |
2330 | Serge | 585 | if (!HAS_PCH_SPLIT(dev)) |
586 | sdvox |= intel_hdmi->color_range; |
||
587 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
||
588 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; |
||
589 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
||
590 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; |
||
591 | |||
592 | if (intel_crtc->bpp > 24) |
||
593 | sdvox |= COLOR_FORMAT_12bpc; |
||
594 | else |
||
595 | sdvox |= COLOR_FORMAT_8bpc; |
||
596 | |||
597 | /* Required on CPT */ |
||
598 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) |
||
599 | sdvox |= HDMI_MODE_SELECT; |
||
600 | |||
601 | if (intel_hdmi->has_audio) { |
||
2342 | Serge | 602 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
603 | pipe_name(intel_crtc->pipe)); |
||
2330 | Serge | 604 | sdvox |= SDVO_AUDIO_ENABLE; |
605 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
||
2342 | Serge | 606 | intel_write_eld(encoder, adjusted_mode); |
2330 | Serge | 607 | } |
608 | |||
609 | if (HAS_PCH_CPT(dev)) |
||
2342 | Serge | 610 | sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); |
3031 | serge | 611 | else if (intel_crtc->pipe == PIPE_B) |
2330 | Serge | 612 | sdvox |= SDVO_PIPE_B_SELECT; |
613 | |||
614 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
||
615 | POSTING_READ(intel_hdmi->sdvox_reg); |
||
616 | |||
3031 | serge | 617 | intel_hdmi->set_infoframes(encoder, adjusted_mode); |
2330 | Serge | 618 | } |
619 | |||
3031 | serge | 620 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
621 | enum pipe *pipe) |
||
2330 | Serge | 622 | { |
3031 | serge | 623 | struct drm_device *dev = encoder->base.dev; |
2330 | Serge | 624 | struct drm_i915_private *dev_priv = dev->dev_private; |
3031 | serge | 625 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
626 | u32 tmp; |
||
627 | |||
628 | tmp = I915_READ(intel_hdmi->sdvox_reg); |
||
629 | |||
630 | if (!(tmp & SDVO_ENABLE)) |
||
631 | return false; |
||
632 | |||
633 | if (HAS_PCH_CPT(dev)) |
||
634 | *pipe = PORT_TO_PIPE_CPT(tmp); |
||
635 | else |
||
636 | *pipe = PORT_TO_PIPE(tmp); |
||
637 | |||
638 | return true; |
||
639 | } |
||
640 | |||
641 | static void intel_enable_hdmi(struct intel_encoder *encoder) |
||
642 | { |
||
643 | struct drm_device *dev = encoder->base.dev; |
||
644 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
645 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
||
2330 | Serge | 646 | u32 temp; |
2342 | Serge | 647 | u32 enable_bits = SDVO_ENABLE; |
2330 | Serge | 648 | |
2342 | Serge | 649 | if (intel_hdmi->has_audio) |
650 | enable_bits |= SDVO_AUDIO_ENABLE; |
||
651 | |||
2330 | Serge | 652 | temp = I915_READ(intel_hdmi->sdvox_reg); |
653 | |||
3031 | serge | 654 | /* HW workaround for IBX, we need to move the port to transcoder A |
655 | * before disabling it. */ |
||
656 | if (HAS_PCH_IBX(dev)) { |
||
657 | struct drm_crtc *crtc = encoder->base.crtc; |
||
658 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; |
||
659 | |||
660 | /* Restore the transcoder select bit. */ |
||
661 | if (pipe == PIPE_B) |
||
662 | enable_bits |= SDVO_PIPE_B_SELECT; |
||
663 | } |
||
664 | |||
2330 | Serge | 665 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
666 | * we do this anyway which shows more stable in testing. |
||
667 | */ |
||
668 | if (HAS_PCH_SPLIT(dev)) { |
||
669 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
||
670 | POSTING_READ(intel_hdmi->sdvox_reg); |
||
671 | } |
||
672 | |||
3031 | serge | 673 | temp |= enable_bits; |
674 | |||
675 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
||
676 | POSTING_READ(intel_hdmi->sdvox_reg); |
||
677 | |||
678 | /* HW workaround, need to write this twice for issue that may result |
||
679 | * in first write getting masked. |
||
680 | */ |
||
681 | if (HAS_PCH_SPLIT(dev)) { |
||
682 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
||
683 | POSTING_READ(intel_hdmi->sdvox_reg); |
||
2330 | Serge | 684 | } |
3031 | serge | 685 | } |
2330 | Serge | 686 | |
3031 | serge | 687 | static void intel_disable_hdmi(struct intel_encoder *encoder) |
688 | { |
||
689 | struct drm_device *dev = encoder->base.dev; |
||
690 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
691 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
||
692 | u32 temp; |
||
693 | u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; |
||
694 | |||
695 | temp = I915_READ(intel_hdmi->sdvox_reg); |
||
696 | |||
697 | /* HW workaround for IBX, we need to move the port to transcoder A |
||
698 | * before disabling it. */ |
||
699 | if (HAS_PCH_IBX(dev)) { |
||
700 | struct drm_crtc *crtc = encoder->base.crtc; |
||
701 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; |
||
702 | |||
703 | if (temp & SDVO_PIPE_B_SELECT) { |
||
704 | temp &= ~SDVO_PIPE_B_SELECT; |
||
705 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
||
706 | POSTING_READ(intel_hdmi->sdvox_reg); |
||
707 | |||
708 | /* Again we need to write this twice. */ |
||
709 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
||
710 | POSTING_READ(intel_hdmi->sdvox_reg); |
||
711 | |||
712 | /* Transcoder selection bits only update |
||
713 | * effectively on vblank. */ |
||
714 | if (crtc) |
||
715 | intel_wait_for_vblank(dev, pipe); |
||
716 | else |
||
717 | msleep(50); |
||
718 | } |
||
719 | } |
||
720 | |||
721 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
||
722 | * we do this anyway which shows more stable in testing. |
||
723 | */ |
||
724 | if (HAS_PCH_SPLIT(dev)) { |
||
725 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
||
726 | POSTING_READ(intel_hdmi->sdvox_reg); |
||
727 | } |
||
728 | |||
729 | temp &= ~enable_bits; |
||
730 | |||
2330 | Serge | 731 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
732 | POSTING_READ(intel_hdmi->sdvox_reg); |
||
733 | |||
734 | /* HW workaround, need to write this twice for issue that may result |
||
735 | * in first write getting masked. |
||
736 | */ |
||
737 | if (HAS_PCH_SPLIT(dev)) { |
||
738 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
||
739 | POSTING_READ(intel_hdmi->sdvox_reg); |
||
740 | } |
||
741 | } |
||
742 | |||
743 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
||
744 | struct drm_display_mode *mode) |
||
745 | { |
||
746 | if (mode->clock > 165000) |
||
747 | return MODE_CLOCK_HIGH; |
||
748 | if (mode->clock < 20000) |
||
749 | return MODE_CLOCK_LOW; |
||
750 | |||
751 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
||
752 | return MODE_NO_DBLESCAN; |
||
753 | |||
754 | return MODE_OK; |
||
755 | } |
||
756 | |||
757 | static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, |
||
3031 | serge | 758 | const struct drm_display_mode *mode, |
2330 | Serge | 759 | struct drm_display_mode *adjusted_mode) |
760 | { |
||
761 | return true; |
||
762 | } |
||
763 | |||
3031 | serge | 764 | static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi) |
765 | { |
||
766 | struct drm_device *dev = intel_hdmi->base.base.dev; |
||
767 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
768 | uint32_t bit; |
||
769 | |||
770 | switch (intel_hdmi->sdvox_reg) { |
||
771 | case SDVOB: |
||
772 | bit = HDMIB_HOTPLUG_LIVE_STATUS; |
||
773 | break; |
||
774 | case SDVOC: |
||
775 | bit = HDMIC_HOTPLUG_LIVE_STATUS; |
||
776 | break; |
||
777 | default: |
||
778 | bit = 0; |
||
779 | break; |
||
780 | } |
||
781 | |||
782 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
||
783 | } |
||
784 | |||
2330 | Serge | 785 | static enum drm_connector_status |
786 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
||
787 | { |
||
788 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
||
789 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
||
790 | struct edid *edid; |
||
791 | enum drm_connector_status status = connector_status_disconnected; |
||
792 | |||
3031 | serge | 793 | if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi)) |
794 | return status; |
||
795 | |||
2330 | Serge | 796 | intel_hdmi->has_hdmi_sink = false; |
797 | intel_hdmi->has_audio = false; |
||
798 | edid = drm_get_edid(connector, |
||
3031 | serge | 799 | intel_gmbus_get_adapter(dev_priv, |
800 | intel_hdmi->ddc_bus)); |
||
2330 | Serge | 801 | |
802 | if (edid) { |
||
803 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
||
804 | status = connector_status_connected; |
||
3031 | serge | 805 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
806 | intel_hdmi->has_hdmi_sink = |
||
807 | drm_detect_hdmi_monitor(edid); |
||
2330 | Serge | 808 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
809 | } |
||
810 | kfree(edid); |
||
811 | } |
||
812 | |||
813 | if (status == connector_status_connected) { |
||
3031 | serge | 814 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
815 | intel_hdmi->has_audio = |
||
816 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); |
||
2330 | Serge | 817 | } |
818 | |||
819 | return status; |
||
820 | } |
||
821 | |||
822 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
||
823 | { |
||
824 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
||
825 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
||
826 | |||
827 | /* We should parse the EDID data and find out if it's an HDMI sink so |
||
828 | * we can send audio to it. |
||
829 | */ |
||
830 | |||
831 | return intel_ddc_get_modes(connector, |
||
3031 | serge | 832 | intel_gmbus_get_adapter(dev_priv, |
833 | intel_hdmi->ddc_bus)); |
||
2330 | Serge | 834 | } |
835 | |||
836 | static bool |
||
837 | intel_hdmi_detect_audio(struct drm_connector *connector) |
||
838 | { |
||
839 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
||
840 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
||
841 | struct edid *edid; |
||
842 | bool has_audio = false; |
||
843 | |||
844 | edid = drm_get_edid(connector, |
||
3031 | serge | 845 | intel_gmbus_get_adapter(dev_priv, |
846 | intel_hdmi->ddc_bus)); |
||
2330 | Serge | 847 | if (edid) { |
848 | if (edid->input & DRM_EDID_INPUT_DIGITAL) |
||
849 | has_audio = drm_detect_monitor_audio(edid); |
||
850 | kfree(edid); |
||
851 | } |
||
852 | |||
853 | return has_audio; |
||
854 | } |
||
855 | |||
856 | static int |
||
857 | intel_hdmi_set_property(struct drm_connector *connector, |
||
858 | struct drm_property *property, |
||
859 | uint64_t val) |
||
860 | { |
||
861 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
||
862 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
||
863 | int ret; |
||
864 | |||
865 | ret = drm_connector_property_set_value(connector, property, val); |
||
866 | if (ret) |
||
867 | return ret; |
||
868 | #if 0 |
||
869 | if (property == dev_priv->force_audio_property) { |
||
3031 | serge | 870 | enum hdmi_force_audio i = val; |
2330 | Serge | 871 | bool has_audio; |
872 | |||
873 | if (i == intel_hdmi->force_audio) |
||
874 | return 0; |
||
875 | |||
876 | intel_hdmi->force_audio = i; |
||
877 | |||
3031 | serge | 878 | if (i == HDMI_AUDIO_AUTO) |
2330 | Serge | 879 | has_audio = intel_hdmi_detect_audio(connector); |
880 | else |
||
3031 | serge | 881 | has_audio = (i == HDMI_AUDIO_ON); |
2330 | Serge | 882 | |
3031 | serge | 883 | if (i == HDMI_AUDIO_OFF_DVI) |
884 | intel_hdmi->has_hdmi_sink = 0; |
||
2330 | Serge | 885 | |
886 | intel_hdmi->has_audio = has_audio; |
||
887 | goto done; |
||
888 | } |
||
3031 | serge | 889 | #endif |
2330 | Serge | 890 | |
891 | if (property == dev_priv->broadcast_rgb_property) { |
||
892 | if (val == !!intel_hdmi->color_range) |
||
893 | return 0; |
||
894 | |||
895 | intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; |
||
896 | goto done; |
||
897 | } |
||
3031 | serge | 898 | |
2330 | Serge | 899 | return -EINVAL; |
900 | |||
901 | done: |
||
902 | if (intel_hdmi->base.base.crtc) { |
||
903 | struct drm_crtc *crtc = intel_hdmi->base.base.crtc; |
||
3031 | serge | 904 | intel_set_mode(crtc, &crtc->mode, |
905 | crtc->x, crtc->y, crtc->fb); |
||
2330 | Serge | 906 | } |
907 | |||
908 | return 0; |
||
909 | } |
||
910 | |||
911 | static void intel_hdmi_destroy(struct drm_connector *connector) |
||
912 | { |
||
913 | drm_sysfs_connector_remove(connector); |
||
914 | drm_connector_cleanup(connector); |
||
915 | kfree(connector); |
||
916 | } |
||
917 | |||
3031 | serge | 918 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = { |
919 | .mode_fixup = intel_hdmi_mode_fixup, |
||
920 | .mode_set = intel_ddi_mode_set, |
||
921 | .disable = intel_encoder_noop, |
||
922 | }; |
||
923 | |||
2330 | Serge | 924 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { |
925 | .mode_fixup = intel_hdmi_mode_fixup, |
||
926 | .mode_set = intel_hdmi_mode_set, |
||
3031 | serge | 927 | .disable = intel_encoder_noop, |
2330 | Serge | 928 | }; |
929 | |||
930 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
||
3031 | serge | 931 | .dpms = intel_connector_dpms, |
2330 | Serge | 932 | .detect = intel_hdmi_detect, |
933 | .fill_modes = drm_helper_probe_single_connector_modes, |
||
934 | .set_property = intel_hdmi_set_property, |
||
935 | .destroy = intel_hdmi_destroy, |
||
936 | }; |
||
937 | |||
938 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { |
||
939 | .get_modes = intel_hdmi_get_modes, |
||
940 | .mode_valid = intel_hdmi_mode_valid, |
||
941 | .best_encoder = intel_best_encoder, |
||
942 | }; |
||
943 | |||
944 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
||
945 | .destroy = intel_encoder_destroy, |
||
946 | }; |
||
947 | |||
948 | static void |
||
949 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) |
||
950 | { |
||
951 | intel_attach_force_audio_property(connector); |
||
952 | intel_attach_broadcast_rgb_property(connector); |
||
953 | } |
||
954 | |||
3031 | serge | 955 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg, enum port port) |
2330 | Serge | 956 | { |
957 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
958 | struct drm_connector *connector; |
||
959 | struct intel_encoder *intel_encoder; |
||
960 | struct intel_connector *intel_connector; |
||
961 | struct intel_hdmi *intel_hdmi; |
||
962 | |||
963 | intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
||
964 | if (!intel_hdmi) |
||
965 | return; |
||
966 | |||
967 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
||
968 | if (!intel_connector) { |
||
969 | kfree(intel_hdmi); |
||
970 | return; |
||
971 | } |
||
972 | |||
973 | intel_encoder = &intel_hdmi->base; |
||
974 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
||
975 | DRM_MODE_ENCODER_TMDS); |
||
976 | |||
977 | connector = &intel_connector->base; |
||
978 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
||
979 | DRM_MODE_CONNECTOR_HDMIA); |
||
980 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
||
981 | |||
982 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
||
983 | |||
984 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
||
3031 | serge | 985 | connector->interlace_allowed = 1; |
2330 | Serge | 986 | connector->doublescan_allowed = 0; |
2342 | Serge | 987 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
2330 | Serge | 988 | |
3031 | serge | 989 | intel_encoder->cloneable = false; |
990 | |||
991 | intel_hdmi->ddi_port = port; |
||
992 | switch (port) { |
||
993 | case PORT_B: |
||
2330 | Serge | 994 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
995 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
||
3031 | serge | 996 | break; |
997 | case PORT_C: |
||
2330 | Serge | 998 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
999 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
||
3031 | serge | 1000 | break; |
1001 | case PORT_D: |
||
2330 | Serge | 1002 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
1003 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
||
3031 | serge | 1004 | break; |
1005 | case PORT_A: |
||
1006 | /* Internal port only for eDP. */ |
||
1007 | default: |
||
1008 | BUG(); |
||
2330 | Serge | 1009 | } |
1010 | |||
1011 | intel_hdmi->sdvox_reg = sdvox_reg; |
||
1012 | |||
2342 | Serge | 1013 | if (!HAS_PCH_SPLIT(dev)) { |
3031 | serge | 1014 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
1015 | intel_hdmi->set_infoframes = g4x_set_infoframes; |
||
1016 | } else if (IS_VALLEYVIEW(dev)) { |
||
1017 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
||
1018 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
||
1019 | } else if (IS_HASWELL(dev)) { |
||
1020 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
||
1021 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
||
1022 | } else if (HAS_PCH_IBX(dev)) { |
||
1023 | intel_hdmi->write_infoframe = ibx_write_infoframe; |
||
1024 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
||
2342 | Serge | 1025 | } else { |
3031 | serge | 1026 | intel_hdmi->write_infoframe = cpt_write_infoframe; |
1027 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
||
2342 | Serge | 1028 | } |
2330 | Serge | 1029 | |
3031 | serge | 1030 | if (IS_HASWELL(dev)) { |
1031 | intel_encoder->enable = intel_enable_ddi; |
||
1032 | intel_encoder->disable = intel_disable_ddi; |
||
1033 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; |
||
1034 | drm_encoder_helper_add(&intel_encoder->base, |
||
1035 | &intel_hdmi_helper_funcs_hsw); |
||
1036 | } else { |
||
1037 | intel_encoder->enable = intel_enable_hdmi; |
||
1038 | intel_encoder->disable = intel_disable_hdmi; |
||
1039 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
||
1040 | drm_encoder_helper_add(&intel_encoder->base, |
||
1041 | &intel_hdmi_helper_funcs); |
||
1042 | } |
||
1043 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
||
2330 | Serge | 1044 | |
3031 | serge | 1045 | |
2330 | Serge | 1046 | intel_hdmi_add_properties(intel_hdmi, connector); |
1047 | |||
1048 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
||
1049 | drm_sysfs_connector_add(connector); |
||
1050 | |||
1051 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
||
1052 | * 0xd. Failure to do so will result in spurious interrupts being |
||
1053 | * generated on the port when a cable is not attached. |
||
1054 | */ |
||
1055 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
||
1056 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
||
1057 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
||
1058 | } |
||
1059 | }><>><>><>>>>>>>>>>>>> |