WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/intel_hdmi.c

Rev	Author	Line No.	Line
2330	Serge	1	/*
		2	* Copyright 2006 Dave Airlie
		3	* Copyright © 2006-2009 Intel Corporation
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice (including the next
		13	* paragraph) shall be included in all copies or substantial portions of the
		14	* Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		21	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
		22	* DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors:
		25	* Eric Anholt
		26	* Jesse Barnes
		27	*/
		28
		29	#include
		30	#include
3031	serge	31	#include
4104	Serge	32	#include
3031	serge	33	#include
6084	serge	34	#include
3031	serge	35	#include
		36	#include
2330	Serge	37	#include "intel_drv.h"
3031	serge	38	#include
2330	Serge	39	#include "i915_drv.h"
		40
3243	Serge	41	static struct drm_device intel_hdmi_to_dev(struct intel_hdmi intel_hdmi)
		42	{
		43	return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
		44	}
		45
3031	serge	46	static void
		47	assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
		48	{
3243	Serge	49	struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
3031	serge	50	struct drm_i915_private *dev_priv = dev->dev_private;
		51	uint32_t enabled_bits;
2330	Serge	52
3480	Serge	53	enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
3031	serge	54
3746	Serge	55	WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
3031	serge	56	"HDMI port enabled, expecting disabled\n");
		57	}
		58
		59	struct intel_hdmi enc_to_intel_hdmi(struct drm_encoder encoder)
2330	Serge	60	{
3243	Serge	61	struct intel_digital_port *intel_dig_port =
		62	container_of(encoder, struct intel_digital_port, base.base);
		63	return &intel_dig_port->hdmi;
2330	Serge	64	}
		65
		66	static struct intel_hdmi intel_attached_hdmi(struct drm_connector connector)
		67	{
3243	Serge	68	return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
2330	Serge	69	}
		70
4104	Serge	71	static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
2330	Serge	72	{
4104	Serge	73	switch (type) {
		74	case HDMI_INFOFRAME_TYPE_AVI:
3031	serge	75	return VIDEO_DIP_SELECT_AVI;
4104	Serge	76	case HDMI_INFOFRAME_TYPE_SPD:
3031	serge	77	return VIDEO_DIP_SELECT_SPD;
4104	Serge	78	case HDMI_INFOFRAME_TYPE_VENDOR:
		79	return VIDEO_DIP_SELECT_VENDOR;
3031	serge	80	default:
6937	serge	81	MISSING_CASE(type);
3031	serge	82	return 0;
		83	}
		84	}
2330	Serge	85
4104	Serge	86	static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
3031	serge	87	{
4104	Serge	88	switch (type) {
		89	case HDMI_INFOFRAME_TYPE_AVI:
3031	serge	90	return VIDEO_DIP_ENABLE_AVI;
4104	Serge	91	case HDMI_INFOFRAME_TYPE_SPD:
3031	serge	92	return VIDEO_DIP_ENABLE_SPD;
4104	Serge	93	case HDMI_INFOFRAME_TYPE_VENDOR:
		94	return VIDEO_DIP_ENABLE_VENDOR;
2330	Serge	95	default:
6937	serge	96	MISSING_CASE(type);
3031	serge	97	return 0;
2330	Serge	98	}
3031	serge	99	}
2330	Serge	100
4104	Serge	101	static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
3031	serge	102	{
4104	Serge	103	switch (type) {
		104	case HDMI_INFOFRAME_TYPE_AVI:
3031	serge	105	return VIDEO_DIP_ENABLE_AVI_HSW;
4104	Serge	106	case HDMI_INFOFRAME_TYPE_SPD:
3031	serge	107	return VIDEO_DIP_ENABLE_SPD_HSW;
4104	Serge	108	case HDMI_INFOFRAME_TYPE_VENDOR:
		109	return VIDEO_DIP_ENABLE_VS_HSW;
3031	serge	110	default:
6937	serge	111	MISSING_CASE(type);
3031	serge	112	return 0;
		113	}
2330	Serge	114	}
		115
6937	serge	116	static i915_reg_t
		117	hsw_dip_data_reg(struct drm_i915_private *dev_priv,
7144	serge	118	enum transcoder cpu_transcoder,
		119	enum hdmi_infoframe_type type,
		120	int i)
2330	Serge	121	{
4104	Serge	122	switch (type) {
		123	case HDMI_INFOFRAME_TYPE_AVI:
6084	serge	124	return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
4104	Serge	125	case HDMI_INFOFRAME_TYPE_SPD:
6084	serge	126	return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
4104	Serge	127	case HDMI_INFOFRAME_TYPE_VENDOR:
6084	serge	128	return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
2330	Serge	129	default:
6937	serge	130	MISSING_CASE(type);
		131	return INVALID_MMIO_REG;
2330	Serge	132	}
		133	}
		134
3031	serge	135	static void g4x_write_infoframe(struct drm_encoder *encoder,
4104	Serge	136	enum hdmi_infoframe_type type,
4560	Serge	137	const void *frame, ssize_t len)
2330	Serge	138	{
4560	Serge	139	const uint32_t *data = frame;
2330	Serge	140	struct drm_device *dev = encoder->dev;
		141	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	142	u32 val = I915_READ(VIDEO_DIP_CTL);
4104	Serge	143	int i;
2330	Serge	144
3031	serge	145	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
2330	Serge	146
3031	serge	147	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */
4104	Serge	148	val \|= g4x_infoframe_index(type);
2330	Serge	149
4104	Serge	150	val &= ~g4x_infoframe_enable(type);
2330	Serge	151
3031	serge	152	I915_WRITE(VIDEO_DIP_CTL, val);
2330	Serge	153
3031	serge	154	mmiowb();
2330	Serge	155	for (i = 0; i < len; i += 4) {
		156	I915_WRITE(VIDEO_DIP_DATA, *data);
		157	data++;
		158	}
3031	serge	159	/* Write every possible data byte to force correct ECC calculation. */
		160	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		161	I915_WRITE(VIDEO_DIP_DATA, 0);
		162	mmiowb();
2330	Serge	163
4104	Serge	164	val \|= g4x_infoframe_enable(type);
3031	serge	165	val &= ~VIDEO_DIP_FREQ_MASK;
		166	val \|= VIDEO_DIP_FREQ_VSYNC;
2330	Serge	167
3031	serge	168	I915_WRITE(VIDEO_DIP_CTL, val);
		169	POSTING_READ(VIDEO_DIP_CTL);
2330	Serge	170	}
		171
6937	serge	172	static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
		173	const struct intel_crtc_state *pipe_config)
5354	serge	174	{
6937	serge	175	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5354	serge	176	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
		177	u32 val = I915_READ(VIDEO_DIP_CTL);
		178
6084	serge	179	if ((val & VIDEO_DIP_ENABLE) == 0)
		180	return false;
5354	serge	181
6084	serge	182	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
		183	return false;
		184
		185	return val & (VIDEO_DIP_ENABLE_AVI \|
		186	VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_SPD);
5354	serge	187	}
		188
3031	serge	189	static void ibx_write_infoframe(struct drm_encoder *encoder,
4104	Serge	190	enum hdmi_infoframe_type type,
4560	Serge	191	const void *frame, ssize_t len)
2330	Serge	192	{
4560	Serge	193	const uint32_t *data = frame;
2330	Serge	194	struct drm_device *dev = encoder->dev;
		195	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	196	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
6937	serge	197	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
3031	serge	198	u32 val = I915_READ(reg);
6937	serge	199	int i;
2330	Serge	200
3031	serge	201	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
2330	Serge	202
3031	serge	203	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */
4104	Serge	204	val \|= g4x_infoframe_index(type);
2330	Serge	205
4104	Serge	206	val &= ~g4x_infoframe_enable(type);
3031	serge	207
		208	I915_WRITE(reg, val);
		209
		210	mmiowb();
		211	for (i = 0; i < len; i += 4) {
		212	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		213	data++;
		214	}
		215	/* Write every possible data byte to force correct ECC calculation. */
		216	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		217	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
		218	mmiowb();
		219
4104	Serge	220	val \|= g4x_infoframe_enable(type);
3031	serge	221	val &= ~VIDEO_DIP_FREQ_MASK;
		222	val \|= VIDEO_DIP_FREQ_VSYNC;
		223
		224	I915_WRITE(reg, val);
		225	POSTING_READ(reg);
		226	}
		227
6937	serge	228	static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
		229	const struct intel_crtc_state *pipe_config)
5354	serge	230	{
6937	serge	231	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6084	serge	232	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
6937	serge	233	enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
		234	i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
5354	serge	235	u32 val = I915_READ(reg);
		236
6084	serge	237	if ((val & VIDEO_DIP_ENABLE) == 0)
		238	return false;
		239
		240	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
		241	return false;
		242
		243	return val & (VIDEO_DIP_ENABLE_AVI \|
		244	VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_GAMUT \|
		245	VIDEO_DIP_ENABLE_SPD \| VIDEO_DIP_ENABLE_GCP);
5354	serge	246	}
		247
3031	serge	248	static void cpt_write_infoframe(struct drm_encoder *encoder,
4104	Serge	249	enum hdmi_infoframe_type type,
4560	Serge	250	const void *frame, ssize_t len)
3031	serge	251	{
4560	Serge	252	const uint32_t *data = frame;
3031	serge	253	struct drm_device *dev = encoder->dev;
		254	struct drm_i915_private *dev_priv = dev->dev_private;
		255	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
6937	serge	256	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
3031	serge	257	u32 val = I915_READ(reg);
6937	serge	258	int i;
3031	serge	259
		260	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
		261
2342	Serge	262	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */
4104	Serge	263	val \|= g4x_infoframe_index(type);
2330	Serge	264
3031	serge	265	/* The DIP control register spec says that we need to update the AVI
		266	* infoframe without clearing its enable bit */
4104	Serge	267	if (type != HDMI_INFOFRAME_TYPE_AVI)
		268	val &= ~g4x_infoframe_enable(type);
2330	Serge	269
3031	serge	270	I915_WRITE(reg, val);
		271
		272	mmiowb();
2330	Serge	273	for (i = 0; i < len; i += 4) {
		274	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		275	data++;
		276	}
3031	serge	277	/* Write every possible data byte to force correct ECC calculation. */
		278	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		279	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
		280	mmiowb();
2330	Serge	281
4104	Serge	282	val \|= g4x_infoframe_enable(type);
3031	serge	283	val &= ~VIDEO_DIP_FREQ_MASK;
		284	val \|= VIDEO_DIP_FREQ_VSYNC;
2330	Serge	285
3031	serge	286	I915_WRITE(reg, val);
		287	POSTING_READ(reg);
2330	Serge	288	}
3031	serge	289
6937	serge	290	static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
		291	const struct intel_crtc_state *pipe_config)
5354	serge	292	{
6937	serge	293	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
		294	enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
		295	u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
5354	serge	296
6084	serge	297	if ((val & VIDEO_DIP_ENABLE) == 0)
		298	return false;
		299
		300	return val & (VIDEO_DIP_ENABLE_AVI \|
		301	VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_GAMUT \|
		302	VIDEO_DIP_ENABLE_SPD \| VIDEO_DIP_ENABLE_GCP);
5354	serge	303	}
		304
3031	serge	305	static void vlv_write_infoframe(struct drm_encoder *encoder,
4104	Serge	306	enum hdmi_infoframe_type type,
4560	Serge	307	const void *frame, ssize_t len)
3031	serge	308	{
4560	Serge	309	const uint32_t *data = frame;
3031	serge	310	struct drm_device *dev = encoder->dev;
		311	struct drm_i915_private *dev_priv = dev->dev_private;
		312	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
6937	serge	313	i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
3031	serge	314	u32 val = I915_READ(reg);
6937	serge	315	int i;
3031	serge	316
		317	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
		318
		319	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */
4104	Serge	320	val \|= g4x_infoframe_index(type);
3031	serge	321
4104	Serge	322	val &= ~g4x_infoframe_enable(type);
3031	serge	323
		324	I915_WRITE(reg, val);
		325
		326	mmiowb();
		327	for (i = 0; i < len; i += 4) {
		328	I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		329	data++;
		330	}
		331	/* Write every possible data byte to force correct ECC calculation. */
		332	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		333	I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
		334	mmiowb();
		335
4104	Serge	336	val \|= g4x_infoframe_enable(type);
3031	serge	337	val &= ~VIDEO_DIP_FREQ_MASK;
		338	val \|= VIDEO_DIP_FREQ_VSYNC;
		339
		340	I915_WRITE(reg, val);
		341	POSTING_READ(reg);
		342	}
		343
6937	serge	344	static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
		345	const struct intel_crtc_state *pipe_config)
5354	serge	346	{
6937	serge	347	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6084	serge	348	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
6937	serge	349	enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
		350	u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
5354	serge	351
6084	serge	352	if ((val & VIDEO_DIP_ENABLE) == 0)
		353	return false;
		354
		355	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
		356	return false;
		357
		358	return val & (VIDEO_DIP_ENABLE_AVI \|
		359	VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_GAMUT \|
		360	VIDEO_DIP_ENABLE_SPD \| VIDEO_DIP_ENABLE_GCP);
5354	serge	361	}
		362
3031	serge	363	static void hsw_write_infoframe(struct drm_encoder *encoder,
4104	Serge	364	enum hdmi_infoframe_type type,
4560	Serge	365	const void *frame, ssize_t len)
3031	serge	366	{
4560	Serge	367	const uint32_t *data = frame;
3031	serge	368	struct drm_device *dev = encoder->dev;
		369	struct drm_i915_private *dev_priv = dev->dev_private;
		370	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
6084	serge	371	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6937	serge	372	i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
		373	i915_reg_t data_reg;
4104	Serge	374	int i;
3031	serge	375	u32 val = I915_READ(ctl_reg);
		376
6084	serge	377	data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
3031	serge	378
4104	Serge	379	val &= ~hsw_infoframe_enable(type);
3031	serge	380	I915_WRITE(ctl_reg, val);
		381
		382	mmiowb();
		383	for (i = 0; i < len; i += 4) {
6084	serge	384	I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
		385	type, i >> 2), *data);
3031	serge	386	data++;
		387	}
		388	/* Write every possible data byte to force correct ECC calculation. */
		389	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
6084	serge	390	I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
		391	type, i >> 2), 0);
3031	serge	392	mmiowb();
		393
4104	Serge	394	val \|= hsw_infoframe_enable(type);
3031	serge	395	I915_WRITE(ctl_reg, val);
		396	POSTING_READ(ctl_reg);
		397	}
		398
6937	serge	399	static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
		400	const struct intel_crtc_state *pipe_config)
5354	serge	401	{
6937	serge	402	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
		403	u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
5354	serge	404
6084	serge	405	return val & (VIDEO_DIP_ENABLE_VSC_HSW \| VIDEO_DIP_ENABLE_AVI_HSW \|
		406	VIDEO_DIP_ENABLE_GCP_HSW \| VIDEO_DIP_ENABLE_VS_HSW \|
		407	VIDEO_DIP_ENABLE_GMP_HSW \| VIDEO_DIP_ENABLE_SPD_HSW);
5354	serge	408	}
		409
4104	Serge	410	/*
		411	* The data we write to the DIP data buffer registers is 1 byte bigger than the
		412	* HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
		413	* at 0). It's also a byte used by DisplayPort so the same DIP registers can be
		414	* used for both technologies.
		415	*
		416	* DW0: Reserved/ECC/DP \| HB2 \| HB1 \| HB0
		417	* DW1: DB3 \| DB2 \| DB1 \| DB0
		418	* DW2: DB7 \| DB6 \| DB5 \| DB4
		419	* DW3: ...
		420	*
		421	* (HB is Header Byte, DB is Data Byte)
		422	*
		423	* The hdmi pack() functions don't know about that hardware specific hole so we
		424	* trick them by giving an offset into the buffer and moving back the header
		425	* bytes by one.
		426	*/
		427	static void intel_write_infoframe(struct drm_encoder *encoder,
		428	union hdmi_infoframe *frame)
2330	Serge	429	{
		430	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
4104	Serge	431	uint8_t buffer[VIDEO_DIP_DATA_SIZE];
		432	ssize_t len;
2330	Serge	433
4104	Serge	434	/* see comment above for the reason for this offset */
		435	len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
		436	if (len < 0)
		437	return;
		438
		439	/* Insert the 'hole' (see big comment above) at position 3 */
		440	buffer[0] = buffer[1];
		441	buffer[1] = buffer[2];
		442	buffer[2] = buffer[3];
		443	buffer[3] = 0;
		444	len++;
		445
		446	intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
2330	Serge	447	}
		448
3031	serge	449	static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
6084	serge	450	const struct drm_display_mode *adjusted_mode)
2330	Serge	451	{
3480	Serge	452	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
3746	Serge	453	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
4104	Serge	454	union hdmi_infoframe frame;
		455	int ret;
2330	Serge	456
4104	Serge	457	ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
		458	adjusted_mode);
		459	if (ret < 0) {
		460	DRM_ERROR("couldn't fill AVI infoframe\n");
		461	return;
		462	}
3031	serge	463
3480	Serge	464	if (intel_hdmi->rgb_quant_range_selectable) {
6084	serge	465	if (intel_crtc->config->limited_color_range)
4104	Serge	466	frame.avi.quantization_range =
		467	HDMI_QUANTIZATION_RANGE_LIMITED;
3480	Serge	468	else
4104	Serge	469	frame.avi.quantization_range =
		470	HDMI_QUANTIZATION_RANGE_FULL;
3480	Serge	471	}
3243	Serge	472
4104	Serge	473	intel_write_infoframe(encoder, &frame);
2330	Serge	474	}
		475
		476	static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
		477	{
4104	Serge	478	union hdmi_infoframe frame;
		479	int ret;
2330	Serge	480
4104	Serge	481	ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
		482	if (ret < 0) {
		483	DRM_ERROR("couldn't fill SPD infoframe\n");
		484	return;
		485	}
2330	Serge	486
4104	Serge	487	frame.spd.sdi = HDMI_SPD_SDI_PC;
		488
		489	intel_write_infoframe(encoder, &frame);
2330	Serge	490	}
		491
4104	Serge	492	static void
		493	intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
6084	serge	494	const struct drm_display_mode *adjusted_mode)
4104	Serge	495	{
		496	union hdmi_infoframe frame;
		497	int ret;
		498
		499	ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
		500	adjusted_mode);
		501	if (ret < 0)
		502	return;
		503
		504	intel_write_infoframe(encoder, &frame);
		505	}
		506
3031	serge	507	static void g4x_set_infoframes(struct drm_encoder *encoder,
5060	serge	508	bool enable,
6084	serge	509	const struct drm_display_mode *adjusted_mode)
3031	serge	510	{
		511	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
3480	Serge	512	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
		513	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
6937	serge	514	i915_reg_t reg = VIDEO_DIP_CTL;
3031	serge	515	u32 val = I915_READ(reg);
5060	serge	516	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
3031	serge	517
		518	assert_hdmi_port_disabled(intel_hdmi);
		519
		520	/* If the registers were not initialized yet, they might be zeroes,
		521	* which means we're selecting the AVI DIP and we're setting its
		522	* frequency to once. This seems to really confuse the HW and make
		523	* things stop working (the register spec says the AVI always needs to
		524	* be sent every VSync). So here we avoid writing to the register more
		525	* than we need and also explicitly select the AVI DIP and explicitly
		526	* set its frequency to every VSync. Avoiding to write it twice seems to
		527	* be enough to solve the problem, but being defensive shouldn't hurt us
		528	* either. */
		529	val \|= VIDEO_DIP_SELECT_AVI \| VIDEO_DIP_FREQ_VSYNC;
		530
5060	serge	531	if (!enable) {
3031	serge	532	if (!(val & VIDEO_DIP_ENABLE))
		533	return;
6084	serge	534	if (port != (val & VIDEO_DIP_PORT_MASK)) {
		535	DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
		536	(val & VIDEO_DIP_PORT_MASK) >> 29);
		537	return;
		538	}
		539	val &= ~(VIDEO_DIP_ENABLE \| VIDEO_DIP_ENABLE_AVI \|
		540	VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_SPD);
3031	serge	541	I915_WRITE(reg, val);
		542	POSTING_READ(reg);
		543	return;
		544	}
		545
		546	if (port != (val & VIDEO_DIP_PORT_MASK)) {
		547	if (val & VIDEO_DIP_ENABLE) {
6084	serge	548	DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
		549	(val & VIDEO_DIP_PORT_MASK) >> 29);
		550	return;
3031	serge	551	}
		552	val &= ~VIDEO_DIP_PORT_MASK;
		553	val \|= port;
		554	}
		555
		556	val \|= VIDEO_DIP_ENABLE;
6084	serge	557	val &= ~(VIDEO_DIP_ENABLE_AVI \|
		558	VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_SPD);
3031	serge	559
		560	I915_WRITE(reg, val);
		561	POSTING_READ(reg);
		562
		563	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
		564	intel_hdmi_set_spd_infoframe(encoder);
4104	Serge	565	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
3031	serge	566	}
		567
6084	serge	568	static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
		569	{
		570	struct drm_device *dev = encoder->dev;
		571	struct drm_connector *connector;
		572
		573	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
		574
		575	/*
		576	* HDMI cloning is only supported on g4x which doesn't
		577	* support deep color or GCP infoframes anyway so no
		578	* need to worry about multiple HDMI sinks here.
		579	*/
		580	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
		581	if (connector->encoder == encoder)
		582	return connector->display_info.bpc > 8;
		583
		584	return false;
		585	}
		586
		587	/*
		588	* Determine if default_phase=1 can be indicated in the GCP infoframe.
		589	*
		590	* From HDMI specification 1.4a:
		591	* - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
		592	* - The first pixel following each Video Data Period shall have a pixel packing phase of 0
		593	* - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
		594	* - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
		595	* phase of 0
		596	*/
		597	static bool gcp_default_phase_possible(int pipe_bpp,
		598	const struct drm_display_mode *mode)
		599	{
		600	unsigned int pixels_per_group;
		601
		602	switch (pipe_bpp) {
		603	case 30:
		604	/* 4 pixels in 5 clocks */
		605	pixels_per_group = 4;
		606	break;
		607	case 36:
		608	/* 2 pixels in 3 clocks */
		609	pixels_per_group = 2;
		610	break;
		611	case 48:
		612	/* 1 pixel in 2 clocks */
		613	pixels_per_group = 1;
		614	break;
		615	default:
		616	/* phase information not relevant for 8bpc */
		617	return false;
		618	}
		619
		620	return mode->crtc_hdisplay % pixels_per_group == 0 &&
		621	mode->crtc_htotal % pixels_per_group == 0 &&
		622	mode->crtc_hblank_start % pixels_per_group == 0 &&
		623	mode->crtc_hblank_end % pixels_per_group == 0 &&
		624	mode->crtc_hsync_start % pixels_per_group == 0 &&
		625	mode->crtc_hsync_end % pixels_per_group == 0 &&
		626	((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 \|\|
		627	mode->crtc_htotal/2 % pixels_per_group == 0);
		628	}
		629
		630	static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
		631	{
		632	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
		633	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6937	serge	634	i915_reg_t reg;
		635	u32 val = 0;
6084	serge	636
		637	if (HAS_DDI(dev_priv))
		638	reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
6937	serge	639	else if (IS_VALLEYVIEW(dev_priv) \|\| IS_CHERRYVIEW(dev_priv))
6084	serge	640	reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
		641	else if (HAS_PCH_SPLIT(dev_priv->dev))
		642	reg = TVIDEO_DIP_GCP(crtc->pipe);
		643	else
		644	return false;
		645
		646	/* Indicate color depth whenever the sink supports deep color */
		647	if (hdmi_sink_is_deep_color(encoder))
		648	val \|= GCP_COLOR_INDICATION;
		649
		650	/* Enable default_phase whenever the display mode is suitably aligned */
		651	if (gcp_default_phase_possible(crtc->config->pipe_bpp,
		652	&crtc->config->base.adjusted_mode))
		653	val \|= GCP_DEFAULT_PHASE_ENABLE;
		654
		655	I915_WRITE(reg, val);
		656
		657	return val != 0;
		658	}
		659
3031	serge	660	static void ibx_set_infoframes(struct drm_encoder *encoder,
5060	serge	661	bool enable,
6084	serge	662	const struct drm_display_mode *adjusted_mode)
3031	serge	663	{
		664	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
		665	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
3480	Serge	666	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
		667	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
6937	serge	668	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
3031	serge	669	u32 val = I915_READ(reg);
5060	serge	670	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
3031	serge	671
		672	assert_hdmi_port_disabled(intel_hdmi);
		673
		674	/* See the big comment in g4x_set_infoframes() */
		675	val \|= VIDEO_DIP_SELECT_AVI \| VIDEO_DIP_FREQ_VSYNC;
		676
5060	serge	677	if (!enable) {
3031	serge	678	if (!(val & VIDEO_DIP_ENABLE))
		679	return;
6084	serge	680	val &= ~(VIDEO_DIP_ENABLE \| VIDEO_DIP_ENABLE_AVI \|
		681	VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_GAMUT \|
		682	VIDEO_DIP_ENABLE_SPD \| VIDEO_DIP_ENABLE_GCP);
3031	serge	683	I915_WRITE(reg, val);
		684	POSTING_READ(reg);
		685	return;
		686	}
		687
		688	if (port != (val & VIDEO_DIP_PORT_MASK)) {
6084	serge	689	WARN(val & VIDEO_DIP_ENABLE,
		690	"DIP already enabled on port %c\n",
		691	(val & VIDEO_DIP_PORT_MASK) >> 29);
3031	serge	692	val &= ~VIDEO_DIP_PORT_MASK;
		693	val \|= port;
		694	}
		695
		696	val \|= VIDEO_DIP_ENABLE;
6084	serge	697	val &= ~(VIDEO_DIP_ENABLE_AVI \|
		698	VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_GAMUT \|
		699	VIDEO_DIP_ENABLE_SPD \| VIDEO_DIP_ENABLE_GCP);
3031	serge	700
6084	serge	701	if (intel_hdmi_set_gcp_infoframe(encoder))
		702	val \|= VIDEO_DIP_ENABLE_GCP;
		703
3031	serge	704	I915_WRITE(reg, val);
		705	POSTING_READ(reg);
		706
		707	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
		708	intel_hdmi_set_spd_infoframe(encoder);
4104	Serge	709	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
3031	serge	710	}
		711
		712	static void cpt_set_infoframes(struct drm_encoder *encoder,
5060	serge	713	bool enable,
6084	serge	714	const struct drm_display_mode *adjusted_mode)
3031	serge	715	{
		716	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
		717	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
		718	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
6937	serge	719	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
3031	serge	720	u32 val = I915_READ(reg);
		721
		722	assert_hdmi_port_disabled(intel_hdmi);
		723
		724	/* See the big comment in g4x_set_infoframes() */
		725	val \|= VIDEO_DIP_SELECT_AVI \| VIDEO_DIP_FREQ_VSYNC;
		726
5060	serge	727	if (!enable) {
3031	serge	728	if (!(val & VIDEO_DIP_ENABLE))
		729	return;
6084	serge	730	val &= ~(VIDEO_DIP_ENABLE \| VIDEO_DIP_ENABLE_AVI \|
		731	VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_GAMUT \|
		732	VIDEO_DIP_ENABLE_SPD \| VIDEO_DIP_ENABLE_GCP);
3031	serge	733	I915_WRITE(reg, val);
		734	POSTING_READ(reg);
		735	return;
		736	}
		737
		738	/* Set both together, unset both together: see the spec. */
		739	val \|= VIDEO_DIP_ENABLE \| VIDEO_DIP_ENABLE_AVI;
		740	val &= ~(VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_GAMUT \|
6084	serge	741	VIDEO_DIP_ENABLE_SPD \| VIDEO_DIP_ENABLE_GCP);
3031	serge	742
6084	serge	743	if (intel_hdmi_set_gcp_infoframe(encoder))
		744	val \|= VIDEO_DIP_ENABLE_GCP;
		745
3031	serge	746	I915_WRITE(reg, val);
		747	POSTING_READ(reg);
		748
		749	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
		750	intel_hdmi_set_spd_infoframe(encoder);
4104	Serge	751	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
3031	serge	752	}
		753
		754	static void vlv_set_infoframes(struct drm_encoder *encoder,
5060	serge	755	bool enable,
6084	serge	756	const struct drm_display_mode *adjusted_mode)
3031	serge	757	{
		758	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
5060	serge	759	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3031	serge	760	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
		761	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
6937	serge	762	i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
3031	serge	763	u32 val = I915_READ(reg);
5060	serge	764	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
3031	serge	765
		766	assert_hdmi_port_disabled(intel_hdmi);
		767
		768	/* See the big comment in g4x_set_infoframes() */
		769	val \|= VIDEO_DIP_SELECT_AVI \| VIDEO_DIP_FREQ_VSYNC;
		770
5060	serge	771	if (!enable) {
3031	serge	772	if (!(val & VIDEO_DIP_ENABLE))
		773	return;
6084	serge	774	val &= ~(VIDEO_DIP_ENABLE \| VIDEO_DIP_ENABLE_AVI \|
		775	VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_GAMUT \|
		776	VIDEO_DIP_ENABLE_SPD \| VIDEO_DIP_ENABLE_GCP);
3031	serge	777	I915_WRITE(reg, val);
		778	POSTING_READ(reg);
		779	return;
		780	}
		781
5060	serge	782	if (port != (val & VIDEO_DIP_PORT_MASK)) {
6084	serge	783	WARN(val & VIDEO_DIP_ENABLE,
		784	"DIP already enabled on port %c\n",
		785	(val & VIDEO_DIP_PORT_MASK) >> 29);
5060	serge	786	val &= ~VIDEO_DIP_PORT_MASK;
		787	val \|= port;
		788	}
		789
3031	serge	790	val \|= VIDEO_DIP_ENABLE;
6084	serge	791	val &= ~(VIDEO_DIP_ENABLE_AVI \|
		792	VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_GAMUT \|
		793	VIDEO_DIP_ENABLE_SPD \| VIDEO_DIP_ENABLE_GCP);
3031	serge	794
6084	serge	795	if (intel_hdmi_set_gcp_infoframe(encoder))
		796	val \|= VIDEO_DIP_ENABLE_GCP;
		797
3031	serge	798	I915_WRITE(reg, val);
		799	POSTING_READ(reg);
		800
		801	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
		802	intel_hdmi_set_spd_infoframe(encoder);
4104	Serge	803	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
3031	serge	804	}
		805
		806	static void hsw_set_infoframes(struct drm_encoder *encoder,
5060	serge	807	bool enable,
6084	serge	808	const struct drm_display_mode *adjusted_mode)
3031	serge	809	{
		810	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
		811	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
		812	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
6937	serge	813	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
3031	serge	814	u32 val = I915_READ(reg);
		815
		816	assert_hdmi_port_disabled(intel_hdmi);
		817
6084	serge	818	val &= ~(VIDEO_DIP_ENABLE_VSC_HSW \| VIDEO_DIP_ENABLE_AVI_HSW \|
		819	VIDEO_DIP_ENABLE_GCP_HSW \| VIDEO_DIP_ENABLE_VS_HSW \|
		820	VIDEO_DIP_ENABLE_GMP_HSW \| VIDEO_DIP_ENABLE_SPD_HSW);
		821
5060	serge	822	if (!enable) {
6084	serge	823	I915_WRITE(reg, val);
3031	serge	824	POSTING_READ(reg);
		825	return;
		826	}
		827
6084	serge	828	if (intel_hdmi_set_gcp_infoframe(encoder))
		829	val \|= VIDEO_DIP_ENABLE_GCP_HSW;
3031	serge	830
		831	I915_WRITE(reg, val);
		832	POSTING_READ(reg);
		833
		834	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
		835	intel_hdmi_set_spd_infoframe(encoder);
4104	Serge	836	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
3031	serge	837	}
		838
7144	serge	839	void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
		840	{
		841	struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
		842	struct i2c_adapter *adapter =
		843	intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
		844
		845	if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
		846	return;
		847
		848	DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
		849	enable ? "Enabling" : "Disabling");
		850
		851	drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
		852	adapter, enable);
		853	}
		854
5060	serge	855	static void intel_hdmi_prepare(struct intel_encoder *encoder)
2330	Serge	856	{
4104	Serge	857	struct drm_device *dev = encoder->base.dev;
2330	Serge	858	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	859	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
		860	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
6084	serge	861	const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
3746	Serge	862	u32 hdmi_val;
2330	Serge	863
7144	serge	864	intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
		865
3746	Serge	866	hdmi_val = SDVO_ENCODING_HDMI;
6084	serge	867	if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
		868	hdmi_val \|= HDMI_COLOR_RANGE_16_235;
2330	Serge	869	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
3746	Serge	870	hdmi_val \|= SDVO_VSYNC_ACTIVE_HIGH;
2330	Serge	871	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
3746	Serge	872	hdmi_val \|= SDVO_HSYNC_ACTIVE_HIGH;
2330	Serge	873
6084	serge	874	if (crtc->config->pipe_bpp > 24)
3746	Serge	875	hdmi_val \|= HDMI_COLOR_FORMAT_12bpc;
2330	Serge	876	else
3746	Serge	877	hdmi_val \|= SDVO_COLOR_FORMAT_8bpc;
2330	Serge	878
6084	serge	879	if (crtc->config->has_hdmi_sink)
3746	Serge	880	hdmi_val \|= HDMI_MODE_SELECT_HDMI;
2330	Serge	881
6084	serge	882	if (HAS_PCH_CPT(dev))
4104	Serge	883	hdmi_val \|= SDVO_PIPE_SEL_CPT(crtc->pipe);
5060	serge	884	else if (IS_CHERRYVIEW(dev))
		885	hdmi_val \|= SDVO_PIPE_SEL_CHV(crtc->pipe);
3746	Serge	886	else
4104	Serge	887	hdmi_val \|= SDVO_PIPE_SEL(crtc->pipe);
2330	Serge	888
3746	Serge	889	I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
		890	POSTING_READ(intel_hdmi->hdmi_reg);
2330	Serge	891	}
		892
3031	serge	893	static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
		894	enum pipe *pipe)
2330	Serge	895	{
3031	serge	896	struct drm_device *dev = encoder->base.dev;
2330	Serge	897	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	898	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
5060	serge	899	enum intel_display_power_domain power_domain;
3031	serge	900	u32 tmp;
6937	serge	901	bool ret;
3031	serge	902
5060	serge	903	power_domain = intel_display_port_power_domain(encoder);
6937	serge	904	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
5060	serge	905	return false;
		906
6937	serge	907	ret = false;
		908
3746	Serge	909	tmp = I915_READ(intel_hdmi->hdmi_reg);
3031	serge	910
		911	if (!(tmp & SDVO_ENABLE))
6937	serge	912	goto out;
3031	serge	913
		914	if (HAS_PCH_CPT(dev))
		915	*pipe = PORT_TO_PIPE_CPT(tmp);
5060	serge	916	else if (IS_CHERRYVIEW(dev))
		917	*pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
3031	serge	918	else
		919	*pipe = PORT_TO_PIPE(tmp);
		920
6937	serge	921	ret = true;
		922
		923	out:
		924	intel_display_power_put(dev_priv, power_domain);
		925
		926	return ret;
3031	serge	927	}
		928
4104	Serge	929	static void intel_hdmi_get_config(struct intel_encoder *encoder,
6084	serge	930	struct intel_crtc_state *pipe_config)
4104	Serge	931	{
		932	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
5139	serge	933	struct drm_device *dev = encoder->base.dev;
		934	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	935	u32 tmp, flags = 0;
4560	Serge	936	int dotclock;
4104	Serge	937
		938	tmp = I915_READ(intel_hdmi->hdmi_reg);
		939
		940	if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
		941	flags \|= DRM_MODE_FLAG_PHSYNC;
		942	else
		943	flags \|= DRM_MODE_FLAG_NHSYNC;
		944
		945	if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
		946	flags \|= DRM_MODE_FLAG_PVSYNC;
		947	else
		948	flags \|= DRM_MODE_FLAG_NVSYNC;
		949
5060	serge	950	if (tmp & HDMI_MODE_SELECT_HDMI)
		951	pipe_config->has_hdmi_sink = true;
		952
6937	serge	953	if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
5354	serge	954	pipe_config->has_infoframe = true;
		955
		956	if (tmp & SDVO_AUDIO_ENABLE)
5060	serge	957	pipe_config->has_audio = true;
		958
5139	serge	959	if (!HAS_PCH_SPLIT(dev) &&
		960	tmp & HDMI_COLOR_RANGE_16_235)
		961	pipe_config->limited_color_range = true;
		962
6084	serge	963	pipe_config->base.adjusted_mode.flags \|= flags;
4560	Serge	964
		965	if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
		966	dotclock = pipe_config->port_clock * 2 / 3;
		967	else
		968	dotclock = pipe_config->port_clock;
		969
6084	serge	970	if (pipe_config->pixel_multiplier)
		971	dotclock /= pipe_config->pixel_multiplier;
		972
4560	Serge	973	if (HAS_PCH_SPLIT(dev_priv->dev))
		974	ironlake_check_encoder_dotclock(pipe_config, dotclock);
		975
6084	serge	976	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
4104	Serge	977	}
		978
6084	serge	979	static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
3031	serge	980	{
6084	serge	981	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
		982
		983	WARN_ON(!crtc->config->has_hdmi_sink);
		984	DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
		985	pipe_name(crtc->pipe));
		986	intel_audio_codec_enable(encoder);
		987	}
		988
		989	static void g4x_enable_hdmi(struct intel_encoder *encoder)
		990	{
3031	serge	991	struct drm_device *dev = encoder->base.dev;
		992	struct drm_i915_private *dev_priv = dev->dev_private;
6084	serge	993	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
3031	serge	994	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2330	Serge	995	u32 temp;
		996
6084	serge	997	temp = I915_READ(intel_hdmi->hdmi_reg);
2342	Serge	998
6084	serge	999	temp \|= SDVO_ENABLE;
		1000	if (crtc->config->has_audio)
		1001	temp \|= SDVO_AUDIO_ENABLE;
		1002
		1003	I915_WRITE(intel_hdmi->hdmi_reg, temp);
		1004	POSTING_READ(intel_hdmi->hdmi_reg);
		1005
		1006	if (crtc->config->has_audio)
		1007	intel_enable_hdmi_audio(encoder);
		1008	}
		1009
		1010	static void ibx_enable_hdmi(struct intel_encoder *encoder)
		1011	{
		1012	struct drm_device *dev = encoder->base.dev;
		1013	struct drm_i915_private *dev_priv = dev->dev_private;
		1014	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
		1015	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
		1016	u32 temp;
		1017
3746	Serge	1018	temp = I915_READ(intel_hdmi->hdmi_reg);
2330	Serge	1019
6084	serge	1020	temp \|= SDVO_ENABLE;
		1021	if (crtc->config->has_audio)
		1022	temp \|= SDVO_AUDIO_ENABLE;
3031	serge	1023
6084	serge	1024	/*
		1025	* HW workaround, need to write this twice for issue
		1026	* that may result in first write getting masked.
2330	Serge	1027	*/
6084	serge	1028	I915_WRITE(intel_hdmi->hdmi_reg, temp);
		1029	POSTING_READ(intel_hdmi->hdmi_reg);
		1030	I915_WRITE(intel_hdmi->hdmi_reg, temp);
		1031	POSTING_READ(intel_hdmi->hdmi_reg);
		1032
		1033	/*
		1034	* HW workaround, need to toggle enable bit off and on
		1035	* for 12bpc with pixel repeat.
		1036	*
		1037	* FIXME: BSpec says this should be done at the end of
		1038	* of the modeset sequence, so not sure if this isn't too soon.
		1039	*/
		1040	if (crtc->config->pipe_bpp > 24 &&
		1041	crtc->config->pixel_multiplier > 1) {
3746	Serge	1042	I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
		1043	POSTING_READ(intel_hdmi->hdmi_reg);
6084	serge	1044
		1045	/*
		1046	* HW workaround, need to write this twice for issue
		1047	* that may result in first write getting masked.
		1048	*/
		1049	I915_WRITE(intel_hdmi->hdmi_reg, temp);
		1050	POSTING_READ(intel_hdmi->hdmi_reg);
		1051	I915_WRITE(intel_hdmi->hdmi_reg, temp);
		1052	POSTING_READ(intel_hdmi->hdmi_reg);
2330	Serge	1053	}
		1054
6084	serge	1055	if (crtc->config->has_audio)
		1056	intel_enable_hdmi_audio(encoder);
		1057	}
3031	serge	1058
6084	serge	1059	static void cpt_enable_hdmi(struct intel_encoder *encoder)
		1060	{
		1061	struct drm_device *dev = encoder->base.dev;
		1062	struct drm_i915_private *dev_priv = dev->dev_private;
		1063	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
		1064	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
		1065	enum pipe pipe = crtc->pipe;
		1066	u32 temp;
		1067
		1068	temp = I915_READ(intel_hdmi->hdmi_reg);
		1069
		1070	temp \|= SDVO_ENABLE;
		1071	if (crtc->config->has_audio)
		1072	temp \|= SDVO_AUDIO_ENABLE;
		1073
		1074	/*
		1075	* WaEnableHDMI8bpcBefore12bpc:snb,ivb
		1076	*
		1077	* The procedure for 12bpc is as follows:
		1078	* 1. disable HDMI clock gating
		1079	* 2. enable HDMI with 8bpc
		1080	* 3. enable HDMI with 12bpc
		1081	* 4. enable HDMI clock gating
		1082	*/
		1083
		1084	if (crtc->config->pipe_bpp > 24) {
		1085	I915_WRITE(TRANS_CHICKEN1(pipe),
		1086	I915_READ(TRANS_CHICKEN1(pipe)) \|
		1087	TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
		1088
		1089	temp &= ~SDVO_COLOR_FORMAT_MASK;
		1090	temp \|= SDVO_COLOR_FORMAT_8bpc;
		1091	}
		1092
3746	Serge	1093	I915_WRITE(intel_hdmi->hdmi_reg, temp);
		1094	POSTING_READ(intel_hdmi->hdmi_reg);
3031	serge	1095
6084	serge	1096	if (crtc->config->pipe_bpp > 24) {
		1097	temp &= ~SDVO_COLOR_FORMAT_MASK;
		1098	temp \|= HDMI_COLOR_FORMAT_12bpc;
		1099
3746	Serge	1100	I915_WRITE(intel_hdmi->hdmi_reg, temp);
		1101	POSTING_READ(intel_hdmi->hdmi_reg);
6084	serge	1102
		1103	I915_WRITE(TRANS_CHICKEN1(pipe),
		1104	I915_READ(TRANS_CHICKEN1(pipe)) &
		1105	~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
2330	Serge	1106	}
5354	serge	1107
6084	serge	1108	if (crtc->config->has_audio)
		1109	intel_enable_hdmi_audio(encoder);
3031	serge	1110	}
2330	Serge	1111
4104	Serge	1112	static void vlv_enable_hdmi(struct intel_encoder *encoder)
		1113	{
		1114	}
		1115
3031	serge	1116	static void intel_disable_hdmi(struct intel_encoder *encoder)
		1117	{
		1118	struct drm_device *dev = encoder->base.dev;
		1119	struct drm_i915_private *dev_priv = dev->dev_private;
		1120	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
5354	serge	1121	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
3031	serge	1122	u32 temp;
		1123
3746	Serge	1124	temp = I915_READ(intel_hdmi->hdmi_reg);
3031	serge	1125
6084	serge	1126	temp &= ~(SDVO_ENABLE \| SDVO_AUDIO_ENABLE);
3746	Serge	1127	I915_WRITE(intel_hdmi->hdmi_reg, temp);
		1128	POSTING_READ(intel_hdmi->hdmi_reg);
2330	Serge	1129
6084	serge	1130	/*
		1131	* HW workaround for IBX, we need to move the port
		1132	* to transcoder A after disabling it to allow the
		1133	* matching DP port to be enabled on transcoder A.
2330	Serge	1134	*/
6084	serge	1135	if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
6937	serge	1136	/*
		1137	* We get CPU/PCH FIFO underruns on the other pipe when
		1138	* doing the workaround. Sweep them under the rug.
		1139	*/
		1140	intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
		1141	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
		1142
6084	serge	1143	temp &= ~SDVO_PIPE_B_SELECT;
		1144	temp \|= SDVO_ENABLE;
		1145	/*
		1146	* HW workaround, need to write this twice for issue
		1147	* that may result in first write getting masked.
		1148	*/
3746	Serge	1149	I915_WRITE(intel_hdmi->hdmi_reg, temp);
		1150	POSTING_READ(intel_hdmi->hdmi_reg);
6084	serge	1151	I915_WRITE(intel_hdmi->hdmi_reg, temp);
		1152	POSTING_READ(intel_hdmi->hdmi_reg);
		1153
		1154	temp &= ~SDVO_ENABLE;
		1155	I915_WRITE(intel_hdmi->hdmi_reg, temp);
		1156	POSTING_READ(intel_hdmi->hdmi_reg);
6937	serge	1157
		1158	intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
		1159	intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
		1160	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
2330	Serge	1161	}
6084	serge	1162
		1163	intel_hdmi->set_infoframes(&encoder->base, false, NULL);
7144	serge	1164
		1165	intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2330	Serge	1166	}
		1167
6084	serge	1168	static void g4x_disable_hdmi(struct intel_encoder *encoder)
4104	Serge	1169	{
6084	serge	1170	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
		1171
		1172	if (crtc->config->has_audio)
		1173	intel_audio_codec_disable(encoder);
		1174
		1175	intel_disable_hdmi(encoder);
		1176	}
		1177
		1178	static void pch_disable_hdmi(struct intel_encoder *encoder)
		1179	{
		1180	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
		1181
		1182	if (crtc->config->has_audio)
		1183	intel_audio_codec_disable(encoder);
		1184	}
		1185
		1186	static void pch_post_disable_hdmi(struct intel_encoder *encoder)
		1187	{
		1188	intel_disable_hdmi(encoder);
		1189	}
		1190
7144	serge	1191	static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv)
6084	serge	1192	{
7144	serge	1193	if (IS_G4X(dev_priv))
4104	Serge	1194	return 165000;
7144	serge	1195	else if (IS_HASWELL(dev_priv) \|\| INTEL_INFO(dev_priv)->gen >= 8)
4104	Serge	1196	return 300000;
		1197	else
		1198	return 225000;
		1199	}
		1200
7144	serge	1201	static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
		1202	bool respect_downstream_limits)
		1203	{
		1204	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
		1205	int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev));
		1206
		1207	if (respect_downstream_limits) {
		1208	if (hdmi->dp_dual_mode.max_tmds_clock)
		1209	max_tmds_clock = min(max_tmds_clock,
		1210	hdmi->dp_dual_mode.max_tmds_clock);
		1211	if (!hdmi->has_hdmi_sink)
		1212	max_tmds_clock = min(max_tmds_clock, 165000);
		1213	}
		1214
		1215	return max_tmds_clock;
		1216	}
		1217
4560	Serge	1218	static enum drm_mode_status
6084	serge	1219	hdmi_port_clock_valid(struct intel_hdmi *hdmi,
7144	serge	1220	int clock, bool respect_downstream_limits)
6084	serge	1221	{
		1222	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
		1223
		1224	if (clock < 25000)
		1225	return MODE_CLOCK_LOW;
7144	serge	1226	if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits))
6084	serge	1227	return MODE_CLOCK_HIGH;
		1228
		1229	/* BXT DPLL can't generate 223-240 MHz */
		1230	if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
		1231	return MODE_CLOCK_RANGE;
		1232
		1233	/* CHV DPLL can't generate 216-240 MHz */
		1234	if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
		1235	return MODE_CLOCK_RANGE;
		1236
		1237	return MODE_OK;
		1238	}
		1239
		1240	static enum drm_mode_status
4560	Serge	1241	intel_hdmi_mode_valid(struct drm_connector *connector,
6084	serge	1242	struct drm_display_mode *mode)
2330	Serge	1243	{
6084	serge	1244	struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
		1245	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
		1246	enum drm_mode_status status;
		1247	int clock;
7144	serge	1248	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
5354	serge	1249
6084	serge	1250	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		1251	return MODE_NO_DBLESCAN;
		1252
		1253	clock = mode->clock;
7144	serge	1254
		1255	if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
		1256	clock *= 2;
		1257
		1258	if (clock > max_dotclk)
		1259	return MODE_CLOCK_HIGH;
		1260
5354	serge	1261	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		1262	clock *= 2;
		1263
6084	serge	1264	/* check if we can do 8bpc */
		1265	status = hdmi_port_clock_valid(hdmi, clock, true);
2330	Serge	1266
6084	serge	1267	/* if we can't do 8bpc we may still be able to do 12bpc */
		1268	if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
		1269	status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
2330	Serge	1270
6084	serge	1271	return status;
2330	Serge	1272	}
		1273
6084	serge	1274	static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
5060	serge	1275	{
6084	serge	1276	struct drm_device *dev = crtc_state->base.crtc->dev;
		1277	struct drm_atomic_state *state;
5060	serge	1278	struct intel_encoder *encoder;
6084	serge	1279	struct drm_connector *connector;
		1280	struct drm_connector_state *connector_state;
5060	serge	1281	int count = 0, count_hdmi = 0;
6084	serge	1282	int i;
5060	serge	1283
		1284	if (HAS_GMCH_DISPLAY(dev))
		1285	return false;
		1286
6084	serge	1287	state = crtc_state->base.state;
		1288
		1289	for_each_connector_in_state(state, connector, connector_state, i) {
		1290	if (connector_state->crtc != crtc_state->base.crtc)
5060	serge	1291	continue;
		1292
6084	serge	1293	encoder = to_intel_encoder(connector_state->best_encoder);
		1294
5060	serge	1295	count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
		1296	count++;
		1297	}
		1298
		1299	/*
		1300	* HDMI 12bpc affects the clocks, so it's only possible
		1301	* when not cloning with other encoder types.
		1302	*/
		1303	return count_hdmi > 0 && count_hdmi == count;
		1304	}
		1305
3746	Serge	1306	bool intel_hdmi_compute_config(struct intel_encoder *encoder,
6084	serge	1307	struct intel_crtc_state *pipe_config)
2330	Serge	1308	{
3746	Serge	1309	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
		1310	struct drm_device *dev = encoder->base.dev;
6084	serge	1311	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
		1312	int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
		1313	int clock_12bpc = clock_8bpc * 3 / 2;
4104	Serge	1314	int desired_bpp;
2330	Serge	1315
5060	serge	1316	pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
		1317
5354	serge	1318	if (pipe_config->has_hdmi_sink)
		1319	pipe_config->has_infoframe = true;
		1320
3480	Serge	1321	if (intel_hdmi->color_range_auto) {
		1322	/* See CEA-861-E - 5.1 Default Encoding Parameters */
6084	serge	1323	pipe_config->limited_color_range =
		1324	pipe_config->has_hdmi_sink &&
		1325	drm_match_cea_mode(adjusted_mode) > 1;
		1326	} else {
		1327	pipe_config->limited_color_range =
		1328	intel_hdmi->limited_color_range;
3031	serge	1329	}
		1330
5354	serge	1331	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
		1332	pipe_config->pixel_multiplier = 2;
6084	serge	1333	clock_8bpc *= 2;
		1334	clock_12bpc *= 2;
5354	serge	1335	}
		1336
3746	Serge	1337	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
		1338	pipe_config->has_pch_encoder = true;
		1339
5060	serge	1340	if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
		1341	pipe_config->has_audio = true;
		1342
3746	Serge	1343	/*
		1344	* HDMI is either 12 or 8, so if the display lets 10bpc sneak
		1345	* through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
4104	Serge	1346	* outputs. We also need to check that the higher clock still fits
		1347	* within limits.
3746	Serge	1348	*/
5060	serge	1349	if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
7144	serge	1350	hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true) == MODE_OK &&
6084	serge	1351	hdmi_12bpc_possible(pipe_config)) {
4104	Serge	1352	DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
		1353	desired_bpp = 12*3;
		1354
		1355	/* Need to adjust the port link by 1.5x for 12bpc. */
		1356	pipe_config->port_clock = clock_12bpc;
3746	Serge	1357	} else {
4104	Serge	1358	DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
		1359	desired_bpp = 8*3;
6084	serge	1360
		1361	pipe_config->port_clock = clock_8bpc;
3746	Serge	1362	}
		1363
4104	Serge	1364	if (!pipe_config->bw_constrained) {
		1365	DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
		1366	pipe_config->pipe_bpp = desired_bpp;
		1367	}
		1368
6084	serge	1369	if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
		1370	false) != MODE_OK) {
		1371	DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
4104	Serge	1372	return false;
		1373	}
		1374
6084	serge	1375	/* Set user selected PAR to incoming mode's member */
		1376	adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
		1377
3480	Serge	1378	return true;
3031	serge	1379	}
		1380
5354	serge	1381	static void
		1382	intel_hdmi_unset_edid(struct drm_connector *connector)
2330	Serge	1383	{
		1384	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
5354	serge	1385
		1386	intel_hdmi->has_hdmi_sink = false;
		1387	intel_hdmi->has_audio = false;
		1388	intel_hdmi->rgb_quant_range_selectable = false;
		1389
7144	serge	1390	intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
		1391	intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
		1392
5354	serge	1393	kfree(to_intel_connector(connector)->detect_edid);
		1394	to_intel_connector(connector)->detect_edid = NULL;
		1395	}
		1396
7144	serge	1397	static void
		1398	intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector)
		1399	{
		1400	struct drm_i915_private *dev_priv = to_i915(connector->dev);
		1401	struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
		1402	struct i2c_adapter *adapter =
		1403	intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
		1404	enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
		1405
		1406	if (type == DRM_DP_DUAL_MODE_NONE \|\|
		1407	type == DRM_DP_DUAL_MODE_UNKNOWN)
		1408	return;
		1409
		1410	hdmi->dp_dual_mode.type = type;
		1411	hdmi->dp_dual_mode.max_tmds_clock =
		1412	drm_dp_dual_mode_max_tmds_clock(type, adapter);
		1413
		1414	DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
		1415	drm_dp_get_dual_mode_type_name(type),
		1416	hdmi->dp_dual_mode.max_tmds_clock);
		1417	}
		1418
5354	serge	1419	static bool
6937	serge	1420	intel_hdmi_set_edid(struct drm_connector *connector, bool force)
5354	serge	1421	{
		1422	struct drm_i915_private *dev_priv = to_i915(connector->dev);
		1423	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
6937	serge	1424	struct edid *edid = NULL;
5354	serge	1425	bool connected = false;
2330	Serge	1426
6937	serge	1427	if (force) {
7144	serge	1428	intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
5060	serge	1429
6084	serge	1430	edid = drm_get_edid(connector,
		1431	intel_gmbus_get_adapter(dev_priv,
		1432	intel_hdmi->ddc_bus));
2330	Serge	1433
7144	serge	1434	intel_hdmi_dp_dual_mode_detect(connector);
		1435
		1436	intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
6937	serge	1437	}
5354	serge	1438
		1439	to_intel_connector(connector)->detect_edid = edid;
		1440	if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
6084	serge	1441	intel_hdmi->rgb_quant_range_selectable =
		1442	drm_rgb_quant_range_selectable(edid);
2330	Serge	1443
5354	serge	1444	intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
3031	serge	1445	if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
		1446	intel_hdmi->has_audio =
5354	serge	1447	intel_hdmi->force_audio == HDMI_AUDIO_ON;
		1448
		1449	if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
		1450	intel_hdmi->has_hdmi_sink =
		1451	drm_detect_hdmi_monitor(edid);
		1452
		1453	connected = true;
2330	Serge	1454	}
		1455
5354	serge	1456	return connected;
		1457	}
5060	serge	1458
5354	serge	1459	static enum drm_connector_status
		1460	intel_hdmi_detect(struct drm_connector *connector, bool force)
		1461	{
		1462	enum drm_connector_status status;
6937	serge	1463	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
6084	serge	1464	struct drm_i915_private *dev_priv = to_i915(connector->dev);
6937	serge	1465	bool live_status = false;
		1466	unsigned int try;
5354	serge	1467
		1468	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		1469	connector->base.id, connector->name);
		1470
6084	serge	1471	intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
		1472
6937	serge	1473	for (try = 0; !live_status && try < 9; try++) {
		1474	if (try)
		1475	msleep(10);
		1476	live_status = intel_digital_port_connected(dev_priv,
		1477	hdmi_to_dig_port(intel_hdmi));
		1478	}
		1479
		1480	if (!live_status) {
		1481	DRM_DEBUG_KMS("HDMI live status down\n");
		1482	/*
		1483	* Live status register is not reliable on all intel platforms.
		1484	* So consider live_status only for certain platforms, for
		1485	* others, read EDID to determine presence of sink.
		1486	*/
		1487	if (INTEL_INFO(dev_priv)->gen < 7 \|\| IS_IVYBRIDGE(dev_priv))
		1488	live_status = true;
		1489	}
		1490
5354	serge	1491	intel_hdmi_unset_edid(connector);
		1492
6937	serge	1493	if (intel_hdmi_set_edid(connector, live_status)) {
5354	serge	1494	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
		1495
		1496	hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
		1497	status = connector_status_connected;
		1498	} else
		1499	status = connector_status_disconnected;
		1500
6084	serge	1501	intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
		1502
2330	Serge	1503	return status;
		1504	}
		1505
5354	serge	1506	static void
		1507	intel_hdmi_force(struct drm_connector *connector)
2330	Serge	1508	{
5354	serge	1509	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2330	Serge	1510
5354	serge	1511	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		1512	connector->base.id, connector->name);
2330	Serge	1513
5354	serge	1514	intel_hdmi_unset_edid(connector);
5060	serge	1515
5354	serge	1516	if (connector->status != connector_status_connected)
		1517	return;
5060	serge	1518
6937	serge	1519	intel_hdmi_set_edid(connector, true);
5354	serge	1520	hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
		1521	}
5060	serge	1522
5354	serge	1523	static int intel_hdmi_get_modes(struct drm_connector *connector)
		1524	{
		1525	struct edid *edid;
		1526
		1527	edid = to_intel_connector(connector)->detect_edid;
		1528	if (edid == NULL)
		1529	return 0;
		1530
		1531	return intel_connector_update_modes(connector, edid);
2330	Serge	1532	}
		1533
		1534	static bool
		1535	intel_hdmi_detect_audio(struct drm_connector *connector)
		1536	{
5354	serge	1537	bool has_audio = false;
2330	Serge	1538	struct edid *edid;
		1539
5354	serge	1540	edid = to_intel_connector(connector)->detect_edid;
		1541	if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
6084	serge	1542	has_audio = drm_detect_monitor_audio(edid);
2330	Serge	1543
		1544	return has_audio;
		1545	}
		1546
		1547	static int
		1548	intel_hdmi_set_property(struct drm_connector *connector,
6084	serge	1549	struct drm_property *property,
		1550	uint64_t val)
2330	Serge	1551	{
		1552	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
3243	Serge	1553	struct intel_digital_port *intel_dig_port =
		1554	hdmi_to_dig_port(intel_hdmi);
2330	Serge	1555	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		1556	int ret;
		1557
3243	Serge	1558	ret = drm_object_property_set_value(&connector->base, property, val);
2330	Serge	1559	if (ret)
		1560	return ret;
3480	Serge	1561
2330	Serge	1562	if (property == dev_priv->force_audio_property) {
3031	serge	1563	enum hdmi_force_audio i = val;
2330	Serge	1564	bool has_audio;
		1565
		1566	if (i == intel_hdmi->force_audio)
		1567	return 0;
		1568
		1569	intel_hdmi->force_audio = i;
		1570
3031	serge	1571	if (i == HDMI_AUDIO_AUTO)
2330	Serge	1572	has_audio = intel_hdmi_detect_audio(connector);
		1573	else
3031	serge	1574	has_audio = (i == HDMI_AUDIO_ON);
2330	Serge	1575
3031	serge	1576	if (i == HDMI_AUDIO_OFF_DVI)
		1577	intel_hdmi->has_hdmi_sink = 0;
2330	Serge	1578
		1579	intel_hdmi->has_audio = has_audio;
		1580	goto done;
		1581	}
		1582
		1583	if (property == dev_priv->broadcast_rgb_property) {
3746	Serge	1584	bool old_auto = intel_hdmi->color_range_auto;
6084	serge	1585	bool old_range = intel_hdmi->limited_color_range;
3746	Serge	1586
3480	Serge	1587	switch (val) {
		1588	case INTEL_BROADCAST_RGB_AUTO:
		1589	intel_hdmi->color_range_auto = true;
		1590	break;
		1591	case INTEL_BROADCAST_RGB_FULL:
		1592	intel_hdmi->color_range_auto = false;
6084	serge	1593	intel_hdmi->limited_color_range = false;
3480	Serge	1594	break;
		1595	case INTEL_BROADCAST_RGB_LIMITED:
		1596	intel_hdmi->color_range_auto = false;
6084	serge	1597	intel_hdmi->limited_color_range = true;
3480	Serge	1598	break;
		1599	default:
		1600	return -EINVAL;
		1601	}
3746	Serge	1602
		1603	if (old_auto == intel_hdmi->color_range_auto &&
6084	serge	1604	old_range == intel_hdmi->limited_color_range)
3746	Serge	1605	return 0;
		1606
2330	Serge	1607	goto done;
		1608	}
3031	serge	1609
5060	serge	1610	if (property == connector->dev->mode_config.aspect_ratio_property) {
		1611	switch (val) {
		1612	case DRM_MODE_PICTURE_ASPECT_NONE:
		1613	intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
		1614	break;
		1615	case DRM_MODE_PICTURE_ASPECT_4_3:
		1616	intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
		1617	break;
		1618	case DRM_MODE_PICTURE_ASPECT_16_9:
		1619	intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
		1620	break;
		1621	default:
		1622	return -EINVAL;
		1623	}
		1624	goto done;
		1625	}
		1626
2330	Serge	1627	return -EINVAL;
		1628
		1629	done:
3480	Serge	1630	if (intel_dig_port->base.base.crtc)
		1631	intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
2330	Serge	1632
		1633	return 0;
		1634	}
		1635
5060	serge	1636	static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
		1637	{
		1638	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
		1639	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
6084	serge	1640	const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
5060	serge	1641
		1642	intel_hdmi_prepare(encoder);
		1643
		1644	intel_hdmi->set_infoframes(&encoder->base,
6084	serge	1645	intel_crtc->config->has_hdmi_sink,
5060	serge	1646	adjusted_mode);
		1647	}
		1648
4560	Serge	1649	static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
4104	Serge	1650	{
		1651	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
5060	serge	1652	struct intel_hdmi *intel_hdmi = &dport->hdmi;
4104	Serge	1653	struct drm_device *dev = encoder->base.dev;
		1654	struct drm_i915_private *dev_priv = dev->dev_private;
		1655	struct intel_crtc *intel_crtc =
		1656	to_intel_crtc(encoder->base.crtc);
6084	serge	1657	const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
4560	Serge	1658	enum dpio_channel port = vlv_dport_to_channel(dport);
4104	Serge	1659	int pipe = intel_crtc->pipe;
		1660	u32 val;
		1661
		1662	/* Enable clock channels for this port */
6084	serge	1663	mutex_lock(&dev_priv->sb_lock);
4560	Serge	1664	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
4104	Serge	1665	val = 0;
		1666	if (pipe)
		1667	val \|= (1<<21);
		1668	else
		1669	val &= ~(1<<21);
		1670	val \|= 0x001000c4;
4560	Serge	1671	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
4104	Serge	1672
		1673	/* HDMI 1.0V-2dB */
4560	Serge	1674	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
		1675	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
		1676	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
		1677	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
		1678	vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
		1679	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
		1680	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
		1681	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
4104	Serge	1682
		1683	/* Program lane clock */
4560	Serge	1684	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
		1685	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
6084	serge	1686	mutex_unlock(&dev_priv->sb_lock);
4104	Serge	1687
5060	serge	1688	intel_hdmi->set_infoframes(&encoder->base,
6084	serge	1689	intel_crtc->config->has_hdmi_sink,
5060	serge	1690	adjusted_mode);
		1691
6084	serge	1692	g4x_enable_hdmi(encoder);
4104	Serge	1693
6084	serge	1694	vlv_wait_port_ready(dev_priv, dport, 0x0);
4104	Serge	1695	}
		1696
4560	Serge	1697	static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
4104	Serge	1698	{
		1699	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
		1700	struct drm_device *dev = encoder->base.dev;
		1701	struct drm_i915_private *dev_priv = dev->dev_private;
4560	Serge	1702	struct intel_crtc *intel_crtc =
		1703	to_intel_crtc(encoder->base.crtc);
		1704	enum dpio_channel port = vlv_dport_to_channel(dport);
		1705	int pipe = intel_crtc->pipe;
4104	Serge	1706
5060	serge	1707	intel_hdmi_prepare(encoder);
4104	Serge	1708
		1709	/* Program Tx lane resets to default */
6084	serge	1710	mutex_lock(&dev_priv->sb_lock);
4560	Serge	1711	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
4104	Serge	1712	DPIO_PCS_TX_LANE2_RESET \|
		1713	DPIO_PCS_TX_LANE1_RESET);
4560	Serge	1714	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
4104	Serge	1715	DPIO_PCS_CLK_CRI_RXEB_EIOS_EN \|
		1716	DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN \|
		1717	(1<
		1718	DPIO_PCS_CLK_SOFT_RESET);
		1719
		1720	/* Fix up inter-pair skew failure */
4560	Serge	1721	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
		1722	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
		1723	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
4104	Serge	1724
4560	Serge	1725	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
		1726	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
6084	serge	1727	mutex_unlock(&dev_priv->sb_lock);
4104	Serge	1728	}
		1729
6084	serge	1730	static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
		1731	bool reset)
		1732	{
		1733	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
		1734	enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
		1735	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
		1736	enum pipe pipe = crtc->pipe;
		1737	uint32_t val;
		1738
		1739	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
		1740	if (reset)
		1741	val &= ~(DPIO_PCS_TX_LANE2_RESET \| DPIO_PCS_TX_LANE1_RESET);
		1742	else
		1743	val \|= DPIO_PCS_TX_LANE2_RESET \| DPIO_PCS_TX_LANE1_RESET;
		1744	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
		1745
		1746	if (crtc->config->lane_count > 2) {
		1747	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
		1748	if (reset)
		1749	val &= ~(DPIO_PCS_TX_LANE2_RESET \| DPIO_PCS_TX_LANE1_RESET);
		1750	else
		1751	val \|= DPIO_PCS_TX_LANE2_RESET \| DPIO_PCS_TX_LANE1_RESET;
		1752	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
		1753	}
		1754
		1755	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
		1756	val \|= CHV_PCS_REQ_SOFTRESET_EN;
		1757	if (reset)
		1758	val &= ~DPIO_PCS_CLK_SOFT_RESET;
		1759	else
		1760	val \|= DPIO_PCS_CLK_SOFT_RESET;
		1761	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
		1762
		1763	if (crtc->config->lane_count > 2) {
		1764	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
		1765	val \|= CHV_PCS_REQ_SOFTRESET_EN;
		1766	if (reset)
		1767	val &= ~DPIO_PCS_CLK_SOFT_RESET;
		1768	else
		1769	val \|= DPIO_PCS_CLK_SOFT_RESET;
		1770	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
		1771	}
		1772	}
		1773
5060	serge	1774	static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
		1775	{
		1776	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
		1777	struct drm_device *dev = encoder->base.dev;
		1778	struct drm_i915_private *dev_priv = dev->dev_private;
		1779	struct intel_crtc *intel_crtc =
		1780	to_intel_crtc(encoder->base.crtc);
		1781	enum dpio_channel ch = vlv_dport_to_channel(dport);
		1782	enum pipe pipe = intel_crtc->pipe;
		1783	u32 val;
		1784
5354	serge	1785	intel_hdmi_prepare(encoder);
		1786
6084	serge	1787	/*
		1788	* Must trick the second common lane into life.
		1789	* Otherwise we can't even access the PLL.
		1790	*/
		1791	if (ch == DPIO_CH0 && pipe == PIPE_B)
		1792	dport->release_cl2_override =
		1793	!chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
5060	serge	1794
6084	serge	1795	chv_phy_powergate_lanes(encoder, true, 0x0);
		1796
		1797	mutex_lock(&dev_priv->sb_lock);
		1798
		1799	/* Assert data lane reset */
		1800	chv_data_lane_soft_reset(encoder, true);
		1801
5060	serge	1802	/* program left/right clock distribution */
		1803	if (pipe != PIPE_B) {
		1804	val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
		1805	val &= ~(CHV_BUFLEFTENA1_MASK \| CHV_BUFRIGHTENA1_MASK);
		1806	if (ch == DPIO_CH0)
		1807	val \|= CHV_BUFLEFTENA1_FORCE;
		1808	if (ch == DPIO_CH1)
		1809	val \|= CHV_BUFRIGHTENA1_FORCE;
		1810	vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
		1811	} else {
		1812	val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
		1813	val &= ~(CHV_BUFLEFTENA2_MASK \| CHV_BUFRIGHTENA2_MASK);
		1814	if (ch == DPIO_CH0)
		1815	val \|= CHV_BUFLEFTENA2_FORCE;
		1816	if (ch == DPIO_CH1)
		1817	val \|= CHV_BUFRIGHTENA2_FORCE;
		1818	vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
		1819	}
		1820
		1821	/* program clock channel usage */
		1822	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
		1823	val \|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
		1824	if (pipe != PIPE_B)
		1825	val &= ~CHV_PCS_USEDCLKCHANNEL;
		1826	else
		1827	val \|= CHV_PCS_USEDCLKCHANNEL;
		1828	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
		1829
		1830	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
		1831	val \|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
		1832	if (pipe != PIPE_B)
		1833	val &= ~CHV_PCS_USEDCLKCHANNEL;
		1834	else
		1835	val \|= CHV_PCS_USEDCLKCHANNEL;
		1836	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
		1837
		1838	/*
		1839	* This a a bit weird since generally CL
		1840	* matches the pipe, but here we need to
		1841	* pick the CL based on the port.
		1842	*/
		1843	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
		1844	if (pipe != PIPE_B)
		1845	val &= ~CHV_CMN_USEDCLKCHANNEL;
		1846	else
		1847	val \|= CHV_CMN_USEDCLKCHANNEL;
		1848	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
		1849
6084	serge	1850	mutex_unlock(&dev_priv->sb_lock);
5060	serge	1851	}
		1852
6084	serge	1853	static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
		1854	{
		1855	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
		1856	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
		1857	u32 val;
		1858
		1859	mutex_lock(&dev_priv->sb_lock);
		1860
		1861	/* disable left/right clock distribution */
		1862	if (pipe != PIPE_B) {
		1863	val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
		1864	val &= ~(CHV_BUFLEFTENA1_MASK \| CHV_BUFRIGHTENA1_MASK);
		1865	vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
		1866	} else {
		1867	val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
		1868	val &= ~(CHV_BUFLEFTENA2_MASK \| CHV_BUFRIGHTENA2_MASK);
		1869	vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
		1870	}
		1871
		1872	mutex_unlock(&dev_priv->sb_lock);
		1873
		1874	/*
		1875	* Leave the power down bit cleared for at least one
		1876	* lane so that chv_powergate_phy_ch() will power
		1877	* on something when the channel is otherwise unused.
		1878	* When the port is off and the override is removed
		1879	* the lanes power down anyway, so otherwise it doesn't
		1880	* really matter what the state of power down bits is
		1881	* after this.
		1882	*/
		1883	chv_phy_powergate_lanes(encoder, false, 0x0);
		1884	}
		1885
4560	Serge	1886	static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
4104	Serge	1887	{
		1888	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
		1889	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
4560	Serge	1890	struct intel_crtc *intel_crtc =
		1891	to_intel_crtc(encoder->base.crtc);
		1892	enum dpio_channel port = vlv_dport_to_channel(dport);
		1893	int pipe = intel_crtc->pipe;
4104	Serge	1894
		1895	/* Reset lanes to avoid HDMI flicker (VLV w/a) */
6084	serge	1896	mutex_lock(&dev_priv->sb_lock);
4560	Serge	1897	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
		1898	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
6084	serge	1899	mutex_unlock(&dev_priv->sb_lock);
4104	Serge	1900	}
		1901
5060	serge	1902	static void chv_hdmi_post_disable(struct intel_encoder *encoder)
		1903	{
		1904	struct drm_device *dev = encoder->base.dev;
		1905	struct drm_i915_private *dev_priv = dev->dev_private;
		1906
6084	serge	1907	mutex_lock(&dev_priv->sb_lock);
5060	serge	1908
6084	serge	1909	/* Assert data lane reset */
		1910	chv_data_lane_soft_reset(encoder, true);
5060	serge	1911
6084	serge	1912	mutex_unlock(&dev_priv->sb_lock);
5060	serge	1913	}
		1914
		1915	static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
		1916	{
		1917	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
5354	serge	1918	struct intel_hdmi *intel_hdmi = &dport->hdmi;
5060	serge	1919	struct drm_device *dev = encoder->base.dev;
		1920	struct drm_i915_private *dev_priv = dev->dev_private;
		1921	struct intel_crtc *intel_crtc =
		1922	to_intel_crtc(encoder->base.crtc);
6084	serge	1923	const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
5060	serge	1924	enum dpio_channel ch = vlv_dport_to_channel(dport);
		1925	int pipe = intel_crtc->pipe;
6084	serge	1926	int data, i, stagger;
5060	serge	1927	u32 val;
		1928
6084	serge	1929	mutex_lock(&dev_priv->sb_lock);
5060	serge	1930
5354	serge	1931	/* allow hardware to manage TX FIFO reset source */
		1932	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
		1933	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
		1934	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
		1935
		1936	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
		1937	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
		1938	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
		1939
5060	serge	1940	/* Program Tx latency optimal setting */
		1941	for (i = 0; i < 4; i++) {
		1942	/* Set the upar bit */
		1943	data = (i == 1) ? 0x0 : 0x1;
		1944	vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
		1945	data << DPIO_UPAR_SHIFT);
		1946	}
		1947
		1948	/* Data lane stagger programming */
6084	serge	1949	if (intel_crtc->config->port_clock > 270000)
		1950	stagger = 0x18;
		1951	else if (intel_crtc->config->port_clock > 135000)
		1952	stagger = 0xd;
		1953	else if (intel_crtc->config->port_clock > 67500)
		1954	stagger = 0x7;
		1955	else if (intel_crtc->config->port_clock > 33750)
		1956	stagger = 0x4;
		1957	else
		1958	stagger = 0x2;
5060	serge	1959
6084	serge	1960	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
		1961	val \|= DPIO_TX2_STAGGER_MASK(0x1f);
		1962	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
		1963
		1964	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
		1965	val \|= DPIO_TX2_STAGGER_MASK(0x1f);
		1966	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
		1967
		1968	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
		1969	DPIO_LANESTAGGER_STRAP(stagger) \|
		1970	DPIO_LANESTAGGER_STRAP_OVRD \|
		1971	DPIO_TX1_STAGGER_MASK(0x1f) \|
		1972	DPIO_TX1_STAGGER_MULT(6) \|
		1973	DPIO_TX2_STAGGER_MULT(0));
		1974
		1975	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
		1976	DPIO_LANESTAGGER_STRAP(stagger) \|
		1977	DPIO_LANESTAGGER_STRAP_OVRD \|
		1978	DPIO_TX1_STAGGER_MASK(0x1f) \|
		1979	DPIO_TX1_STAGGER_MULT(7) \|
		1980	DPIO_TX2_STAGGER_MULT(5));
		1981
		1982	/* Deassert data lane reset */
		1983	chv_data_lane_soft_reset(encoder, false);
		1984
5060	serge	1985	/* Clear calc init */
		1986	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
		1987	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 \| DPIO_PCS_SWING_CALC_TX1_TX3);
5354	serge	1988	val &= ~(DPIO_PCS_TX1DEEMP_MASK \| DPIO_PCS_TX2DEEMP_MASK);
		1989	val \|= DPIO_PCS_TX1DEEMP_9P5 \| DPIO_PCS_TX2DEEMP_9P5;
5060	serge	1990	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
		1991
		1992	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
		1993	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 \| DPIO_PCS_SWING_CALC_TX1_TX3);
5354	serge	1994	val &= ~(DPIO_PCS_TX1DEEMP_MASK \| DPIO_PCS_TX2DEEMP_MASK);
		1995	val \|= DPIO_PCS_TX1DEEMP_9P5 \| DPIO_PCS_TX2DEEMP_9P5;
5060	serge	1996	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
		1997
5354	serge	1998	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
		1999	val &= ~(DPIO_PCS_TX1MARGIN_MASK \| DPIO_PCS_TX2MARGIN_MASK);
		2000	val \|= DPIO_PCS_TX1MARGIN_000 \| DPIO_PCS_TX2MARGIN_000;
		2001	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
		2002
		2003	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
		2004	val &= ~(DPIO_PCS_TX1MARGIN_MASK \| DPIO_PCS_TX2MARGIN_MASK);
		2005	val \|= DPIO_PCS_TX1MARGIN_000 \| DPIO_PCS_TX2MARGIN_000;
		2006	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
		2007
5060	serge	2008	/* FIXME: Program the support xxx V-dB */
		2009	/* Use 800mV-0dB */
		2010	for (i = 0; i < 4; i++) {
		2011	val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
		2012	val &= ~DPIO_SWING_DEEMPH9P5_MASK;
		2013	val \|= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
		2014	vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
		2015	}
		2016
		2017	for (i = 0; i < 4; i++) {
		2018	val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
6084	serge	2019
5354	serge	2020	val &= ~DPIO_SWING_MARGIN000_MASK;
		2021	val \|= 102 << DPIO_SWING_MARGIN000_SHIFT;
6084	serge	2022
		2023	/*
		2024	* Supposedly this value shouldn't matter when unique transition
		2025	* scale is disabled, but in fact it does matter. Let's just
		2026	* always program the same value and hope it's OK.
		2027	*/
		2028	val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
		2029	val \|= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
		2030
5060	serge	2031	vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
		2032	}
		2033
6084	serge	2034	/*
		2035	* The document said it needs to set bit 27 for ch0 and bit 26
		2036	* for ch1. Might be a typo in the doc.
		2037	* For now, for this unique transition scale selection, set bit
		2038	* 27 for ch0 and ch1.
		2039	*/
5060	serge	2040	for (i = 0; i < 4; i++) {
		2041	val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
		2042	val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
		2043	vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
		2044	}
		2045
		2046	/* Start swing calculation */
		2047	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
		2048	val \|= DPIO_PCS_SWING_CALC_TX0_TX2 \| DPIO_PCS_SWING_CALC_TX1_TX3;
		2049	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
		2050
		2051	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
		2052	val \|= DPIO_PCS_SWING_CALC_TX0_TX2 \| DPIO_PCS_SWING_CALC_TX1_TX3;
		2053	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
		2054
6084	serge	2055	mutex_unlock(&dev_priv->sb_lock);
5060	serge	2056
5354	serge	2057	intel_hdmi->set_infoframes(&encoder->base,
6084	serge	2058	intel_crtc->config->has_hdmi_sink,
5354	serge	2059	adjusted_mode);
		2060
6084	serge	2061	g4x_enable_hdmi(encoder);
5060	serge	2062
6084	serge	2063	vlv_wait_port_ready(dev_priv, dport, 0x0);
		2064
		2065	/* Second common lane will stay alive on its own now */
		2066	if (dport->release_cl2_override) {
		2067	chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
		2068	dport->release_cl2_override = false;
		2069	}
5060	serge	2070	}
		2071
2330	Serge	2072	static void intel_hdmi_destroy(struct drm_connector *connector)
		2073	{
5354	serge	2074	kfree(to_intel_connector(connector)->detect_edid);
2330	Serge	2075	drm_connector_cleanup(connector);
		2076	kfree(connector);
		2077	}
		2078
		2079	static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
6084	serge	2080	.dpms = drm_atomic_helper_connector_dpms,
2330	Serge	2081	.detect = intel_hdmi_detect,
5354	serge	2082	.force = intel_hdmi_force,
2330	Serge	2083	.fill_modes = drm_helper_probe_single_connector_modes,
		2084	.set_property = intel_hdmi_set_property,
6084	serge	2085	.atomic_get_property = intel_connector_atomic_get_property,
2330	Serge	2086	.destroy = intel_hdmi_destroy,
6084	serge	2087	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
		2088	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2330	Serge	2089	};
		2090
		2091	static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
		2092	.get_modes = intel_hdmi_get_modes,
		2093	.mode_valid = intel_hdmi_mode_valid,
		2094	.best_encoder = intel_best_encoder,
		2095	};
		2096
		2097	static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
		2098	.destroy = intel_encoder_destroy,
		2099	};
		2100
		2101	static void
		2102	intel_hdmi_add_properties(struct intel_hdmi intel_hdmi, struct drm_connector connector)
		2103	{
		2104	intel_attach_force_audio_property(connector);
		2105	intel_attach_broadcast_rgb_property(connector);
3480	Serge	2106	intel_hdmi->color_range_auto = true;
5060	serge	2107	intel_attach_aspect_ratio_property(connector);
		2108	intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2330	Serge	2109	}
		2110
3243	Serge	2111	void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
		2112	struct intel_connector *intel_connector)
2330	Serge	2113	{
3243	Serge	2114	struct drm_connector *connector = &intel_connector->base;
		2115	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
		2116	struct intel_encoder *intel_encoder = &intel_dig_port->base;
		2117	struct drm_device *dev = intel_encoder->base.dev;
2330	Serge	2118	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	2119	enum port port = intel_dig_port->port;
6937	serge	2120	uint8_t alternate_ddc_pin;
2330	Serge	2121
7144	serge	2122	if (WARN(intel_dig_port->max_lanes < 4,
		2123	"Not enough lanes (%d) for HDMI on port %c\n",
		2124	intel_dig_port->max_lanes, port_name(port)))
		2125	return;
		2126
2330	Serge	2127	drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
		2128	DRM_MODE_CONNECTOR_HDMIA);
		2129	drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
		2130
3031	serge	2131	connector->interlace_allowed = 1;
2330	Serge	2132	connector->doublescan_allowed = 0;
4560	Serge	2133	connector->stereo_allowed = 1;
2330	Serge	2134
3031	serge	2135	switch (port) {
		2136	case PORT_B:
6937	serge	2137	if (IS_BROXTON(dev_priv))
		2138	intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
		2139	else
		2140	intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
6084	serge	2141	/*
		2142	* On BXT A0/A1, sw needs to activate DDIA HPD logic and
		2143	* interrupts to check the external panel connection.
		2144	*/
6937	serge	2145	if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
6084	serge	2146	intel_encoder->hpd_pin = HPD_PORT_A;
		2147	else
		2148	intel_encoder->hpd_pin = HPD_PORT_B;
3031	serge	2149	break;
		2150	case PORT_C:
6937	serge	2151	if (IS_BROXTON(dev_priv))
		2152	intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;
		2153	else
		2154	intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
3746	Serge	2155	intel_encoder->hpd_pin = HPD_PORT_C;
3031	serge	2156	break;
		2157	case PORT_D:
6937	serge	2158	if (WARN_ON(IS_BROXTON(dev_priv)))
		2159	intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;
		2160	else if (IS_CHERRYVIEW(dev_priv))
		2161	intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;
		2162	else
		2163	intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
3746	Serge	2164	intel_encoder->hpd_pin = HPD_PORT_D;
3031	serge	2165	break;
6084	serge	2166	case PORT_E:
6937	serge	2167	/* On SKL PORT E doesn't have seperate GMBUS pin
		2168	* We rely on VBT to set a proper alternate GMBUS pin. */
		2169	alternate_ddc_pin =
		2170	dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin;
		2171	switch (alternate_ddc_pin) {
		2172	case DDC_PIN_B:
		2173	intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
		2174	break;
		2175	case DDC_PIN_C:
		2176	intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
		2177	break;
		2178	case DDC_PIN_D:
		2179	intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
		2180	break;
		2181	default:
		2182	MISSING_CASE(alternate_ddc_pin);
		2183	}
6084	serge	2184	intel_encoder->hpd_pin = HPD_PORT_E;
		2185	break;
6937	serge	2186	case PORT_A:
		2187	intel_encoder->hpd_pin = HPD_PORT_A;
		2188	/* Internal port only for eDP. */
3031	serge	2189	default:
6937	serge	2190	BUG();
2330	Serge	2191	}
		2192
6937	serge	2193	if (IS_VALLEYVIEW(dev) \|\| IS_CHERRYVIEW(dev)) {
3746	Serge	2194	intel_hdmi->write_infoframe = vlv_write_infoframe;
		2195	intel_hdmi->set_infoframes = vlv_set_infoframes;
5354	serge	2196	intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
5060	serge	2197	} else if (IS_G4X(dev)) {
3031	serge	2198	intel_hdmi->write_infoframe = g4x_write_infoframe;
		2199	intel_hdmi->set_infoframes = g4x_set_infoframes;
5354	serge	2200	intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
3746	Serge	2201	} else if (HAS_DDI(dev)) {
3031	serge	2202	intel_hdmi->write_infoframe = hsw_write_infoframe;
		2203	intel_hdmi->set_infoframes = hsw_set_infoframes;
5354	serge	2204	intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
3031	serge	2205	} else if (HAS_PCH_IBX(dev)) {
		2206	intel_hdmi->write_infoframe = ibx_write_infoframe;
		2207	intel_hdmi->set_infoframes = ibx_set_infoframes;
5354	serge	2208	intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
2342	Serge	2209	} else {
3031	serge	2210	intel_hdmi->write_infoframe = cpt_write_infoframe;
		2211	intel_hdmi->set_infoframes = cpt_set_infoframes;
5354	serge	2212	intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
2342	Serge	2213	}
2330	Serge	2214
3480	Serge	2215	if (HAS_DDI(dev))
3243	Serge	2216	intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
		2217	else
6084	serge	2218	intel_connector->get_hw_state = intel_connector_get_hw_state;
5060	serge	2219	intel_connector->unregister = intel_connector_unregister;
2330	Serge	2220
		2221	intel_hdmi_add_properties(intel_hdmi, connector);
		2222
		2223	intel_connector_attach_encoder(intel_connector, intel_encoder);
5060	serge	2224	drm_connector_register(connector);
6084	serge	2225	intel_hdmi->attached_connector = intel_connector;
2330	Serge	2226
		2227	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
		2228	* 0xd. Failure to do so will result in spurious interrupts being
		2229	* generated on the port when a cable is not attached.
		2230	*/
		2231	if (IS_G4X(dev) && !IS_GM45(dev)) {
		2232	u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		2233	I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) \| 0xd);
		2234	}
		2235	}
3243	Serge	2236
6937	serge	2237	void intel_hdmi_init(struct drm_device *dev,
		2238	i915_reg_t hdmi_reg, enum port port)
3243	Serge	2239	{
		2240	struct intel_digital_port *intel_dig_port;
		2241	struct intel_encoder *intel_encoder;
		2242	struct intel_connector *intel_connector;
		2243
4560	Serge	2244	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3243	Serge	2245	if (!intel_dig_port)
		2246	return;
		2247
6084	serge	2248	intel_connector = intel_connector_alloc();
3243	Serge	2249	if (!intel_connector) {
		2250	kfree(intel_dig_port);
		2251	return;
		2252	}
		2253
		2254	intel_encoder = &intel_dig_port->base;
		2255
		2256	drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
6937	serge	2257	DRM_MODE_ENCODER_TMDS, NULL);
3243	Serge	2258
3746	Serge	2259	intel_encoder->compute_config = intel_hdmi_compute_config;
6084	serge	2260	if (HAS_PCH_SPLIT(dev)) {
		2261	intel_encoder->disable = pch_disable_hdmi;
		2262	intel_encoder->post_disable = pch_post_disable_hdmi;
		2263	} else {
		2264	intel_encoder->disable = g4x_disable_hdmi;
		2265	}
3243	Serge	2266	intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
4104	Serge	2267	intel_encoder->get_config = intel_hdmi_get_config;
5060	serge	2268	if (IS_CHERRYVIEW(dev)) {
		2269	intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
		2270	intel_encoder->pre_enable = chv_hdmi_pre_enable;
		2271	intel_encoder->enable = vlv_enable_hdmi;
		2272	intel_encoder->post_disable = chv_hdmi_post_disable;
6084	serge	2273	intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
5060	serge	2274	} else if (IS_VALLEYVIEW(dev)) {
4560	Serge	2275	intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
		2276	intel_encoder->pre_enable = vlv_hdmi_pre_enable;
4104	Serge	2277	intel_encoder->enable = vlv_enable_hdmi;
4560	Serge	2278	intel_encoder->post_disable = vlv_hdmi_post_disable;
4104	Serge	2279	} else {
5060	serge	2280	intel_encoder->pre_enable = intel_hdmi_pre_enable;
6084	serge	2281	if (HAS_PCH_CPT(dev))
		2282	intel_encoder->enable = cpt_enable_hdmi;
		2283	else if (HAS_PCH_IBX(dev))
		2284	intel_encoder->enable = ibx_enable_hdmi;
		2285	else
		2286	intel_encoder->enable = g4x_enable_hdmi;
4104	Serge	2287	}
3243	Serge	2288
		2289	intel_encoder->type = INTEL_OUTPUT_HDMI;
5060	serge	2290	if (IS_CHERRYVIEW(dev)) {
		2291	if (port == PORT_D)
		2292	intel_encoder->crtc_mask = 1 << 2;
		2293	else
		2294	intel_encoder->crtc_mask = (1 << 0) \| (1 << 1);
		2295	} else {
6084	serge	2296	intel_encoder->crtc_mask = (1 << 0) \| (1 << 1) \| (1 << 2);
5060	serge	2297	}
		2298	intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
		2299	/*
		2300	* BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
		2301	* to work on real hardware. And since g4x can send infoframes to
		2302	* only one port anyway, nothing is lost by allowing it.
		2303	*/
		2304	if (IS_G4X(dev))
		2305	intel_encoder->cloneable \|= 1 << INTEL_OUTPUT_HDMI;
3243	Serge	2306
		2307	intel_dig_port->port = port;
3746	Serge	2308	intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
6937	serge	2309	intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
7144	serge	2310	intel_dig_port->max_lanes = 4;
3243	Serge	2311
		2312	intel_hdmi_init_connector(intel_dig_port, intel_connector);
		2313	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_hdmi.c @ 6660 – Rev 7144