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6084 | serge | 1 | /* |
2 | * Copyright © 2014 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Vinit Azad |
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25 | * Ben Widawsky |
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26 | * Dave Gordon |
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27 | * Alex Dai |
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28 | */ |
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29 | #include |
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30 | #include "intel_drv.h" |
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31 | #include "i915_drv.h" |
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32 | #include "intel_guc.h" |
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33 | |||
34 | /** |
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35 | * DOC: GuC |
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36 | * |
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37 | * intel_guc: |
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38 | * Top level structure of guc. It handles firmware loading and manages client |
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39 | * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy |
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40 | * ExecList submission. |
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41 | * |
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42 | * Firmware versioning: |
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43 | * The firmware build process will generate a version header file with major and |
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44 | * minor version defined. The versions are built into CSS header of firmware. |
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45 | * i915 kernel driver set the minimal firmware version required per platform. |
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46 | * The firmware installation package will install (symbolic link) proper version |
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47 | * of firmware. |
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48 | * |
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49 | * GuC address space: |
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50 | * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP), |
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51 | * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is |
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52 | * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects |
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53 | * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM. |
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54 | * |
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55 | * Firmware log: |
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56 | * Firmware log is enabled by setting i915.guc_log_level to non-negative level. |
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57 | * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from |
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58 | * i915_guc_load_status will print out firmware loading status and scratch |
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59 | * registers value. |
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60 | * |
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61 | */ |
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62 | |||
63 | #define I915_SKL_GUC_UCODE "i915/skl_guc_ver4.bin" |
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64 | MODULE_FIRMWARE(I915_SKL_GUC_UCODE); |
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65 | |||
66 | /* User-friendly representation of an enum */ |
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67 | const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status) |
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68 | { |
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69 | switch (status) { |
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70 | case GUC_FIRMWARE_FAIL: |
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71 | return "FAIL"; |
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72 | case GUC_FIRMWARE_NONE: |
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73 | return "NONE"; |
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74 | case GUC_FIRMWARE_PENDING: |
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75 | return "PENDING"; |
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76 | case GUC_FIRMWARE_SUCCESS: |
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77 | return "SUCCESS"; |
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78 | default: |
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79 | return "UNKNOWN!"; |
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80 | } |
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81 | }; |
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82 | |||
83 | static void direct_interrupts_to_host(struct drm_i915_private *dev_priv) |
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84 | { |
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85 | struct intel_engine_cs *ring; |
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86 | int i, irqs; |
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87 | |||
88 | /* tell all command streamers NOT to forward interrupts and vblank to GuC */ |
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89 | irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER); |
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90 | irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING); |
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91 | for_each_ring(ring, dev_priv, i) |
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92 | I915_WRITE(RING_MODE_GEN7(ring), irqs); |
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93 | |||
94 | /* route all GT interrupts to the host */ |
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95 | I915_WRITE(GUC_BCS_RCS_IER, 0); |
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96 | I915_WRITE(GUC_VCS2_VCS1_IER, 0); |
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97 | I915_WRITE(GUC_WD_VECS_IER, 0); |
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98 | } |
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99 | |||
100 | static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv) |
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101 | { |
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102 | struct intel_engine_cs *ring; |
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103 | int i, irqs; |
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104 | |||
105 | /* tell all command streamers to forward interrupts and vblank to GuC */ |
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106 | irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_ALWAYS); |
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107 | irqs |= _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING); |
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108 | for_each_ring(ring, dev_priv, i) |
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109 | I915_WRITE(RING_MODE_GEN7(ring), irqs); |
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110 | |||
111 | /* route USER_INTERRUPT to Host, all others are sent to GuC. */ |
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112 | irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
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113 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; |
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114 | /* These three registers have the same bit definitions */ |
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115 | I915_WRITE(GUC_BCS_RCS_IER, ~irqs); |
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116 | I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs); |
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117 | I915_WRITE(GUC_WD_VECS_IER, ~irqs); |
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118 | } |
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119 | |||
120 | static u32 get_gttype(struct drm_i915_private *dev_priv) |
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121 | { |
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122 | /* XXX: GT type based on PCI device ID? field seems unused by fw */ |
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123 | return 0; |
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124 | } |
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125 | |||
126 | static u32 get_core_family(struct drm_i915_private *dev_priv) |
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127 | { |
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128 | switch (INTEL_INFO(dev_priv)->gen) { |
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129 | case 9: |
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130 | return GFXCORE_FAMILY_GEN9; |
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131 | |||
132 | default: |
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133 | DRM_ERROR("GUC: unsupported core family\n"); |
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134 | return GFXCORE_FAMILY_UNKNOWN; |
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135 | } |
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136 | } |
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137 | |||
138 | static void set_guc_init_params(struct drm_i915_private *dev_priv) |
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139 | { |
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140 | struct intel_guc *guc = &dev_priv->guc; |
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141 | u32 params[GUC_CTL_MAX_DWORDS]; |
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142 | int i; |
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143 | |||
144 | memset(¶ms, 0, sizeof(params)); |
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145 | |||
146 | params[GUC_CTL_DEVICE_INFO] |= |
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147 | (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) | |
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148 | (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT); |
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149 | |||
150 | /* |
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151 | * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one |
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152 | * second. This ARAR is calculated by: |
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153 | * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10 |
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154 | */ |
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155 | params[GUC_CTL_ARAT_HIGH] = 0; |
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156 | params[GUC_CTL_ARAT_LOW] = 100000000; |
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157 | |||
158 | params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER; |
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159 | |||
160 | params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER | |
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161 | GUC_CTL_VCS2_ENABLED; |
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162 | |||
163 | if (i915.guc_log_level >= 0) { |
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164 | params[GUC_CTL_LOG_PARAMS] = guc->log_flags; |
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165 | params[GUC_CTL_DEBUG] = |
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166 | i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT; |
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167 | } |
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168 | |||
169 | /* If GuC submission is enabled, set up additional parameters here */ |
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170 | if (i915.enable_guc_submission) { |
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171 | u32 pgs = i915_gem_obj_ggtt_offset(dev_priv->guc.ctx_pool_obj); |
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172 | u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16; |
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173 | |||
174 | pgs >>= PAGE_SHIFT; |
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175 | params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) | |
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176 | (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT); |
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177 | |||
178 | params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS; |
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179 | |||
180 | /* Unmask this bit to enable the GuC's internal scheduler */ |
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181 | params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER; |
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182 | } |
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183 | |||
184 | I915_WRITE(SOFT_SCRATCH(0), 0); |
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185 | |||
186 | for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) |
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187 | I915_WRITE(SOFT_SCRATCH(1 + i), params[i]); |
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188 | } |
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189 | |||
190 | /* |
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191 | * Read the GuC status register (GUC_STATUS) and store it in the |
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192 | * specified location; then return a boolean indicating whether |
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193 | * the value matches either of two values representing completion |
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194 | * of the GuC boot process. |
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195 | * |
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196 | * This is used for polling the GuC status in a wait_for_atomic() |
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197 | * loop below. |
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198 | */ |
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199 | static inline bool guc_ucode_response(struct drm_i915_private *dev_priv, |
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200 | u32 *status) |
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201 | { |
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202 | u32 val = I915_READ(GUC_STATUS); |
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203 | u32 uk_val = val & GS_UKERNEL_MASK; |
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204 | *status = val; |
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205 | return (uk_val == GS_UKERNEL_READY || |
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206 | ((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE)); |
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207 | } |
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208 | |||
209 | /* |
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210 | * Transfer the firmware image to RAM for execution by the microcontroller. |
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211 | * |
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212 | * GuC Firmware layout: |
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213 | * +-------------------------------+ ---- |
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214 | * | CSS header | 128B |
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215 | * | contains major/minor version | |
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216 | * +-------------------------------+ ---- |
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217 | * | uCode | |
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218 | * +-------------------------------+ ---- |
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219 | * | RSA signature | 256B |
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220 | * +-------------------------------+ ---- |
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221 | * |
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222 | * Architecturally, the DMA engine is bidirectional, and can potentially even |
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223 | * transfer between GTT locations. This functionality is left out of the API |
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224 | * for now as there is no need for it. |
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225 | * |
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226 | * Note that GuC needs the CSS header plus uKernel code to be copied by the |
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227 | * DMA engine in one operation, whereas the RSA signature is loaded via MMIO. |
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228 | */ |
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229 | |||
230 | #define UOS_CSS_HEADER_OFFSET 0 |
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231 | #define UOS_VER_MINOR_OFFSET 0x44 |
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232 | #define UOS_VER_MAJOR_OFFSET 0x46 |
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233 | #define UOS_CSS_HEADER_SIZE 0x80 |
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234 | #define UOS_RSA_SIG_SIZE 0x100 |
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235 | |||
236 | static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv) |
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237 | { |
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238 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
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239 | struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj; |
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240 | unsigned long offset; |
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241 | struct sg_table *sg = fw_obj->pages; |
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242 | u32 status, ucode_size, rsa[UOS_RSA_SIG_SIZE / sizeof(u32)]; |
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243 | int i, ret = 0; |
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244 | |||
245 | /* uCode size, also is where RSA signature starts */ |
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246 | offset = ucode_size = guc_fw->guc_fw_size - UOS_RSA_SIG_SIZE; |
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247 | I915_WRITE(DMA_COPY_SIZE, ucode_size); |
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248 | |||
249 | /* Copy RSA signature from the fw image to HW for verification */ |
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250 | sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, UOS_RSA_SIG_SIZE, offset); |
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251 | for (i = 0; i < UOS_RSA_SIG_SIZE / sizeof(u32); i++) |
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252 | I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]); |
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253 | |||
254 | /* Set the source address for the new blob */ |
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255 | offset = i915_gem_obj_ggtt_offset(fw_obj); |
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256 | I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset)); |
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257 | I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF); |
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258 | |||
259 | /* |
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260 | * Set the DMA destination. Current uCode expects the code to be |
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261 | * loaded at 8k; locations below this are used for the stack. |
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262 | */ |
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263 | I915_WRITE(DMA_ADDR_1_LOW, 0x2000); |
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264 | I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM); |
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265 | |||
266 | /* Finally start the DMA */ |
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267 | I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA)); |
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268 | |||
269 | /* |
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270 | * Spin-wait for the DMA to complete & the GuC to start up. |
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271 | * NB: Docs recommend not using the interrupt for completion. |
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272 | * Measurements indicate this should take no more than 20ms, so a |
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273 | * timeout here indicates that the GuC has failed and is unusable. |
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274 | * (Higher levels of the driver will attempt to fall back to |
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275 | * execlist mode if this happens.) |
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276 | */ |
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277 | ret = wait_for_atomic(guc_ucode_response(dev_priv, &status), 100); |
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278 | |||
279 | DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n", |
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280 | I915_READ(DMA_CTRL), status); |
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281 | |||
282 | if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) { |
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283 | DRM_ERROR("GuC firmware signature verification failed\n"); |
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284 | ret = -ENOEXEC; |
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285 | } |
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286 | |||
287 | DRM_DEBUG_DRIVER("returning %d\n", ret); |
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288 | |||
289 | return ret; |
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290 | } |
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291 | |||
292 | /* |
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293 | * Load the GuC firmware blob into the MinuteIA. |
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294 | */ |
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295 | static int guc_ucode_xfer(struct drm_i915_private *dev_priv) |
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296 | { |
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297 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
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298 | struct drm_device *dev = dev_priv->dev; |
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299 | int ret; |
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300 | |||
301 | ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false); |
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302 | if (ret) { |
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303 | DRM_DEBUG_DRIVER("set-domain failed %d\n", ret); |
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304 | return ret; |
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305 | } |
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306 | |||
307 | ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0); |
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308 | if (ret) { |
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309 | DRM_DEBUG_DRIVER("pin failed %d\n", ret); |
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310 | return ret; |
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311 | } |
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312 | |||
313 | /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ |
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314 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); |
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315 | |||
316 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
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317 | |||
318 | /* init WOPCM */ |
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319 | I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE); |
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320 | I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE); |
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321 | |||
322 | /* Enable MIA caching. GuC clock gating is disabled. */ |
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323 | I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE); |
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324 | |||
325 | /* WaDisableMinuteIaClockGating:skl,bxt */ |
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326 | if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) || |
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327 | (IS_BROXTON(dev) && INTEL_REVID(dev) == BXT_REVID_A0)) { |
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328 | I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) & |
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329 | ~GUC_ENABLE_MIA_CLOCK_GATING)); |
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330 | } |
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331 | |||
332 | /* WaC6DisallowByGfxPause*/ |
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333 | I915_WRITE(GEN6_GFXPAUSE, 0x30FFF); |
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334 | |||
335 | if (IS_BROXTON(dev)) |
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336 | I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE); |
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337 | else |
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338 | I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE); |
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339 | |||
340 | if (IS_GEN9(dev)) { |
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341 | /* DOP Clock Gating Enable for GuC clocks */ |
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342 | I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE | |
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343 | I915_READ(GEN7_MISCCPCTL))); |
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344 | |||
345 | /* allows for 5us before GT can go to RC6 */ |
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346 | I915_WRITE(GUC_ARAT_C6DIS, 0x1FF); |
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347 | } |
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348 | |||
349 | set_guc_init_params(dev_priv); |
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350 | |||
351 | ret = guc_ucode_xfer_dma(dev_priv); |
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352 | |||
353 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
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354 | |||
355 | /* |
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356 | * We keep the object pages for reuse during resume. But we can unpin it |
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357 | * now that DMA has completed, so it doesn't continue to take up space. |
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358 | */ |
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359 | i915_gem_object_ggtt_unpin(guc_fw->guc_fw_obj); |
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360 | |||
361 | return ret; |
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362 | } |
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363 | |||
364 | /** |
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365 | * intel_guc_ucode_load() - load GuC uCode into the device |
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366 | * @dev: drm device |
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367 | * |
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368 | * Called from gem_init_hw() during driver loading and also after a GPU reset. |
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369 | * |
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370 | * The firmware image should have already been fetched into memory by the |
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371 | * earlier call to intel_guc_ucode_init(), so here we need only check that |
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372 | * is succeeded, and then transfer the image to the h/w. |
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373 | * |
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374 | * Return: non-zero code on error |
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375 | */ |
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376 | int intel_guc_ucode_load(struct drm_device *dev) |
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377 | { |
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378 | struct drm_i915_private *dev_priv = dev->dev_private; |
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379 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
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380 | int err = 0; |
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381 | |||
382 | DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n", |
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383 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status), |
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384 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); |
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385 | |||
386 | direct_interrupts_to_host(dev_priv); |
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387 | |||
388 | if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_NONE) |
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389 | return 0; |
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390 | |||
391 | if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_SUCCESS && |
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392 | guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) |
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393 | return -ENOEXEC; |
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394 | |||
395 | guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING; |
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396 | |||
397 | DRM_DEBUG_DRIVER("GuC fw fetch status %s\n", |
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398 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); |
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399 | |||
400 | switch (guc_fw->guc_fw_fetch_status) { |
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401 | case GUC_FIRMWARE_FAIL: |
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402 | /* something went wrong :( */ |
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403 | err = -EIO; |
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404 | goto fail; |
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405 | |||
406 | case GUC_FIRMWARE_NONE: |
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407 | case GUC_FIRMWARE_PENDING: |
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408 | default: |
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409 | /* "can't happen" */ |
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410 | WARN_ONCE(1, "GuC fw %s invalid guc_fw_fetch_status %s [%d]\n", |
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411 | guc_fw->guc_fw_path, |
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412 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status), |
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413 | guc_fw->guc_fw_fetch_status); |
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414 | err = -ENXIO; |
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415 | goto fail; |
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416 | |||
417 | case GUC_FIRMWARE_SUCCESS: |
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418 | break; |
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419 | } |
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420 | |||
421 | err = i915_guc_submission_init(dev); |
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422 | if (err) |
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423 | goto fail; |
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424 | |||
425 | err = guc_ucode_xfer(dev_priv); |
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426 | if (err) |
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427 | goto fail; |
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428 | |||
429 | guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS; |
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430 | |||
431 | DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n", |
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432 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status), |
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433 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); |
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434 | |||
435 | if (i915.enable_guc_submission) { |
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436 | /* The execbuf_client will be recreated. Release it first. */ |
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437 | i915_guc_submission_disable(dev); |
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438 | |||
439 | err = i915_guc_submission_enable(dev); |
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440 | if (err) |
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441 | goto fail; |
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442 | direct_interrupts_to_guc(dev_priv); |
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443 | } |
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444 | |||
445 | return 0; |
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446 | |||
447 | fail: |
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448 | if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING) |
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449 | guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL; |
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450 | |||
451 | direct_interrupts_to_host(dev_priv); |
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452 | i915_guc_submission_disable(dev); |
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453 | |||
454 | return err; |
||
455 | } |
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456 | |||
457 | static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw) |
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458 | { |
||
459 | struct drm_i915_gem_object *obj; |
||
460 | const struct firmware *fw; |
||
461 | const u8 *css_header; |
||
462 | const size_t minsize = UOS_CSS_HEADER_SIZE + UOS_RSA_SIG_SIZE; |
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463 | const size_t maxsize = GUC_WOPCM_SIZE_VALUE + UOS_RSA_SIG_SIZE |
||
464 | - 0x8000; /* 32k reserved (8K stack + 24k context) */ |
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465 | int err; |
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466 | |||
467 | DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n", |
||
468 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); |
||
469 | |||
470 | err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev); |
||
471 | if (err) |
||
472 | goto fail; |
||
473 | if (!fw) |
||
474 | goto fail; |
||
475 | |||
476 | DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n", |
||
477 | guc_fw->guc_fw_path, fw); |
||
478 | DRM_DEBUG_DRIVER("firmware file size %zu (minimum %zu, maximum %zu)\n", |
||
479 | fw->size, minsize, maxsize); |
||
480 | |||
481 | /* Check the size of the blob befoe examining buffer contents */ |
||
482 | if (fw->size < minsize || fw->size > maxsize) |
||
483 | goto fail; |
||
484 | |||
485 | /* |
||
486 | * The GuC firmware image has the version number embedded at a well-known |
||
487 | * offset within the firmware blob; note that major / minor version are |
||
488 | * TWO bytes each (i.e. u16), although all pointers and offsets are defined |
||
489 | * in terms of bytes (u8). |
||
490 | */ |
||
491 | css_header = fw->data + UOS_CSS_HEADER_OFFSET; |
||
492 | guc_fw->guc_fw_major_found = *(u16 *)(css_header + UOS_VER_MAJOR_OFFSET); |
||
493 | guc_fw->guc_fw_minor_found = *(u16 *)(css_header + UOS_VER_MINOR_OFFSET); |
||
494 | |||
495 | if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted || |
||
496 | guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) { |
||
497 | DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n", |
||
498 | guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found, |
||
499 | guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); |
||
500 | err = -ENOEXEC; |
||
501 | goto fail; |
||
502 | } |
||
503 | |||
504 | DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n", |
||
505 | guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found, |
||
506 | guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); |
||
507 | |||
508 | mutex_lock(&dev->struct_mutex); |
||
509 | obj = i915_gem_object_create_from_data(dev, fw->data, fw->size); |
||
510 | mutex_unlock(&dev->struct_mutex); |
||
511 | if (IS_ERR_OR_NULL(obj)) { |
||
512 | err = obj ? PTR_ERR(obj) : -ENOMEM; |
||
513 | goto fail; |
||
514 | } |
||
515 | |||
516 | guc_fw->guc_fw_obj = obj; |
||
517 | guc_fw->guc_fw_size = fw->size; |
||
518 | |||
519 | DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n", |
||
520 | guc_fw->guc_fw_obj); |
||
521 | |||
522 | release_firmware(fw); |
||
523 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS; |
||
524 | return; |
||
525 | |||
526 | fail: |
||
527 | DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n", |
||
528 | err, fw, guc_fw->guc_fw_obj); |
||
529 | DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n", |
||
530 | guc_fw->guc_fw_path, err); |
||
531 | |||
532 | obj = guc_fw->guc_fw_obj; |
||
533 | if (obj) |
||
534 | drm_gem_object_unreference(&obj->base); |
||
535 | guc_fw->guc_fw_obj = NULL; |
||
536 | |||
537 | release_firmware(fw); /* OK even if fw is NULL */ |
||
538 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL; |
||
539 | } |
||
540 | |||
541 | /** |
||
542 | * intel_guc_ucode_init() - define parameters and fetch firmware |
||
543 | * @dev: drm device |
||
544 | * |
||
545 | * Called early during driver load, but after GEM is initialised. |
||
546 | * |
||
547 | * The firmware will be transferred to the GuC's memory later, |
||
548 | * when intel_guc_ucode_load() is called. |
||
549 | */ |
||
550 | void intel_guc_ucode_init(struct drm_device *dev) |
||
551 | { |
||
552 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
553 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
||
554 | const char *fw_path; |
||
555 | |||
556 | if (!HAS_GUC_SCHED(dev)) |
||
557 | i915.enable_guc_submission = false; |
||
558 | |||
559 | if (!HAS_GUC_UCODE(dev)) { |
||
560 | fw_path = NULL; |
||
561 | } else if (IS_SKYLAKE(dev)) { |
||
562 | fw_path = I915_SKL_GUC_UCODE; |
||
563 | guc_fw->guc_fw_major_wanted = 4; |
||
564 | guc_fw->guc_fw_minor_wanted = 3; |
||
565 | } else { |
||
566 | i915.enable_guc_submission = false; |
||
567 | fw_path = ""; /* unknown device */ |
||
568 | } |
||
569 | |||
570 | guc_fw->guc_dev = dev; |
||
571 | guc_fw->guc_fw_path = fw_path; |
||
572 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE; |
||
573 | guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE; |
||
574 | |||
575 | if (fw_path == NULL) |
||
576 | return; |
||
577 | |||
578 | if (*fw_path == '\0') { |
||
579 | DRM_ERROR("No GuC firmware known for this platform\n"); |
||
580 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL; |
||
581 | return; |
||
582 | } |
||
583 | |||
584 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING; |
||
585 | DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path); |
||
586 | guc_fw_fetch(dev, guc_fw); |
||
587 | /* status must now be FAIL or SUCCESS */ |
||
588 | } |
||
589 | |||
590 | /** |
||
591 | * intel_guc_ucode_fini() - clean up all allocated resources |
||
592 | * @dev: drm device |
||
593 | */ |
||
594 | void intel_guc_ucode_fini(struct drm_device *dev) |
||
595 | { |
||
596 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
597 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
||
598 | |||
599 | direct_interrupts_to_host(dev_priv); |
||
600 | i915_guc_submission_fini(dev); |
||
601 | |||
602 | mutex_lock(&dev->struct_mutex); |
||
603 | if (guc_fw->guc_fw_obj) |
||
604 | drm_gem_object_unreference(&guc_fw->guc_fw_obj->base); |
||
605 | guc_fw->guc_fw_obj = NULL; |
||
606 | mutex_unlock(&dev->struct_mutex); |
||
607 | |||
608 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE; |
||
609 | }>>=>>>><>><>><>><>><>><>><> |