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5354 | serge | 1 | /* |
2 | * Copyright © 2014 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Daniel Vetter |
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25 | * |
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26 | */ |
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27 | |||
28 | #include "i915_drv.h" |
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29 | #include "intel_drv.h" |
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30 | |||
31 | /** |
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32 | * DOC: fifo underrun handling |
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33 | * |
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34 | * The i915 driver checks for display fifo underruns using the interrupt signals |
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35 | * provided by the hardware. This is enabled by default and fairly useful to |
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36 | * debug display issues, especially watermark settings. |
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37 | * |
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38 | * If an underrun is detected this is logged into dmesg. To avoid flooding logs |
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39 | * and occupying the cpu underrun interrupts are disabled after the first |
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40 | * occurrence until the next modeset on a given pipe. |
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41 | * |
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42 | * Note that underrun detection on gmch platforms is a bit more ugly since there |
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43 | * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe |
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44 | * interrupt register). Also on some other platforms underrun interrupts are |
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45 | * shared, which means that if we detect an underrun we need to disable underrun |
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46 | * reporting on all pipes. |
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47 | * |
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48 | * The code also supports underrun detection on the PCH transcoder. |
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49 | */ |
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50 | |||
51 | static bool ivb_can_enable_err_int(struct drm_device *dev) |
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52 | { |
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53 | struct drm_i915_private *dev_priv = dev->dev_private; |
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54 | struct intel_crtc *crtc; |
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55 | enum pipe pipe; |
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56 | |||
57 | assert_spin_locked(&dev_priv->irq_lock); |
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58 | |||
59 | for_each_pipe(dev_priv, pipe) { |
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60 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
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61 | |||
62 | if (crtc->cpu_fifo_underrun_disabled) |
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63 | return false; |
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64 | } |
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65 | |||
66 | return true; |
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67 | } |
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68 | |||
69 | static bool cpt_can_enable_serr_int(struct drm_device *dev) |
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70 | { |
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71 | struct drm_i915_private *dev_priv = dev->dev_private; |
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72 | enum pipe pipe; |
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73 | struct intel_crtc *crtc; |
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74 | |||
75 | assert_spin_locked(&dev_priv->irq_lock); |
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76 | |||
77 | for_each_pipe(dev_priv, pipe) { |
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78 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
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79 | |||
80 | if (crtc->pch_fifo_underrun_disabled) |
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81 | return false; |
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82 | } |
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83 | |||
84 | return true; |
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85 | } |
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86 | |||
87 | /** |
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88 | * i9xx_check_fifo_underruns - check for fifo underruns |
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89 | * @dev_priv: i915 device instance |
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90 | * |
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91 | * This function checks for fifo underruns on GMCH platforms. This needs to be |
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92 | * done manually on modeset to make sure that we catch all underruns since they |
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93 | * do not generate an interrupt by themselves on these platforms. |
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94 | */ |
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95 | void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv) |
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96 | { |
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97 | struct intel_crtc *crtc; |
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98 | |||
99 | spin_lock_irq(&dev_priv->irq_lock); |
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100 | |||
101 | for_each_intel_crtc(dev_priv->dev, crtc) { |
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102 | u32 reg = PIPESTAT(crtc->pipe); |
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103 | u32 pipestat; |
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104 | |||
105 | if (crtc->cpu_fifo_underrun_disabled) |
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106 | continue; |
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107 | |||
108 | pipestat = I915_READ(reg) & 0xffff0000; |
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109 | if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0) |
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110 | continue; |
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111 | |||
112 | I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); |
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113 | POSTING_READ(reg); |
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114 | |||
115 | DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe)); |
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116 | } |
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117 | |||
118 | spin_unlock_irq(&dev_priv->irq_lock); |
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119 | } |
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120 | |||
121 | static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev, |
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122 | enum pipe pipe, |
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123 | bool enable, bool old) |
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124 | { |
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125 | struct drm_i915_private *dev_priv = dev->dev_private; |
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126 | u32 reg = PIPESTAT(pipe); |
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127 | u32 pipestat = I915_READ(reg) & 0xffff0000; |
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128 | |||
129 | assert_spin_locked(&dev_priv->irq_lock); |
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130 | |||
131 | if (enable) { |
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132 | I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); |
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133 | POSTING_READ(reg); |
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134 | } else { |
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135 | if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS) |
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136 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
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137 | } |
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138 | } |
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139 | |||
140 | static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, |
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141 | enum pipe pipe, bool enable) |
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142 | { |
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143 | struct drm_i915_private *dev_priv = dev->dev_private; |
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144 | uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : |
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145 | DE_PIPEB_FIFO_UNDERRUN; |
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146 | |||
147 | if (enable) |
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148 | ironlake_enable_display_irq(dev_priv, bit); |
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149 | else |
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150 | ironlake_disable_display_irq(dev_priv, bit); |
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151 | } |
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152 | |||
153 | static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, |
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154 | enum pipe pipe, |
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155 | bool enable, bool old) |
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156 | { |
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157 | struct drm_i915_private *dev_priv = dev->dev_private; |
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158 | if (enable) { |
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159 | I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); |
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160 | |||
161 | if (!ivb_can_enable_err_int(dev)) |
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162 | return; |
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163 | |||
164 | ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); |
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165 | } else { |
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166 | ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); |
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167 | |||
168 | if (old && |
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169 | I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { |
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170 | DRM_ERROR("uncleared fifo underrun on pipe %c\n", |
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171 | pipe_name(pipe)); |
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172 | } |
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173 | } |
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174 | } |
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175 | |||
176 | static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev, |
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177 | enum pipe pipe, bool enable) |
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178 | { |
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179 | struct drm_i915_private *dev_priv = dev->dev_private; |
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180 | |||
181 | assert_spin_locked(&dev_priv->irq_lock); |
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182 | |||
183 | if (enable) |
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184 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN; |
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185 | else |
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186 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN; |
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187 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); |
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188 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); |
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189 | } |
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190 | |||
191 | static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, |
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192 | enum transcoder pch_transcoder, |
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193 | bool enable) |
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194 | { |
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195 | struct drm_i915_private *dev_priv = dev->dev_private; |
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196 | uint32_t bit = (pch_transcoder == TRANSCODER_A) ? |
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197 | SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; |
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198 | |||
199 | if (enable) |
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200 | ibx_enable_display_interrupt(dev_priv, bit); |
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201 | else |
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202 | ibx_disable_display_interrupt(dev_priv, bit); |
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203 | } |
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204 | |||
205 | static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, |
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206 | enum transcoder pch_transcoder, |
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207 | bool enable, bool old) |
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208 | { |
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209 | struct drm_i915_private *dev_priv = dev->dev_private; |
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210 | |||
211 | if (enable) { |
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212 | I915_WRITE(SERR_INT, |
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213 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); |
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214 | |||
215 | if (!cpt_can_enable_serr_int(dev)) |
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216 | return; |
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217 | |||
218 | ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
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219 | } else { |
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220 | ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
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221 | |||
222 | if (old && I915_READ(SERR_INT) & |
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223 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) { |
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224 | DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n", |
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225 | transcoder_name(pch_transcoder)); |
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226 | } |
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227 | } |
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228 | } |
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229 | |||
230 | static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
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231 | enum pipe pipe, bool enable) |
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232 | { |
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233 | struct drm_i915_private *dev_priv = dev->dev_private; |
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234 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
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235 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
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236 | bool old; |
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237 | |||
238 | assert_spin_locked(&dev_priv->irq_lock); |
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239 | |||
240 | old = !intel_crtc->cpu_fifo_underrun_disabled; |
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241 | intel_crtc->cpu_fifo_underrun_disabled = !enable; |
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242 | |||
243 | if (HAS_GMCH_DISPLAY(dev)) |
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244 | i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); |
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245 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
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246 | ironlake_set_fifo_underrun_reporting(dev, pipe, enable); |
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247 | else if (IS_GEN7(dev)) |
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248 | ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); |
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249 | else if (IS_GEN8(dev) || IS_GEN9(dev)) |
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250 | broadwell_set_fifo_underrun_reporting(dev, pipe, enable); |
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251 | |||
252 | return old; |
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253 | } |
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254 | |||
255 | /** |
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256 | * intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrrun reporting state |
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257 | * @dev_priv: i915 device instance |
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258 | * @pipe: (CPU) pipe to set state for |
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259 | * @enable: whether underruns should be reported or not |
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260 | * |
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261 | * This function sets the fifo underrun state for @pipe. It is used in the |
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262 | * modeset code to avoid false positives since on many platforms underruns are |
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263 | * expected when disabling or enabling the pipe. |
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264 | * |
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265 | * Notice that on some platforms disabling underrun reports for one pipe |
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266 | * disables for all due to shared interrupts. Actual reporting is still per-pipe |
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267 | * though. |
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268 | * |
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