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6084 | serge | 1 | /* |
2 | * Copyright © 2014 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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21 | * DEALINGS IN THE SOFTWARE. |
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22 | */ |
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23 | |||
24 | /** |
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25 | * DOC: Frame Buffer Compression (FBC) |
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26 | * |
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27 | * FBC tries to save memory bandwidth (and so power consumption) by |
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28 | * compressing the amount of memory used by the display. It is total |
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29 | * transparent to user space and completely handled in the kernel. |
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30 | * |
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31 | * The benefits of FBC are mostly visible with solid backgrounds and |
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32 | * variation-less patterns. It comes from keeping the memory footprint small |
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33 | * and having fewer memory pages opened and accessed for refreshing the display. |
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34 | * |
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35 | * i915 is responsible to reserve stolen memory for FBC and configure its |
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36 | * offset on proper registers. The hardware takes care of all |
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37 | * compress/decompress. However there are many known cases where we have to |
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38 | * forcibly disable it to allow proper screen updates. |
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39 | */ |
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40 | |||
41 | #include "intel_drv.h" |
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42 | #include "i915_drv.h" |
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43 | |||
44 | static inline bool fbc_supported(struct drm_i915_private *dev_priv) |
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45 | { |
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46 | return dev_priv->fbc.enable_fbc != NULL; |
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47 | } |
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48 | |||
49 | /* |
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50 | * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the |
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51 | * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's |
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52 | * origin so the x and y offsets can actually fit the registers. As a |
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53 | * consequence, the fence doesn't really start exactly at the display plane |
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54 | * address we program because it starts at the real start of the buffer, so we |
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55 | * have to take this into consideration here. |
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56 | */ |
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57 | static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc) |
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58 | { |
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59 | return crtc->base.y - crtc->adjusted_y; |
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60 | } |
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61 | |||
62 | static void i8xx_fbc_disable(struct drm_i915_private *dev_priv) |
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63 | { |
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64 | u32 fbc_ctl; |
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65 | |||
66 | dev_priv->fbc.enabled = false; |
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67 | |||
68 | /* Disable compression */ |
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69 | fbc_ctl = I915_READ(FBC_CONTROL); |
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70 | if ((fbc_ctl & FBC_CTL_EN) == 0) |
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71 | return; |
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72 | |||
73 | fbc_ctl &= ~FBC_CTL_EN; |
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74 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
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75 | |||
76 | /* Wait for compressing bit to clear */ |
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77 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { |
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78 | DRM_DEBUG_KMS("FBC idle timed out\n"); |
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79 | return; |
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80 | } |
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81 | |||
82 | DRM_DEBUG_KMS("disabled FBC\n"); |
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83 | } |
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84 | |||
85 | static void i8xx_fbc_enable(struct intel_crtc *crtc) |
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86 | { |
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87 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
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88 | struct drm_framebuffer *fb = crtc->base.primary->fb; |
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89 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
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90 | int cfb_pitch; |
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91 | int i; |
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92 | u32 fbc_ctl; |
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93 | |||
94 | dev_priv->fbc.enabled = true; |
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95 | |||
96 | /* Note: fbc.threshold == 1 for i8xx */ |
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97 | cfb_pitch = dev_priv->fbc.uncompressed_size / FBC_LL_SIZE; |
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98 | if (fb->pitches[0] < cfb_pitch) |
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99 | cfb_pitch = fb->pitches[0]; |
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100 | |||
101 | /* FBC_CTL wants 32B or 64B units */ |
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102 | if (IS_GEN2(dev_priv)) |
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103 | cfb_pitch = (cfb_pitch / 32) - 1; |
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104 | else |
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105 | cfb_pitch = (cfb_pitch / 64) - 1; |
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106 | |||
107 | /* Clear old tags */ |
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108 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) |
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109 | I915_WRITE(FBC_TAG(i), 0); |
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110 | |||
111 | if (IS_GEN4(dev_priv)) { |
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112 | u32 fbc_ctl2; |
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113 | |||
114 | /* Set it up... */ |
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115 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; |
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116 | fbc_ctl2 |= FBC_CTL_PLANE(crtc->plane); |
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117 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
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118 | I915_WRITE(FBC_FENCE_OFF, get_crtc_fence_y_offset(crtc)); |
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119 | } |
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120 | |||
121 | /* enable it... */ |
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122 | fbc_ctl = I915_READ(FBC_CONTROL); |
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123 | fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; |
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124 | fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; |
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125 | if (IS_I945GM(dev_priv)) |
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126 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
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127 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
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128 | fbc_ctl |= obj->fence_reg; |
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129 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
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130 | |||
131 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n", |
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132 | cfb_pitch, crtc->base.y, plane_name(crtc->plane)); |
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133 | } |
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134 | |||
135 | static bool i8xx_fbc_enabled(struct drm_i915_private *dev_priv) |
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136 | { |
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137 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
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138 | } |
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139 | |||
140 | static void g4x_fbc_enable(struct intel_crtc *crtc) |
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141 | { |
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142 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
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143 | struct drm_framebuffer *fb = crtc->base.primary->fb; |
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144 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
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145 | u32 dpfc_ctl; |
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146 | |||
147 | dev_priv->fbc.enabled = true; |
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148 | |||
149 | dpfc_ctl = DPFC_CTL_PLANE(crtc->plane) | DPFC_SR_EN; |
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150 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
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151 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; |
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152 | else |
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153 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; |
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154 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; |
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155 | |||
156 | I915_WRITE(DPFC_FENCE_YOFF, get_crtc_fence_y_offset(crtc)); |
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157 | |||
158 | /* enable it... */ |
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159 | I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
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160 | |||
161 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); |
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162 | } |
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163 | |||
164 | static void g4x_fbc_disable(struct drm_i915_private *dev_priv) |
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165 | { |
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166 | u32 dpfc_ctl; |
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167 | |||
168 | dev_priv->fbc.enabled = false; |
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169 | |||
170 | /* Disable compression */ |
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171 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
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172 | if (dpfc_ctl & DPFC_CTL_EN) { |
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173 | dpfc_ctl &= ~DPFC_CTL_EN; |
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174 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); |
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175 | |||
176 | DRM_DEBUG_KMS("disabled FBC\n"); |
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177 | } |
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178 | } |
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179 | |||
180 | static bool g4x_fbc_enabled(struct drm_i915_private *dev_priv) |
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181 | { |
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182 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
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183 | } |
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184 | |||
185 | static void intel_fbc_nuke(struct drm_i915_private *dev_priv) |
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186 | { |
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187 | I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); |
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188 | POSTING_READ(MSG_FBC_REND_STATE); |
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189 | } |
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190 | |||
191 | static void ilk_fbc_enable(struct intel_crtc *crtc) |
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192 | { |
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193 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
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194 | struct drm_framebuffer *fb = crtc->base.primary->fb; |
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195 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
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196 | u32 dpfc_ctl; |
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197 | int threshold = dev_priv->fbc.threshold; |
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198 | unsigned int y_offset; |
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199 | |||
200 | dev_priv->fbc.enabled = true; |
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201 | |||
202 | dpfc_ctl = DPFC_CTL_PLANE(crtc->plane); |
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203 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
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204 | threshold++; |
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205 | |||
206 | switch (threshold) { |
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207 | case 4: |
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208 | case 3: |
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209 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; |
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210 | break; |
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211 | case 2: |
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212 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; |
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213 | break; |
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214 | case 1: |
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215 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; |
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216 | break; |
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217 | } |
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218 | dpfc_ctl |= DPFC_CTL_FENCE_EN; |
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219 | if (IS_GEN5(dev_priv)) |
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220 | dpfc_ctl |= obj->fence_reg; |
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221 | |||
222 | y_offset = get_crtc_fence_y_offset(crtc); |
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223 | I915_WRITE(ILK_DPFC_FENCE_YOFF, y_offset); |
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224 | I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); |
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225 | /* enable it... */ |
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226 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
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227 | |||
228 | if (IS_GEN6(dev_priv)) { |
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229 | I915_WRITE(SNB_DPFC_CTL_SA, |
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230 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
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231 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, y_offset); |
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232 | } |
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233 | |||
234 | intel_fbc_nuke(dev_priv); |
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235 | |||
236 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); |
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237 | } |
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238 | |||
239 | static void ilk_fbc_disable(struct drm_i915_private *dev_priv) |
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240 | { |
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241 | u32 dpfc_ctl; |
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242 | |||
243 | dev_priv->fbc.enabled = false; |
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244 | |||
245 | /* Disable compression */ |
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246 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
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247 | if (dpfc_ctl & DPFC_CTL_EN) { |
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248 | dpfc_ctl &= ~DPFC_CTL_EN; |
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249 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); |
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250 | |||
251 | DRM_DEBUG_KMS("disabled FBC\n"); |
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252 | } |
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253 | } |
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254 | |||
255 | static bool ilk_fbc_enabled(struct drm_i915_private *dev_priv) |
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256 | { |
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257 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
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258 | } |
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259 | |||
260 | static void gen7_fbc_enable(struct intel_crtc *crtc) |
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261 | { |
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262 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
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263 | struct drm_framebuffer *fb = crtc->base.primary->fb; |
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264 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
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265 | u32 dpfc_ctl; |
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266 | int threshold = dev_priv->fbc.threshold; |
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267 | |||
268 | dev_priv->fbc.enabled = true; |
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269 | |||
270 | dpfc_ctl = 0; |
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271 | if (IS_IVYBRIDGE(dev_priv)) |
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272 | dpfc_ctl |= IVB_DPFC_CTL_PLANE(crtc->plane); |
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273 | |||
274 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
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275 | threshold++; |
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276 | |||
277 | switch (threshold) { |
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278 | case 4: |
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279 | case 3: |
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280 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; |
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281 | break; |
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282 | case 2: |
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283 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; |
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284 | break; |
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285 | case 1: |
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286 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; |
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287 | break; |
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288 | } |
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289 | |||
290 | dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; |
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291 | |||
292 | if (dev_priv->fbc.false_color) |
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293 | dpfc_ctl |= FBC_CTL_FALSE_COLOR; |
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294 | |||
295 | if (IS_IVYBRIDGE(dev_priv)) { |
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296 | /* WaFbcAsynchFlipDisableFbcQueue:ivb */ |
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297 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
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298 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
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299 | ILK_FBCQ_DIS); |
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300 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
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301 | /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ |
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302 | I915_WRITE(CHICKEN_PIPESL_1(crtc->pipe), |
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303 | I915_READ(CHICKEN_PIPESL_1(crtc->pipe)) | |
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304 | HSW_FBCQ_DIS); |
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305 | } |
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306 | |||
307 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
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308 | |||
309 | I915_WRITE(SNB_DPFC_CTL_SA, |
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310 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
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311 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, get_crtc_fence_y_offset(crtc)); |
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312 | |||
313 | intel_fbc_nuke(dev_priv); |
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314 | |||
315 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); |
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316 | } |
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317 | |||
318 | /** |
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319 | * intel_fbc_enabled - Is FBC enabled? |
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320 | * @dev_priv: i915 device instance |
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321 | * |
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322 | * This function is used to verify the current state of FBC. |
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323 | * FIXME: This should be tracked in the plane config eventually |
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324 | * instead of queried at runtime for most callers. |
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325 | */ |
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326 | bool intel_fbc_enabled(struct drm_i915_private *dev_priv) |
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327 | { |
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328 | return dev_priv->fbc.enabled; |
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329 | } |
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330 | |||
331 | static void intel_fbc_enable(struct intel_crtc *crtc, |
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332 | const struct drm_framebuffer *fb) |
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333 | { |
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334 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
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335 | |||
336 | dev_priv->fbc.enable_fbc(crtc); |
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337 | |||
338 | dev_priv->fbc.crtc = crtc; |
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339 | dev_priv->fbc.fb_id = fb->base.id; |
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340 | dev_priv->fbc.y = crtc->base.y; |
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341 | } |
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342 | |||
343 | static void intel_fbc_work_fn(struct work_struct *__work) |
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344 | { |
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345 | struct intel_fbc_work *work = |
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346 | container_of(to_delayed_work(__work), |
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347 | struct intel_fbc_work, work); |
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348 | struct drm_i915_private *dev_priv = work->crtc->base.dev->dev_private; |
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349 | struct drm_framebuffer *crtc_fb = work->crtc->base.primary->fb; |
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350 | |||
351 | mutex_lock(&dev_priv->fbc.lock); |
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352 | if (work == dev_priv->fbc.fbc_work) { |
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353 | /* Double check that we haven't switched fb without cancelling |
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354 | * the prior work. |
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355 | */ |
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356 | if (crtc_fb == work->fb) |
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357 | intel_fbc_enable(work->crtc, work->fb); |
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358 | |||
359 | dev_priv->fbc.fbc_work = NULL; |
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360 | } |
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361 | mutex_unlock(&dev_priv->fbc.lock); |
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362 | |||
363 | kfree(work); |
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364 | } |
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365 | |||
366 | static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv) |
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367 | { |
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368 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
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369 | |||
370 | if (dev_priv->fbc.fbc_work == NULL) |
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371 | return; |
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372 | |||
373 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); |
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374 | |||
375 | /* Synchronisation is provided by struct_mutex and checking of |
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376 | * dev_priv->fbc.fbc_work, so we can perform the cancellation |
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377 | * entirely asynchronously. |
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378 | */ |
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379 | if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work)) |
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380 | /* tasklet was killed before being run, clean up */ |
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381 | kfree(dev_priv->fbc.fbc_work); |
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382 | |||
383 | /* Mark the work as no longer wanted so that if it does |
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384 | * wake-up (because the work was already running and waiting |
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385 | * for our mutex), it will discover that is no longer |
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386 | * necessary to run. |
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387 | */ |
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388 | dev_priv->fbc.fbc_work = NULL; |
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389 | } |
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390 | |||
391 | static void intel_fbc_schedule_enable(struct intel_crtc *crtc) |
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392 | { |
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393 | struct intel_fbc_work *work; |
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394 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
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395 | |||
396 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
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397 | |||
398 | intel_fbc_cancel_work(dev_priv); |
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399 | |||
400 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
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401 | if (work == NULL) { |
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402 | DRM_ERROR("Failed to allocate FBC work structure\n"); |
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403 | intel_fbc_enable(crtc, crtc->base.primary->fb); |
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404 | return; |
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405 | } |
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406 | |||
407 | work->crtc = crtc; |
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408 | work->fb = crtc->base.primary->fb; |
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409 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); |
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410 | |||
411 | dev_priv->fbc.fbc_work = work; |
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412 | |||
413 | /* Delay the actual enabling to let pageflipping cease and the |
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414 | * display to settle before starting the compression. Note that |
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415 | * this delay also serves a second purpose: it allows for a |
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416 | * vblank to pass after disabling the FBC before we attempt |
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417 | * to modify the control registers. |
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418 | * |
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419 | * A more complicated solution would involve tracking vblanks |
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420 | * following the termination of the page-flipping sequence |
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421 | * and indeed performing the enable as a co-routine and not |
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422 | * waiting synchronously upon the vblank. |
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423 | * |
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424 | * WaFbcWaitForVBlankBeforeEnable:ilk,snb |
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425 | */ |
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426 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); |
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427 | } |
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428 | |||
429 | static void __intel_fbc_disable(struct drm_i915_private *dev_priv) |
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430 | { |
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431 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
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432 | |||
433 | intel_fbc_cancel_work(dev_priv); |
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434 | |||
435 | dev_priv->fbc.disable_fbc(dev_priv); |
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436 | dev_priv->fbc.crtc = NULL; |
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437 | } |
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438 | |||
439 | /** |
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440 | * intel_fbc_disable - disable FBC |
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441 | * @dev_priv: i915 device instance |
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442 | * |
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443 | * This function disables FBC. |
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444 | */ |
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445 | void intel_fbc_disable(struct drm_i915_private *dev_priv) |
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446 | { |
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447 | if (!fbc_supported(dev_priv)) |
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448 | return; |
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449 | |||
450 | mutex_lock(&dev_priv->fbc.lock); |
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451 | __intel_fbc_disable(dev_priv); |
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452 | mutex_unlock(&dev_priv->fbc.lock); |
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453 | } |
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454 | |||
455 | /* |
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456 | * intel_fbc_disable_crtc - disable FBC if it's associated with crtc |
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457 | * @crtc: the CRTC |
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458 | * |
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459 | * This function disables FBC if it's associated with the provided CRTC. |
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460 | */ |
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461 | void intel_fbc_disable_crtc(struct intel_crtc *crtc) |
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462 | { |
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463 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
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464 | |||
465 | if (!fbc_supported(dev_priv)) |
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466 | return; |
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467 | |||
468 | mutex_lock(&dev_priv->fbc.lock); |
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469 | if (dev_priv->fbc.crtc == crtc) |
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470 | __intel_fbc_disable(dev_priv); |
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471 | mutex_unlock(&dev_priv->fbc.lock); |
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472 | } |
||
473 | |||
474 | const char *intel_no_fbc_reason_str(enum no_fbc_reason reason) |
||
475 | { |
||
476 | switch (reason) { |
||
477 | case FBC_OK: |
||
478 | return "FBC enabled but currently disabled in hardware"; |
||
479 | case FBC_UNSUPPORTED: |
||
480 | return "unsupported by this chipset"; |
||
481 | case FBC_NO_OUTPUT: |
||
482 | return "no output"; |
||
483 | case FBC_STOLEN_TOO_SMALL: |
||
484 | return "not enough stolen memory"; |
||
485 | case FBC_UNSUPPORTED_MODE: |
||
486 | return "mode incompatible with compression"; |
||
487 | case FBC_MODE_TOO_LARGE: |
||
488 | return "mode too large for compression"; |
||
489 | case FBC_BAD_PLANE: |
||
490 | return "FBC unsupported on plane"; |
||
491 | case FBC_NOT_TILED: |
||
492 | return "framebuffer not tiled or fenced"; |
||
493 | case FBC_MULTIPLE_PIPES: |
||
494 | return "more than one pipe active"; |
||
495 | case FBC_MODULE_PARAM: |
||
496 | return "disabled per module param"; |
||
497 | case FBC_CHIP_DEFAULT: |
||
498 | return "disabled per chip default"; |
||
499 | case FBC_ROTATION: |
||
500 | return "rotation unsupported"; |
||
501 | case FBC_IN_DBG_MASTER: |
||
502 | return "Kernel debugger is active"; |
||
503 | case FBC_BAD_STRIDE: |
||
504 | return "framebuffer stride not supported"; |
||
505 | case FBC_PIXEL_RATE: |
||
506 | return "pixel rate is too big"; |
||
507 | case FBC_PIXEL_FORMAT: |
||
508 | return "pixel format is invalid"; |
||
509 | default: |
||
510 | MISSING_CASE(reason); |
||
511 | return "unknown reason"; |
||
512 | } |
||
513 | } |
||
514 | |||
515 | static void set_no_fbc_reason(struct drm_i915_private *dev_priv, |
||
516 | enum no_fbc_reason reason) |
||
517 | { |
||
518 | if (dev_priv->fbc.no_fbc_reason == reason) |
||
519 | return; |
||
520 | |||
521 | dev_priv->fbc.no_fbc_reason = reason; |
||
522 | DRM_DEBUG_KMS("Disabling FBC: %s\n", intel_no_fbc_reason_str(reason)); |
||
523 | } |
||
524 | |||
525 | static struct drm_crtc *intel_fbc_find_crtc(struct drm_i915_private *dev_priv) |
||
526 | { |
||
527 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
||
528 | enum pipe pipe; |
||
529 | bool pipe_a_only = false; |
||
530 | |||
531 | if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) |
||
532 | pipe_a_only = true; |
||
533 | |||
534 | for_each_pipe(dev_priv, pipe) { |
||
535 | tmp_crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
||
536 | |||
537 | if (intel_crtc_active(tmp_crtc) && |
||
538 | to_intel_plane_state(tmp_crtc->primary->state)->visible) |
||
539 | crtc = tmp_crtc; |
||
540 | |||
541 | if (pipe_a_only) |
||
542 | break; |
||
543 | } |
||
544 | |||
545 | if (!crtc || crtc->primary->fb == NULL) |
||
546 | return NULL; |
||
547 | |||
548 | return crtc; |
||
549 | } |
||
550 | |||
551 | static bool multiple_pipes_ok(struct drm_i915_private *dev_priv) |
||
552 | { |
||
553 | enum pipe pipe; |
||
554 | int n_pipes = 0; |
||
555 | struct drm_crtc *crtc; |
||
556 | |||
557 | if (INTEL_INFO(dev_priv)->gen > 4) |
||
558 | return true; |
||
559 | |||
560 | for_each_pipe(dev_priv, pipe) { |
||
561 | crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
||
562 | |||
563 | if (intel_crtc_active(crtc) && |
||
564 | to_intel_plane_state(crtc->primary->state)->visible) |
||
565 | n_pipes++; |
||
566 | } |
||
567 | |||
568 | return (n_pipes < 2); |
||
569 | } |
||
570 | |||
571 | static int find_compression_threshold(struct drm_i915_private *dev_priv, |
||
572 | struct drm_mm_node *node, |
||
573 | int size, |
||
574 | int fb_cpp) |
||
575 | { |
||
576 | int compression_threshold = 1; |
||
577 | int ret; |
||
578 | u64 end; |
||
579 | |||
580 | /* The FBC hardware for BDW/SKL doesn't have access to the stolen |
||
581 | * reserved range size, so it always assumes the maximum (8mb) is used. |
||
582 | * If we enable FBC using a CFB on that memory range we'll get FIFO |
||
583 | * underruns, even if that range is not reserved by the BIOS. */ |
||
584 | if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) |
||
585 | end = dev_priv->gtt.stolen_size - 8 * 1024 * 1024; |
||
586 | else |
||
587 | end = dev_priv->gtt.stolen_usable_size; |
||
588 | |||
589 | /* HACK: This code depends on what we will do in *_enable_fbc. If that |
||
590 | * code changes, this code needs to change as well. |
||
591 | * |
||
592 | * The enable_fbc code will attempt to use one of our 2 compression |
||
593 | * thresholds, therefore, in that case, we only have 1 resort. |
||
594 | */ |
||
595 | |||
596 | /* Try to over-allocate to reduce reallocations and fragmentation. */ |
||
597 | ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1, |
||
598 | 4096, 0, end); |
||
599 | if (ret == 0) |
||
600 | return compression_threshold; |
||
601 | |||
602 | again: |
||
603 | /* HW's ability to limit the CFB is 1:4 */ |
||
604 | if (compression_threshold > 4 || |
||
605 | (fb_cpp == 2 && compression_threshold == 2)) |
||
606 | return 0; |
||
607 | |||
608 | ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1, |
||
609 | 4096, 0, end); |
||
610 | if (ret && INTEL_INFO(dev_priv)->gen <= 4) { |
||
611 | return 0; |
||
612 | } else if (ret) { |
||
613 | compression_threshold <<= 1; |
||
614 | goto again; |
||
615 | } else { |
||
616 | return compression_threshold; |
||
617 | } |
||
618 | } |
||
619 | |||
620 | static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv, int size, |
||
621 | int fb_cpp) |
||
622 | { |
||
623 | struct drm_mm_node *uninitialized_var(compressed_llb); |
||
624 | int ret; |
||
625 | |||
626 | ret = find_compression_threshold(dev_priv, &dev_priv->fbc.compressed_fb, |
||
627 | size, fb_cpp); |
||
628 | if (!ret) |
||
629 | goto err_llb; |
||
630 | else if (ret > 1) { |
||
631 | DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n"); |
||
632 | |||
633 | } |
||
634 | |||
635 | dev_priv->fbc.threshold = ret; |
||
636 | |||
637 | if (INTEL_INFO(dev_priv)->gen >= 5) |
||
638 | I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); |
||
639 | else if (IS_GM45(dev_priv)) { |
||
640 | I915_WRITE(DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); |
||
641 | } else { |
||
642 | compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL); |
||
643 | if (!compressed_llb) |
||
644 | goto err_fb; |
||
645 | |||
646 | ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb, |
||
647 | 4096, 4096); |
||
648 | if (ret) |
||
649 | goto err_fb; |
||
650 | |||
651 | dev_priv->fbc.compressed_llb = compressed_llb; |
||
652 | |||
653 | I915_WRITE(FBC_CFB_BASE, |
||
654 | dev_priv->mm.stolen_base + dev_priv->fbc.compressed_fb.start); |
||
655 | I915_WRITE(FBC_LL_BASE, |
||
656 | dev_priv->mm.stolen_base + compressed_llb->start); |
||
657 | } |
||
658 | |||
659 | dev_priv->fbc.uncompressed_size = size; |
||
660 | |||
661 | DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n", |
||
662 | dev_priv->fbc.compressed_fb.size, |
||
663 | dev_priv->fbc.threshold); |
||
664 | |||
665 | return 0; |
||
666 | |||
667 | err_fb: |
||
668 | kfree(compressed_llb); |
||
669 | i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb); |
||
670 | err_llb: |
||
671 | pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); |
||
672 | return -ENOSPC; |
||
673 | } |
||
674 | |||
675 | static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
||
676 | { |
||
677 | if (dev_priv->fbc.uncompressed_size == 0) |
||
678 | return; |
||
679 | |||
680 | i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb); |
||
681 | |||
682 | if (dev_priv->fbc.compressed_llb) { |
||
683 | i915_gem_stolen_remove_node(dev_priv, |
||
684 | dev_priv->fbc.compressed_llb); |
||
685 | kfree(dev_priv->fbc.compressed_llb); |
||
686 | } |
||
687 | |||
688 | dev_priv->fbc.uncompressed_size = 0; |
||
689 | } |
||
690 | |||
691 | void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
||
692 | { |
||
693 | if (!fbc_supported(dev_priv)) |
||
694 | return; |
||
695 | |||
696 | mutex_lock(&dev_priv->fbc.lock); |
||
697 | __intel_fbc_cleanup_cfb(dev_priv); |
||
698 | mutex_unlock(&dev_priv->fbc.lock); |
||
699 | } |
||
700 | |||
701 | /* |
||
702 | * For SKL+, the plane source size used by the hardware is based on the value we |
||
703 | * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value |
||
704 | * we wrote to PIPESRC. |
||
705 | */ |
||
706 | static void intel_fbc_get_plane_source_size(struct intel_crtc *crtc, |
||
707 | int *width, int *height) |
||
708 | { |
||
709 | struct intel_plane_state *plane_state = |
||
710 | to_intel_plane_state(crtc->base.primary->state); |
||
711 | int w, h; |
||
712 | |||
713 | if (intel_rotation_90_or_270(plane_state->base.rotation)) { |
||
714 | w = drm_rect_height(&plane_state->src) >> 16; |
||
715 | h = drm_rect_width(&plane_state->src) >> 16; |
||
716 | } else { |
||
717 | w = drm_rect_width(&plane_state->src) >> 16; |
||
718 | h = drm_rect_height(&plane_state->src) >> 16; |
||
719 | } |
||
720 | |||
721 | if (width) |
||
722 | *width = w; |
||
723 | if (height) |
||
724 | *height = h; |
||
725 | } |
||
726 | |||
727 | static int intel_fbc_calculate_cfb_size(struct intel_crtc *crtc) |
||
728 | { |
||
729 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
||
730 | struct drm_framebuffer *fb = crtc->base.primary->fb; |
||
731 | int lines; |
||
732 | |||
733 | intel_fbc_get_plane_source_size(crtc, NULL, &lines); |
||
734 | if (INTEL_INFO(dev_priv)->gen >= 7) |
||
735 | lines = min(lines, 2048); |
||
736 | |||
737 | return lines * fb->pitches[0]; |
||
738 | } |
||
739 | |||
740 | static int intel_fbc_setup_cfb(struct intel_crtc *crtc) |
||
741 | { |
||
742 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
||
743 | struct drm_framebuffer *fb = crtc->base.primary->fb; |
||
744 | int size, cpp; |
||
745 | |||
746 | size = intel_fbc_calculate_cfb_size(crtc); |
||
747 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
||
748 | |||
749 | if (size <= dev_priv->fbc.uncompressed_size) |
||
750 | return 0; |
||
751 | |||
752 | /* Release any current block */ |
||
753 | __intel_fbc_cleanup_cfb(dev_priv); |
||
754 | |||
755 | return intel_fbc_alloc_cfb(dev_priv, size, cpp); |
||
756 | } |
||
757 | |||
758 | static bool stride_is_valid(struct drm_i915_private *dev_priv, |
||
759 | unsigned int stride) |
||
760 | { |
||
761 | /* These should have been caught earlier. */ |
||
762 | WARN_ON(stride < 512); |
||
763 | WARN_ON((stride & (64 - 1)) != 0); |
||
764 | |||
765 | /* Below are the additional FBC restrictions. */ |
||
766 | |||
767 | if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv)) |
||
768 | return stride == 4096 || stride == 8192; |
||
769 | |||
770 | if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048) |
||
771 | return false; |
||
772 | |||
773 | if (stride > 16384) |
||
774 | return false; |
||
775 | |||
776 | return true; |
||
777 | } |
||
778 | |||
779 | static bool pixel_format_is_valid(struct drm_framebuffer *fb) |
||
780 | { |
||
781 | struct drm_device *dev = fb->dev; |
||
782 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
783 | |||
784 | switch (fb->pixel_format) { |
||
785 | case DRM_FORMAT_XRGB8888: |
||
786 | case DRM_FORMAT_XBGR8888: |
||
787 | return true; |
||
788 | case DRM_FORMAT_XRGB1555: |
||
789 | case DRM_FORMAT_RGB565: |
||
790 | /* 16bpp not supported on gen2 */ |
||
791 | if (IS_GEN2(dev)) |
||
792 | return false; |
||
793 | /* WaFbcOnly1to1Ratio:ctg */ |
||
794 | if (IS_G4X(dev_priv)) |
||
795 | return false; |
||
796 | return true; |
||
797 | default: |
||
798 | return false; |
||
799 | } |
||
800 | } |
||
801 | |||
802 | /* |
||
803 | * For some reason, the hardware tracking starts looking at whatever we |
||
804 | * programmed as the display plane base address register. It does not look at |
||
805 | * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y} |
||
806 | * variables instead of just looking at the pipe/plane size. |
||
807 | */ |
||
808 | static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc) |
||
809 | { |
||
810 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
||
811 | unsigned int effective_w, effective_h, max_w, max_h; |
||
812 | |||
813 | if (INTEL_INFO(dev_priv)->gen >= 8 || IS_HASWELL(dev_priv)) { |
||
814 | max_w = 4096; |
||
815 | max_h = 4096; |
||
816 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { |
||
817 | max_w = 4096; |
||
818 | max_h = 2048; |
||
819 | } else { |
||
820 | max_w = 2048; |
||
821 | max_h = 1536; |
||
822 | } |
||
823 | |||
824 | intel_fbc_get_plane_source_size(crtc, &effective_w, &effective_h); |
||
825 | effective_w += crtc->adjusted_x; |
||
826 | effective_h += crtc->adjusted_y; |
||
827 | |||
828 | return effective_w <= max_w && effective_h <= max_h; |
||
829 | } |
||
830 | |||
831 | /** |
||
832 | * __intel_fbc_update - enable/disable FBC as needed, unlocked |
||
833 | * @dev_priv: i915 device instance |
||
834 | * |
||
835 | * Set up the framebuffer compression hardware at mode set time. We |
||
836 | * enable it if possible: |
||
837 | * - plane A only (on pre-965) |
||
838 | * - no pixel mulitply/line duplication |
||
839 | * - no alpha buffer discard |
||
840 | * - no dual wide |
||
841 | * - framebuffer <= max_hdisplay in width, max_vdisplay in height |
||
842 | * |
||
843 | * We can't assume that any compression will take place (worst case), |
||
844 | * so the compressed buffer has to be the same size as the uncompressed |
||
845 | * one. It also must reside (along with the line length buffer) in |
||
846 | * stolen memory. |
||
847 | * |
||
848 | * We need to enable/disable FBC on a global basis. |
||
849 | */ |
||
850 | static void __intel_fbc_update(struct drm_i915_private *dev_priv) |
||
851 | { |
||
852 | struct drm_crtc *crtc = NULL; |
||
853 | struct intel_crtc *intel_crtc; |
||
854 | struct drm_framebuffer *fb; |
||
855 | struct drm_i915_gem_object *obj; |
||
856 | const struct drm_display_mode *adjusted_mode; |
||
857 | |||
858 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
||
859 | |||
860 | /* disable framebuffer compression in vGPU */ |
||
861 | if (intel_vgpu_active(dev_priv->dev)) |
||
862 | i915.enable_fbc = 0; |
||
863 | |||
864 | if (i915.enable_fbc < 0) { |
||
865 | set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT); |
||
866 | goto out_disable; |
||
867 | } |
||
868 | |||
869 | if (!i915.enable_fbc) { |
||
870 | set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM); |
||
871 | goto out_disable; |
||
872 | } |
||
873 | |||
874 | /* |
||
875 | * If FBC is already on, we just have to verify that we can |
||
876 | * keep it that way... |
||
877 | * Need to disable if: |
||
878 | * - more than one pipe is active |
||
879 | * - changing FBC params (stride, fence, mode) |
||
880 | * - new fb is too large to fit in compressed buffer |
||
881 | * - going to an unsupported config (interlace, pixel multiply, etc.) |
||
882 | */ |
||
883 | crtc = intel_fbc_find_crtc(dev_priv); |
||
884 | if (!crtc) { |
||
885 | set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT); |
||
886 | goto out_disable; |
||
887 | } |
||
888 | |||
889 | if (!multiple_pipes_ok(dev_priv)) { |
||
890 | set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES); |
||
891 | goto out_disable; |
||
892 | } |
||
893 | |||
894 | intel_crtc = to_intel_crtc(crtc); |
||
895 | fb = crtc->primary->fb; |
||
896 | obj = intel_fb_obj(fb); |
||
897 | adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
||
898 | |||
899 | if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) || |
||
900 | (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) { |
||
901 | set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE); |
||
902 | goto out_disable; |
||
903 | } |
||
904 | |||
905 | if (!intel_fbc_hw_tracking_covers_screen(intel_crtc)) { |
||
906 | set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE); |
||
907 | goto out_disable; |
||
908 | } |
||
909 | |||
910 | if ((INTEL_INFO(dev_priv)->gen < 4 || HAS_DDI(dev_priv)) && |
||
911 | intel_crtc->plane != PLANE_A) { |
||
912 | set_no_fbc_reason(dev_priv, FBC_BAD_PLANE); |
||
913 | goto out_disable; |
||
914 | } |
||
915 | |||
916 | /* The use of a CPU fence is mandatory in order to detect writes |
||
917 | * by the CPU to the scanout and trigger updates to the FBC. |
||
918 | */ |
||
919 | if (obj->tiling_mode != I915_TILING_X || |
||
920 | obj->fence_reg == I915_FENCE_REG_NONE) { |
||
921 | set_no_fbc_reason(dev_priv, FBC_NOT_TILED); |
||
922 | goto out_disable; |
||
923 | } |
||
924 | if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) && |
||
925 | crtc->primary->state->rotation != BIT(DRM_ROTATE_0)) { |
||
926 | set_no_fbc_reason(dev_priv, FBC_ROTATION); |
||
927 | goto out_disable; |
||
928 | } |
||
929 | |||
930 | if (!stride_is_valid(dev_priv, fb->pitches[0])) { |
||
931 | set_no_fbc_reason(dev_priv, FBC_BAD_STRIDE); |
||
932 | goto out_disable; |
||
933 | } |
||
934 | |||
935 | if (!pixel_format_is_valid(fb)) { |
||
936 | set_no_fbc_reason(dev_priv, FBC_PIXEL_FORMAT); |
||
937 | goto out_disable; |
||
938 | } |
||
939 | |||
940 | /* If the kernel debugger is active, always disable compression */ |
||
941 | if (in_dbg_master()) { |
||
942 | set_no_fbc_reason(dev_priv, FBC_IN_DBG_MASTER); |
||
943 | goto out_disable; |
||
944 | } |
||
945 | |||
946 | /* WaFbcExceedCdClockThreshold:hsw,bdw */ |
||
947 | if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && |
||
948 | ilk_pipe_pixel_rate(intel_crtc->config) >= |
||
949 | dev_priv->cdclk_freq * 95 / 100) { |
||
950 | set_no_fbc_reason(dev_priv, FBC_PIXEL_RATE); |
||
951 | goto out_disable; |
||
952 | } |
||
953 | |||
954 | if (intel_fbc_setup_cfb(intel_crtc)) { |
||
955 | set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL); |
||
956 | goto out_disable; |
||
957 | } |
||
958 | |||
959 | /* If the scanout has not changed, don't modify the FBC settings. |
||
960 | * Note that we make the fundamental assumption that the fb->obj |
||
961 | * cannot be unpinned (and have its GTT offset and fence revoked) |
||
962 | * without first being decoupled from the scanout and FBC disabled. |
||
963 | */ |
||
964 | if (dev_priv->fbc.crtc == intel_crtc && |
||
965 | dev_priv->fbc.fb_id == fb->base.id && |
||
966 | dev_priv->fbc.y == crtc->y) |
||
967 | return; |
||
968 | |||
969 | if (intel_fbc_enabled(dev_priv)) { |
||
970 | /* We update FBC along two paths, after changing fb/crtc |
||
971 | * configuration (modeswitching) and after page-flipping |
||
972 | * finishes. For the latter, we know that not only did |
||
973 | * we disable the FBC at the start of the page-flip |
||
974 | * sequence, but also more than one vblank has passed. |
||
975 | * |
||
976 | * For the former case of modeswitching, it is possible |
||
977 | * to switch between two FBC valid configurations |
||
978 | * instantaneously so we do need to disable the FBC |
||
979 | * before we can modify its control registers. We also |
||
980 | * have to wait for the next vblank for that to take |
||
981 | * effect. However, since we delay enabling FBC we can |
||
982 | * assume that a vblank has passed since disabling and |
||
983 | * that we can safely alter the registers in the deferred |
||
984 | * callback. |
||
985 | * |
||
986 | * In the scenario that we go from a valid to invalid |
||
987 | * and then back to valid FBC configuration we have |
||
988 | * no strict enforcement that a vblank occurred since |
||
989 | * disabling the FBC. However, along all current pipe |
||
990 | * disabling paths we do need to wait for a vblank at |
||
991 | * some point. And we wait before enabling FBC anyway. |
||
992 | */ |
||
993 | DRM_DEBUG_KMS("disabling active FBC for update\n"); |
||
994 | __intel_fbc_disable(dev_priv); |
||
995 | } |
||
996 | |||
997 | intel_fbc_schedule_enable(intel_crtc); |
||
998 | dev_priv->fbc.no_fbc_reason = FBC_OK; |
||
999 | return; |
||
1000 | |||
1001 | out_disable: |
||
1002 | /* Multiple disables should be harmless */ |
||
1003 | if (intel_fbc_enabled(dev_priv)) { |
||
1004 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); |
||
1005 | __intel_fbc_disable(dev_priv); |
||
1006 | } |
||
1007 | __intel_fbc_cleanup_cfb(dev_priv); |
||
1008 | } |
||
1009 | |||
1010 | /* |
||
1011 | * intel_fbc_update - enable/disable FBC as needed |
||
1012 | * @dev_priv: i915 device instance |
||
1013 | * |
||
1014 | * This function reevaluates the overall state and enables or disables FBC. |
||
1015 | */ |
||
1016 | void intel_fbc_update(struct drm_i915_private *dev_priv) |
||
1017 | { |
||
1018 | if (!fbc_supported(dev_priv)) |
||
1019 | return; |
||
1020 | |||
1021 | mutex_lock(&dev_priv->fbc.lock); |
||
1022 | __intel_fbc_update(dev_priv); |
||
1023 | mutex_unlock(&dev_priv->fbc.lock); |
||
1024 | } |
||
1025 | |||
1026 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, |
||
1027 | unsigned int frontbuffer_bits, |
||
1028 | enum fb_op_origin origin) |
||
1029 | { |
||
1030 | unsigned int fbc_bits; |
||
1031 | |||
1032 | if (!fbc_supported(dev_priv)) |
||
1033 | return; |
||
1034 | |||
1035 | if (origin == ORIGIN_GTT) |
||
1036 | return; |
||
1037 | |||
1038 | mutex_lock(&dev_priv->fbc.lock); |
||
1039 | |||
1040 | if (dev_priv->fbc.enabled) |
||
1041 | fbc_bits = INTEL_FRONTBUFFER_PRIMARY(dev_priv->fbc.crtc->pipe); |
||
1042 | else if (dev_priv->fbc.fbc_work) |
||
1043 | fbc_bits = INTEL_FRONTBUFFER_PRIMARY( |
||
1044 | dev_priv->fbc.fbc_work->crtc->pipe); |
||
1045 | else |
||
1046 | fbc_bits = dev_priv->fbc.possible_framebuffer_bits; |
||
1047 | |||
1048 | dev_priv->fbc.busy_bits |= (fbc_bits & frontbuffer_bits); |
||
1049 | |||
1050 | if (dev_priv->fbc.busy_bits) |
||
1051 | __intel_fbc_disable(dev_priv); |
||
1052 | |||
1053 | mutex_unlock(&dev_priv->fbc.lock); |
||
1054 | } |
||
1055 | |||
1056 | void intel_fbc_flush(struct drm_i915_private *dev_priv, |
||
1057 | unsigned int frontbuffer_bits, enum fb_op_origin origin) |
||
1058 | { |
||
1059 | if (!fbc_supported(dev_priv)) |
||
1060 | return; |
||
1061 | |||
1062 | if (origin == ORIGIN_GTT) |
||
1063 | return; |
||
1064 | |||
1065 | mutex_lock(&dev_priv->fbc.lock); |
||
1066 | |||
1067 | dev_priv->fbc.busy_bits &= ~frontbuffer_bits; |
||
1068 | |||
1069 | if (!dev_priv->fbc.busy_bits) { |
||
1070 | __intel_fbc_disable(dev_priv); |
||
1071 | __intel_fbc_update(dev_priv); |
||
1072 | } |
||
1073 | |||
1074 | mutex_unlock(&dev_priv->fbc.lock); |
||
1075 | } |
||
1076 | |||
1077 | /** |
||
1078 | * intel_fbc_init - Initialize FBC |
||
1079 | * @dev_priv: the i915 device |
||
1080 | * |
||
1081 | * This function might be called during PM init process. |
||
1082 | */ |
||
1083 | void intel_fbc_init(struct drm_i915_private *dev_priv) |
||
1084 | { |
||
1085 | enum pipe pipe; |
||
1086 | |||
1087 | mutex_init(&dev_priv->fbc.lock); |
||
1088 | |||
1089 | if (!HAS_FBC(dev_priv)) { |
||
1090 | dev_priv->fbc.enabled = false; |
||
1091 | dev_priv->fbc.no_fbc_reason = FBC_UNSUPPORTED; |
||
1092 | return; |
||
1093 | } |
||
1094 | |||
1095 | for_each_pipe(dev_priv, pipe) { |
||
1096 | dev_priv->fbc.possible_framebuffer_bits |= |
||
1097 | INTEL_FRONTBUFFER_PRIMARY(pipe); |
||
1098 | |||
1099 | if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) |
||
1100 | break; |
||
1101 | } |
||
1102 | |||
1103 | if (INTEL_INFO(dev_priv)->gen >= 7) { |
||
1104 | dev_priv->fbc.fbc_enabled = ilk_fbc_enabled; |
||
1105 | dev_priv->fbc.enable_fbc = gen7_fbc_enable; |
||
1106 | dev_priv->fbc.disable_fbc = ilk_fbc_disable; |
||
1107 | } else if (INTEL_INFO(dev_priv)->gen >= 5) { |
||
1108 | dev_priv->fbc.fbc_enabled = ilk_fbc_enabled; |
||
1109 | dev_priv->fbc.enable_fbc = ilk_fbc_enable; |
||
1110 | dev_priv->fbc.disable_fbc = ilk_fbc_disable; |
||
1111 | } else if (IS_GM45(dev_priv)) { |
||
1112 | dev_priv->fbc.fbc_enabled = g4x_fbc_enabled; |
||
1113 | dev_priv->fbc.enable_fbc = g4x_fbc_enable; |
||
1114 | dev_priv->fbc.disable_fbc = g4x_fbc_disable; |
||
1115 | } else { |
||
1116 | dev_priv->fbc.fbc_enabled = i8xx_fbc_enabled; |
||
1117 | dev_priv->fbc.enable_fbc = i8xx_fbc_enable; |
||
1118 | dev_priv->fbc.disable_fbc = i8xx_fbc_disable; |
||
1119 | |||
1120 | /* This value was pulled out of someone's hat */ |
||
1121 | I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); |
||
1122 | } |
||
1123 | |||
1124 | dev_priv->fbc.enabled = dev_priv->fbc.fbc_enabled(dev_priv); |
||
1125 | }><>=>>>=>=>=>>>=>=><=>=>=><=>>><>><>>> |