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Rev | Author | Line No. | Line |
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2330 | Serge | 1 | /* |
2 | * Copyright 2006 Dave Airlie |
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3 | * Copyright © 2006-2007 Intel Corporation |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice (including the next |
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13 | * paragraph) shall be included in all copies or substantial portions of the |
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14 | * Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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22 | * DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: |
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25 | * Eric Anholt |
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26 | */ |
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27 | #include |
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28 | #include |
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3031 | serge | 29 | #include |
30 | #include |
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2330 | Serge | 31 | #include "intel_drv.h" |
3031 | serge | 32 | #include |
2330 | Serge | 33 | #include "i915_drv.h" |
34 | #include "dvo.h" |
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35 | |||
36 | #define SIL164_ADDR 0x38 |
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37 | #define CH7xxx_ADDR 0x76 |
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38 | #define TFP410_ADDR 0x38 |
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3031 | serge | 39 | #define NS2501_ADDR 0x38 |
2330 | Serge | 40 | |
41 | static const struct intel_dvo_device intel_dvo_devices[] = { |
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42 | { |
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43 | .type = INTEL_DVO_CHIP_TMDS, |
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44 | .name = "sil164", |
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45 | .dvo_reg = DVOC, |
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46 | .slave_addr = SIL164_ADDR, |
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47 | .dev_ops = &sil164_ops, |
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48 | }, |
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49 | { |
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50 | .type = INTEL_DVO_CHIP_TMDS, |
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51 | .name = "ch7xxx", |
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52 | .dvo_reg = DVOC, |
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53 | .slave_addr = CH7xxx_ADDR, |
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54 | .dev_ops = &ch7xxx_ops, |
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55 | }, |
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56 | { |
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4104 | Serge | 57 | .type = INTEL_DVO_CHIP_TMDS, |
58 | .name = "ch7xxx", |
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59 | .dvo_reg = DVOC, |
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60 | .slave_addr = 0x75, /* For some ch7010 */ |
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61 | .dev_ops = &ch7xxx_ops, |
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62 | }, |
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63 | { |
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2330 | Serge | 64 | .type = INTEL_DVO_CHIP_LVDS, |
65 | .name = "ivch", |
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66 | .dvo_reg = DVOA, |
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67 | .slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */ |
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68 | .dev_ops = &ivch_ops, |
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69 | }, |
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70 | { |
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71 | .type = INTEL_DVO_CHIP_TMDS, |
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72 | .name = "tfp410", |
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73 | .dvo_reg = DVOC, |
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74 | .slave_addr = TFP410_ADDR, |
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75 | .dev_ops = &tfp410_ops, |
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76 | }, |
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77 | { |
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78 | .type = INTEL_DVO_CHIP_LVDS, |
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79 | .name = "ch7017", |
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80 | .dvo_reg = DVOC, |
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81 | .slave_addr = 0x75, |
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82 | .gpio = GMBUS_PORT_DPB, |
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83 | .dev_ops = &ch7017_ops, |
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3031 | serge | 84 | }, |
85 | { |
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86 | .type = INTEL_DVO_CHIP_TMDS, |
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87 | .name = "ns2501", |
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5354 | serge | 88 | .dvo_reg = DVOB, |
3031 | serge | 89 | .slave_addr = NS2501_ADDR, |
90 | .dev_ops = &ns2501_ops, |
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2330 | Serge | 91 | } |
92 | }; |
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93 | |||
94 | struct intel_dvo { |
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95 | struct intel_encoder base; |
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96 | |||
97 | struct intel_dvo_device dev; |
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98 | |||
99 | struct drm_display_mode *panel_fixed_mode; |
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100 | bool panel_wants_dither; |
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101 | }; |
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102 | |||
4104 | Serge | 103 | static struct intel_dvo *enc_to_dvo(struct intel_encoder *encoder) |
2330 | Serge | 104 | { |
4104 | Serge | 105 | return container_of(encoder, struct intel_dvo, base); |
2330 | Serge | 106 | } |
107 | |||
108 | static struct intel_dvo *intel_attached_dvo(struct drm_connector *connector) |
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109 | { |
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4104 | Serge | 110 | return enc_to_dvo(intel_attached_encoder(connector)); |
2330 | Serge | 111 | } |
112 | |||
3031 | serge | 113 | static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector) |
2330 | Serge | 114 | { |
5060 | serge | 115 | struct drm_device *dev = connector->base.dev; |
116 | struct drm_i915_private *dev_priv = dev->dev_private; |
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3031 | serge | 117 | struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base); |
5060 | serge | 118 | u32 tmp; |
3031 | serge | 119 | |
5060 | serge | 120 | tmp = I915_READ(intel_dvo->dev.dvo_reg); |
121 | |||
122 | if (!(tmp & DVO_ENABLE)) |
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123 | return false; |
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124 | |||
3031 | serge | 125 | return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev); |
126 | } |
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127 | |||
128 | static bool intel_dvo_get_hw_state(struct intel_encoder *encoder, |
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129 | enum pipe *pipe) |
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130 | { |
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131 | struct drm_device *dev = encoder->base.dev; |
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132 | struct drm_i915_private *dev_priv = dev->dev_private; |
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4104 | Serge | 133 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
3031 | serge | 134 | u32 tmp; |
135 | |||
136 | tmp = I915_READ(intel_dvo->dev.dvo_reg); |
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137 | |||
138 | if (!(tmp & DVO_ENABLE)) |
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139 | return false; |
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140 | |||
141 | *pipe = PORT_TO_PIPE(tmp); |
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142 | |||
143 | return true; |
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144 | } |
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145 | |||
4104 | Serge | 146 | static void intel_dvo_get_config(struct intel_encoder *encoder, |
147 | struct intel_crtc_config *pipe_config) |
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148 | { |
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149 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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150 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
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151 | u32 tmp, flags = 0; |
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152 | |||
153 | tmp = I915_READ(intel_dvo->dev.dvo_reg); |
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154 | if (tmp & DVO_HSYNC_ACTIVE_HIGH) |
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155 | flags |= DRM_MODE_FLAG_PHSYNC; |
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156 | else |
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157 | flags |= DRM_MODE_FLAG_NHSYNC; |
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158 | if (tmp & DVO_VSYNC_ACTIVE_HIGH) |
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159 | flags |= DRM_MODE_FLAG_PVSYNC; |
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160 | else |
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161 | flags |= DRM_MODE_FLAG_NVSYNC; |
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162 | |||
163 | pipe_config->adjusted_mode.flags |= flags; |
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4560 | Serge | 164 | |
165 | pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock; |
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4104 | Serge | 166 | } |
167 | |||
3031 | serge | 168 | static void intel_disable_dvo(struct intel_encoder *encoder) |
169 | { |
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170 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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4104 | Serge | 171 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
2330 | Serge | 172 | u32 dvo_reg = intel_dvo->dev.dvo_reg; |
173 | u32 temp = I915_READ(dvo_reg); |
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174 | |||
3031 | serge | 175 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false); |
176 | I915_WRITE(dvo_reg, temp & ~DVO_ENABLE); |
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177 | I915_READ(dvo_reg); |
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178 | } |
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179 | |||
180 | static void intel_enable_dvo(struct intel_encoder *encoder) |
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181 | { |
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182 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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4104 | Serge | 183 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
4398 | Serge | 184 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
3031 | serge | 185 | u32 dvo_reg = intel_dvo->dev.dvo_reg; |
186 | u32 temp = I915_READ(dvo_reg); |
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187 | |||
4398 | Serge | 188 | intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, |
189 | &crtc->config.requested_mode, |
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190 | &crtc->config.adjusted_mode); |
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191 | |||
5354 | serge | 192 | I915_WRITE(dvo_reg, temp | DVO_ENABLE); |
193 | I915_READ(dvo_reg); |
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194 | |||
3031 | serge | 195 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true); |
196 | } |
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197 | |||
4104 | Serge | 198 | /* Special dpms function to support cloning between dvo/sdvo/crt. */ |
3031 | serge | 199 | static void intel_dvo_dpms(struct drm_connector *connector, int mode) |
200 | { |
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201 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
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202 | struct drm_crtc *crtc; |
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4398 | Serge | 203 | struct intel_crtc_config *config; |
3031 | serge | 204 | |
205 | /* dvo supports only 2 dpms states. */ |
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206 | if (mode != DRM_MODE_DPMS_ON) |
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207 | mode = DRM_MODE_DPMS_OFF; |
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208 | |||
209 | if (mode == connector->dpms) |
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210 | return; |
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211 | |||
212 | connector->dpms = mode; |
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213 | |||
214 | /* Only need to change hw state when actually enabled */ |
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215 | crtc = intel_dvo->base.base.crtc; |
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216 | if (!crtc) { |
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217 | intel_dvo->base.connectors_active = false; |
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218 | return; |
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219 | } |
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220 | |||
4104 | Serge | 221 | /* We call connector dpms manually below in case pipe dpms doesn't |
222 | * change due to cloning. */ |
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3031 | serge | 223 | if (mode == DRM_MODE_DPMS_ON) { |
4398 | Serge | 224 | config = &to_intel_crtc(crtc)->config; |
225 | |||
3031 | serge | 226 | intel_dvo->base.connectors_active = true; |
227 | |||
228 | intel_crtc_update_dpms(crtc); |
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229 | |||
230 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true); |
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2330 | Serge | 231 | } else { |
3031 | serge | 232 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false); |
233 | |||
234 | intel_dvo->base.connectors_active = false; |
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235 | |||
236 | intel_crtc_update_dpms(crtc); |
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2330 | Serge | 237 | } |
3031 | serge | 238 | |
239 | intel_modeset_check_state(connector->dev); |
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2330 | Serge | 240 | } |
241 | |||
4560 | Serge | 242 | static enum drm_mode_status |
243 | intel_dvo_mode_valid(struct drm_connector *connector, |
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2330 | Serge | 244 | struct drm_display_mode *mode) |
245 | { |
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246 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
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247 | |||
248 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
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249 | return MODE_NO_DBLESCAN; |
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250 | |||
251 | /* XXX: Validate clock range */ |
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252 | |||
253 | if (intel_dvo->panel_fixed_mode) { |
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254 | if (mode->hdisplay > intel_dvo->panel_fixed_mode->hdisplay) |
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255 | return MODE_PANEL; |
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256 | if (mode->vdisplay > intel_dvo->panel_fixed_mode->vdisplay) |
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257 | return MODE_PANEL; |
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258 | } |
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259 | |||
260 | return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode); |
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261 | } |
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262 | |||
4104 | Serge | 263 | static bool intel_dvo_compute_config(struct intel_encoder *encoder, |
264 | struct intel_crtc_config *pipe_config) |
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2330 | Serge | 265 | { |
4104 | Serge | 266 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
267 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
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2330 | Serge | 268 | |
269 | /* If we have timings from the BIOS for the panel, put them in |
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270 | * to the adjusted mode. The CRTC will be set up for this mode, |
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271 | * with the panel scaling set up to source from the H/VDisplay |
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272 | * of the original mode. |
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273 | */ |
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274 | if (intel_dvo->panel_fixed_mode != NULL) { |
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275 | #define C(x) adjusted_mode->x = intel_dvo->panel_fixed_mode->x |
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276 | C(hdisplay); |
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277 | C(hsync_start); |
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278 | C(hsync_end); |
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279 | C(htotal); |
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280 | C(vdisplay); |
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281 | C(vsync_start); |
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282 | C(vsync_end); |
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283 | C(vtotal); |
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284 | C(clock); |
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285 | #undef C |
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4104 | Serge | 286 | |
287 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
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2330 | Serge | 288 | } |
289 | |||
290 | return true; |
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291 | } |
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292 | |||
5060 | serge | 293 | static void intel_dvo_pre_enable(struct intel_encoder *encoder) |
2330 | Serge | 294 | { |
4104 | Serge | 295 | struct drm_device *dev = encoder->base.dev; |
2330 | Serge | 296 | struct drm_i915_private *dev_priv = dev->dev_private; |
4104 | Serge | 297 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
298 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; |
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299 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
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300 | int pipe = crtc->pipe; |
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2330 | Serge | 301 | u32 dvo_val; |
302 | u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg; |
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303 | |||
304 | switch (dvo_reg) { |
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305 | case DVOA: |
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306 | default: |
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307 | dvo_srcdim_reg = DVOA_SRCDIM; |
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308 | break; |
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309 | case DVOB: |
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310 | dvo_srcdim_reg = DVOB_SRCDIM; |
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311 | break; |
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312 | case DVOC: |
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313 | dvo_srcdim_reg = DVOC_SRCDIM; |
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314 | break; |
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315 | } |
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316 | |||
317 | /* Save the data order, since I don't know what it should be set to. */ |
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318 | dvo_val = I915_READ(dvo_reg) & |
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319 | (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG); |
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320 | dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE | |
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321 | DVO_BLANK_ACTIVE_HIGH; |
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322 | |||
323 | if (pipe == 1) |
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324 | dvo_val |= DVO_PIPE_B_SELECT; |
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325 | dvo_val |= DVO_PIPE_STALL; |
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326 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
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327 | dvo_val |= DVO_HSYNC_ACTIVE_HIGH; |
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328 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
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329 | dvo_val |= DVO_VSYNC_ACTIVE_HIGH; |
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330 | |||
331 | /*I915_WRITE(DVOB_SRCDIM, |
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332 | (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | |
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333 | (adjusted_mode->VDisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/ |
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334 | I915_WRITE(dvo_srcdim_reg, |
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335 | (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | |
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336 | (adjusted_mode->vdisplay << DVO_SRCDIM_VERTICAL_SHIFT)); |
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337 | /*I915_WRITE(DVOB, dvo_val);*/ |
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338 | I915_WRITE(dvo_reg, dvo_val); |
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339 | } |
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340 | |||
341 | /** |
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342 | * Detect the output connection on our DVO device. |
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343 | * |
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344 | * Unimplemented. |
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345 | */ |
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346 | static enum drm_connector_status |
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347 | intel_dvo_detect(struct drm_connector *connector, bool force) |
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348 | { |
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349 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
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4104 | Serge | 350 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
5060 | serge | 351 | connector->base.id, connector->name); |
2330 | Serge | 352 | return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev); |
353 | } |
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354 | |||
355 | static int intel_dvo_get_modes(struct drm_connector *connector) |
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356 | { |
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357 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
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358 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
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359 | |||
360 | /* We should probably have an i2c driver get_modes function for those |
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361 | * devices which will have a fixed set of modes determined by the chip |
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362 | * (TV-out, for example), but for now with just TMDS and LVDS, |
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363 | * that's not the case. |
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364 | */ |
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365 | intel_ddc_get_modes(connector, |
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3031 | serge | 366 | intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPC)); |
2330 | Serge | 367 | if (!list_empty(&connector->probed_modes)) |
368 | return 1; |
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369 | |||
370 | if (intel_dvo->panel_fixed_mode != NULL) { |
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371 | struct drm_display_mode *mode; |
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372 | mode = drm_mode_duplicate(connector->dev, intel_dvo->panel_fixed_mode); |
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373 | if (mode) { |
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374 | drm_mode_probed_add(connector, mode); |
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375 | return 1; |
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376 | } |
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377 | } |
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378 | |||
379 | return 0; |
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380 | } |
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381 | |||
382 | static void intel_dvo_destroy(struct drm_connector *connector) |
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383 | { |
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384 | drm_connector_cleanup(connector); |
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385 | kfree(connector); |
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386 | } |
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387 | |||
388 | static const struct drm_connector_funcs intel_dvo_connector_funcs = { |
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3031 | serge | 389 | .dpms = intel_dvo_dpms, |
2330 | Serge | 390 | .detect = intel_dvo_detect, |
391 | .destroy = intel_dvo_destroy, |
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392 | .fill_modes = drm_helper_probe_single_connector_modes, |
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393 | }; |
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394 | |||
395 | static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = { |
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396 | .mode_valid = intel_dvo_mode_valid, |
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397 | .get_modes = intel_dvo_get_modes, |
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398 | .best_encoder = intel_best_encoder, |
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399 | }; |
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400 | |||
401 | static void intel_dvo_enc_destroy(struct drm_encoder *encoder) |
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402 | { |
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4104 | Serge | 403 | struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder)); |
2330 | Serge | 404 | |
405 | if (intel_dvo->dev.dev_ops->destroy) |
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406 | intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev); |
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407 | |||
408 | kfree(intel_dvo->panel_fixed_mode); |
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409 | |||
410 | intel_encoder_destroy(encoder); |
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411 | } |
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412 | |||
413 | static const struct drm_encoder_funcs intel_dvo_enc_funcs = { |
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414 | .destroy = intel_dvo_enc_destroy, |
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415 | }; |
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416 | |||
417 | /** |
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418 | * Attempts to get a fixed panel timing for LVDS (currently only the i830). |
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419 | * |
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420 | * Other chips with DVO LVDS will need to extend this to deal with the LVDS |
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421 | * chip being on DVOB/C and having multiple pipes. |
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422 | */ |
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423 | static struct drm_display_mode * |
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424 | intel_dvo_get_current_mode(struct drm_connector *connector) |
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425 | { |
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426 | struct drm_device *dev = connector->dev; |
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427 | struct drm_i915_private *dev_priv = dev->dev_private; |
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428 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
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429 | uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg); |
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430 | struct drm_display_mode *mode = NULL; |
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431 | |||
432 | /* If the DVO port is active, that'll be the LVDS, so we can pull out |
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433 | * its timings to get how the BIOS set up the panel. |
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434 | */ |
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435 | if (dvo_val & DVO_ENABLE) { |
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436 | struct drm_crtc *crtc; |
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437 | int pipe = (dvo_val & DVO_PIPE_B_SELECT) ? 1 : 0; |
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438 | |||
439 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
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440 | if (crtc) { |
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441 | mode = intel_crtc_mode_get(dev, crtc); |
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442 | if (mode) { |
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443 | mode->type |= DRM_MODE_TYPE_PREFERRED; |
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444 | if (dvo_val & DVO_HSYNC_ACTIVE_HIGH) |
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445 | mode->flags |= DRM_MODE_FLAG_PHSYNC; |
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446 | if (dvo_val & DVO_VSYNC_ACTIVE_HIGH) |
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447 | mode->flags |= DRM_MODE_FLAG_PVSYNC; |
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448 | } |
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449 | } |
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450 | } |
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451 | |||
452 | return mode; |
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453 | } |
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454 | |||
455 | void intel_dvo_init(struct drm_device *dev) |
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456 | { |
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457 | struct drm_i915_private *dev_priv = dev->dev_private; |
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458 | struct intel_encoder *intel_encoder; |
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459 | struct intel_dvo *intel_dvo; |
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460 | struct intel_connector *intel_connector; |
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461 | int i; |
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462 | int encoder_type = DRM_MODE_ENCODER_NONE; |
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463 | |||
4560 | Serge | 464 | intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL); |
2330 | Serge | 465 | if (!intel_dvo) |
466 | return; |
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467 | |||
4560 | Serge | 468 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
2330 | Serge | 469 | if (!intel_connector) { |
470 | kfree(intel_dvo); |
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471 | return; |
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472 | } |
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473 | |||
474 | intel_encoder = &intel_dvo->base; |
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475 | drm_encoder_init(dev, &intel_encoder->base, |
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476 | &intel_dvo_enc_funcs, encoder_type); |
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477 | |||
3031 | serge | 478 | intel_encoder->disable = intel_disable_dvo; |
479 | intel_encoder->enable = intel_enable_dvo; |
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480 | intel_encoder->get_hw_state = intel_dvo_get_hw_state; |
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4104 | Serge | 481 | intel_encoder->get_config = intel_dvo_get_config; |
482 | intel_encoder->compute_config = intel_dvo_compute_config; |
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5060 | serge | 483 | intel_encoder->pre_enable = intel_dvo_pre_enable; |
3031 | serge | 484 | intel_connector->get_hw_state = intel_dvo_connector_get_hw_state; |
5060 | serge | 485 | intel_connector->unregister = intel_connector_unregister; |
3031 | serge | 486 | |
2330 | Serge | 487 | /* Now, try to find a controller */ |
488 | for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) { |
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489 | struct drm_connector *connector = &intel_connector->base; |
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490 | const struct intel_dvo_device *dvo = &intel_dvo_devices[i]; |
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491 | struct i2c_adapter *i2c; |
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492 | int gpio; |
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3746 | Serge | 493 | bool dvoinit; |
2330 | Serge | 494 | |
495 | /* Allow the I2C driver info to specify the GPIO to be used in |
||
496 | * special cases, but otherwise default to what's defined |
||
497 | * in the spec. |
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498 | */ |
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3031 | serge | 499 | if (intel_gmbus_is_port_valid(dvo->gpio)) |
2330 | Serge | 500 | gpio = dvo->gpio; |
501 | else if (dvo->type == INTEL_DVO_CHIP_LVDS) |
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502 | gpio = GMBUS_PORT_SSC; |
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503 | else |
||
504 | gpio = GMBUS_PORT_DPB; |
||
505 | |||
506 | /* Set up the I2C bus necessary for the chip we're probing. |
||
507 | * It appears that everything is on GPIOE except for panels |
||
508 | * on i830 laptops, which are on GPIOB (DVOA). |
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509 | */ |
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3031 | serge | 510 | i2c = intel_gmbus_get_adapter(dev_priv, gpio); |
2330 | Serge | 511 | |
512 | intel_dvo->dev = *dvo; |
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3746 | Serge | 513 | |
514 | /* GMBUS NAK handling seems to be unstable, hence let the |
||
515 | * transmitter detection run in bit banging mode for now. |
||
516 | */ |
||
517 | intel_gmbus_force_bit(i2c, true); |
||
518 | |||
519 | dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c); |
||
520 | |||
521 | intel_gmbus_force_bit(i2c, false); |
||
522 | |||
523 | if (!dvoinit) |
||
2330 | Serge | 524 | continue; |
525 | |||
526 | intel_encoder->type = INTEL_OUTPUT_DVO; |
||
527 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
||
528 | switch (dvo->type) { |
||
529 | case INTEL_DVO_CHIP_TMDS: |
||
5060 | serge | 530 | intel_encoder->cloneable = (1 << INTEL_OUTPUT_ANALOG) | |
531 | (1 << INTEL_OUTPUT_DVO); |
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2330 | Serge | 532 | drm_connector_init(dev, connector, |
533 | &intel_dvo_connector_funcs, |
||
534 | DRM_MODE_CONNECTOR_DVII); |
||
535 | encoder_type = DRM_MODE_ENCODER_TMDS; |
||
536 | break; |
||
537 | case INTEL_DVO_CHIP_LVDS: |
||
5060 | serge | 538 | intel_encoder->cloneable = 0; |
2330 | Serge | 539 | drm_connector_init(dev, connector, |
540 | &intel_dvo_connector_funcs, |
||
541 | DRM_MODE_CONNECTOR_LVDS); |
||
542 | encoder_type = DRM_MODE_ENCODER_LVDS; |
||
543 | break; |
||
544 | } |
||
545 | |||
546 | drm_connector_helper_add(connector, |
||
547 | &intel_dvo_connector_helper_funcs); |
||
548 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; |
||
549 | connector->interlace_allowed = false; |
||
550 | connector->doublescan_allowed = false; |
||
551 | |||
552 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
||
553 | if (dvo->type == INTEL_DVO_CHIP_LVDS) { |
||
554 | /* For our LVDS chipsets, we should hopefully be able |
||
555 | * to dig the fixed panel mode out of the BIOS data. |
||
556 | * However, it's in a different format from the BIOS |
||
557 | * data on chipsets with integrated LVDS (stored in AIM |
||
558 | * headers, likely), so for now, just get the current |
||
559 | * mode being output through DVO. |
||
560 | */ |
||
561 | intel_dvo->panel_fixed_mode = |
||
562 | intel_dvo_get_current_mode(connector); |
||
563 | intel_dvo->panel_wants_dither = true; |
||
564 | } |
||
565 | |||
5060 | serge | 566 | drm_connector_register(connector); |
2330 | Serge | 567 | return; |
568 | } |
||
569 | |||
570 | drm_encoder_cleanup(&intel_encoder->base); |
||
571 | kfree(intel_dvo); |
||
572 | kfree(intel_connector); |
||
573 | }><>><>><>><>>><>><>><>><> |