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Rev | Author | Line No. | Line |
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4560 | Serge | 1 | /* |
2 | * Copyright © 2013 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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21 | * DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Shobhit Kumar |
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25 | * Yogesh Mohan Marimuthu |
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26 | */ |
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27 | |||
28 | #include |
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29 | #include "intel_drv.h" |
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30 | #include "i915_drv.h" |
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31 | #include "intel_dsi.h" |
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32 | |||
7144 | serge | 33 | int dsi_pixel_format_bpp(int pixel_format) |
6084 | serge | 34 | { |
35 | int bpp; |
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36 | |||
37 | switch (pixel_format) { |
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38 | default: |
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39 | case VID_MODE_FORMAT_RGB888: |
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40 | case VID_MODE_FORMAT_RGB666_LOOSE: |
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41 | bpp = 24; |
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42 | break; |
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43 | case VID_MODE_FORMAT_RGB666: |
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44 | bpp = 18; |
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45 | break; |
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46 | case VID_MODE_FORMAT_RGB565: |
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47 | bpp = 16; |
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48 | break; |
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49 | } |
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50 | |||
51 | return bpp; |
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52 | } |
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53 | |||
4560 | Serge | 54 | struct dsi_mnp { |
55 | u32 dsi_pll_ctrl; |
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56 | u32 dsi_pll_div; |
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57 | }; |
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58 | |||
59 | static const u32 lfsr_converts[] = { |
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60 | 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */ |
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61 | 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */ |
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6084 | serge | 62 | 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */ |
63 | 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */ |
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4560 | Serge | 64 | }; |
65 | |||
66 | /* Get DSI clock from pixel clock */ |
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5354 | serge | 67 | static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count) |
4560 | Serge | 68 | { |
69 | u32 dsi_clk_khz; |
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6084 | serge | 70 | u32 bpp = dsi_pixel_format_bpp(pixel_format); |
4560 | Serge | 71 | |
72 | /* DSI data rate = pixel clock * bits per pixel / lane count |
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73 | pixel clock is converted from KHz to Hz */ |
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5354 | serge | 74 | dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); |
4560 | Serge | 75 | |
76 | return dsi_clk_khz; |
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77 | } |
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78 | |||
6084 | serge | 79 | static int dsi_calc_mnp(struct drm_i915_private *dev_priv, |
80 | struct dsi_mnp *dsi_mnp, int target_dsi_clk) |
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4560 | Serge | 81 | { |
6084 | serge | 82 | unsigned int calc_m = 0, calc_p = 0; |
83 | unsigned int m_min, m_max, p_min = 2, p_max = 6; |
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84 | unsigned int m, n, p; |
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85 | int ref_clk; |
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86 | int delta = target_dsi_clk; |
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4560 | Serge | 87 | u32 m_seed; |
88 | |||
6084 | serge | 89 | /* target_dsi_clk is expected in kHz */ |
90 | if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) { |
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4560 | Serge | 91 | DRM_ERROR("DSI CLK Out of Range\n"); |
92 | return -ECHRNG; |
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93 | } |
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94 | |||
6084 | serge | 95 | if (IS_CHERRYVIEW(dev_priv)) { |
96 | ref_clk = 100000; |
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97 | n = 4; |
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98 | m_min = 70; |
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99 | m_max = 96; |
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100 | } else { |
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101 | ref_clk = 25000; |
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102 | n = 1; |
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103 | m_min = 62; |
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104 | m_max = 92; |
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105 | } |
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4560 | Serge | 106 | |
6084 | serge | 107 | for (m = m_min; m <= m_max && delta; m++) { |
108 | for (p = p_min; p <= p_max && delta; p++) { |
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109 | /* |
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110 | * Find the optimal m and p divisors with minimal delta |
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111 | * +/- the required clock |
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112 | */ |
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113 | int calc_dsi_clk = (m * ref_clk) / (p * n); |
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114 | int d = abs(target_dsi_clk - calc_dsi_clk); |
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115 | if (d < delta) { |
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116 | delta = d; |
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4560 | Serge | 117 | calc_m = m; |
118 | calc_p = p; |
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119 | } |
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120 | } |
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121 | } |
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122 | |||
6084 | serge | 123 | /* register has log2(N1), this works fine for powers of two */ |
124 | n = ffs(n) - 1; |
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4560 | Serge | 125 | m_seed = lfsr_converts[calc_m - 62]; |
126 | dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2); |
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6084 | serge | 127 | dsi_mnp->dsi_pll_div = n << DSI_PLL_N1_DIV_SHIFT | |
4560 | Serge | 128 | m_seed << DSI_PLL_M1_DIV_SHIFT; |
129 | |||
130 | return 0; |
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131 | } |
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132 | |||
133 | /* |
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134 | * XXX: The muxing and gating is hard coded for now. Need to add support for |
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135 | * sharing PLLs with two DSI outputs. |
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136 | */ |
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137 | static void vlv_configure_dsi_pll(struct intel_encoder *encoder) |
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138 | { |
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139 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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140 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
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141 | int ret; |
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142 | struct dsi_mnp dsi_mnp; |
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143 | u32 dsi_clk; |
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144 | |||
5354 | serge | 145 | dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, |
6084 | serge | 146 | intel_dsi->lane_count); |
4560 | Serge | 147 | |
6084 | serge | 148 | ret = dsi_calc_mnp(dev_priv, &dsi_mnp, dsi_clk); |
4560 | Serge | 149 | if (ret) { |
150 | DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); |
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151 | return; |
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152 | } |
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153 | |||
6084 | serge | 154 | if (intel_dsi->ports & (1 << PORT_A)) |
155 | dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL; |
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4560 | Serge | 156 | |
6084 | serge | 157 | if (intel_dsi->ports & (1 << PORT_C)) |
158 | dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL; |
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159 | |||
4560 | Serge | 160 | DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n", |
161 | dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl); |
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162 | |||
163 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0); |
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164 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div); |
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165 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl); |
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166 | } |
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167 | |||
6084 | serge | 168 | static void vlv_enable_dsi_pll(struct intel_encoder *encoder) |
4560 | Serge | 169 | { |
170 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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171 | u32 tmp; |
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172 | |||
173 | DRM_DEBUG_KMS("\n"); |
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174 | |||
6084 | serge | 175 | mutex_lock(&dev_priv->sb_lock); |
4560 | Serge | 176 | |
177 | vlv_configure_dsi_pll(encoder); |
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178 | |||
179 | /* wait at least 0.5 us after ungating before enabling VCO */ |
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180 | usleep_range(1, 10); |
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181 | |||
182 | tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
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183 | tmp |= DSI_PLL_VCO_EN; |
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184 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); |
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185 | |||
6084 | serge | 186 | if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & |
187 | DSI_PLL_LOCK, 20)) { |
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4560 | Serge | 188 | |
6084 | serge | 189 | mutex_unlock(&dev_priv->sb_lock); |
4560 | Serge | 190 | DRM_ERROR("DSI PLL lock failed\n"); |
191 | return; |
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192 | } |
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6084 | serge | 193 | mutex_unlock(&dev_priv->sb_lock); |
4560 | Serge | 194 | |
195 | DRM_DEBUG_KMS("DSI PLL locked\n"); |
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196 | } |
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197 | |||
6084 | serge | 198 | static void vlv_disable_dsi_pll(struct intel_encoder *encoder) |
4560 | Serge | 199 | { |
200 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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201 | u32 tmp; |
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202 | |||
203 | DRM_DEBUG_KMS("\n"); |
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204 | |||
6084 | serge | 205 | mutex_lock(&dev_priv->sb_lock); |
4560 | Serge | 206 | |
207 | tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
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208 | tmp &= ~DSI_PLL_VCO_EN; |
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209 | tmp |= DSI_PLL_LDO_GATE; |
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210 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); |
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211 | |||
6084 | serge | 212 | mutex_unlock(&dev_priv->sb_lock); |
4560 | Serge | 213 | } |
5060 | serge | 214 | |
6084 | serge | 215 | static void bxt_disable_dsi_pll(struct intel_encoder *encoder) |
216 | { |
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217 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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218 | u32 val; |
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219 | |||
220 | DRM_DEBUG_KMS("\n"); |
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221 | |||
222 | val = I915_READ(BXT_DSI_PLL_ENABLE); |
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223 | val &= ~BXT_DSI_PLL_DO_ENABLE; |
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224 | I915_WRITE(BXT_DSI_PLL_ENABLE, val); |
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225 | |||
226 | /* |
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227 | * PLL lock should deassert within 200us. |
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228 | * Wait up to 1ms before timing out. |
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229 | */ |
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230 | if (wait_for((I915_READ(BXT_DSI_PLL_ENABLE) |
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231 | & BXT_DSI_PLL_LOCKED) == 0, 1)) |
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232 | DRM_ERROR("Timeout waiting for PLL lock deassertion\n"); |
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233 | } |
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234 | |||
5060 | serge | 235 | static void assert_bpp_mismatch(int pixel_format, int pipe_bpp) |
236 | { |
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6084 | serge | 237 | int bpp = dsi_pixel_format_bpp(pixel_format); |
5060 | serge | 238 | |
239 | WARN(bpp != pipe_bpp, |
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6084 | serge | 240 | "bpp match assertion failure (expected %d, current %d)\n", |
241 | bpp, pipe_bpp); |
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5060 | serge | 242 | } |
243 | |||
7144 | serge | 244 | static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp) |
5060 | serge | 245 | { |
246 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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247 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
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248 | u32 dsi_clock, pclk; |
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249 | u32 pll_ctl, pll_div; |
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6084 | serge | 250 | u32 m = 0, p = 0, n; |
5060 | serge | 251 | int refclk = 25000; |
252 | int i; |
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253 | |||
254 | DRM_DEBUG_KMS("\n"); |
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255 | |||
6084 | serge | 256 | mutex_lock(&dev_priv->sb_lock); |
5060 | serge | 257 | pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
258 | pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); |
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6084 | serge | 259 | mutex_unlock(&dev_priv->sb_lock); |
5060 | serge | 260 | |
261 | /* mask out other bits and extract the P1 divisor */ |
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262 | pll_ctl &= DSI_PLL_P1_POST_DIV_MASK; |
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263 | pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2); |
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264 | |||
6084 | serge | 265 | /* N1 divisor */ |
266 | n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT; |
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267 | n = 1 << n; /* register has log2(N1) */ |
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268 | |||
5060 | serge | 269 | /* mask out the other bits and extract the M1 divisor */ |
270 | pll_div &= DSI_PLL_M1_DIV_MASK; |
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271 | pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT; |
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272 | |||
273 | while (pll_ctl) { |
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274 | pll_ctl = pll_ctl >> 1; |
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275 | p++; |
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276 | } |
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277 | p--; |
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278 | |||
279 | if (!p) { |
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280 | DRM_ERROR("wrong P1 divisor\n"); |
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281 | return 0; |
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282 | } |
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283 | |||
284 | for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) { |
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285 | if (lfsr_converts[i] == pll_div) |
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286 | break; |
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287 | } |
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288 | |||
289 | if (i == ARRAY_SIZE(lfsr_converts)) { |
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290 | DRM_ERROR("wrong m_seed programmed\n"); |
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291 | return 0; |
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292 | } |
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293 | |||
294 | m = i + 62; |
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295 | |||
6084 | serge | 296 | dsi_clock = (m * refclk) / (p * n); |
5060 | serge | 297 | |
298 | /* pixel_format and pipe_bpp should agree */ |
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299 | assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); |
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300 | |||
301 | pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp); |
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302 | |||
303 | return pclk; |
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304 | } |
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6084 | serge | 305 | |
7144 | serge | 306 | static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp) |
6084 | serge | 307 | { |
308 | u32 pclk; |
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309 | u32 dsi_clk; |
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310 | u32 dsi_ratio; |
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311 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
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312 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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313 | |||
314 | /* Divide by zero */ |
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315 | if (!pipe_bpp) { |
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316 | DRM_ERROR("Invalid BPP(0)\n"); |
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317 | return 0; |
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318 | } |
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319 | |||
320 | dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) & |
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321 | BXT_DSI_PLL_RATIO_MASK; |
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322 | |||
323 | /* Invalid DSI ratio ? */ |
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324 | if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN || |
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325 | dsi_ratio > BXT_DSI_PLL_RATIO_MAX) { |
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326 | DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio); |
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327 | return 0; |
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328 | } |
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329 | |||
330 | dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2; |
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331 | |||
332 | /* pixel_format and pipe_bpp should agree */ |
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333 | assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); |
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334 | |||
335 | pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp); |
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336 | |||
337 | DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk); |
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338 | return pclk; |
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339 | } |
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340 | |||
7144 | serge | 341 | u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp) |
342 | { |
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343 | if (IS_BROXTON(encoder->base.dev)) |
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344 | return bxt_dsi_get_pclk(encoder, pipe_bpp); |
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345 | else |
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346 | return vlv_dsi_get_pclk(encoder, pipe_bpp); |
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347 | } |
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348 | |||
6084 | serge | 349 | static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) |
350 | { |
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351 | u32 temp; |
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352 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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353 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
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354 | |||
355 | temp = I915_READ(MIPI_CTRL(port)); |
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356 | temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; |
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357 | I915_WRITE(MIPI_CTRL(port), temp | |
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358 | intel_dsi->escape_clk_div << |
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359 | ESCAPE_CLOCK_DIVIDER_SHIFT); |
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360 | } |
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361 | |||
362 | /* Program BXT Mipi clocks and dividers */ |
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363 | static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port) |
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364 | { |
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365 | u32 tmp; |
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366 | u32 divider; |
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367 | u32 dsi_rate; |
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368 | u32 pll_ratio; |
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369 | struct drm_i915_private *dev_priv = dev->dev_private; |
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370 | |||
371 | /* Clear old configurations */ |
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372 | tmp = I915_READ(BXT_MIPI_CLOCK_CTL); |
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373 | tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); |
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374 | tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port)); |
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375 | tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port)); |
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376 | tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port)); |
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377 | |||
378 | /* Get the current DSI rate(actual) */ |
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379 | pll_ratio = I915_READ(BXT_DSI_PLL_CTL) & |
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380 | BXT_DSI_PLL_RATIO_MASK; |
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381 | dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; |
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382 | |||
383 | /* Max possible output of clock is 39.5 MHz, program value -1 */ |
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384 | divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1; |
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385 | tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider); |
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386 | |||
387 | /* |
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388 | * Tx escape clock must be as close to 20MHz possible, but should |
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389 | * not exceed it. Hence select divide by 2 |
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390 | */ |
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391 | tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port); |
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392 | |||
393 | tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port); |
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394 | |||
395 | I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); |
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396 | } |
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397 | |||
398 | static bool bxt_configure_dsi_pll(struct intel_encoder *encoder) |
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399 | { |
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400 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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401 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
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402 | u8 dsi_ratio; |
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403 | u32 dsi_clk; |
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404 | u32 val; |
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405 | |||
406 | dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, |
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407 | intel_dsi->lane_count); |
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408 | |||
409 | /* |
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410 | * From clock diagram, to get PLL ratio divider, divide double of DSI |
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411 | * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to |
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412 | * round 'up' the result |
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413 | */ |
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414 | dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ); |
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415 | if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN || |
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416 | dsi_ratio > BXT_DSI_PLL_RATIO_MAX) { |
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417 | DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n"); |
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418 | return false; |
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419 | } |
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420 | |||
421 | /* |
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422 | * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x |
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423 | * Spec says both have to be programmed, even if one is not getting |
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424 | * used. Configure MIPI_CLOCK_CTL dividers in modeset |
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425 | */ |
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426 | val = I915_READ(BXT_DSI_PLL_CTL); |
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427 | val &= ~BXT_DSI_PLL_PVD_RATIO_MASK; |
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428 | val &= ~BXT_DSI_FREQ_SEL_MASK; |
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429 | val &= ~BXT_DSI_PLL_RATIO_MASK; |
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430 | val |= (dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2); |
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431 | |||
432 | /* As per recommendation from hardware team, |
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433 | * Prog PVD ratio =1 if dsi ratio <= 50 |
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434 | */ |
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435 | if (dsi_ratio <= 50) { |
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436 | val &= ~BXT_DSI_PLL_PVD_RATIO_MASK; |
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437 | val |= BXT_DSI_PLL_PVD_RATIO_1; |
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438 | } |
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439 | |||
440 | I915_WRITE(BXT_DSI_PLL_CTL, val); |
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441 | POSTING_READ(BXT_DSI_PLL_CTL); |
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442 | |||
443 | return true; |
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444 | } |
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445 | |||
446 | static void bxt_enable_dsi_pll(struct intel_encoder *encoder) |
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447 | { |
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448 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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449 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
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450 | enum port port; |
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451 | u32 val; |
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452 | |||
453 | DRM_DEBUG_KMS("\n"); |
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454 | |||
455 | val = I915_READ(BXT_DSI_PLL_ENABLE); |
||
456 | |||
457 | if (val & BXT_DSI_PLL_DO_ENABLE) { |
||
458 | WARN(1, "DSI PLL already enabled. Disabling it.\n"); |
||
459 | val &= ~BXT_DSI_PLL_DO_ENABLE; |
||
460 | I915_WRITE(BXT_DSI_PLL_ENABLE, val); |
||
461 | } |
||
462 | |||
463 | /* Configure PLL vales */ |
||
464 | if (!bxt_configure_dsi_pll(encoder)) { |
||
465 | DRM_ERROR("Configure DSI PLL failed, abort PLL enable\n"); |
||
466 | return; |
||
467 | } |
||
468 | |||
469 | /* Program TX, RX, Dphy clocks */ |
||
470 | for_each_dsi_port(port, intel_dsi->ports) |
||
471 | bxt_dsi_program_clocks(encoder->base.dev, port); |
||
472 | |||
473 | /* Enable DSI PLL */ |
||
474 | val = I915_READ(BXT_DSI_PLL_ENABLE); |
||
475 | val |= BXT_DSI_PLL_DO_ENABLE; |
||
476 | I915_WRITE(BXT_DSI_PLL_ENABLE, val); |
||
477 | |||
478 | /* Timeout and fail if PLL not locked */ |
||
479 | if (wait_for(I915_READ(BXT_DSI_PLL_ENABLE) & BXT_DSI_PLL_LOCKED, 1)) { |
||
480 | DRM_ERROR("Timed out waiting for DSI PLL to lock\n"); |
||
481 | return; |
||
482 | } |
||
483 | |||
484 | DRM_DEBUG_KMS("DSI PLL locked\n"); |
||
485 | } |
||
486 | |||
487 | void intel_enable_dsi_pll(struct intel_encoder *encoder) |
||
488 | { |
||
489 | struct drm_device *dev = encoder->base.dev; |
||
490 | |||
6937 | serge | 491 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6084 | serge | 492 | vlv_enable_dsi_pll(encoder); |
493 | else if (IS_BROXTON(dev)) |
||
494 | bxt_enable_dsi_pll(encoder); |
||
495 | } |
||
496 | |||
497 | void intel_disable_dsi_pll(struct intel_encoder *encoder) |
||
498 | { |
||
499 | struct drm_device *dev = encoder->base.dev; |
||
500 | |||
6937 | serge | 501 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6084 | serge | 502 | vlv_disable_dsi_pll(encoder); |
503 | else if (IS_BROXTON(dev)) |
||
504 | bxt_disable_dsi_pll(encoder); |
||
505 | } |
||
506 | |||
507 | static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) |
||
508 | { |
||
509 | u32 tmp; |
||
510 | struct drm_device *dev = encoder->base.dev; |
||
511 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
512 | |||
513 | /* Clear old configurations */ |
||
514 | tmp = I915_READ(BXT_MIPI_CLOCK_CTL); |
||
515 | tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); |
||
516 | tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port)); |
||
517 | tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port)); |
||
518 | tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port)); |
||
519 | I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); |
||
520 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); |
||
521 | } |
||
522 | |||
523 | void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) |
||
524 | { |
||
525 | struct drm_device *dev = encoder->base.dev; |
||
526 | |||
527 | if (IS_BROXTON(dev)) |
||
528 | bxt_dsi_reset_clocks(encoder, port); |
||
6937 | serge | 529 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6084 | serge | 530 | vlv_dsi_reset_clocks(encoder, port); |
531 | }=>=>> |