Rev 6937 | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
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5060 | serge | 1 | /* |
2 | * Copyright © 2014 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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21 | * DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Author: Shobhit Kumar |
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24 | * |
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25 | */ |
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26 | |||
27 | #include |
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28 | #include |
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29 | #include |
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30 | #include |
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6084 | serge | 31 | #include |
5060 | serge | 32 | #include |
33 | #include |
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6084 | serge | 34 | #include |
5060 | serge | 35 | #include |
36 | #include "i915_drv.h" |
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37 | #include "intel_drv.h" |
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38 | #include "intel_dsi.h" |
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39 | |||
6084 | serge | 40 | struct vbt_panel { |
41 | struct drm_panel panel; |
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42 | struct intel_dsi *intel_dsi; |
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43 | }; |
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44 | |||
45 | static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel) |
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46 | { |
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47 | return container_of(panel, struct vbt_panel, panel); |
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48 | } |
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49 | |||
5060 | serge | 50 | #define MIPI_TRANSFER_MODE_SHIFT 0 |
51 | #define MIPI_VIRTUAL_CHANNEL_SHIFT 1 |
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52 | #define MIPI_PORT_SHIFT 3 |
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53 | |||
54 | #define PREPARE_CNT_MAX 0x3F |
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55 | #define EXIT_ZERO_CNT_MAX 0x3F |
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56 | #define CLK_ZERO_CNT_MAX 0xFF |
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57 | #define TRAIL_CNT_MAX 0x1F |
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58 | |||
59 | #define NS_KHZ_RATIO 1000000 |
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60 | |||
61 | #define GPI0_NC_0_HV_DDI0_HPD 0x4130 |
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62 | #define GPIO_NC_0_HV_DDI0_PAD 0x4138 |
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63 | #define GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120 |
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64 | #define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD 0x4128 |
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65 | #define GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110 |
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66 | #define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD 0x4118 |
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67 | #define GPIO_NC_3_PANEL0_VDDEN 0x4140 |
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68 | #define GPIO_NC_3_PANEL0_VDDEN_PAD 0x4148 |
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69 | #define GPIO_NC_4_PANEL0_BLKEN 0x4150 |
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70 | #define GPIO_NC_4_PANEL0_BLKEN_PAD 0x4158 |
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71 | #define GPIO_NC_5_PANEL0_BLKCTL 0x4160 |
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72 | #define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168 |
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73 | #define GPIO_NC_6_PCONF0 0x4180 |
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74 | #define GPIO_NC_6_PAD 0x4188 |
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75 | #define GPIO_NC_7_PCONF0 0x4190 |
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76 | #define GPIO_NC_7_PAD 0x4198 |
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77 | #define GPIO_NC_8_PCONF0 0x4170 |
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78 | #define GPIO_NC_8_PAD 0x4178 |
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79 | #define GPIO_NC_9_PCONF0 0x4100 |
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80 | #define GPIO_NC_9_PAD 0x4108 |
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81 | #define GPIO_NC_10_PCONF0 0x40E0 |
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82 | #define GPIO_NC_10_PAD 0x40E8 |
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83 | #define GPIO_NC_11_PCONF0 0x40F0 |
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84 | #define GPIO_NC_11_PAD 0x40F8 |
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85 | |||
86 | struct gpio_table { |
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87 | u16 function_reg; |
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88 | u16 pad_reg; |
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89 | u8 init; |
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90 | }; |
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91 | |||
92 | static struct gpio_table gtable[] = { |
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93 | { GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 }, |
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94 | { GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 }, |
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95 | { GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 }, |
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96 | { GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 }, |
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97 | { GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 }, |
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98 | { GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 }, |
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99 | { GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 }, |
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100 | { GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 }, |
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101 | { GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 }, |
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102 | { GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 }, |
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103 | { GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0}, |
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104 | { GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0} |
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105 | }; |
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106 | |||
6084 | serge | 107 | static inline enum port intel_dsi_seq_port_to_port(u8 port) |
5060 | serge | 108 | { |
6084 | serge | 109 | return port ? PORT_C : PORT_A; |
110 | } |
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111 | |||
112 | static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, |
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113 | const u8 *data) |
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114 | { |
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115 | struct mipi_dsi_device *dsi_device; |
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116 | u8 type, flags, seq_port; |
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5060 | serge | 117 | u16 len; |
6084 | serge | 118 | enum port port; |
5060 | serge | 119 | |
6084 | serge | 120 | flags = *data++; |
5060 | serge | 121 | type = *data++; |
122 | |||
123 | len = *((u16 *) data); |
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124 | data += 2; |
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125 | |||
6084 | serge | 126 | seq_port = (flags >> MIPI_PORT_SHIFT) & 3; |
127 | |||
128 | /* For DSI single link on Port A & C, the seq_port value which is |
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129 | * parsed from Sequence Block#53 of VBT has been set to 0 |
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130 | * Now, read/write of packets for the DSI single link on Port A and |
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131 | * Port C will based on the DVO port from VBT block 2. |
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132 | */ |
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133 | if (intel_dsi->ports == (1 << PORT_C)) |
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134 | port = PORT_C; |
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135 | else |
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136 | port = intel_dsi_seq_port_to_port(seq_port); |
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137 | |||
138 | dsi_device = intel_dsi->dsi_hosts[port]->device; |
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139 | if (!dsi_device) { |
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140 | DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port)); |
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141 | goto out; |
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142 | } |
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143 | |||
144 | if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1) |
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145 | dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM; |
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146 | else |
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147 | dsi_device->mode_flags |= MIPI_DSI_MODE_LPM; |
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148 | |||
149 | dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3; |
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150 | |||
5060 | serge | 151 | switch (type) { |
152 | case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: |
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6084 | serge | 153 | mipi_dsi_generic_write(dsi_device, NULL, 0); |
5060 | serge | 154 | break; |
155 | case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: |
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6084 | serge | 156 | mipi_dsi_generic_write(dsi_device, data, 1); |
5060 | serge | 157 | break; |
158 | case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: |
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6084 | serge | 159 | mipi_dsi_generic_write(dsi_device, data, 2); |
5060 | serge | 160 | break; |
161 | case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: |
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162 | case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: |
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163 | case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: |
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164 | DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n"); |
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165 | break; |
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166 | case MIPI_DSI_GENERIC_LONG_WRITE: |
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6084 | serge | 167 | mipi_dsi_generic_write(dsi_device, data, len); |
5060 | serge | 168 | break; |
169 | case MIPI_DSI_DCS_SHORT_WRITE: |
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6084 | serge | 170 | mipi_dsi_dcs_write_buffer(dsi_device, data, 1); |
5060 | serge | 171 | break; |
172 | case MIPI_DSI_DCS_SHORT_WRITE_PARAM: |
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6084 | serge | 173 | mipi_dsi_dcs_write_buffer(dsi_device, data, 2); |
5060 | serge | 174 | break; |
175 | case MIPI_DSI_DCS_READ: |
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176 | DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n"); |
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177 | break; |
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178 | case MIPI_DSI_DCS_LONG_WRITE: |
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6084 | serge | 179 | mipi_dsi_dcs_write_buffer(dsi_device, data, len); |
5060 | serge | 180 | break; |
181 | } |
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182 | |||
6084 | serge | 183 | out: |
5060 | serge | 184 | data += len; |
185 | |||
186 | return data; |
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187 | } |
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188 | |||
6084 | serge | 189 | static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) |
5060 | serge | 190 | { |
6084 | serge | 191 | u32 delay = *((const u32 *) data); |
5060 | serge | 192 | |
193 | usleep_range(delay, delay + 10); |
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194 | data += 4; |
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195 | |||
196 | return data; |
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197 | } |
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198 | |||
6084 | serge | 199 | static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) |
5060 | serge | 200 | { |
201 | u8 gpio, action; |
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202 | u16 function, pad; |
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203 | u32 val; |
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204 | struct drm_device *dev = intel_dsi->base.base.dev; |
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205 | struct drm_i915_private *dev_priv = dev->dev_private; |
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206 | |||
6937 | serge | 207 | if (dev_priv->vbt.dsi.seq_version >= 3) |
208 | data++; |
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209 | |||
5060 | serge | 210 | gpio = *data++; |
211 | |||
212 | /* pull up/down */ |
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6320 | serge | 213 | action = *data++ & 1; |
5060 | serge | 214 | |
6320 | serge | 215 | if (gpio >= ARRAY_SIZE(gtable)) { |
216 | DRM_DEBUG_KMS("unknown gpio %u\n", gpio); |
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217 | goto out; |
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218 | } |
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219 | |||
6937 | serge | 220 | if (!IS_VALLEYVIEW(dev_priv)) { |
221 | DRM_DEBUG_KMS("GPIO element not supported on this platform\n"); |
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222 | goto out; |
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223 | } |
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224 | |||
225 | if (dev_priv->vbt.dsi.seq_version >= 3) { |
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226 | DRM_DEBUG_KMS("GPIO element v3 not supported\n"); |
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227 | goto out; |
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228 | } |
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229 | |||
5060 | serge | 230 | function = gtable[gpio].function_reg; |
231 | pad = gtable[gpio].pad_reg; |
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232 | |||
6084 | serge | 233 | mutex_lock(&dev_priv->sb_lock); |
5060 | serge | 234 | if (!gtable[gpio].init) { |
235 | /* program the function */ |
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236 | /* FIXME: remove constant below */ |
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7144 | serge | 237 | vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function, |
238 | 0x2000CC00); |
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5060 | serge | 239 | gtable[gpio].init = 1; |
240 | } |
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241 | |||
242 | val = 0x4 | action; |
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243 | |||
244 | /* pull up/down */ |
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7144 | serge | 245 | vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val); |
6084 | serge | 246 | mutex_unlock(&dev_priv->sb_lock); |
5060 | serge | 247 | |
6320 | serge | 248 | out: |
5060 | serge | 249 | return data; |
250 | } |
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251 | |||
7144 | serge | 252 | static const u8 *mipi_exec_i2c_skip(struct intel_dsi *intel_dsi, const u8 *data) |
253 | { |
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254 | return data + *(data + 6) + 7; |
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255 | } |
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256 | |||
6084 | serge | 257 | typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, |
258 | const u8 *data); |
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5060 | serge | 259 | static const fn_mipi_elem_exec exec_elem[] = { |
7144 | serge | 260 | [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet, |
261 | [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay, |
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262 | [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio, |
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263 | [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c_skip, |
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5060 | serge | 264 | }; |
265 | |||
266 | /* |
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267 | * MIPI Sequence from VBT #53 parsing logic |
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268 | * We have already separated each seqence during bios parsing |
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269 | * Following is generic execution function for any sequence |
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270 | */ |
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271 | |||
272 | static const char * const seq_name[] = { |
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7144 | serge | 273 | [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET", |
274 | [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP", |
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275 | [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON", |
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276 | [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF", |
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277 | [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET", |
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278 | [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON", |
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279 | [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF", |
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280 | [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON", |
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281 | [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF", |
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282 | [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON", |
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283 | [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF", |
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5060 | serge | 284 | }; |
285 | |||
7144 | serge | 286 | static const char *sequence_name(enum mipi_seq seq_id) |
5060 | serge | 287 | { |
7144 | serge | 288 | if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id]) |
289 | return seq_name[seq_id]; |
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290 | else |
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291 | return "(unknown)"; |
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292 | } |
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293 | |||
294 | static void generic_exec_sequence(struct drm_panel *panel, enum mipi_seq seq_id) |
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295 | { |
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296 | struct vbt_panel *vbt_panel = to_vbt_panel(panel); |
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297 | struct intel_dsi *intel_dsi = vbt_panel->intel_dsi; |
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298 | struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); |
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299 | const u8 *data; |
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5060 | serge | 300 | fn_mipi_elem_exec mipi_elem_exec; |
301 | |||
7144 | serge | 302 | if (WARN_ON(seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence))) |
5060 | serge | 303 | return; |
304 | |||
7144 | serge | 305 | data = dev_priv->vbt.dsi.sequence[seq_id]; |
306 | if (!data) { |
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307 | DRM_DEBUG_KMS("MIPI sequence %d - %s not available\n", |
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308 | seq_id, sequence_name(seq_id)); |
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309 | return; |
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310 | } |
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5060 | serge | 311 | |
7144 | serge | 312 | WARN_ON(*data != seq_id); |
313 | |||
314 | DRM_DEBUG_KMS("Starting MIPI sequence %d - %s\n", |
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315 | seq_id, sequence_name(seq_id)); |
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316 | |||
317 | /* Skip Sequence Byte. */ |
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5060 | serge | 318 | data++; |
319 | |||
7144 | serge | 320 | /* Skip Size of Sequence. */ |
321 | if (dev_priv->vbt.dsi.seq_version >= 3) |
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322 | data += 4; |
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323 | |||
5060 | serge | 324 | while (1) { |
7144 | serge | 325 | u8 operation_byte = *data++; |
326 | u8 operation_size = 0; |
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5060 | serge | 327 | |
7144 | serge | 328 | if (operation_byte == MIPI_SEQ_ELEM_END) |
329 | break; |
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5060 | serge | 330 | |
7144 | serge | 331 | if (operation_byte < ARRAY_SIZE(exec_elem)) |
332 | mipi_elem_exec = exec_elem[operation_byte]; |
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333 | else |
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334 | mipi_elem_exec = NULL; |
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5060 | serge | 335 | |
7144 | serge | 336 | /* Size of Operation. */ |
337 | if (dev_priv->vbt.dsi.seq_version >= 3) |
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338 | operation_size = *data++; |
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339 | |||
340 | if (mipi_elem_exec) { |
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341 | data = mipi_elem_exec(intel_dsi, data); |
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342 | } else if (operation_size) { |
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343 | /* We have size, skip. */ |
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344 | DRM_DEBUG_KMS("Unsupported MIPI operation byte %u\n", |
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345 | operation_byte); |
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346 | data += operation_size; |
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347 | } else { |
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348 | /* No size, can't skip without parsing. */ |
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349 | DRM_ERROR("Unsupported MIPI operation byte %u\n", |
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350 | operation_byte); |
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351 | return; |
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352 | } |
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5060 | serge | 353 | } |
354 | } |
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355 | |||
6084 | serge | 356 | static int vbt_panel_prepare(struct drm_panel *panel) |
5060 | serge | 357 | { |
7144 | serge | 358 | generic_exec_sequence(panel, MIPI_SEQ_ASSERT_RESET); |
359 | generic_exec_sequence(panel, MIPI_SEQ_INIT_OTP); |
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6084 | serge | 360 | |
361 | return 0; |
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362 | } |
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363 | |||
364 | static int vbt_panel_unprepare(struct drm_panel *panel) |
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365 | { |
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7144 | serge | 366 | generic_exec_sequence(panel, MIPI_SEQ_DEASSERT_RESET); |
6084 | serge | 367 | |
368 | return 0; |
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369 | } |
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370 | |||
371 | static int vbt_panel_enable(struct drm_panel *panel) |
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372 | { |
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7144 | serge | 373 | generic_exec_sequence(panel, MIPI_SEQ_DISPLAY_ON); |
6084 | serge | 374 | |
375 | return 0; |
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376 | } |
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377 | |||
378 | static int vbt_panel_disable(struct drm_panel *panel) |
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379 | { |
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7144 | serge | 380 | generic_exec_sequence(panel, MIPI_SEQ_DISPLAY_OFF); |
6084 | serge | 381 | |
382 | return 0; |
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383 | } |
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384 | |||
385 | static int vbt_panel_get_modes(struct drm_panel *panel) |
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386 | { |
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387 | struct vbt_panel *vbt_panel = to_vbt_panel(panel); |
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388 | struct intel_dsi *intel_dsi = vbt_panel->intel_dsi; |
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389 | struct drm_device *dev = intel_dsi->base.base.dev; |
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390 | struct drm_i915_private *dev_priv = dev->dev_private; |
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391 | struct drm_display_mode *mode; |
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392 | |||
393 | if (!panel->connector) |
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394 | return 0; |
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395 | |||
396 | mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode); |
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397 | if (!mode) |
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398 | return 0; |
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399 | |||
400 | mode->type |= DRM_MODE_TYPE_PREFERRED; |
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401 | |||
402 | drm_mode_probed_add(panel->connector, mode); |
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403 | |||
404 | return 1; |
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405 | } |
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406 | |||
407 | static const struct drm_panel_funcs vbt_panel_funcs = { |
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408 | .disable = vbt_panel_disable, |
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409 | .unprepare = vbt_panel_unprepare, |
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410 | .prepare = vbt_panel_prepare, |
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411 | .enable = vbt_panel_enable, |
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412 | .get_modes = vbt_panel_get_modes, |
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413 | }; |
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414 | |||
415 | struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id) |
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416 | { |
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417 | struct drm_device *dev = intel_dsi->base.base.dev; |
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418 | struct drm_i915_private *dev_priv = dev->dev_private; |
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5060 | serge | 419 | struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; |
420 | struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps; |
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421 | struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode; |
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6084 | serge | 422 | struct vbt_panel *vbt_panel; |
5060 | serge | 423 | u32 bits_per_pixel = 24; |
424 | u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui; |
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425 | u32 ui_num, ui_den; |
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426 | u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; |
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427 | u32 ths_prepare_ns, tclk_trail_ns; |
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428 | u32 tclk_prepare_clkzero, ths_prepare_hszero; |
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429 | u32 lp_to_hs_switch, hs_to_lp_switch; |
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5354 | serge | 430 | u32 pclk, computed_ddr; |
431 | u16 burst_mode_ratio; |
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6084 | serge | 432 | enum port port; |
5060 | serge | 433 | |
434 | DRM_DEBUG_KMS("\n"); |
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435 | |||
436 | intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1; |
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437 | intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; |
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438 | intel_dsi->lane_count = mipi_config->lane_cnt + 1; |
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439 | intel_dsi->pixel_format = mipi_config->videomode_color_format << 7; |
||
6084 | serge | 440 | intel_dsi->dual_link = mipi_config->dual_link; |
441 | intel_dsi->pixel_overlap = mipi_config->pixel_overlap; |
||
5060 | serge | 442 | |
7144 | serge | 443 | bits_per_pixel = dsi_pixel_format_bpp(intel_dsi->pixel_format); |
5060 | serge | 444 | |
445 | intel_dsi->operation_mode = mipi_config->is_cmd_mode; |
||
446 | intel_dsi->video_mode_format = mipi_config->video_transfer_mode; |
||
447 | intel_dsi->escape_clk_div = mipi_config->byte_clk_sel; |
||
448 | intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout; |
||
449 | intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout; |
||
450 | intel_dsi->rst_timer_val = mipi_config->device_reset_timer; |
||
451 | intel_dsi->init_count = mipi_config->master_init_timer; |
||
452 | intel_dsi->bw_timer = mipi_config->dbi_bw_timer; |
||
453 | intel_dsi->video_frmt_cfg_bits = |
||
454 | mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0; |
||
455 | |||
5354 | serge | 456 | pclk = mode->clock; |
457 | |||
6084 | serge | 458 | /* In dual link mode each port needs half of pixel clock */ |
459 | if (intel_dsi->dual_link) { |
||
460 | pclk = pclk / 2; |
||
461 | |||
462 | /* we can enable pixel_overlap if needed by panel. In this |
||
463 | * case we need to increase the pixelclock for extra pixels |
||
464 | */ |
||
465 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { |
||
466 | pclk += DIV_ROUND_UP(mode->vtotal * |
||
467 | intel_dsi->pixel_overlap * |
||
468 | 60, 1000); |
||
469 | } |
||
470 | } |
||
471 | |||
5354 | serge | 472 | /* Burst Mode Ratio |
473 | * Target ddr frequency from VBT / non burst ddr freq |
||
474 | * multiply by 100 to preserve remainder |
||
475 | */ |
||
476 | if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) { |
||
477 | if (mipi_config->target_burst_mode_freq) { |
||
478 | computed_ddr = |
||
479 | (pclk * bits_per_pixel) / intel_dsi->lane_count; |
||
480 | |||
481 | if (mipi_config->target_burst_mode_freq < |
||
482 | computed_ddr) { |
||
483 | DRM_ERROR("Burst mode freq is less than computed\n"); |
||
6084 | serge | 484 | return NULL; |
5354 | serge | 485 | } |
486 | |||
487 | burst_mode_ratio = DIV_ROUND_UP( |
||
488 | mipi_config->target_burst_mode_freq * 100, |
||
489 | computed_ddr); |
||
490 | |||
491 | pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100); |
||
492 | } else { |
||
493 | DRM_ERROR("Burst mode target is not set\n"); |
||
6084 | serge | 494 | return NULL; |
5354 | serge | 495 | } |
496 | } else |
||
497 | burst_mode_ratio = 100; |
||
498 | |||
499 | intel_dsi->burst_mode_ratio = burst_mode_ratio; |
||
500 | intel_dsi->pclk = pclk; |
||
501 | |||
502 | bitrate = (pclk * bits_per_pixel) / intel_dsi->lane_count; |
||
503 | |||
5060 | serge | 504 | switch (intel_dsi->escape_clk_div) { |
505 | case 0: |
||
506 | tlpx_ns = 50; |
||
507 | break; |
||
508 | case 1: |
||
509 | tlpx_ns = 100; |
||
510 | break; |
||
511 | |||
512 | case 2: |
||
513 | tlpx_ns = 200; |
||
514 | break; |
||
515 | default: |
||
516 | tlpx_ns = 50; |
||
517 | break; |
||
518 | } |
||
519 | |||
520 | switch (intel_dsi->lane_count) { |
||
521 | case 1: |
||
522 | case 2: |
||
523 | extra_byte_count = 2; |
||
524 | break; |
||
525 | case 3: |
||
526 | extra_byte_count = 4; |
||
527 | break; |
||
528 | case 4: |
||
529 | default: |
||
530 | extra_byte_count = 3; |
||
531 | break; |
||
532 | } |
||
533 | |||
534 | /* |
||
535 | * ui(s) = 1/f [f in hz] |
||
536 | * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz) |
||
537 | */ |
||
538 | |||
539 | /* in Kbps */ |
||
540 | ui_num = NS_KHZ_RATIO; |
||
541 | ui_den = bitrate; |
||
542 | |||
543 | tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero; |
||
544 | ths_prepare_hszero = mipi_config->ths_prepare_hszero; |
||
545 | |||
546 | /* |
||
547 | * B060 |
||
548 | * LP byte clock = TLPX/ (8UI) |
||
549 | */ |
||
550 | intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num); |
||
551 | |||
552 | /* count values in UI = (ns value) * (bitrate / (2 * 10^6)) |
||
553 | * |
||
554 | * Since txddrclkhs_i is 2xUI, all the count values programmed in |
||
555 | * DPHY param register are divided by 2 |
||
556 | * |
||
557 | * prepare count |
||
558 | */ |
||
559 | ths_prepare_ns = max(mipi_config->ths_prepare, |
||
560 | mipi_config->tclk_prepare); |
||
561 | prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2); |
||
562 | |||
563 | /* exit zero count */ |
||
564 | exit_zero_cnt = DIV_ROUND_UP( |
||
565 | (ths_prepare_hszero - ths_prepare_ns) * ui_den, |
||
566 | ui_num * 2 |
||
567 | ); |
||
568 | |||
569 | /* |
||
570 | * Exit zero is unified val ths_zero and ths_exit |
||
571 | * minimum value for ths_exit = 110ns |
||
572 | * min (exit_zero_cnt * 2) = 110/UI |
||
573 | * exit_zero_cnt = 55/UI |
||
574 | */ |
||
575 | if (exit_zero_cnt < (55 * ui_den / ui_num)) |
||
576 | if ((55 * ui_den) % ui_num) |
||
577 | exit_zero_cnt += 1; |
||
578 | |||
579 | /* clk zero count */ |
||
580 | clk_zero_cnt = DIV_ROUND_UP( |
||
581 | (tclk_prepare_clkzero - ths_prepare_ns) |
||
582 | * ui_den, 2 * ui_num); |
||
583 | |||
584 | /* trail count */ |
||
585 | tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); |
||
586 | trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num); |
||
587 | |||
588 | if (prepare_cnt > PREPARE_CNT_MAX || |
||
589 | exit_zero_cnt > EXIT_ZERO_CNT_MAX || |
||
590 | clk_zero_cnt > CLK_ZERO_CNT_MAX || |
||
591 | trail_cnt > TRAIL_CNT_MAX) |
||
592 | DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n"); |
||
593 | |||
594 | if (prepare_cnt > PREPARE_CNT_MAX) |
||
595 | prepare_cnt = PREPARE_CNT_MAX; |
||
596 | |||
597 | if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) |
||
598 | exit_zero_cnt = EXIT_ZERO_CNT_MAX; |
||
599 | |||
600 | if (clk_zero_cnt > CLK_ZERO_CNT_MAX) |
||
601 | clk_zero_cnt = CLK_ZERO_CNT_MAX; |
||
602 | |||
603 | if (trail_cnt > TRAIL_CNT_MAX) |
||
604 | trail_cnt = TRAIL_CNT_MAX; |
||
605 | |||
606 | /* B080 */ |
||
607 | intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 | |
||
608 | clk_zero_cnt << 8 | prepare_cnt; |
||
609 | |||
610 | /* |
||
611 | * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2 |
||
612 | * + 10UI + Extra Byte Count |
||
613 | * |
||
614 | * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count |
||
615 | * Extra Byte Count is calculated according to number of lanes. |
||
616 | * High Low Switch Count is the Max of LP to HS and |
||
617 | * HS to LP switch count |
||
618 | * |
||
619 | */ |
||
620 | tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num); |
||
621 | |||
622 | /* B044 */ |
||
623 | /* FIXME: |
||
624 | * The comment above does not match with the code */ |
||
625 | lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 + |
||
626 | exit_zero_cnt * 2 + 10, 8); |
||
627 | |||
628 | hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); |
||
629 | |||
630 | intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch); |
||
631 | intel_dsi->hs_to_lp_count += extra_byte_count; |
||
632 | |||
633 | /* B088 */ |
||
634 | /* LP -> HS for clock lanes |
||
635 | * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero + |
||
636 | * extra byte count |
||
637 | * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt * |
||
638 | * 2(in UI) + extra byte count |
||
639 | * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) / |
||
640 | * 8 + extra byte count |
||
641 | */ |
||
642 | intel_dsi->clk_lp_to_hs_count = |
||
643 | DIV_ROUND_UP( |
||
644 | 4 * tlpx_ui + prepare_cnt * 2 + |
||
645 | clk_zero_cnt * 2, |
||
646 | 8); |
||
647 | |||
648 | intel_dsi->clk_lp_to_hs_count += extra_byte_count; |
||
649 | |||
650 | /* HS->LP for Clock Lanes |
||
651 | * Low Power clock synchronisations + 1Tx byteclk + tclk_trail + |
||
652 | * Extra byte count |
||
653 | * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count |
||
654 | * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 + |
||
655 | * Extra byte count |
||
656 | */ |
||
657 | intel_dsi->clk_hs_to_lp_count = |
||
658 | DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8, |
||
659 | 8); |
||
660 | intel_dsi->clk_hs_to_lp_count += extra_byte_count; |
||
661 | |||
662 | DRM_DEBUG_KMS("Eot %s\n", intel_dsi->eotp_pkt ? "enabled" : "disabled"); |
||
663 | DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ? |
||
664 | "disabled" : "enabled"); |
||
665 | DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video"); |
||
6084 | serge | 666 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) |
667 | DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); |
||
668 | else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT) |
||
669 | DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"); |
||
670 | else |
||
671 | DRM_DEBUG_KMS("Dual link: NONE\n"); |
||
5060 | serge | 672 | DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format); |
673 | DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div); |
||
674 | DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout); |
||
675 | DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val); |
||
676 | DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count); |
||
677 | DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count); |
||
678 | DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk); |
||
679 | DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer); |
||
680 | DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count); |
||
681 | DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count); |
||
682 | DRM_DEBUG_KMS("BTA %s\n", |
||
683 | intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA ? |
||
684 | "disabled" : "enabled"); |
||
685 | |||
686 | /* delays in VBT are in unit of 100us, so need to convert |
||
687 | * here in ms |
||
688 | * Delay (100us) * 100 /1000 = Delay / 10 (ms) */ |
||
689 | intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10; |
||
690 | intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10; |
||
691 | intel_dsi->panel_on_delay = pps->panel_on_delay / 10; |
||
692 | intel_dsi->panel_off_delay = pps->panel_off_delay / 10; |
||
693 | intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10; |
||
694 | |||
6084 | serge | 695 | /* This is cheating a bit with the cleanup. */ |
696 | vbt_panel = kzalloc(sizeof(*vbt_panel), GFP_KERNEL); |
||
7144 | serge | 697 | if (!vbt_panel) |
698 | return NULL; |
||
5060 | serge | 699 | |
6084 | serge | 700 | vbt_panel->intel_dsi = intel_dsi; |
701 | drm_panel_init(&vbt_panel->panel); |
||
702 | vbt_panel->panel.funcs = &vbt_panel_funcs; |
||
703 | drm_panel_add(&vbt_panel->panel); |
||
5060 | serge | 704 | |
6084 | serge | 705 | /* a regular driver would get the device in probe */ |
706 | for_each_dsi_port(port, intel_dsi->ports) { |
||
707 | mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device); |
||
708 | } |
||
5060 | serge | 709 | |
6084 | serge | 710 | return &vbt_panel->panel; |
5060 | serge | 711 | }><>><>><>> |