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Rev | Author | Line No. | Line |
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4560 | Serge | 1 | /* |
2 | * Copyright © 2013 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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21 | * DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Author: Jani Nikula |
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24 | */ |
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25 | |||
26 | #include |
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27 | #include |
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28 | #include |
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29 | #include |
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30 | #include |
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31 | #include "i915_drv.h" |
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32 | #include "intel_drv.h" |
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33 | #include "intel_dsi.h" |
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34 | #include "intel_dsi_cmd.h" |
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35 | |||
36 | /* the sub-encoders aka panel drivers */ |
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37 | static const struct intel_dsi_device intel_dsi_devices[] = { |
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5060 | serge | 38 | { |
39 | .panel_id = MIPI_DSI_GENERIC_PANEL_ID, |
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40 | .name = "vbt-generic-dsi-vid-mode-display", |
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41 | .dev_ops = &vbt_generic_dsi_display_ops, |
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42 | }, |
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4560 | Serge | 43 | }; |
44 | |||
45 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
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46 | { |
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47 | mutex_lock(&dev_priv->dpio_lock); |
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48 | |||
49 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
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50 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); |
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51 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); |
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52 | udelay(150); |
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53 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); |
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54 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); |
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55 | |||
56 | mutex_unlock(&dev_priv->dpio_lock); |
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57 | } |
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58 | |||
59 | static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector) |
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60 | { |
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61 | return container_of(intel_attached_encoder(connector), |
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62 | struct intel_dsi, base); |
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63 | } |
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64 | |||
65 | static inline bool is_vid_mode(struct intel_dsi *intel_dsi) |
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66 | { |
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5060 | serge | 67 | return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; |
4560 | Serge | 68 | } |
69 | |||
70 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) |
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71 | { |
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5060 | serge | 72 | return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; |
4560 | Serge | 73 | } |
74 | |||
75 | static void intel_dsi_hot_plug(struct intel_encoder *encoder) |
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76 | { |
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77 | DRM_DEBUG_KMS("\n"); |
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78 | } |
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79 | |||
80 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, |
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81 | struct intel_crtc_config *config) |
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82 | { |
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83 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, |
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84 | base); |
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85 | struct intel_connector *intel_connector = intel_dsi->attached_connector; |
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86 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
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87 | struct drm_display_mode *adjusted_mode = &config->adjusted_mode; |
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88 | struct drm_display_mode *mode = &config->requested_mode; |
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89 | |||
90 | DRM_DEBUG_KMS("\n"); |
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91 | |||
92 | if (fixed_mode) |
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93 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); |
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94 | |||
5060 | serge | 95 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
96 | adjusted_mode->flags = 0; |
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97 | |||
4560 | Serge | 98 | if (intel_dsi->dev.dev_ops->mode_fixup) |
99 | return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev, |
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100 | mode, adjusted_mode); |
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101 | |||
102 | return true; |
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103 | } |
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104 | |||
105 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
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106 | { |
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107 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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108 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
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109 | int pipe = intel_crtc->pipe; |
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110 | u32 val; |
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111 | |||
112 | DRM_DEBUG_KMS("\n"); |
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113 | |||
5060 | serge | 114 | mutex_lock(&dev_priv->dpio_lock); |
115 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms |
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116 | * needed everytime after power gate */ |
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117 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); |
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118 | mutex_unlock(&dev_priv->dpio_lock); |
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119 | |||
120 | /* bandgap reset is needed after everytime we do power gate */ |
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121 | band_gap_reset(dev_priv); |
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122 | |||
123 | I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER); |
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124 | usleep_range(2500, 3000); |
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125 | |||
4560 | Serge | 126 | val = I915_READ(MIPI_PORT_CTRL(pipe)); |
127 | I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD); |
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128 | usleep_range(1000, 1500); |
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129 | |||
5060 | serge | 130 | I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT); |
131 | usleep_range(2500, 3000); |
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4560 | Serge | 132 | |
5060 | serge | 133 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY); |
134 | usleep_range(2500, 3000); |
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4560 | Serge | 135 | } |
136 | |||
137 | static void intel_dsi_enable(struct intel_encoder *encoder) |
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138 | { |
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139 | struct drm_device *dev = encoder->base.dev; |
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140 | struct drm_i915_private *dev_priv = dev->dev_private; |
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141 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
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142 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
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143 | int pipe = intel_crtc->pipe; |
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144 | u32 temp; |
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145 | |||
146 | DRM_DEBUG_KMS("\n"); |
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147 | |||
148 | if (is_cmd_mode(intel_dsi)) |
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149 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4); |
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150 | else { |
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151 | msleep(20); /* XXX */ |
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5060 | serge | 152 | dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN); |
4560 | Serge | 153 | msleep(100); |
154 | |||
5060 | serge | 155 | if (intel_dsi->dev.dev_ops->enable) |
156 | intel_dsi->dev.dev_ops->enable(&intel_dsi->dev); |
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157 | |||
158 | wait_for_dsi_fifo_empty(intel_dsi); |
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159 | |||
4560 | Serge | 160 | /* assert ip_tg_enable signal */ |
161 | temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK; |
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162 | temp = temp | intel_dsi->port_bits; |
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163 | I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE); |
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164 | POSTING_READ(MIPI_PORT_CTRL(pipe)); |
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165 | } |
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5060 | serge | 166 | } |
4560 | Serge | 167 | |
5060 | serge | 168 | static void intel_dsi_pre_enable(struct intel_encoder *encoder) |
169 | { |
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170 | struct drm_device *dev = encoder->base.dev; |
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171 | struct drm_i915_private *dev_priv = dev->dev_private; |
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172 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
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173 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
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174 | enum pipe pipe = intel_crtc->pipe; |
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175 | u32 tmp; |
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176 | |||
177 | DRM_DEBUG_KMS("\n"); |
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178 | |||
179 | /* Disable DPOunit clock gating, can stall pipe |
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180 | * and we need DPLL REFA always enabled */ |
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181 | tmp = I915_READ(DPLL(pipe)); |
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182 | tmp |= DPLL_REFA_CLK_ENABLE_VLV; |
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183 | I915_WRITE(DPLL(pipe), tmp); |
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184 | |||
185 | /* update the hw state for DPLL */ |
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186 | intel_crtc->config.dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV | |
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187 | DPLL_REFA_CLK_ENABLE_VLV; |
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188 | |||
189 | tmp = I915_READ(DSPCLK_GATE_D); |
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190 | tmp |= DPOUNIT_CLOCK_GATE_DISABLE; |
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191 | I915_WRITE(DSPCLK_GATE_D, tmp); |
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192 | |||
193 | /* put device in ready state */ |
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194 | intel_dsi_device_ready(encoder); |
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195 | |||
196 | msleep(intel_dsi->panel_on_delay); |
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197 | |||
198 | if (intel_dsi->dev.dev_ops->panel_reset) |
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199 | intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev); |
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200 | |||
201 | if (intel_dsi->dev.dev_ops->send_otp_cmds) |
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202 | intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev); |
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203 | |||
204 | wait_for_dsi_fifo_empty(intel_dsi); |
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205 | |||
206 | /* Enable port in pre-enable phase itself because as per hw team |
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207 | * recommendation, port should be enabled befor plane & pipe */ |
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208 | intel_dsi_enable(encoder); |
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4560 | Serge | 209 | } |
210 | |||
5060 | serge | 211 | static void intel_dsi_enable_nop(struct intel_encoder *encoder) |
212 | { |
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213 | DRM_DEBUG_KMS("\n"); |
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214 | |||
215 | /* for DSI port enable has to be done before pipe |
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216 | * and plane enable, so port enable is done in |
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217 | * pre_enable phase itself unlike other encoders |
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218 | */ |
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219 | } |
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220 | |||
221 | static void intel_dsi_pre_disable(struct intel_encoder *encoder) |
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222 | { |
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223 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
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224 | |||
225 | DRM_DEBUG_KMS("\n"); |
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226 | |||
227 | if (is_vid_mode(intel_dsi)) { |
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228 | /* Send Shutdown command to the panel in LP mode */ |
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229 | dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN); |
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230 | msleep(10); |
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231 | } |
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232 | } |
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233 | |||
4560 | Serge | 234 | static void intel_dsi_disable(struct intel_encoder *encoder) |
235 | { |
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236 | struct drm_device *dev = encoder->base.dev; |
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237 | struct drm_i915_private *dev_priv = dev->dev_private; |
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238 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
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239 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
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240 | int pipe = intel_crtc->pipe; |
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241 | u32 temp; |
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242 | |||
243 | DRM_DEBUG_KMS("\n"); |
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244 | |||
245 | if (is_vid_mode(intel_dsi)) { |
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5060 | serge | 246 | wait_for_dsi_fifo_empty(intel_dsi); |
4560 | Serge | 247 | |
248 | /* de-assert ip_tg_enable signal */ |
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249 | temp = I915_READ(MIPI_PORT_CTRL(pipe)); |
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250 | I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE); |
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251 | POSTING_READ(MIPI_PORT_CTRL(pipe)); |
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252 | |||
253 | msleep(2); |
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254 | } |
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255 | |||
5060 | serge | 256 | /* Panel commands can be sent when clock is in LP11 */ |
257 | I915_WRITE(MIPI_DEVICE_READY(pipe), 0x0); |
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258 | |||
259 | temp = I915_READ(MIPI_CTRL(pipe)); |
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260 | temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; |
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261 | I915_WRITE(MIPI_CTRL(pipe), temp | |
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262 | intel_dsi->escape_clk_div << |
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263 | ESCAPE_CLOCK_DIVIDER_SHIFT); |
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264 | |||
265 | I915_WRITE(MIPI_EOT_DISABLE(pipe), CLOCKSTOP); |
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266 | |||
267 | temp = I915_READ(MIPI_DSI_FUNC_PRG(pipe)); |
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268 | temp &= ~VID_MODE_FORMAT_MASK; |
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269 | I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), temp); |
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270 | |||
271 | I915_WRITE(MIPI_DEVICE_READY(pipe), 0x1); |
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272 | |||
4560 | Serge | 273 | /* if disable packets are sent before sending shutdown packet then in |
274 | * some next enable sequence send turn on packet error is observed */ |
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275 | if (intel_dsi->dev.dev_ops->disable) |
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276 | intel_dsi->dev.dev_ops->disable(&intel_dsi->dev); |
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5060 | serge | 277 | |
278 | wait_for_dsi_fifo_empty(intel_dsi); |
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4560 | Serge | 279 | } |
280 | |||
281 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
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282 | { |
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283 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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284 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
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285 | int pipe = intel_crtc->pipe; |
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286 | u32 val; |
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287 | |||
288 | DRM_DEBUG_KMS("\n"); |
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289 | |||
5060 | serge | 290 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER); |
4560 | Serge | 291 | usleep_range(2000, 2500); |
292 | |||
5060 | serge | 293 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT); |
4560 | Serge | 294 | usleep_range(2000, 2500); |
295 | |||
5060 | serge | 296 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER); |
4560 | Serge | 297 | usleep_range(2000, 2500); |
298 | |||
5060 | serge | 299 | if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT) |
300 | == 0x00000), 30)) |
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301 | DRM_ERROR("DSI LP not going Low\n"); |
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302 | |||
4560 | Serge | 303 | val = I915_READ(MIPI_PORT_CTRL(pipe)); |
304 | I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD); |
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305 | usleep_range(1000, 1500); |
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306 | |||
307 | I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00); |
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308 | usleep_range(2000, 2500); |
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309 | |||
310 | vlv_disable_dsi_pll(encoder); |
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311 | } |
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5060 | serge | 312 | |
4560 | Serge | 313 | static void intel_dsi_post_disable(struct intel_encoder *encoder) |
314 | { |
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5060 | serge | 315 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
4560 | Serge | 316 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
5060 | serge | 317 | u32 val; |
4560 | Serge | 318 | |
319 | DRM_DEBUG_KMS("\n"); |
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320 | |||
5060 | serge | 321 | intel_dsi_disable(encoder); |
322 | |||
4560 | Serge | 323 | intel_dsi_clear_device_ready(encoder); |
324 | |||
5060 | serge | 325 | val = I915_READ(DSPCLK_GATE_D); |
326 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; |
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327 | I915_WRITE(DSPCLK_GATE_D, val); |
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328 | |||
4560 | Serge | 329 | if (intel_dsi->dev.dev_ops->disable_panel_power) |
330 | intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev); |
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5060 | serge | 331 | |
332 | msleep(intel_dsi->panel_off_delay); |
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333 | msleep(intel_dsi->panel_pwr_cycle_delay); |
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4560 | Serge | 334 | } |
335 | |||
336 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, |
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337 | enum pipe *pipe) |
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338 | { |
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339 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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5060 | serge | 340 | enum intel_display_power_domain power_domain; |
4560 | Serge | 341 | u32 port, func; |
342 | enum pipe p; |
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343 | |||
344 | DRM_DEBUG_KMS("\n"); |
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345 | |||
5060 | serge | 346 | power_domain = intel_display_port_power_domain(encoder); |
347 | if (!intel_display_power_enabled(dev_priv, power_domain)) |
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348 | return false; |
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349 | |||
4560 | Serge | 350 | /* XXX: this only works for one DSI output */ |
351 | for (p = PIPE_A; p <= PIPE_B; p++) { |
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352 | port = I915_READ(MIPI_PORT_CTRL(p)); |
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353 | func = I915_READ(MIPI_DSI_FUNC_PRG(p)); |
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354 | |||
355 | if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) { |
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356 | if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) { |
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357 | *pipe = p; |
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358 | return true; |
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359 | } |
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360 | } |
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361 | } |
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362 | |||
363 | return false; |
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364 | } |
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365 | |||
366 | static void intel_dsi_get_config(struct intel_encoder *encoder, |
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367 | struct intel_crtc_config *pipe_config) |
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368 | { |
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5060 | serge | 369 | u32 pclk; |
4560 | Serge | 370 | DRM_DEBUG_KMS("\n"); |
371 | |||
5060 | serge | 372 | /* |
373 | * DPLL_MD is not used in case of DSI, reading will get some default value |
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374 | * set dpll_md = 0 |
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375 | */ |
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376 | pipe_config->dpll_hw_state.dpll_md = 0; |
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377 | |||
378 | pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); |
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379 | if (!pclk) |
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380 | return; |
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381 | |||
382 | pipe_config->adjusted_mode.crtc_clock = pclk; |
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383 | pipe_config->port_clock = pclk; |
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4560 | Serge | 384 | } |
385 | |||
386 | static enum drm_mode_status |
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387 | intel_dsi_mode_valid(struct drm_connector *connector, |
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388 | struct drm_display_mode *mode) |
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389 | { |
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390 | struct intel_connector *intel_connector = to_intel_connector(connector); |
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391 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
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392 | struct intel_dsi *intel_dsi = intel_attached_dsi(connector); |
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393 | |||
394 | DRM_DEBUG_KMS("\n"); |
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395 | |||
396 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { |
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397 | DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); |
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398 | return MODE_NO_DBLESCAN; |
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399 | } |
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400 | |||
401 | if (fixed_mode) { |
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402 | if (mode->hdisplay > fixed_mode->hdisplay) |
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403 | return MODE_PANEL; |
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404 | if (mode->vdisplay > fixed_mode->vdisplay) |
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405 | return MODE_PANEL; |
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406 | } |
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407 | |||
408 | return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode); |
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409 | } |
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410 | |||
411 | /* return txclkesc cycles in terms of divider and duration in us */ |
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412 | static u16 txclkesc(u32 divider, unsigned int us) |
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413 | { |
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414 | switch (divider) { |
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415 | case ESCAPE_CLOCK_DIVIDER_1: |
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416 | default: |
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417 | return 20 * us; |
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418 | case ESCAPE_CLOCK_DIVIDER_2: |
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419 | return 10 * us; |
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420 | case ESCAPE_CLOCK_DIVIDER_4: |
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421 | return 5 * us; |
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422 | } |
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423 | } |
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424 | |||
425 | /* return pixels in terms of txbyteclkhs */ |
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426 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count) |
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427 | { |
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428 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count); |
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429 | } |
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430 | |||
431 | static void set_dsi_timings(struct drm_encoder *encoder, |
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432 | const struct drm_display_mode *mode) |
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433 | { |
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434 | struct drm_device *dev = encoder->dev; |
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435 | struct drm_i915_private *dev_priv = dev->dev_private; |
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436 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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437 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
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438 | int pipe = intel_crtc->pipe; |
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439 | unsigned int bpp = intel_crtc->config.pipe_bpp; |
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440 | unsigned int lane_count = intel_dsi->lane_count; |
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441 | |||
442 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; |
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443 | |||
444 | hactive = mode->hdisplay; |
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445 | hfp = mode->hsync_start - mode->hdisplay; |
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446 | hsync = mode->hsync_end - mode->hsync_start; |
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447 | hbp = mode->htotal - mode->hsync_end; |
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448 | |||
449 | vfp = mode->vsync_start - mode->vdisplay; |
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450 | vsync = mode->vsync_end - mode->vsync_start; |
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451 | vbp = mode->vtotal - mode->vsync_end; |
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452 | |||
453 | /* horizontal values are in terms of high speed byte clock */ |
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454 | hactive = txbyteclkhs(hactive, bpp, lane_count); |
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455 | hfp = txbyteclkhs(hfp, bpp, lane_count); |
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456 | hsync = txbyteclkhs(hsync, bpp, lane_count); |
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457 | hbp = txbyteclkhs(hbp, bpp, lane_count); |
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458 | |||
459 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive); |
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460 | I915_WRITE(MIPI_HFP_COUNT(pipe), hfp); |
||
461 | |||
462 | /* meaningful for video mode non-burst sync pulse mode only, can be zero |
||
463 | * for non-burst sync events and burst modes */ |
||
464 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync); |
||
465 | I915_WRITE(MIPI_HBP_COUNT(pipe), hbp); |
||
466 | |||
467 | /* vertical values are in terms of lines */ |
||
468 | I915_WRITE(MIPI_VFP_COUNT(pipe), vfp); |
||
469 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync); |
||
470 | I915_WRITE(MIPI_VBP_COUNT(pipe), vbp); |
||
471 | } |
||
472 | |||
5060 | serge | 473 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder) |
4560 | Serge | 474 | { |
475 | struct drm_encoder *encoder = &intel_encoder->base; |
||
476 | struct drm_device *dev = encoder->dev; |
||
477 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
478 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
||
479 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
||
480 | struct drm_display_mode *adjusted_mode = |
||
481 | &intel_crtc->config.adjusted_mode; |
||
482 | int pipe = intel_crtc->pipe; |
||
483 | unsigned int bpp = intel_crtc->config.pipe_bpp; |
||
484 | u32 val, tmp; |
||
485 | |||
486 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe)); |
||
487 | |||
488 | /* escape clock divider, 20MHz, shared for A and C. device ready must be |
||
489 | * off when doing this! txclkesc? */ |
||
490 | tmp = I915_READ(MIPI_CTRL(0)); |
||
491 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; |
||
492 | I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1); |
||
493 | |||
494 | /* read request priority is per pipe */ |
||
495 | tmp = I915_READ(MIPI_CTRL(pipe)); |
||
496 | tmp &= ~READ_REQUEST_PRIORITY_MASK; |
||
497 | I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH); |
||
498 | |||
499 | /* XXX: why here, why like this? handling in irq handler?! */ |
||
500 | I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff); |
||
501 | I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff); |
||
502 | |||
503 | I915_WRITE(MIPI_DPHY_PARAM(pipe), intel_dsi->dphy_reg); |
||
504 | |||
505 | I915_WRITE(MIPI_DPI_RESOLUTION(pipe), |
||
506 | adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT | |
||
507 | adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT); |
||
508 | |||
509 | set_dsi_timings(encoder, adjusted_mode); |
||
510 | |||
511 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; |
||
512 | if (is_cmd_mode(intel_dsi)) { |
||
513 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; |
||
514 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ |
||
515 | } else { |
||
516 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; |
||
517 | |||
518 | /* XXX: cross-check bpp vs. pixel format? */ |
||
519 | val |= intel_dsi->pixel_format; |
||
520 | } |
||
521 | I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val); |
||
522 | |||
523 | /* timeouts for recovery. one frame IIUC. if counter expires, EOT and |
||
524 | * stop state. */ |
||
525 | |||
526 | /* |
||
527 | * In burst mode, value greater than one DPI line Time in byte clock |
||
528 | * (txbyteclkhs) To timeout this timer 1+ of the above said value is |
||
529 | * recommended. |
||
530 | * |
||
531 | * In non-burst mode, Value greater than one DPI frame time in byte |
||
532 | * clock(txbyteclkhs) To timeout this timer 1+ of the above said value |
||
533 | * is recommended. |
||
534 | * |
||
535 | * In DBI only mode, value greater than one DBI frame time in byte |
||
536 | * clock(txbyteclkhs) To timeout this timer 1+ of the above said value |
||
537 | * is recommended. |
||
538 | */ |
||
539 | |||
540 | if (is_vid_mode(intel_dsi) && |
||
541 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { |
||
542 | I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), |
||
543 | txbyteclkhs(adjusted_mode->htotal, bpp, |
||
544 | intel_dsi->lane_count) + 1); |
||
545 | } else { |
||
546 | I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), |
||
547 | txbyteclkhs(adjusted_mode->vtotal * |
||
548 | adjusted_mode->htotal, |
||
549 | bpp, intel_dsi->lane_count) + 1); |
||
550 | } |
||
551 | I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout); |
||
552 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val); |
||
553 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val); |
||
554 | |||
555 | /* dphy stuff */ |
||
556 | |||
557 | /* in terms of low power clock */ |
||
5060 | serge | 558 | I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(intel_dsi->escape_clk_div, 100)); |
4560 | Serge | 559 | |
5060 | serge | 560 | val = 0; |
561 | if (intel_dsi->eotp_pkt == 0) |
||
562 | val |= EOT_DISABLE; |
||
563 | |||
564 | if (intel_dsi->clock_stop) |
||
565 | val |= CLOCKSTOP; |
||
566 | |||
4560 | Serge | 567 | /* recovery disables */ |
5060 | serge | 568 | I915_WRITE(MIPI_EOT_DISABLE(pipe), val); |
4560 | Serge | 569 | |
5060 | serge | 570 | /* in terms of low power clock */ |
571 | I915_WRITE(MIPI_INIT_COUNT(pipe), intel_dsi->init_count); |
||
572 | |||
4560 | Serge | 573 | /* in terms of txbyteclkhs. actual high to low switch + |
574 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. |
||
575 | * |
||
576 | * XXX: write MIPI_STOP_STATE_STALL? |
||
577 | */ |
||
578 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe), |
||
579 | intel_dsi->hs_to_lp_count); |
||
580 | |||
581 | /* XXX: low power clock equivalence in terms of byte clock. the number |
||
582 | * of byte clocks occupied in one low power clock. based on txbyteclkhs |
||
583 | * and txclkesc. txclkesc time / txbyteclk time * (105 + |
||
584 | * MIPI_STOP_STATE_STALL) / 105.??? |
||
585 | */ |
||
586 | I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk); |
||
587 | |||
588 | /* the bw essential for transmitting 16 long packets containing 252 |
||
589 | * bytes meant for dcs write memory command is programmed in this |
||
590 | * register in terms of byte clocks. based on dsi transfer rate and the |
||
591 | * number of lanes configured the time taken to transmit 16 long packets |
||
592 | * in a dsi stream varies. */ |
||
593 | I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer); |
||
594 | |||
595 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe), |
||
596 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | |
||
597 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); |
||
598 | |||
599 | if (is_vid_mode(intel_dsi)) |
||
5060 | serge | 600 | /* Some panels might have resolution which is not a multiple of |
601 | * 64 like 1366 x 768. Enable RANDOM resolution support for such |
||
602 | * panels by default */ |
||
4560 | Serge | 603 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe), |
604 | intel_dsi->video_frmt_cfg_bits | |
||
5060 | serge | 605 | intel_dsi->video_mode_format | |
606 | IP_TG_CONFIG | |
||
607 | RANDOM_DPI_DISPLAY_RESOLUTION); |
||
4560 | Serge | 608 | } |
609 | |||
5060 | serge | 610 | static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder) |
611 | { |
||
612 | DRM_DEBUG_KMS("\n"); |
||
613 | |||
614 | intel_dsi_prepare(encoder); |
||
615 | |||
616 | vlv_enable_dsi_pll(encoder); |
||
617 | } |
||
618 | |||
4560 | Serge | 619 | static enum drm_connector_status |
620 | intel_dsi_detect(struct drm_connector *connector, bool force) |
||
621 | { |
||
622 | struct intel_dsi *intel_dsi = intel_attached_dsi(connector); |
||
5060 | serge | 623 | struct intel_encoder *intel_encoder = &intel_dsi->base; |
624 | enum intel_display_power_domain power_domain; |
||
625 | enum drm_connector_status connector_status; |
||
626 | struct drm_i915_private *dev_priv = intel_encoder->base.dev->dev_private; |
||
627 | |||
4560 | Serge | 628 | DRM_DEBUG_KMS("\n"); |
5060 | serge | 629 | power_domain = intel_display_port_power_domain(intel_encoder); |
630 | |||
631 | intel_display_power_get(dev_priv, power_domain); |
||
632 | connector_status = intel_dsi->dev.dev_ops->detect(&intel_dsi->dev); |
||
633 | intel_display_power_put(dev_priv, power_domain); |
||
634 | |||
635 | return connector_status; |
||
4560 | Serge | 636 | } |
637 | |||
638 | static int intel_dsi_get_modes(struct drm_connector *connector) |
||
639 | { |
||
640 | struct intel_connector *intel_connector = to_intel_connector(connector); |
||
641 | struct drm_display_mode *mode; |
||
642 | |||
643 | DRM_DEBUG_KMS("\n"); |
||
644 | |||
645 | if (!intel_connector->panel.fixed_mode) { |
||
646 | DRM_DEBUG_KMS("no fixed mode\n"); |
||
647 | return 0; |
||
648 | } |
||
649 | |||
650 | mode = drm_mode_duplicate(connector->dev, |
||
651 | intel_connector->panel.fixed_mode); |
||
652 | if (!mode) { |
||
653 | DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); |
||
654 | return 0; |
||
655 | } |
||
656 | |||
657 | drm_mode_probed_add(connector, mode); |
||
658 | return 1; |
||
659 | } |
||
660 | |||
661 | static void intel_dsi_destroy(struct drm_connector *connector) |
||
662 | { |
||
663 | struct intel_connector *intel_connector = to_intel_connector(connector); |
||
664 | |||
665 | DRM_DEBUG_KMS("\n"); |
||
666 | intel_panel_fini(&intel_connector->panel); |
||
667 | drm_connector_cleanup(connector); |
||
668 | kfree(connector); |
||
669 | } |
||
670 | |||
671 | static const struct drm_encoder_funcs intel_dsi_funcs = { |
||
672 | .destroy = intel_encoder_destroy, |
||
673 | }; |
||
674 | |||
675 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { |
||
676 | .get_modes = intel_dsi_get_modes, |
||
677 | .mode_valid = intel_dsi_mode_valid, |
||
678 | .best_encoder = intel_best_encoder, |
||
679 | }; |
||
680 | |||
681 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { |
||
682 | .dpms = intel_connector_dpms, |
||
683 | .detect = intel_dsi_detect, |
||
684 | .destroy = intel_dsi_destroy, |
||
685 | .fill_modes = drm_helper_probe_single_connector_modes, |
||
686 | }; |
||
687 | |||
5060 | serge | 688 | void intel_dsi_init(struct drm_device *dev) |
4560 | Serge | 689 | { |
690 | struct intel_dsi *intel_dsi; |
||
691 | struct intel_encoder *intel_encoder; |
||
692 | struct drm_encoder *encoder; |
||
693 | struct intel_connector *intel_connector; |
||
694 | struct drm_connector *connector; |
||
695 | struct drm_display_mode *fixed_mode = NULL; |
||
5060 | serge | 696 | struct drm_i915_private *dev_priv = dev->dev_private; |
4560 | Serge | 697 | const struct intel_dsi_device *dsi; |
698 | unsigned int i; |
||
699 | |||
700 | DRM_DEBUG_KMS("\n"); |
||
701 | |||
5060 | serge | 702 | /* There is no detection method for MIPI so rely on VBT */ |
703 | if (!dev_priv->vbt.has_mipi) |
||
704 | return; |
||
705 | |||
706 | if (IS_VALLEYVIEW(dev)) { |
||
707 | dev_priv->mipi_mmio_base = VLV_MIPI_BASE; |
||
708 | } else { |
||
709 | DRM_ERROR("Unsupported Mipi device to reg base"); |
||
710 | return; |
||
711 | } |
||
712 | |||
4560 | Serge | 713 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
714 | if (!intel_dsi) |
||
5060 | serge | 715 | return; |
4560 | Serge | 716 | |
717 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
||
718 | if (!intel_connector) { |
||
719 | kfree(intel_dsi); |
||
5060 | serge | 720 | return; |
4560 | Serge | 721 | } |
722 | |||
723 | intel_encoder = &intel_dsi->base; |
||
724 | encoder = &intel_encoder->base; |
||
725 | intel_dsi->attached_connector = intel_connector; |
||
726 | |||
727 | connector = &intel_connector->base; |
||
728 | |||
729 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI); |
||
730 | |||
731 | /* XXX: very likely not all of these are needed */ |
||
732 | intel_encoder->hot_plug = intel_dsi_hot_plug; |
||
733 | intel_encoder->compute_config = intel_dsi_compute_config; |
||
734 | intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable; |
||
735 | intel_encoder->pre_enable = intel_dsi_pre_enable; |
||
5060 | serge | 736 | intel_encoder->enable = intel_dsi_enable_nop; |
737 | intel_encoder->disable = intel_dsi_pre_disable; |
||
4560 | Serge | 738 | intel_encoder->post_disable = intel_dsi_post_disable; |
739 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; |
||
740 | intel_encoder->get_config = intel_dsi_get_config; |
||
741 | |||
742 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
||
5060 | serge | 743 | intel_connector->unregister = intel_connector_unregister; |
4560 | Serge | 744 | |
745 | for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) { |
||
746 | dsi = &intel_dsi_devices[i]; |
||
747 | intel_dsi->dev = *dsi; |
||
748 | |||
749 | if (dsi->dev_ops->init(&intel_dsi->dev)) |
||
750 | break; |
||
751 | } |
||
752 | |||
753 | if (i == ARRAY_SIZE(intel_dsi_devices)) { |
||
754 | DRM_DEBUG_KMS("no device found\n"); |
||
755 | goto err; |
||
756 | } |
||
757 | |||
758 | intel_encoder->type = INTEL_OUTPUT_DSI; |
||
759 | intel_encoder->crtc_mask = (1 << 0); /* XXX */ |
||
760 | |||
5060 | serge | 761 | intel_encoder->cloneable = 0; |
4560 | Serge | 762 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, |
763 | DRM_MODE_CONNECTOR_DSI); |
||
764 | |||
765 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); |
||
766 | |||
767 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ |
||
768 | connector->interlace_allowed = false; |
||
769 | connector->doublescan_allowed = false; |
||
770 | |||
771 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
||
772 | |||
5060 | serge | 773 | drm_connector_register(connector); |
4560 | Serge | 774 | |
775 | fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev); |
||
776 | if (!fixed_mode) { |
||
777 | DRM_DEBUG_KMS("no fixed mode\n"); |
||
778 | goto err; |
||
779 | } |
||
780 | |||
781 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
||
5060 | serge | 782 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
4560 | Serge | 783 | |
5060 | serge | 784 | return; |
4560 | Serge | 785 | |
786 | err: |
||
787 | drm_encoder_cleanup(&intel_encoder->base); |
||
788 | kfree(intel_dsi); |
||
789 | kfree(intel_connector); |
||
790 | }><>>><>><>><>><>><>><>><>=> |