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Rev | Author | Line No. | Line |
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2326 | Serge | 1 | /* |
2 | * Copyright (c) 2006 Dave Airlie |
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3 | * Copyright (c) 2007-2008 Intel Corporation |
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4 | * Jesse Barnes |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice (including the next |
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14 | * paragraph) shall be included in all copies or substantial portions of the |
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15 | * Software. |
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16 | * |
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17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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23 | * IN THE SOFTWARE. |
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24 | */ |
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25 | #ifndef __INTEL_DRV_H__ |
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26 | #define __INTEL_DRV_H__ |
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27 | |||
5354 | serge | 28 | #include |
2326 | Serge | 29 | #include |
4104 | Serge | 30 | #include |
3031 | serge | 31 | #include |
2326 | Serge | 32 | #include "i915_drv.h" |
3031 | serge | 33 | #include |
34 | #include |
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35 | #include |
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7144 | serge | 36 | #include |
5060 | serge | 37 | #include |
5354 | serge | 38 | #include |
6084 | serge | 39 | #include |
2326 | Serge | 40 | |
3746 | Serge | 41 | /** |
42 | * _wait_for - magic (register) wait macro |
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43 | * |
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44 | * Does the right thing for modeset paths when run under kdgb or similar atomic |
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45 | * contexts. Note that it's important that we check the condition again after |
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46 | * having timed out, since the timeout could be due to preemption or similar and |
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47 | * we've never had a chance to check the condition before the timeout. |
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48 | */ |
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2326 | Serge | 49 | #define _wait_for(COND, MS, W) ({ \ |
5060 | serge | 50 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ |
2326 | Serge | 51 | int ret__ = 0; \ |
2342 | Serge | 52 | while (!(COND)) { \ |
5060 | serge | 53 | if (time_after(jiffies, timeout__)) { \ |
3746 | Serge | 54 | if (!(COND)) \ |
6084 | serge | 55 | ret__ = -ETIMEDOUT; \ |
2326 | Serge | 56 | break; \ |
57 | } \ |
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3031 | serge | 58 | if (W ) { \ |
59 | msleep(W); \ |
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60 | } else { \ |
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61 | cpu_relax(); \ |
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62 | } \ |
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2326 | Serge | 63 | } \ |
64 | ret__; \ |
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65 | }) |
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66 | |||
67 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
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68 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) |
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4104 | Serge | 69 | #define wait_for_atomic_us(COND, US) _wait_for((COND), \ |
70 | DIV_ROUND_UP((US), 1000), 0) |
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2326 | Serge | 71 | |
4560 | Serge | 72 | #define KHz(x) (1000 * (x)) |
73 | #define MHz(x) KHz(1000 * (x)) |
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2326 | Serge | 74 | |
75 | /* |
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76 | * Display related stuff |
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77 | */ |
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78 | |||
79 | /* store information about an Ixxx DVO */ |
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80 | /* The i830->i865 use multiple DVOs with multiple i2cs */ |
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81 | /* the i915, i945 have a single sDVO i2c bus - which is different */ |
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82 | #define MAX_OUTPUTS 6 |
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83 | /* maximum connectors per crtcs in the mode set */ |
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84 | |||
5060 | serge | 85 | /* Maximum cursor sizes */ |
86 | #define GEN2_CURSOR_WIDTH 64 |
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87 | #define GEN2_CURSOR_HEIGHT 64 |
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88 | #define MAX_CURSOR_WIDTH 256 |
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89 | #define MAX_CURSOR_HEIGHT 256 |
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90 | |||
2326 | Serge | 91 | #define INTEL_I2C_BUS_DVO 1 |
92 | #define INTEL_I2C_BUS_SDVO 2 |
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93 | |||
94 | /* these are outputs from the chip - integrated only |
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95 | external chips are via DVO or SDVO output */ |
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5354 | serge | 96 | enum intel_output_type { |
97 | INTEL_OUTPUT_UNUSED = 0, |
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98 | INTEL_OUTPUT_ANALOG = 1, |
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99 | INTEL_OUTPUT_DVO = 2, |
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100 | INTEL_OUTPUT_SDVO = 3, |
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101 | INTEL_OUTPUT_LVDS = 4, |
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102 | INTEL_OUTPUT_TVOUT = 5, |
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103 | INTEL_OUTPUT_HDMI = 6, |
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104 | INTEL_OUTPUT_DISPLAYPORT = 7, |
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105 | INTEL_OUTPUT_EDP = 8, |
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106 | INTEL_OUTPUT_DSI = 9, |
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107 | INTEL_OUTPUT_UNKNOWN = 10, |
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108 | INTEL_OUTPUT_DP_MST = 11, |
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109 | }; |
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2326 | Serge | 110 | |
111 | #define INTEL_DVO_CHIP_NONE 0 |
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112 | #define INTEL_DVO_CHIP_LVDS 1 |
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113 | #define INTEL_DVO_CHIP_TMDS 2 |
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114 | #define INTEL_DVO_CHIP_TVOUT 4 |
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115 | |||
5060 | serge | 116 | #define INTEL_DSI_VIDEO_MODE 0 |
117 | #define INTEL_DSI_COMMAND_MODE 1 |
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4560 | Serge | 118 | |
2326 | Serge | 119 | struct intel_framebuffer { |
120 | struct drm_framebuffer base; |
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6320 | serge | 121 | struct drm_i915_gem_object *obj; |
6935 | serge | 122 | void *private; /*Kolibri */ |
2326 | Serge | 123 | }; |
124 | |||
125 | struct intel_fbdev { |
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126 | struct drm_fb_helper helper; |
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5060 | serge | 127 | struct intel_framebuffer *fb; |
128 | int preferred_bpp; |
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2326 | Serge | 129 | }; |
130 | |||
131 | struct intel_encoder { |
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132 | struct drm_encoder base; |
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3031 | serge | 133 | |
5354 | serge | 134 | enum intel_output_type type; |
5060 | serge | 135 | unsigned int cloneable; |
2326 | Serge | 136 | void (*hot_plug)(struct intel_encoder *); |
3746 | Serge | 137 | bool (*compute_config)(struct intel_encoder *, |
6084 | serge | 138 | struct intel_crtc_state *); |
3480 | Serge | 139 | void (*pre_pll_enable)(struct intel_encoder *); |
3031 | serge | 140 | void (*pre_enable)(struct intel_encoder *); |
141 | void (*enable)(struct intel_encoder *); |
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3746 | Serge | 142 | void (*mode_set)(struct intel_encoder *intel_encoder); |
3031 | serge | 143 | void (*disable)(struct intel_encoder *); |
144 | void (*post_disable)(struct intel_encoder *); |
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6084 | serge | 145 | void (*post_pll_disable)(struct intel_encoder *); |
3031 | serge | 146 | /* Read out the current hw state of this connector, returning true if |
147 | * the encoder is active. If the encoder is enabled it also set the pipe |
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148 | * it is connected to in the pipe parameter. */ |
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149 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); |
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4104 | Serge | 150 | /* Reconstructs the equivalent mode flags for the current hardware |
151 | * state. This must be called _after_ display->get_pipe_config has |
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152 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
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153 | * be set correctly before calling this function. */ |
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154 | void (*get_config)(struct intel_encoder *, |
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6084 | serge | 155 | struct intel_crtc_state *pipe_config); |
5060 | serge | 156 | /* |
157 | * Called during system suspend after all pending requests for the |
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158 | * encoder are flushed (for example for DP AUX transactions) and |
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159 | * device interrupts are disabled. |
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160 | */ |
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161 | void (*suspend)(struct intel_encoder *); |
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2326 | Serge | 162 | int crtc_mask; |
3746 | Serge | 163 | enum hpd_pin hpd_pin; |
2326 | Serge | 164 | }; |
165 | |||
3243 | Serge | 166 | struct intel_panel { |
167 | struct drm_display_mode *fixed_mode; |
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4560 | Serge | 168 | struct drm_display_mode *downclock_mode; |
3243 | Serge | 169 | int fitting_mode; |
4560 | Serge | 170 | |
171 | /* backlight */ |
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172 | struct { |
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173 | bool present; |
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174 | u32 level; |
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5060 | serge | 175 | u32 min; |
4560 | Serge | 176 | u32 max; |
177 | bool enabled; |
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178 | bool combination_mode; /* gen 2/4 only */ |
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179 | bool active_low_pwm; |
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6084 | serge | 180 | |
181 | /* PWM chip */ |
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182 | bool util_pin_active_low; /* bxt+ */ |
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183 | u8 controller; /* bxt+ only */ |
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184 | struct pwm_device *pwm; |
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185 | |||
4560 | Serge | 186 | struct backlight_device *device; |
6084 | serge | 187 | |
188 | /* Connector and platform specific backlight functions */ |
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189 | int (*setup)(struct intel_connector *connector, enum pipe pipe); |
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190 | uint32_t (*get)(struct intel_connector *connector); |
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191 | void (*set)(struct intel_connector *connector, uint32_t level); |
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192 | void (*disable)(struct intel_connector *connector); |
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193 | void (*enable)(struct intel_connector *connector); |
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194 | uint32_t (*hz_to_pwm)(struct intel_connector *connector, |
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195 | uint32_t hz); |
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196 | void (*power)(struct intel_connector *, bool enable); |
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4560 | Serge | 197 | } backlight; |
3243 | Serge | 198 | }; |
199 | |||
2326 | Serge | 200 | struct intel_connector { |
201 | struct drm_connector base; |
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3031 | serge | 202 | /* |
203 | * The fixed encoder this connector is connected to. |
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204 | */ |
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2326 | Serge | 205 | struct intel_encoder *encoder; |
3031 | serge | 206 | |
207 | /* Reads out the current hw, returning true if the connector is enabled |
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208 | * and active (i.e. dpms ON state). */ |
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209 | bool (*get_hw_state)(struct intel_connector *); |
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3243 | Serge | 210 | |
5060 | serge | 211 | /* |
212 | * Removes all interfaces through which the connector is accessible |
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213 | * - like sysfs, debugfs entries -, so that no new operations can be |
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214 | * started on the connector. Also makes sure all currently pending |
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215 | * operations finish before returing. |
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216 | */ |
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217 | void (*unregister)(struct intel_connector *); |
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218 | |||
3243 | Serge | 219 | /* Panel info for eDP and LVDS */ |
220 | struct intel_panel panel; |
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221 | |||
222 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ |
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223 | struct edid *edid; |
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5354 | serge | 224 | struct edid *detect_edid; |
3746 | Serge | 225 | |
226 | /* since POLL and HPD connectors may use the same HPD line keep the native |
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227 | state of connector->polled in case hotplug storm detection changes it */ |
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228 | u8 polled; |
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5060 | serge | 229 | |
230 | void *port; /* store this opaque as its illegal to dereference it */ |
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231 | |||
232 | struct intel_dp *mst_port; |
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2326 | Serge | 233 | }; |
234 | |||
4104 | Serge | 235 | typedef struct dpll { |
236 | /* given values */ |
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237 | int n; |
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238 | int m1, m2; |
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239 | int p1, p2; |
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240 | /* derived values */ |
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241 | int dot; |
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242 | int vco; |
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243 | int m; |
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244 | int p; |
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245 | } intel_clock_t; |
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246 | |||
6084 | serge | 247 | struct intel_atomic_state { |
248 | struct drm_atomic_state base; |
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249 | |||
250 | unsigned int cdclk; |
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7144 | serge | 251 | |
252 | /* |
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253 | * Calculated device cdclk, can be different from cdclk |
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254 | * only when all crtc's are DPMS off. |
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255 | */ |
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256 | unsigned int dev_cdclk; |
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257 | |||
258 | bool dpll_set, modeset; |
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259 | |||
260 | unsigned int active_crtcs; |
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261 | unsigned int min_pixclk[I915_MAX_PIPES]; |
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262 | |||
6084 | serge | 263 | struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS]; |
6937 | serge | 264 | struct intel_wm_config wm_config; |
6084 | serge | 265 | }; |
266 | |||
5354 | serge | 267 | struct intel_plane_state { |
6084 | serge | 268 | struct drm_plane_state base; |
5354 | serge | 269 | struct drm_rect src; |
270 | struct drm_rect dst; |
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271 | struct drm_rect clip; |
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272 | bool visible; |
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6084 | serge | 273 | |
274 | /* |
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275 | * scaler_id |
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276 | * = -1 : not using a scaler |
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277 | * >= 0 : using a scalers |
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278 | * |
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279 | * plane requiring a scaler: |
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280 | * - During check_plane, its bit is set in |
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281 | * crtc_state->scaler_state.scaler_users by calling helper function |
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282 | * update_scaler_plane. |
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283 | * - scaler_id indicates the scaler it got assigned. |
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284 | * |
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285 | * plane doesn't require a scaler: |
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286 | * - this can happen when scaling is no more required or plane simply |
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287 | * got disabled. |
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288 | * - During check_plane, corresponding bit is reset in |
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289 | * crtc_state->scaler_state.scaler_users by calling helper function |
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290 | * update_scaler_plane. |
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291 | */ |
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292 | int scaler_id; |
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293 | |||
294 | struct drm_intel_sprite_colorkey ckey; |
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6937 | serge | 295 | |
296 | /* async flip related structures */ |
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297 | struct drm_i915_gem_request *wait_req; |
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5354 | serge | 298 | }; |
299 | |||
6084 | serge | 300 | struct intel_initial_plane_config { |
301 | struct intel_framebuffer *fb; |
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302 | unsigned int tiling; |
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5060 | serge | 303 | int size; |
304 | u32 base; |
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305 | }; |
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306 | |||
6084 | serge | 307 | #define SKL_MIN_SRC_W 8 |
308 | #define SKL_MAX_SRC_W 4096 |
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309 | #define SKL_MIN_SRC_H 8 |
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310 | #define SKL_MAX_SRC_H 4096 |
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311 | #define SKL_MIN_DST_W 8 |
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312 | #define SKL_MAX_DST_W 4096 |
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313 | #define SKL_MIN_DST_H 8 |
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314 | #define SKL_MAX_DST_H 4096 |
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315 | |||
316 | struct intel_scaler { |
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317 | int in_use; |
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318 | uint32_t mode; |
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319 | }; |
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320 | |||
321 | struct intel_crtc_scaler_state { |
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322 | #define SKL_NUM_SCALERS 2 |
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323 | struct intel_scaler scalers[SKL_NUM_SCALERS]; |
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324 | |||
325 | /* |
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326 | * scaler_users: keeps track of users requesting scalers on this crtc. |
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327 | * |
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328 | * If a bit is set, a user is using a scaler. |
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329 | * Here user can be a plane or crtc as defined below: |
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330 | * bits 0-30 - plane (bit position is index from drm_plane_index) |
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331 | * bit 31 - crtc |
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332 | * |
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333 | * Instead of creating a new index to cover planes and crtc, using |
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334 | * existing drm_plane_index for planes which is well less than 31 |
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335 | * planes and bit 31 for crtc. This should be fine to cover all |
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336 | * our platforms. |
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337 | * |
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338 | * intel_atomic_setup_scalers will setup available scalers to users |
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339 | * requesting scalers. It will gracefully fail if request exceeds |
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340 | * avilability. |
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341 | */ |
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342 | #define SKL_CRTC_INDEX 31 |
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343 | unsigned scaler_users; |
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344 | |||
345 | /* scaler used by crtc for panel fitting purpose */ |
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346 | int scaler_id; |
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347 | }; |
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348 | |||
349 | /* drm_mode->private_flags */ |
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350 | #define I915_MODE_FLAG_INHERITED 1 |
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351 | |||
6937 | serge | 352 | struct intel_pipe_wm { |
353 | struct intel_wm_level wm[5]; |
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354 | uint32_t linetime; |
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355 | bool fbc_wm_enabled; |
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356 | bool pipe_enabled; |
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357 | bool sprites_enabled; |
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358 | bool sprites_scaled; |
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359 | }; |
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360 | |||
361 | struct skl_pipe_wm { |
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362 | struct skl_wm_level wm[8]; |
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363 | struct skl_wm_level trans_wm; |
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364 | uint32_t linetime; |
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365 | }; |
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366 | |||
6084 | serge | 367 | struct intel_crtc_state { |
368 | struct drm_crtc_state base; |
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369 | |||
4104 | Serge | 370 | /** |
371 | * quirks - bitfield with hw state readout quirks |
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372 | * |
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373 | * For various reasons the hw state readout code might not be able to |
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374 | * completely faithfully read out the current state. These cases are |
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375 | * tracked with quirk flags so that fastboot and state checker can act |
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376 | * accordingly. |
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377 | */ |
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6084 | serge | 378 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ |
4104 | Serge | 379 | unsigned long quirks; |
380 | |||
6937 | serge | 381 | bool update_pipe; /* can a fast modeset be performed? */ |
382 | bool disable_cxsr; |
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383 | bool update_wm_pre, update_wm_post; /* watermarks are updated */ |
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7144 | serge | 384 | bool fb_changed; /* fb on any of the planes is changed */ |
4560 | Serge | 385 | |
386 | /* Pipe source size (ie. panel fitter input size) |
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387 | * All planes will be positioned inside this space, |
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388 | * and get clipped at the edges. */ |
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389 | int pipe_src_w, pipe_src_h; |
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390 | |||
3746 | Serge | 391 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
392 | * between pch encoders and cpu encoders. */ |
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393 | bool has_pch_encoder; |
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394 | |||
5354 | serge | 395 | /* Are we sending infoframes on the attached port */ |
396 | bool has_infoframe; |
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397 | |||
3746 | Serge | 398 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
399 | * pipe on Haswell (where we have a special eDP transcoder). */ |
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400 | enum transcoder cpu_transcoder; |
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401 | |||
402 | /* |
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403 | * Use reduced/limited/broadcast rbg range, compressing from the full |
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404 | * range fed into the crtcs. |
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405 | */ |
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406 | bool limited_color_range; |
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407 | |||
408 | /* DP has a bunch of special case unfortunately, so mark the pipe |
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409 | * accordingly. */ |
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410 | bool has_dp_encoder; |
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4104 | Serge | 411 | |
6937 | serge | 412 | /* DSI has special cases */ |
413 | bool has_dsi_encoder; |
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414 | |||
5060 | serge | 415 | /* Whether we should send NULL infoframes. Required for audio. */ |
416 | bool has_hdmi_sink; |
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417 | |||
418 | /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or |
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419 | * has_dp_encoder is set. */ |
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420 | bool has_audio; |
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421 | |||
4104 | Serge | 422 | /* |
423 | * Enable dithering, used when the selected pipe bpp doesn't match the |
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424 | * plane bpp. |
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425 | */ |
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3746 | Serge | 426 | bool dither; |
427 | |||
428 | /* Controls for the clock computation, to override various stages. */ |
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429 | bool clock_set; |
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430 | |||
4104 | Serge | 431 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
432 | * work correctly, we need to track this at runtime.*/ |
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433 | bool sdvo_tv_clock; |
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434 | |||
435 | /* |
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436 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really |
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437 | * required. This is set in the 2nd loop of calling encoder's |
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438 | * ->compute_config if the first pick doesn't work out. |
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439 | */ |
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440 | bool bw_constrained; |
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441 | |||
3746 | Serge | 442 | /* Settings for the intel dpll used on pretty much everything but |
443 | * haswell. */ |
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4104 | Serge | 444 | struct dpll dpll; |
3746 | Serge | 445 | |
4104 | Serge | 446 | /* Selected dpll when shared or DPLL_ID_PRIVATE. */ |
447 | enum intel_dpll_id shared_dpll; |
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448 | |||
5354 | serge | 449 | /* |
450 | * - PORT_CLK_SEL for DDI ports on HSW/BDW. |
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451 | * - enum skl_dpll on SKL |
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452 | */ |
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5060 | serge | 453 | uint32_t ddi_pll_sel; |
454 | |||
4104 | Serge | 455 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
456 | struct intel_dpll_hw_state dpll_hw_state; |
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457 | |||
3746 | Serge | 458 | int pipe_bpp; |
459 | struct intel_link_m_n dp_m_n; |
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4104 | Serge | 460 | |
5060 | serge | 461 | /* m2_n2 for eDP downclock */ |
462 | struct intel_link_m_n dp_m2_n2; |
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5354 | serge | 463 | bool has_drrs; |
5060 | serge | 464 | |
4104 | Serge | 465 | /* |
466 | * Frequence the dpll for the port should run at. Differs from the |
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4560 | Serge | 467 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
468 | * already multiplied by pixel_multiplier. |
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3746 | Serge | 469 | */ |
4104 | Serge | 470 | int port_clock; |
471 | |||
3746 | Serge | 472 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
473 | unsigned pixel_multiplier; |
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4104 | Serge | 474 | |
6084 | serge | 475 | uint8_t lane_count; |
476 | |||
4104 | Serge | 477 | /* Panel fitter controls for gen2-gen4 + VLV */ |
478 | struct { |
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479 | u32 control; |
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480 | u32 pgm_ratios; |
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481 | u32 lvds_border_bits; |
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482 | } gmch_pfit; |
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483 | |||
484 | /* Panel fitter placement and size for Ironlake+ */ |
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485 | struct { |
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486 | u32 pos; |
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487 | u32 size; |
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488 | bool enabled; |
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5060 | serge | 489 | bool force_thru; |
4104 | Serge | 490 | } pch_pfit; |
491 | |||
492 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
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493 | int fdi_lanes; |
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494 | struct intel_link_m_n fdi_m_n; |
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495 | |||
496 | bool ips_enabled; |
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4560 | Serge | 497 | |
7144 | serge | 498 | bool enable_fbc; |
499 | |||
4560 | Serge | 500 | bool double_wide; |
5060 | serge | 501 | |
502 | bool dp_encoder_is_mst; |
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503 | int pbn; |
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6084 | serge | 504 | |
505 | struct intel_crtc_scaler_state scaler_state; |
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506 | |||
507 | /* w/a for waiting 2 vblanks during crtc enable */ |
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508 | enum pipe hsw_workaround_pipe; |
||
6937 | serge | 509 | |
510 | /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */ |
||
511 | bool disable_lp_wm; |
||
512 | |||
513 | struct { |
||
514 | /* |
||
515 | * optimal watermarks, programmed post-vblank when this state |
||
516 | * is committed |
||
517 | */ |
||
518 | union { |
||
519 | struct intel_pipe_wm ilk; |
||
520 | struct skl_pipe_wm skl; |
||
521 | } optimal; |
||
522 | } wm; |
||
3746 | Serge | 523 | }; |
524 | |||
6084 | serge | 525 | struct vlv_wm_state { |
526 | struct vlv_pipe_wm wm[3]; |
||
527 | struct vlv_sr_wm sr[3]; |
||
528 | uint8_t num_active_planes; |
||
529 | uint8_t num_levels; |
||
530 | uint8_t level; |
||
531 | bool cxsr; |
||
532 | }; |
||
533 | |||
5060 | serge | 534 | struct intel_mmio_flip { |
5354 | serge | 535 | struct work_struct work; |
6084 | serge | 536 | struct drm_i915_private *i915; |
537 | struct drm_i915_gem_request *req; |
||
538 | struct intel_crtc *crtc; |
||
6937 | serge | 539 | unsigned int rotation; |
5060 | serge | 540 | }; |
541 | |||
6084 | serge | 542 | /* |
543 | * Tracking of operations that need to be performed at the beginning/end of an |
||
544 | * atomic commit, outside the atomic section where interrupts are disabled. |
||
545 | * These are generally operations that grab mutexes or might otherwise sleep |
||
546 | * and thus can't be run with interrupts disabled. |
||
547 | */ |
||
548 | struct intel_crtc_atomic_commit { |
||
549 | /* Sleepable operations to perform before commit */ |
||
550 | |||
551 | /* Sleepable operations to perform after commit */ |
||
552 | unsigned fb_bits; |
||
7144 | serge | 553 | bool post_enable_primary; |
554 | |||
555 | /* Sleepable operations to perform before and after commit */ |
||
6084 | serge | 556 | bool update_fbc; |
557 | }; |
||
558 | |||
2326 | Serge | 559 | struct intel_crtc { |
560 | struct drm_crtc base; |
||
561 | enum pipe pipe; |
||
562 | enum plane plane; |
||
563 | u8 lut_r[256], lut_g[256], lut_b[256]; |
||
3031 | serge | 564 | /* |
565 | * Whether the crtc and the connected output pipeline is active. Implies |
||
566 | * that crtc->enabled is set, i.e. the current mode configuration has |
||
567 | * some outputs connected to this crtc. |
||
568 | */ |
||
569 | bool active; |
||
4560 | Serge | 570 | unsigned long enabled_power_domains; |
2326 | Serge | 571 | bool lowfreq_avail; |
572 | struct intel_overlay *overlay; |
||
573 | struct intel_unpin_work *unpin_work; |
||
574 | |||
3243 | Serge | 575 | atomic_t unpin_work_count; |
576 | |||
3031 | serge | 577 | /* Display surface base address adjustement for pageflips. Note that on |
578 | * gen4+ this only adjusts up to a tile, offsets within a tile are |
||
579 | * handled in the hw itself (with the TILEOFF register). */ |
||
7144 | serge | 580 | u32 dspaddr_offset; |
6084 | serge | 581 | int adjusted_x; |
582 | int adjusted_y; |
||
3031 | serge | 583 | |
2326 | Serge | 584 | uint32_t cursor_addr; |
5060 | serge | 585 | uint32_t cursor_cntl; |
5354 | serge | 586 | uint32_t cursor_size; |
5060 | serge | 587 | uint32_t cursor_base; |
2342 | Serge | 588 | |
6084 | serge | 589 | struct intel_crtc_state *config; |
3746 | Serge | 590 | |
3480 | Serge | 591 | /* reset counter value when the last flip was submitted */ |
592 | unsigned int reset_counter; |
||
4104 | Serge | 593 | |
594 | /* Access to these should be protected by dev_priv->irq_lock. */ |
||
595 | bool cpu_fifo_underrun_disabled; |
||
596 | bool pch_fifo_underrun_disabled; |
||
4560 | Serge | 597 | |
598 | /* per-pipe watermark state */ |
||
599 | struct { |
||
600 | /* watermarks currently being used */ |
||
6937 | serge | 601 | union { |
602 | struct intel_pipe_wm ilk; |
||
603 | struct skl_pipe_wm skl; |
||
604 | } active; |
||
6084 | serge | 605 | /* allow CxSR on this pipe */ |
606 | bool cxsr_allowed; |
||
4560 | Serge | 607 | } wm; |
5060 | serge | 608 | |
609 | int scanline_offset; |
||
6084 | serge | 610 | |
611 | struct { |
||
612 | unsigned start_vbl_count; |
||
613 | ktime_t start_vbl_time; |
||
614 | int min_vbl, max_vbl; |
||
615 | int scanline_start; |
||
616 | } debug; |
||
617 | |||
618 | struct intel_crtc_atomic_commit atomic; |
||
619 | |||
620 | /* scalers available on this crtc */ |
||
621 | int num_scalers; |
||
622 | |||
623 | struct vlv_wm_state wm_state; |
||
2326 | Serge | 624 | }; |
625 | |||
4104 | Serge | 626 | struct intel_plane_wm_parameters { |
627 | uint32_t horiz_pixels; |
||
5060 | serge | 628 | uint32_t vert_pixels; |
6084 | serge | 629 | /* |
630 | * For packed pixel formats: |
||
631 | * bytes_per_pixel - holds bytes per pixel |
||
632 | * For planar pixel formats: |
||
633 | * bytes_per_pixel - holds bytes per pixel for uv-plane |
||
634 | * y_bytes_per_pixel - holds bytes per pixel for y-plane |
||
635 | */ |
||
4104 | Serge | 636 | uint8_t bytes_per_pixel; |
6084 | serge | 637 | uint8_t y_bytes_per_pixel; |
4104 | Serge | 638 | bool enabled; |
639 | bool scaled; |
||
6084 | serge | 640 | u64 tiling; |
641 | unsigned int rotation; |
||
642 | uint16_t fifo_size; |
||
4104 | Serge | 643 | }; |
644 | |||
2342 | Serge | 645 | struct intel_plane { |
646 | struct drm_plane base; |
||
3746 | Serge | 647 | int plane; |
2342 | Serge | 648 | enum pipe pipe; |
3243 | Serge | 649 | bool can_scale; |
2342 | Serge | 650 | int max_downscale; |
6084 | serge | 651 | uint32_t frontbuffer_bit; |
4104 | Serge | 652 | |
653 | /* Since we need to change the watermarks before/after |
||
654 | * enabling/disabling the planes, we need to store the parameters here |
||
655 | * as the other pieces of the struct may not reflect the values we want |
||
656 | * for the watermark calculations. Currently only Haswell uses this. |
||
657 | */ |
||
658 | struct intel_plane_wm_parameters wm; |
||
659 | |||
6084 | serge | 660 | /* |
661 | * NOTE: Do not place new plane state fields here (e.g., when adding |
||
662 | * new plane properties). New runtime state should now be placed in |
||
7144 | serge | 663 | * the intel_plane_state structure and accessed via plane_state. |
6084 | serge | 664 | */ |
665 | |||
2342 | Serge | 666 | void (*update_plane)(struct drm_plane *plane, |
7144 | serge | 667 | const struct intel_crtc_state *crtc_state, |
668 | const struct intel_plane_state *plane_state); |
||
4104 | Serge | 669 | void (*disable_plane)(struct drm_plane *plane, |
670 | struct drm_crtc *crtc); |
||
6084 | serge | 671 | int (*check_plane)(struct drm_plane *plane, |
672 | struct intel_crtc_state *crtc_state, |
||
673 | struct intel_plane_state *state); |
||
2342 | Serge | 674 | }; |
675 | |||
3031 | serge | 676 | struct intel_watermark_params { |
677 | unsigned long fifo_size; |
||
678 | unsigned long max_wm; |
||
679 | unsigned long default_wm; |
||
680 | unsigned long guard_size; |
||
681 | unsigned long cacheline_size; |
||
682 | }; |
||
683 | |||
684 | struct cxsr_latency { |
||
685 | int is_desktop; |
||
686 | int is_ddr3; |
||
687 | unsigned long fsb_freq; |
||
688 | unsigned long mem_freq; |
||
689 | unsigned long display_sr; |
||
690 | unsigned long display_hpll_disable; |
||
691 | unsigned long cursor_sr; |
||
692 | unsigned long cursor_hpll_disable; |
||
693 | }; |
||
694 | |||
6084 | serge | 695 | #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base) |
2326 | Serge | 696 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
6084 | serge | 697 | #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base) |
2326 | Serge | 698 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
699 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
||
700 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
||
2342 | Serge | 701 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
6084 | serge | 702 | #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base) |
5060 | serge | 703 | #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL) |
2326 | Serge | 704 | |
3031 | serge | 705 | struct intel_hdmi { |
6937 | serge | 706 | i915_reg_t hdmi_reg; |
3031 | serge | 707 | int ddc_bus; |
7144 | serge | 708 | struct { |
709 | enum drm_dp_dual_mode_type type; |
||
710 | int max_tmds_clock; |
||
711 | } dp_dual_mode; |
||
6084 | serge | 712 | bool limited_color_range; |
3480 | Serge | 713 | bool color_range_auto; |
3031 | serge | 714 | bool has_hdmi_sink; |
715 | bool has_audio; |
||
716 | enum hdmi_force_audio force_audio; |
||
3480 | Serge | 717 | bool rgb_quant_range_selectable; |
5060 | serge | 718 | enum hdmi_picture_aspect aspect_ratio; |
6084 | serge | 719 | struct intel_connector *attached_connector; |
3031 | serge | 720 | void (*write_infoframe)(struct drm_encoder *encoder, |
4104 | Serge | 721 | enum hdmi_infoframe_type type, |
4560 | Serge | 722 | const void *frame, ssize_t len); |
3031 | serge | 723 | void (*set_infoframes)(struct drm_encoder *encoder, |
5060 | serge | 724 | bool enable, |
6084 | serge | 725 | const struct drm_display_mode *adjusted_mode); |
6937 | serge | 726 | bool (*infoframe_enabled)(struct drm_encoder *encoder, |
727 | const struct intel_crtc_state *pipe_config); |
||
3031 | serge | 728 | }; |
729 | |||
5060 | serge | 730 | struct intel_dp_mst_encoder; |
3031 | serge | 731 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
732 | |||
6084 | serge | 733 | /* |
734 | * enum link_m_n_set: |
||
735 | * When platform provides two set of M_N registers for dp, we can |
||
736 | * program them and switch between them incase of DRRS. |
||
737 | * But When only one such register is provided, we have to program the |
||
738 | * required divider value on that registers itself based on the DRRS state. |
||
739 | * |
||
740 | * M1_N1 : Program dp_m_n on M1_N1 registers |
||
741 | * dp_m2_n2 on M2_N2 registers (If supported) |
||
742 | * |
||
743 | * M2_N2 : Program dp_m2_n2 on M1_N1 registers |
||
744 | * M2_N2 registers are not supported |
||
5060 | serge | 745 | */ |
6084 | serge | 746 | |
747 | enum link_m_n_set { |
||
748 | /* Sets the m1_n1 and m2_n2 */ |
||
749 | M1_N1 = 0, |
||
750 | M2_N2 |
||
5060 | serge | 751 | }; |
752 | |||
3031 | serge | 753 | struct intel_dp { |
6937 | serge | 754 | i915_reg_t output_reg; |
755 | i915_reg_t aux_ch_ctl_reg; |
||
756 | i915_reg_t aux_ch_data_reg[5]; |
||
3031 | serge | 757 | uint32_t DP; |
6084 | serge | 758 | int link_rate; |
759 | uint8_t lane_count; |
||
3031 | serge | 760 | bool has_audio; |
761 | enum hdmi_force_audio force_audio; |
||
6084 | serge | 762 | bool limited_color_range; |
3480 | Serge | 763 | bool color_range_auto; |
3031 | serge | 764 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
4104 | Serge | 765 | uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
3031 | serge | 766 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
6084 | serge | 767 | /* sink rates as reported by DP_SUPPORTED_LINK_RATES */ |
768 | uint8_t num_sink_rates; |
||
769 | int sink_rates[DP_MAX_SUPPORTED_RATES]; |
||
5060 | serge | 770 | struct drm_dp_aux aux; |
3031 | serge | 771 | uint8_t train_set[4]; |
772 | int panel_power_up_delay; |
||
773 | int panel_power_down_delay; |
||
774 | int panel_power_cycle_delay; |
||
775 | int backlight_on_delay; |
||
776 | int backlight_off_delay; |
||
777 | struct delayed_work panel_vdd_work; |
||
778 | bool want_panel_vdd; |
||
5060 | serge | 779 | unsigned long last_power_on; |
780 | unsigned long last_backlight_off; |
||
7144 | serge | 781 | ktime_t panel_power_off_time; |
5060 | serge | 782 | |
6937 | serge | 783 | struct notifier_block edp_notifier; |
784 | |||
5354 | serge | 785 | /* |
786 | * Pipe whose power sequencer is currently locked into |
||
787 | * this port. Only relevant on VLV/CHV. |
||
788 | */ |
||
789 | enum pipe pps_pipe; |
||
790 | struct edp_power_seq pps_delays; |
||
791 | |||
5060 | serge | 792 | bool can_mst; /* this port supports mst */ |
793 | bool is_mst; |
||
794 | int active_mst_links; |
||
795 | /* connector directly attached - won't be use for modeset in mst world */ |
||
3243 | Serge | 796 | struct intel_connector *attached_connector; |
5060 | serge | 797 | |
798 | /* mst connector list */ |
||
799 | struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; |
||
800 | struct drm_dp_mst_topology_mgr mst_mgr; |
||
801 | |||
802 | uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index); |
||
803 | /* |
||
804 | * This function returns the value we have to program the AUX_CTL |
||
805 | * register with to kick off an AUX transaction. |
||
806 | */ |
||
807 | uint32_t (*get_aux_send_ctl)(struct intel_dp *dp, |
||
808 | bool has_aux_irq, |
||
809 | int send_bytes, |
||
810 | uint32_t aux_clock_divider); |
||
811 | |||
6937 | serge | 812 | /* This is called before a link training is starterd */ |
813 | void (*prepare_link_retrain)(struct intel_dp *intel_dp); |
||
814 | |||
6084 | serge | 815 | /* Displayport compliance testing */ |
816 | unsigned long compliance_test_type; |
||
817 | unsigned long compliance_test_data; |
||
818 | bool compliance_test_active; |
||
3031 | serge | 819 | }; |
820 | |||
3243 | Serge | 821 | struct intel_digital_port { |
822 | struct intel_encoder base; |
||
823 | enum port port; |
||
4104 | Serge | 824 | u32 saved_port_bits; |
3243 | Serge | 825 | struct intel_dp dp; |
826 | struct intel_hdmi hdmi; |
||
6084 | serge | 827 | enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool); |
828 | bool release_cl2_override; |
||
7144 | serge | 829 | uint8_t max_lanes; |
6937 | serge | 830 | /* for communication with audio component; protected by av_mutex */ |
831 | const struct drm_connector *audio_connector; |
||
3243 | Serge | 832 | }; |
833 | |||
5060 | serge | 834 | struct intel_dp_mst_encoder { |
835 | struct intel_encoder base; |
||
836 | enum pipe pipe; |
||
837 | struct intel_digital_port *primary; |
||
838 | void *port; /* store this opaque as its illegal to dereference it */ |
||
839 | }; |
||
840 | |||
6084 | serge | 841 | static inline enum dpio_channel |
4104 | Serge | 842 | vlv_dport_to_channel(struct intel_digital_port *dport) |
843 | { |
||
844 | switch (dport->port) { |
||
845 | case PORT_B: |
||
5060 | serge | 846 | case PORT_D: |
4560 | Serge | 847 | return DPIO_CH0; |
4104 | Serge | 848 | case PORT_C: |
4560 | Serge | 849 | return DPIO_CH1; |
4104 | Serge | 850 | default: |
851 | BUG(); |
||
852 | } |
||
853 | } |
||
854 | |||
6084 | serge | 855 | static inline enum dpio_phy |
856 | vlv_dport_to_phy(struct intel_digital_port *dport) |
||
857 | { |
||
858 | switch (dport->port) { |
||
859 | case PORT_B: |
||
860 | case PORT_C: |
||
861 | return DPIO_PHY0; |
||
862 | case PORT_D: |
||
863 | return DPIO_PHY1; |
||
864 | default: |
||
865 | BUG(); |
||
866 | } |
||
867 | } |
||
868 | |||
869 | static inline enum dpio_channel |
||
5060 | serge | 870 | vlv_pipe_to_channel(enum pipe pipe) |
871 | { |
||
872 | switch (pipe) { |
||
873 | case PIPE_A: |
||
874 | case PIPE_C: |
||
875 | return DPIO_CH0; |
||
876 | case PIPE_B: |
||
877 | return DPIO_CH1; |
||
878 | default: |
||
879 | BUG(); |
||
880 | } |
||
881 | } |
||
882 | |||
2326 | Serge | 883 | static inline struct drm_crtc * |
884 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) |
||
885 | { |
||
886 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
887 | return dev_priv->pipe_to_crtc_mapping[pipe]; |
||
888 | } |
||
889 | |||
890 | static inline struct drm_crtc * |
||
891 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) |
||
892 | { |
||
893 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
894 | return dev_priv->plane_to_crtc_mapping[plane]; |
||
895 | } |
||
896 | |||
897 | struct intel_unpin_work { |
||
2360 | Serge | 898 | struct work_struct work; |
3243 | Serge | 899 | struct drm_crtc *crtc; |
6084 | serge | 900 | struct drm_framebuffer *old_fb; |
2326 | Serge | 901 | struct drm_i915_gem_object *pending_flip_obj; |
902 | struct drm_pending_vblank_event *event; |
||
3243 | Serge | 903 | atomic_t pending; |
904 | #define INTEL_FLIP_INACTIVE 0 |
||
905 | #define INTEL_FLIP_PENDING 1 |
||
906 | #define INTEL_FLIP_COMPLETE 2 |
||
5060 | serge | 907 | u32 flip_count; |
908 | u32 gtt_offset; |
||
6084 | serge | 909 | struct drm_i915_gem_request *flip_queued_req; |
910 | u32 flip_queued_vblank; |
||
911 | u32 flip_ready_vblank; |
||
2326 | Serge | 912 | bool enable_stall_check; |
913 | }; |
||
914 | |||
4560 | Serge | 915 | struct intel_load_detect_pipe { |
7144 | serge | 916 | struct drm_atomic_state *restore_state; |
4560 | Serge | 917 | }; |
2326 | Serge | 918 | |
4560 | Serge | 919 | static inline struct intel_encoder * |
920 | intel_attached_encoder(struct drm_connector *connector) |
||
2326 | Serge | 921 | { |
922 | return to_intel_connector(connector)->encoder; |
||
923 | } |
||
924 | |||
3243 | Serge | 925 | static inline struct intel_digital_port * |
926 | enc_to_dig_port(struct drm_encoder *encoder) |
||
927 | { |
||
928 | return container_of(encoder, struct intel_digital_port, base.base); |
||
929 | } |
||
930 | |||
5060 | serge | 931 | static inline struct intel_dp_mst_encoder * |
932 | enc_to_mst(struct drm_encoder *encoder) |
||
933 | { |
||
934 | return container_of(encoder, struct intel_dp_mst_encoder, base.base); |
||
935 | } |
||
936 | |||
4104 | Serge | 937 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
938 | { |
||
939 | return &enc_to_dig_port(encoder)->dp; |
||
940 | } |
||
941 | |||
3243 | Serge | 942 | static inline struct intel_digital_port * |
943 | dp_to_dig_port(struct intel_dp *intel_dp) |
||
944 | { |
||
945 | return container_of(intel_dp, struct intel_digital_port, dp); |
||
946 | } |
||
947 | |||
948 | static inline struct intel_digital_port * |
||
949 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) |
||
950 | { |
||
951 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); |
||
952 | } |
||
953 | |||
5354 | serge | 954 | /* |
955 | * Returns the number of planes for this pipe, ie the number of sprites + 1 |
||
956 | * (primary plane). This doesn't count the cursor plane then. |
||
957 | */ |
||
958 | static inline unsigned int intel_num_planes(struct intel_crtc *crtc) |
||
959 | { |
||
960 | return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1; |
||
961 | } |
||
4560 | Serge | 962 | |
5354 | serge | 963 | /* intel_fifo_underrun.c */ |
964 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
||
4560 | Serge | 965 | enum pipe pipe, bool enable); |
5354 | serge | 966 | bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
4560 | Serge | 967 | enum transcoder pch_transcoder, |
968 | bool enable); |
||
5354 | serge | 969 | void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
970 | enum pipe pipe); |
||
971 | void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
||
972 | enum transcoder pch_transcoder); |
||
6937 | serge | 973 | void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv); |
974 | void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv); |
||
5354 | serge | 975 | |
976 | /* i915_irq.c */ |
||
5060 | serge | 977 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
978 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
||
979 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
||
980 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
||
5354 | serge | 981 | void gen6_reset_rps_interrupts(struct drm_device *dev); |
982 | void gen6_enable_rps_interrupts(struct drm_device *dev); |
||
983 | void gen6_disable_rps_interrupts(struct drm_device *dev); |
||
6084 | serge | 984 | u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask); |
5354 | serge | 985 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); |
986 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); |
||
5060 | serge | 987 | static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) |
988 | { |
||
989 | /* |
||
990 | * We only use drm_irq_uninstall() at unload and VT switch, so |
||
991 | * this is the only thing we need to check. |
||
992 | */ |
||
5354 | serge | 993 | return dev_priv->pm.irqs_enabled; |
5060 | serge | 994 | } |
4560 | Serge | 995 | |
5060 | serge | 996 | int intel_get_crtc_scanline(struct intel_crtc *crtc); |
6084 | serge | 997 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, |
998 | unsigned int pipe_mask); |
||
7144 | serge | 999 | void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, |
1000 | unsigned int pipe_mask); |
||
4560 | Serge | 1001 | |
1002 | /* intel_crt.c */ |
||
1003 | void intel_crt_init(struct drm_device *dev); |
||
1004 | |||
1005 | |||
1006 | /* intel_ddi.c */ |
||
6937 | serge | 1007 | void intel_ddi_clk_select(struct intel_encoder *encoder, |
1008 | const struct intel_crtc_state *pipe_config); |
||
7144 | serge | 1009 | void intel_prepare_ddi_buffer(struct intel_encoder *encoder); |
4560 | Serge | 1010 | void hsw_fdi_link_train(struct drm_crtc *crtc); |
1011 | void intel_ddi_init(struct drm_device *dev, enum port port); |
||
1012 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); |
||
1013 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); |
||
1014 | void intel_ddi_pll_init(struct drm_device *dev); |
||
1015 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); |
||
1016 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
||
1017 | enum transcoder cpu_transcoder); |
||
1018 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); |
||
1019 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); |
||
6084 | serge | 1020 | bool intel_ddi_pll_select(struct intel_crtc *crtc, |
1021 | struct intel_crtc_state *crtc_state); |
||
4560 | Serge | 1022 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
6937 | serge | 1023 | void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp); |
4560 | Serge | 1024 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); |
1025 | void intel_ddi_fdi_disable(struct drm_crtc *crtc); |
||
1026 | void intel_ddi_get_config(struct intel_encoder *encoder, |
||
6084 | serge | 1027 | struct intel_crtc_state *pipe_config); |
1028 | struct intel_encoder * |
||
1029 | intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state); |
||
4560 | Serge | 1030 | |
5060 | serge | 1031 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder); |
1032 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
||
6084 | serge | 1033 | struct intel_crtc_state *pipe_config); |
5060 | serge | 1034 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state); |
6084 | serge | 1035 | uint32_t ddi_signal_levels(struct intel_dp *intel_dp); |
4560 | Serge | 1036 | |
5354 | serge | 1037 | /* intel_frontbuffer.c */ |
5060 | serge | 1038 | void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, |
6084 | serge | 1039 | enum fb_op_origin origin); |
5060 | serge | 1040 | void intel_frontbuffer_flip_prepare(struct drm_device *dev, |
1041 | unsigned frontbuffer_bits); |
||
1042 | void intel_frontbuffer_flip_complete(struct drm_device *dev, |
||
1043 | unsigned frontbuffer_bits); |
||
1044 | void intel_frontbuffer_flip(struct drm_device *dev, |
||
6084 | serge | 1045 | unsigned frontbuffer_bits); |
1046 | unsigned int intel_fb_align_height(struct drm_device *dev, |
||
1047 | unsigned int height, |
||
1048 | uint32_t pixel_format, |
||
1049 | uint64_t fb_format_modifier); |
||
1050 | void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire, |
||
1051 | enum fb_op_origin origin); |
||
7144 | serge | 1052 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
1053 | uint64_t fb_modifier, uint32_t pixel_format); |
||
5060 | serge | 1054 | |
5354 | serge | 1055 | /* intel_audio.c */ |
1056 | void intel_init_audio(struct drm_device *dev); |
||
1057 | void intel_audio_codec_enable(struct intel_encoder *encoder); |
||
1058 | void intel_audio_codec_disable(struct intel_encoder *encoder); |
||
6084 | serge | 1059 | void i915_audio_component_init(struct drm_i915_private *dev_priv); |
1060 | void i915_audio_component_cleanup(struct drm_i915_private *dev_priv); |
||
5354 | serge | 1061 | |
1062 | /* intel_display.c */ |
||
6084 | serge | 1063 | extern const struct drm_plane_funcs intel_plane_funcs; |
5354 | serge | 1064 | bool intel_has_pending_fb_unpin(struct drm_device *dev); |
1065 | int intel_pch_rawclk(struct drm_device *dev); |
||
6084 | serge | 1066 | int intel_hrawclk(struct drm_device *dev); |
5354 | serge | 1067 | void intel_mark_busy(struct drm_device *dev); |
4560 | Serge | 1068 | void intel_mark_idle(struct drm_device *dev); |
1069 | void intel_crtc_restore_mode(struct drm_crtc *crtc); |
||
6084 | serge | 1070 | int intel_display_suspend(struct drm_device *dev); |
4560 | Serge | 1071 | void intel_encoder_destroy(struct drm_encoder *encoder); |
6084 | serge | 1072 | int intel_connector_init(struct intel_connector *); |
1073 | struct intel_connector *intel_connector_alloc(void); |
||
4560 | Serge | 1074 | bool intel_connector_get_hw_state(struct intel_connector *connector); |
1075 | void intel_connector_attach_encoder(struct intel_connector *connector, |
||
6084 | serge | 1076 | struct intel_encoder *encoder); |
4560 | Serge | 1077 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector); |
1078 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
||
6084 | serge | 1079 | struct drm_crtc *crtc); |
4560 | Serge | 1080 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector); |
2326 | Serge | 1081 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
1082 | struct drm_file *file_priv); |
||
4560 | Serge | 1083 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
6084 | serge | 1084 | enum pipe pipe); |
5354 | serge | 1085 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type); |
1086 | static inline void |
||
1087 | intel_wait_for_vblank(struct drm_device *dev, int pipe) |
||
1088 | { |
||
1089 | drm_wait_one_vblank(dev, pipe); |
||
1090 | } |
||
6937 | serge | 1091 | static inline void |
1092 | intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe) |
||
1093 | { |
||
1094 | const struct intel_crtc *crtc = |
||
1095 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); |
||
1096 | |||
1097 | if (crtc->active) |
||
1098 | intel_wait_for_vblank(dev, pipe); |
||
1099 | } |
||
4560 | Serge | 1100 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
1101 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
||
6084 | serge | 1102 | struct intel_digital_port *dport, |
1103 | unsigned int expected_mask); |
||
4560 | Serge | 1104 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
6084 | serge | 1105 | struct drm_display_mode *mode, |
5060 | serge | 1106 | struct intel_load_detect_pipe *old, |
1107 | struct drm_modeset_acquire_ctx *ctx); |
||
4560 | Serge | 1108 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
6084 | serge | 1109 | struct intel_load_detect_pipe *old, |
1110 | struct drm_modeset_acquire_ctx *ctx); |
||
5354 | serge | 1111 | int intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
1112 | struct drm_framebuffer *fb, |
||
6937 | serge | 1113 | const struct drm_plane_state *plane_state); |
5060 | serge | 1114 | struct drm_framebuffer * |
1115 | __intel_framebuffer_create(struct drm_device *dev, |
||
6084 | serge | 1116 | struct drm_mode_fb_cmd2 *mode_cmd, |
1117 | struct drm_i915_gem_object *obj); |
||
4560 | Serge | 1118 | void intel_prepare_page_flip(struct drm_device *dev, int plane); |
1119 | void intel_finish_page_flip(struct drm_device *dev, int pipe); |
||
1120 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane); |
||
5354 | serge | 1121 | void intel_check_page_flip(struct drm_device *dev, int pipe); |
6084 | serge | 1122 | int intel_prepare_plane_fb(struct drm_plane *plane, |
1123 | const struct drm_plane_state *new_state); |
||
1124 | void intel_cleanup_plane_fb(struct drm_plane *plane, |
||
1125 | const struct drm_plane_state *old_state); |
||
1126 | int intel_plane_atomic_get_property(struct drm_plane *plane, |
||
1127 | const struct drm_plane_state *state, |
||
1128 | struct drm_property *property, |
||
1129 | uint64_t *val); |
||
1130 | int intel_plane_atomic_set_property(struct drm_plane *plane, |
||
1131 | struct drm_plane_state *state, |
||
1132 | struct drm_property *property, |
||
1133 | uint64_t val); |
||
1134 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
||
1135 | struct drm_plane_state *plane_state); |
||
5060 | serge | 1136 | |
7144 | serge | 1137 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
1138 | uint64_t fb_modifier, unsigned int cpp); |
||
6084 | serge | 1139 | |
1140 | static inline bool |
||
1141 | intel_rotation_90_or_270(unsigned int rotation) |
||
1142 | { |
||
1143 | return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270)); |
||
1144 | } |
||
1145 | |||
1146 | void intel_create_rotation_property(struct drm_device *dev, |
||
1147 | struct intel_plane *plane); |
||
1148 | |||
5060 | serge | 1149 | /* shared dpll functions */ |
4560 | Serge | 1150 | struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc); |
4104 | Serge | 1151 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1152 | struct intel_shared_dpll *pll, |
||
1153 | bool state); |
||
1154 | #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) |
||
1155 | #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) |
||
6084 | serge | 1156 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
1157 | struct intel_crtc_state *state); |
||
5060 | serge | 1158 | |
7144 | serge | 1159 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
1160 | const struct dpll *dpll); |
||
5354 | serge | 1161 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe); |
1162 | |||
5060 | serge | 1163 | /* modesetting asserts */ |
5354 | serge | 1164 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1165 | enum pipe pipe); |
||
4104 | Serge | 1166 | void assert_pll(struct drm_i915_private *dev_priv, |
1167 | enum pipe pipe, bool state); |
||
1168 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) |
||
1169 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) |
||
1170 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
||
1171 | enum pipe pipe, bool state); |
||
1172 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) |
||
1173 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) |
||
4560 | Serge | 1174 | void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); |
2342 | Serge | 1175 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
1176 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) |
||
7144 | serge | 1177 | u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv, |
1178 | int *x, int *y, |
||
1179 | uint64_t fb_modifier, |
||
1180 | unsigned int cpp, |
||
1181 | unsigned int pitch); |
||
5354 | serge | 1182 | void intel_prepare_reset(struct drm_device *dev); |
1183 | void intel_finish_reset(struct drm_device *dev); |
||
5060 | serge | 1184 | void hsw_enable_pc8(struct drm_i915_private *dev_priv); |
1185 | void hsw_disable_pc8(struct drm_i915_private *dev_priv); |
||
6084 | serge | 1186 | void broxton_init_cdclk(struct drm_device *dev); |
1187 | void broxton_uninit_cdclk(struct drm_device *dev); |
||
1188 | void broxton_ddi_phy_init(struct drm_device *dev); |
||
1189 | void broxton_ddi_phy_uninit(struct drm_device *dev); |
||
1190 | void bxt_enable_dc9(struct drm_i915_private *dev_priv); |
||
1191 | void bxt_disable_dc9(struct drm_i915_private *dev_priv); |
||
1192 | void skl_init_cdclk(struct drm_i915_private *dev_priv); |
||
6937 | serge | 1193 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv); |
6084 | serge | 1194 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv); |
6937 | serge | 1195 | void skl_enable_dc6(struct drm_i915_private *dev_priv); |
1196 | void skl_disable_dc6(struct drm_i915_private *dev_priv); |
||
4560 | Serge | 1197 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
6084 | serge | 1198 | struct intel_crtc_state *pipe_config); |
1199 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n); |
||
4560 | Serge | 1200 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); |
1201 | void |
||
6084 | serge | 1202 | ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
4560 | Serge | 1203 | int dotclock); |
6084 | serge | 1204 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
1205 | intel_clock_t *best_clock); |
||
1206 | int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock); |
||
1207 | |||
4560 | Serge | 1208 | bool intel_crtc_active(struct drm_crtc *crtc); |
1209 | void hsw_enable_ips(struct intel_crtc *crtc); |
||
1210 | void hsw_disable_ips(struct intel_crtc *crtc); |
||
5060 | serge | 1211 | enum intel_display_power_domain |
1212 | intel_display_port_power_domain(struct intel_encoder *intel_encoder); |
||
6084 | serge | 1213 | enum intel_display_power_domain |
1214 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder); |
||
5060 | serge | 1215 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
6084 | serge | 1216 | struct intel_crtc_state *pipe_config); |
3243 | Serge | 1217 | |
6084 | serge | 1218 | int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state); |
1219 | int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state); |
||
1220 | |||
6660 | serge | 1221 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
7144 | serge | 1222 | struct drm_i915_gem_object *obj, |
1223 | unsigned int plane); |
||
6084 | serge | 1224 | |
1225 | u32 skl_plane_ctl_format(uint32_t pixel_format); |
||
1226 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier); |
||
1227 | u32 skl_plane_ctl_rotation(unsigned int rotation); |
||
1228 | |||
1229 | /* intel_csr.c */ |
||
6937 | serge | 1230 | void intel_csr_ucode_init(struct drm_i915_private *); |
7144 | serge | 1231 | bool intel_csr_load_program(struct drm_i915_private *); |
6937 | serge | 1232 | void intel_csr_ucode_fini(struct drm_i915_private *); |
6084 | serge | 1233 | |
4560 | Serge | 1234 | /* intel_dp.c */ |
6937 | serge | 1235 | void intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port); |
4560 | Serge | 1236 | bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
1237 | struct intel_connector *intel_connector); |
||
6084 | serge | 1238 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
1239 | const struct intel_crtc_state *pipe_config); |
||
4560 | Serge | 1240 | void intel_dp_start_link_train(struct intel_dp *intel_dp); |
1241 | void intel_dp_stop_link_train(struct intel_dp *intel_dp); |
||
1242 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); |
||
6660 | serge | 1243 | void intel_dp_encoder_reset(struct drm_encoder *encoder); |
1244 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); |
||
4560 | Serge | 1245 | void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
5060 | serge | 1246 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); |
4560 | Serge | 1247 | bool intel_dp_compute_config(struct intel_encoder *encoder, |
6084 | serge | 1248 | struct intel_crtc_state *pipe_config); |
4560 | Serge | 1249 | bool intel_dp_is_edp(struct drm_device *dev, enum port port); |
6084 | serge | 1250 | enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, |
1251 | bool long_hpd); |
||
5060 | serge | 1252 | void intel_edp_backlight_on(struct intel_dp *intel_dp); |
1253 | void intel_edp_backlight_off(struct intel_dp *intel_dp); |
||
1254 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); |
||
1255 | void intel_edp_panel_on(struct intel_dp *intel_dp); |
||
1256 | void intel_edp_panel_off(struct intel_dp *intel_dp); |
||
1257 | void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector); |
||
1258 | void intel_dp_mst_suspend(struct drm_device *dev); |
||
1259 | void intel_dp_mst_resume(struct drm_device *dev); |
||
6084 | serge | 1260 | int intel_dp_max_link_rate(struct intel_dp *intel_dp); |
1261 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); |
||
5060 | serge | 1262 | void intel_dp_hot_plug(struct intel_encoder *intel_encoder); |
5354 | serge | 1263 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv); |
1264 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes); |
||
6084 | serge | 1265 | void intel_plane_destroy(struct drm_plane *plane); |
1266 | void intel_edp_drrs_enable(struct intel_dp *intel_dp); |
||
1267 | void intel_edp_drrs_disable(struct intel_dp *intel_dp); |
||
1268 | void intel_edp_drrs_invalidate(struct drm_device *dev, |
||
1269 | unsigned frontbuffer_bits); |
||
1270 | void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits); |
||
6937 | serge | 1271 | bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
1272 | struct intel_digital_port *port); |
||
6084 | serge | 1273 | void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config); |
5354 | serge | 1274 | |
6937 | serge | 1275 | void |
1276 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
||
1277 | uint8_t dp_train_pat); |
||
1278 | void |
||
1279 | intel_dp_set_signal_levels(struct intel_dp *intel_dp); |
||
1280 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp); |
||
1281 | uint8_t |
||
1282 | intel_dp_voltage_max(struct intel_dp *intel_dp); |
||
1283 | uint8_t |
||
1284 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing); |
||
1285 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
||
1286 | uint8_t *link_bw, uint8_t *rate_select); |
||
1287 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp); |
||
1288 | bool |
||
1289 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]); |
||
1290 | |||
5060 | serge | 1291 | /* intel_dp_mst.c */ |
1292 | int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); |
||
1293 | void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); |
||
4560 | Serge | 1294 | /* intel_dsi.c */ |
5060 | serge | 1295 | void intel_dsi_init(struct drm_device *dev); |
4560 | Serge | 1296 | |
1297 | |||
1298 | /* intel_dvo.c */ |
||
1299 | void intel_dvo_init(struct drm_device *dev); |
||
1300 | |||
1301 | |||
1302 | /* legacy fbdev emulation in intel_fbdev.c */ |
||
6084 | serge | 1303 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
4560 | Serge | 1304 | extern int intel_fbdev_init(struct drm_device *dev); |
6937 | serge | 1305 | extern void intel_fbdev_initial_config_async(struct drm_device *dev); |
4560 | Serge | 1306 | extern void intel_fbdev_fini(struct drm_device *dev); |
5354 | serge | 1307 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); |
4560 | Serge | 1308 | extern void intel_fbdev_output_poll_changed(struct drm_device *dev); |
1309 | extern void intel_fbdev_restore_mode(struct drm_device *dev); |
||
1310 | #else |
||
1311 | static inline int intel_fbdev_init(struct drm_device *dev) |
||
1312 | { |
||
1313 | return 0; |
||
1314 | } |
||
1315 | |||
6937 | serge | 1316 | static inline void intel_fbdev_initial_config_async(struct drm_device *dev) |
4560 | Serge | 1317 | { |
1318 | } |
||
1319 | |||
1320 | static inline void intel_fbdev_fini(struct drm_device *dev) |
||
1321 | { |
||
1322 | } |
||
1323 | |||
5354 | serge | 1324 | static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) |
4560 | Serge | 1325 | { |
1326 | } |
||
1327 | |||
1328 | static inline void intel_fbdev_restore_mode(struct drm_device *dev) |
||
1329 | { |
||
1330 | } |
||
1331 | #endif |
||
1332 | |||
6084 | serge | 1333 | /* intel_fbc.c */ |
7144 | serge | 1334 | void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, |
1335 | struct drm_atomic_state *state); |
||
6937 | serge | 1336 | bool intel_fbc_is_active(struct drm_i915_private *dev_priv); |
7144 | serge | 1337 | void intel_fbc_pre_update(struct intel_crtc *crtc); |
1338 | void intel_fbc_post_update(struct intel_crtc *crtc); |
||
6084 | serge | 1339 | void intel_fbc_init(struct drm_i915_private *dev_priv); |
7144 | serge | 1340 | void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv); |
6937 | serge | 1341 | void intel_fbc_enable(struct intel_crtc *crtc); |
7144 | serge | 1342 | void intel_fbc_disable(struct intel_crtc *crtc); |
1343 | void intel_fbc_global_disable(struct drm_i915_private *dev_priv); |
||
6084 | serge | 1344 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, |
1345 | unsigned int frontbuffer_bits, |
||
1346 | enum fb_op_origin origin); |
||
1347 | void intel_fbc_flush(struct drm_i915_private *dev_priv, |
||
1348 | unsigned int frontbuffer_bits, enum fb_op_origin origin); |
||
1349 | void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv); |
||
1350 | |||
4560 | Serge | 1351 | /* intel_hdmi.c */ |
6937 | serge | 1352 | void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port); |
4560 | Serge | 1353 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1354 | struct intel_connector *intel_connector); |
||
1355 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); |
||
1356 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
||
6084 | serge | 1357 | struct intel_crtc_state *pipe_config); |
7144 | serge | 1358 | void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable); |
4560 | Serge | 1359 | |
1360 | |||
1361 | /* intel_lvds.c */ |
||
1362 | void intel_lvds_init(struct drm_device *dev); |
||
1363 | bool intel_is_dual_link_lvds(struct drm_device *dev); |
||
1364 | |||
1365 | |||
1366 | /* intel_modes.c */ |
||
1367 | int intel_connector_update_modes(struct drm_connector *connector, |
||
1368 | struct edid *edid); |
||
1369 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
||
1370 | void intel_attach_force_audio_property(struct drm_connector *connector); |
||
1371 | void intel_attach_broadcast_rgb_property(struct drm_connector *connector); |
||
6084 | serge | 1372 | void intel_attach_aspect_ratio_property(struct drm_connector *connector); |
4560 | Serge | 1373 | |
1374 | |||
1375 | /* intel_overlay.c */ |
||
1376 | void intel_setup_overlay(struct drm_device *dev); |
||
1377 | void intel_cleanup_overlay(struct drm_device *dev); |
||
1378 | int intel_overlay_switch_off(struct intel_overlay *overlay); |
||
1379 | int intel_overlay_put_image(struct drm_device *dev, void *data, |
||
6084 | serge | 1380 | struct drm_file *file_priv); |
4560 | Serge | 1381 | int intel_overlay_attrs(struct drm_device *dev, void *data, |
6084 | serge | 1382 | struct drm_file *file_priv); |
1383 | void intel_overlay_reset(struct drm_i915_private *dev_priv); |
||
2342 | Serge | 1384 | |
3031 | serge | 1385 | |
4560 | Serge | 1386 | /* intel_panel.c */ |
1387 | int intel_panel_init(struct intel_panel *panel, |
||
5060 | serge | 1388 | struct drm_display_mode *fixed_mode, |
1389 | struct drm_display_mode *downclock_mode); |
||
4560 | Serge | 1390 | void intel_panel_fini(struct intel_panel *panel); |
1391 | void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, |
||
1392 | struct drm_display_mode *adjusted_mode); |
||
1393 | void intel_pch_panel_fitting(struct intel_crtc *crtc, |
||
6084 | serge | 1394 | struct intel_crtc_state *pipe_config, |
4560 | Serge | 1395 | int fitting_mode); |
1396 | void intel_gmch_panel_fitting(struct intel_crtc *crtc, |
||
6084 | serge | 1397 | struct intel_crtc_state *pipe_config, |
4560 | Serge | 1398 | int fitting_mode); |
5060 | serge | 1399 | void intel_panel_set_backlight_acpi(struct intel_connector *connector, |
1400 | u32 level, u32 max); |
||
5354 | serge | 1401 | int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe); |
4560 | Serge | 1402 | void intel_panel_enable_backlight(struct intel_connector *connector); |
1403 | void intel_panel_disable_backlight(struct intel_connector *connector); |
||
1404 | void intel_panel_destroy_backlight(struct drm_connector *connector); |
||
1405 | enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
||
1406 | extern struct drm_display_mode *intel_find_panel_downclock( |
||
1407 | struct drm_device *dev, |
||
1408 | struct drm_display_mode *fixed_mode, |
||
1409 | struct drm_connector *connector); |
||
5354 | serge | 1410 | void intel_backlight_register(struct drm_device *dev); |
1411 | void intel_backlight_unregister(struct drm_device *dev); |
||
4104 | Serge | 1412 | |
5354 | serge | 1413 | |
1414 | /* intel_psr.c */ |
||
1415 | void intel_psr_enable(struct intel_dp *intel_dp); |
||
1416 | void intel_psr_disable(struct intel_dp *intel_dp); |
||
1417 | void intel_psr_invalidate(struct drm_device *dev, |
||
6084 | serge | 1418 | unsigned frontbuffer_bits); |
5354 | serge | 1419 | void intel_psr_flush(struct drm_device *dev, |
6084 | serge | 1420 | unsigned frontbuffer_bits, |
1421 | enum fb_op_origin origin); |
||
5354 | serge | 1422 | void intel_psr_init(struct drm_device *dev); |
6084 | serge | 1423 | void intel_psr_single_frame_update(struct drm_device *dev, |
1424 | unsigned frontbuffer_bits); |
||
5354 | serge | 1425 | |
1426 | /* intel_runtime_pm.c */ |
||
1427 | int intel_power_domains_init(struct drm_i915_private *); |
||
1428 | void intel_power_domains_fini(struct drm_i915_private *); |
||
6937 | serge | 1429 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); |
1430 | void intel_power_domains_suspend(struct drm_i915_private *dev_priv); |
||
1431 | void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv); |
||
1432 | void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv); |
||
5354 | serge | 1433 | void intel_runtime_pm_enable(struct drm_i915_private *dev_priv); |
6937 | serge | 1434 | const char * |
1435 | intel_display_power_domain_str(enum intel_display_power_domain domain); |
||
5354 | serge | 1436 | |
1437 | bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
||
1438 | enum intel_display_power_domain domain); |
||
1439 | bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
||
1440 | enum intel_display_power_domain domain); |
||
1441 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
||
1442 | enum intel_display_power_domain domain); |
||
6937 | serge | 1443 | bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, |
1444 | enum intel_display_power_domain domain); |
||
5354 | serge | 1445 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
1446 | enum intel_display_power_domain domain); |
||
6937 | serge | 1447 | |
1448 | static inline void |
||
1449 | assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv) |
||
1450 | { |
||
1451 | WARN_ONCE(dev_priv->pm.suspended, |
||
1452 | "Device suspended during HW access\n"); |
||
1453 | } |
||
1454 | |||
1455 | static inline void |
||
1456 | assert_rpm_wakelock_held(struct drm_i915_private *dev_priv) |
||
1457 | { |
||
1458 | assert_rpm_device_not_suspended(dev_priv); |
||
1459 | /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes |
||
1460 | * too much noise. */ |
||
1461 | if (!atomic_read(&dev_priv->pm.wakeref_count)) |
||
1462 | DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access"); |
||
1463 | } |
||
1464 | |||
1465 | static inline int |
||
1466 | assert_rpm_atomic_begin(struct drm_i915_private *dev_priv) |
||
1467 | { |
||
1468 | int seq = atomic_read(&dev_priv->pm.atomic_seq); |
||
1469 | |||
1470 | assert_rpm_wakelock_held(dev_priv); |
||
1471 | |||
1472 | return seq; |
||
1473 | } |
||
1474 | |||
1475 | static inline void |
||
1476 | assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq) |
||
1477 | { |
||
1478 | WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq, |
||
1479 | "HW access outside of RPM atomic section\n"); |
||
1480 | } |
||
1481 | |||
1482 | /** |
||
1483 | * disable_rpm_wakeref_asserts - disable the RPM assert checks |
||
1484 | * @dev_priv: i915 device instance |
||
1485 | * |
||
1486 | * This function disable asserts that check if we hold an RPM wakelock |
||
1487 | * reference, while keeping the device-not-suspended checks still enabled. |
||
1488 | * It's meant to be used only in special circumstances where our rule about |
||
1489 | * the wakelock refcount wrt. the device power state doesn't hold. According |
||
1490 | * to this rule at any point where we access the HW or want to keep the HW in |
||
1491 | * an active state we must hold an RPM wakelock reference acquired via one of |
||
1492 | * the intel_runtime_pm_get() helpers. Currently there are a few special spots |
||
1493 | * where this rule doesn't hold: the IRQ and suspend/resume handlers, the |
||
1494 | * forcewake release timer, and the GPU RPS and hangcheck works. All other |
||
1495 | * users should avoid using this function. |
||
1496 | * |
||
1497 | * Any calls to this function must have a symmetric call to |
||
1498 | * enable_rpm_wakeref_asserts(). |
||
1499 | */ |
||
1500 | static inline void |
||
1501 | disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv) |
||
1502 | { |
||
1503 | atomic_inc(&dev_priv->pm.wakeref_count); |
||
1504 | } |
||
1505 | |||
1506 | /** |
||
1507 | * enable_rpm_wakeref_asserts - re-enable the RPM assert checks |
||
1508 | * @dev_priv: i915 device instance |
||
1509 | * |
||
1510 | * This function re-enables the RPM assert checks after disabling them with |
||
1511 | * disable_rpm_wakeref_asserts. It's meant to be used only in special |
||
1512 | * circumstances otherwise its use should be avoided. |
||
1513 | * |
||
1514 | * Any calls to this function must have a symmetric call to |
||
1515 | * disable_rpm_wakeref_asserts(). |
||
1516 | */ |
||
1517 | static inline void |
||
1518 | enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv) |
||
1519 | { |
||
1520 | atomic_dec(&dev_priv->pm.wakeref_count); |
||
1521 | } |
||
1522 | |||
1523 | /* TODO: convert users of these to rely instead on proper RPM refcounting */ |
||
1524 | #define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv) \ |
||
1525 | disable_rpm_wakeref_asserts(dev_priv) |
||
1526 | |||
1527 | #define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv) \ |
||
1528 | enable_rpm_wakeref_asserts(dev_priv) |
||
1529 | |||
5354 | serge | 1530 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv); |
6937 | serge | 1531 | bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv); |
5354 | serge | 1532 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); |
1533 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv); |
||
1534 | |||
1535 | void intel_display_set_init_power(struct drm_i915_private *dev, bool enable); |
||
1536 | |||
6084 | serge | 1537 | void chv_phy_powergate_lanes(struct intel_encoder *encoder, |
1538 | bool override, unsigned int mask); |
||
1539 | bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, |
||
1540 | enum dpio_channel ch, bool override); |
||
1541 | |||
1542 | |||
4560 | Serge | 1543 | /* intel_pm.c */ |
1544 | void intel_init_clock_gating(struct drm_device *dev); |
||
1545 | void intel_suspend_hw(struct drm_device *dev); |
||
5060 | serge | 1546 | int ilk_wm_max_level(const struct drm_device *dev); |
4560 | Serge | 1547 | void intel_update_watermarks(struct drm_crtc *crtc); |
1548 | void intel_init_pm(struct drm_device *dev); |
||
1549 | void intel_pm_setup(struct drm_device *dev); |
||
1550 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv); |
||
1551 | void intel_gpu_ips_teardown(void); |
||
5060 | serge | 1552 | void intel_init_gt_powersave(struct drm_device *dev); |
1553 | void intel_cleanup_gt_powersave(struct drm_device *dev); |
||
4560 | Serge | 1554 | void intel_enable_gt_powersave(struct drm_device *dev); |
1555 | void intel_disable_gt_powersave(struct drm_device *dev); |
||
5060 | serge | 1556 | void intel_suspend_gt_powersave(struct drm_device *dev); |
1557 | void intel_reset_gt_powersave(struct drm_device *dev); |
||
4104 | Serge | 1558 | void gen6_update_ring_freq(struct drm_device *dev); |
6084 | serge | 1559 | void gen6_rps_busy(struct drm_i915_private *dev_priv); |
1560 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); |
||
4560 | Serge | 1561 | void gen6_rps_idle(struct drm_i915_private *dev_priv); |
6084 | serge | 1562 | void gen6_rps_boost(struct drm_i915_private *dev_priv, |
1563 | struct intel_rps_client *rps, |
||
1564 | unsigned long submitted); |
||
1565 | void intel_queue_rps_boost_for_request(struct drm_device *dev, |
||
1566 | struct drm_i915_gem_request *req); |
||
1567 | void vlv_wm_get_hw_state(struct drm_device *dev); |
||
4560 | Serge | 1568 | void ilk_wm_get_hw_state(struct drm_device *dev); |
5354 | serge | 1569 | void skl_wm_get_hw_state(struct drm_device *dev); |
1570 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
||
1571 | struct skl_ddb_allocation *ddb /* out */); |
||
6084 | serge | 1572 | uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config); |
7144 | serge | 1573 | int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6); |
3031 | serge | 1574 | |
4560 | Serge | 1575 | /* intel_sdvo.c */ |
6937 | serge | 1576 | bool intel_sdvo_init(struct drm_device *dev, |
1577 | i915_reg_t reg, enum port port); |
||
3746 | Serge | 1578 | |
4104 | Serge | 1579 | |
4560 | Serge | 1580 | /* intel_sprite.c */ |
1581 | int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
||
1582 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
||
1583 | struct drm_file *file_priv); |
||
6084 | serge | 1584 | void intel_pipe_update_start(struct intel_crtc *crtc); |
1585 | void intel_pipe_update_end(struct intel_crtc *crtc); |
||
4560 | Serge | 1586 | |
1587 | /* intel_tv.c */ |
||
1588 | void intel_tv_init(struct drm_device *dev); |
||
1589 | |||
6084 | serge | 1590 | /* intel_atomic.c */ |
1591 | int intel_connector_atomic_get_property(struct drm_connector *connector, |
||
1592 | const struct drm_connector_state *state, |
||
1593 | struct drm_property *property, |
||
1594 | uint64_t *val); |
||
1595 | struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc); |
||
1596 | void intel_crtc_destroy_state(struct drm_crtc *crtc, |
||
1597 | struct drm_crtc_state *state); |
||
1598 | struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev); |
||
1599 | void intel_atomic_state_clear(struct drm_atomic_state *); |
||
1600 | struct intel_shared_dpll_config * |
||
1601 | intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s); |
||
1602 | |||
1603 | static inline struct intel_crtc_state * |
||
1604 | intel_atomic_get_crtc_state(struct drm_atomic_state *state, |
||
1605 | struct intel_crtc *crtc) |
||
1606 | { |
||
1607 | struct drm_crtc_state *crtc_state; |
||
1608 | crtc_state = drm_atomic_get_crtc_state(state, &crtc->base); |
||
1609 | if (IS_ERR(crtc_state)) |
||
1610 | return ERR_CAST(crtc_state); |
||
1611 | |||
1612 | return to_intel_crtc_state(crtc_state); |
||
1613 | } |
||
1614 | int intel_atomic_setup_scalers(struct drm_device *dev, |
||
1615 | struct intel_crtc *intel_crtc, |
||
1616 | struct intel_crtc_state *crtc_state); |
||
1617 | |||
1618 | /* intel_atomic_plane.c */ |
||
1619 | struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane); |
||
1620 | struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane); |
||
1621 | void intel_plane_destroy_state(struct drm_plane *plane, |
||
1622 | struct drm_plane_state *state); |
||
1623 | extern const struct drm_plane_helper_funcs intel_plane_helper_funcs; |
||
1624 | |||
6937 | serge | 1625 | int drm_core_init(void); |
1626 | void set_fake_framebuffer(); |
||
1627 | int kolibri_framebuffer_init(void *param); |
||
1628 | void shmem_file_delete(struct file *filep); |
||
1629 | void intel_fbdev_initial_config(void *data, async_cookie_t cookie); |
||
1630 | int drm_get_pci_dev(struct pci_dev *pdev, const struct pci_device_id *ent, |
||
1631 | struct drm_driver *driver); |
||
7144 | serge | 1632 | #define synchronize_irq(x) |
6937 | serge | 1633 | |
2326 | Serge | 1634 | #endif /* __INTEL_DRV_H__ */0)><0)> |