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2326 Serge 1
/*
2
 * Copyright (c) 2006 Dave Airlie 
3
 * Copyright (c) 2007-2008 Intel Corporation
4
 *   Jesse Barnes 
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a
7
 * copy of this software and associated documentation files (the "Software"),
8
 * to deal in the Software without restriction, including without limitation
9
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10
 * and/or sell copies of the Software, and to permit persons to whom the
11
 * Software is furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice (including the next
14
 * paragraph) shall be included in all copies or substantial portions of the
15
 * Software.
16
 *
17
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23
 * IN THE SOFTWARE.
24
 */
25
#ifndef __INTEL_DRV_H__
26
#define __INTEL_DRV_H__
27
 
5354 serge 28
#include 
2326 Serge 29
#include 
4104 Serge 30
#include 
3031 serge 31
#include 
2326 Serge 32
#include "i915_drv.h"
3031 serge 33
#include 
34
#include 
35
#include 
5060 serge 36
#include 
5354 serge 37
#include 
6084 serge 38
#include 
2326 Serge 39
 
3746 Serge 40
/**
41
 * _wait_for - magic (register) wait macro
42
 *
43
 * Does the right thing for modeset paths when run under kdgb or similar atomic
44
 * contexts. Note that it's important that we check the condition again after
45
 * having timed out, since the timeout could be due to preemption or similar and
46
 * we've never had a chance to check the condition before the timeout.
47
 */
2326 Serge 48
#define _wait_for(COND, MS, W) ({ \
5060 serge 49
	unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;	\
2326 Serge 50
	int ret__ = 0;							\
2342 Serge 51
	while (!(COND)) {						\
5060 serge 52
		if (time_after(jiffies, timeout__)) {			\
3746 Serge 53
			if (!(COND))					\
6084 serge 54
				ret__ = -ETIMEDOUT;			\
2326 Serge 55
			break;						\
56
		}							\
3031 serge 57
		if (W )  {				\
58
         msleep(W); \
59
		} else {						\
60
			cpu_relax();					\
61
		}							\
2326 Serge 62
	}								\
63
	ret__;								\
64
})
65
 
66
#define wait_for(COND, MS) _wait_for(COND, MS, 1)
67
#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
4104 Serge 68
#define wait_for_atomic_us(COND, US) _wait_for((COND), \
69
					       DIV_ROUND_UP((US), 1000), 0)
2326 Serge 70
 
4560 Serge 71
#define KHz(x) (1000 * (x))
72
#define MHz(x) KHz(1000 * (x))
2326 Serge 73
 
74
/*
75
 * Display related stuff
76
 */
77
 
78
/* store information about an Ixxx DVO */
79
/* The i830->i865 use multiple DVOs with multiple i2cs */
80
/* the i915, i945 have a single sDVO i2c bus - which is different */
81
#define MAX_OUTPUTS 6
82
/* maximum connectors per crtcs in the mode set */
83
 
5060 serge 84
/* Maximum cursor sizes */
85
#define GEN2_CURSOR_WIDTH 64
86
#define GEN2_CURSOR_HEIGHT 64
87
#define MAX_CURSOR_WIDTH 256
88
#define MAX_CURSOR_HEIGHT 256
89
 
2326 Serge 90
#define INTEL_I2C_BUS_DVO 1
91
#define INTEL_I2C_BUS_SDVO 2
92
 
93
/* these are outputs from the chip - integrated only
94
   external chips are via DVO or SDVO output */
5354 serge 95
enum intel_output_type {
96
	INTEL_OUTPUT_UNUSED = 0,
97
	INTEL_OUTPUT_ANALOG = 1,
98
	INTEL_OUTPUT_DVO = 2,
99
	INTEL_OUTPUT_SDVO = 3,
100
	INTEL_OUTPUT_LVDS = 4,
101
	INTEL_OUTPUT_TVOUT = 5,
102
	INTEL_OUTPUT_HDMI = 6,
103
	INTEL_OUTPUT_DISPLAYPORT = 7,
104
	INTEL_OUTPUT_EDP = 8,
105
	INTEL_OUTPUT_DSI = 9,
106
	INTEL_OUTPUT_UNKNOWN = 10,
107
	INTEL_OUTPUT_DP_MST = 11,
108
};
2326 Serge 109
 
110
#define INTEL_DVO_CHIP_NONE 0
111
#define INTEL_DVO_CHIP_LVDS 1
112
#define INTEL_DVO_CHIP_TMDS 2
113
#define INTEL_DVO_CHIP_TVOUT 4
114
 
5060 serge 115
#define INTEL_DSI_VIDEO_MODE	0
116
#define INTEL_DSI_COMMAND_MODE	1
4560 Serge 117
 
2326 Serge 118
struct intel_framebuffer {
119
	struct drm_framebuffer base;
6320 serge 120
	struct drm_i915_gem_object *obj;
6935 serge 121
	void   *private; /*Kolibri */
2326 Serge 122
};
123
 
124
struct intel_fbdev {
125
	struct drm_fb_helper helper;
5060 serge 126
	struct intel_framebuffer *fb;
127
	int preferred_bpp;
2326 Serge 128
};
129
 
130
struct intel_encoder {
131
	struct drm_encoder base;
3031 serge 132
 
5354 serge 133
	enum intel_output_type type;
5060 serge 134
	unsigned int cloneable;
2326 Serge 135
	void (*hot_plug)(struct intel_encoder *);
3746 Serge 136
	bool (*compute_config)(struct intel_encoder *,
6084 serge 137
			       struct intel_crtc_state *);
3480 Serge 138
	void (*pre_pll_enable)(struct intel_encoder *);
3031 serge 139
	void (*pre_enable)(struct intel_encoder *);
140
	void (*enable)(struct intel_encoder *);
3746 Serge 141
	void (*mode_set)(struct intel_encoder *intel_encoder);
3031 serge 142
	void (*disable)(struct intel_encoder *);
143
	void (*post_disable)(struct intel_encoder *);
6084 serge 144
	void (*post_pll_disable)(struct intel_encoder *);
3031 serge 145
	/* Read out the current hw state of this connector, returning true if
146
	 * the encoder is active. If the encoder is enabled it also set the pipe
147
	 * it is connected to in the pipe parameter. */
148
	bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
4104 Serge 149
	/* Reconstructs the equivalent mode flags for the current hardware
150
	 * state. This must be called _after_ display->get_pipe_config has
151
	 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
152
	 * be set correctly before calling this function. */
153
	void (*get_config)(struct intel_encoder *,
6084 serge 154
			   struct intel_crtc_state *pipe_config);
5060 serge 155
	/*
156
	 * Called during system suspend after all pending requests for the
157
	 * encoder are flushed (for example for DP AUX transactions) and
158
	 * device interrupts are disabled.
159
	 */
160
	void (*suspend)(struct intel_encoder *);
2326 Serge 161
	int crtc_mask;
3746 Serge 162
	enum hpd_pin hpd_pin;
2326 Serge 163
};
164
 
3243 Serge 165
struct intel_panel {
166
	struct drm_display_mode *fixed_mode;
4560 Serge 167
	struct drm_display_mode *downclock_mode;
3243 Serge 168
	int fitting_mode;
4560 Serge 169
 
170
	/* backlight */
171
	struct {
172
		bool present;
173
		u32 level;
5060 serge 174
		u32 min;
4560 Serge 175
		u32 max;
176
		bool enabled;
177
		bool combination_mode;	/* gen 2/4 only */
178
		bool active_low_pwm;
6084 serge 179
 
180
		/* PWM chip */
181
		bool util_pin_active_low;	/* bxt+ */
182
		u8 controller;		/* bxt+ only */
183
		struct pwm_device *pwm;
184
 
4560 Serge 185
		struct backlight_device *device;
6084 serge 186
 
187
		/* Connector and platform specific backlight functions */
188
		int (*setup)(struct intel_connector *connector, enum pipe pipe);
189
		uint32_t (*get)(struct intel_connector *connector);
190
		void (*set)(struct intel_connector *connector, uint32_t level);
191
		void (*disable)(struct intel_connector *connector);
192
		void (*enable)(struct intel_connector *connector);
193
		uint32_t (*hz_to_pwm)(struct intel_connector *connector,
194
				      uint32_t hz);
195
		void (*power)(struct intel_connector *, bool enable);
4560 Serge 196
	} backlight;
3243 Serge 197
};
198
 
2326 Serge 199
struct intel_connector {
200
	struct drm_connector base;
3031 serge 201
	/*
202
	 * The fixed encoder this connector is connected to.
203
	 */
2326 Serge 204
	struct intel_encoder *encoder;
3031 serge 205
 
206
	/* Reads out the current hw, returning true if the connector is enabled
207
	 * and active (i.e. dpms ON state). */
208
	bool (*get_hw_state)(struct intel_connector *);
3243 Serge 209
 
5060 serge 210
	/*
211
	 * Removes all interfaces through which the connector is accessible
212
	 * - like sysfs, debugfs entries -, so that no new operations can be
213
	 * started on the connector. Also makes sure all currently pending
214
	 * operations finish before returing.
215
	 */
216
	void (*unregister)(struct intel_connector *);
217
 
3243 Serge 218
	/* Panel info for eDP and LVDS */
219
	struct intel_panel panel;
220
 
221
	/* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
222
	struct edid *edid;
5354 serge 223
	struct edid *detect_edid;
3746 Serge 224
 
225
	/* since POLL and HPD connectors may use the same HPD line keep the native
226
	   state of connector->polled in case hotplug storm detection changes it */
227
	u8 polled;
5060 serge 228
 
229
	void *port; /* store this opaque as its illegal to dereference it */
230
 
231
	struct intel_dp *mst_port;
2326 Serge 232
};
233
 
4104 Serge 234
typedef struct dpll {
235
	/* given values */
236
	int n;
237
	int m1, m2;
238
	int p1, p2;
239
	/* derived values */
240
	int	dot;
241
	int	vco;
242
	int	m;
243
	int	p;
244
} intel_clock_t;
245
 
6084 serge 246
struct intel_atomic_state {
247
	struct drm_atomic_state base;
248
 
249
	unsigned int cdclk;
250
	bool dpll_set;
251
	struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
6937 serge 252
	struct intel_wm_config wm_config;
6084 serge 253
};
254
 
5354 serge 255
struct intel_plane_state {
6084 serge 256
	struct drm_plane_state base;
5354 serge 257
	struct drm_rect src;
258
	struct drm_rect dst;
259
	struct drm_rect clip;
260
	bool visible;
6084 serge 261
 
262
	/*
263
	 * scaler_id
264
	 *    = -1 : not using a scaler
265
	 *    >=  0 : using a scalers
266
	 *
267
	 * plane requiring a scaler:
268
	 *   - During check_plane, its bit is set in
269
	 *     crtc_state->scaler_state.scaler_users by calling helper function
270
	 *     update_scaler_plane.
271
	 *   - scaler_id indicates the scaler it got assigned.
272
	 *
273
	 * plane doesn't require a scaler:
274
	 *   - this can happen when scaling is no more required or plane simply
275
	 *     got disabled.
276
	 *   - During check_plane, corresponding bit is reset in
277
	 *     crtc_state->scaler_state.scaler_users by calling helper function
278
	 *     update_scaler_plane.
279
	 */
280
	int scaler_id;
281
 
282
	struct drm_intel_sprite_colorkey ckey;
6937 serge 283
 
284
	/* async flip related structures */
285
	struct drm_i915_gem_request *wait_req;
5354 serge 286
};
287
 
6084 serge 288
struct intel_initial_plane_config {
289
	struct intel_framebuffer *fb;
290
	unsigned int tiling;
5060 serge 291
	int size;
292
	u32 base;
293
};
294
 
6084 serge 295
#define SKL_MIN_SRC_W 8
296
#define SKL_MAX_SRC_W 4096
297
#define SKL_MIN_SRC_H 8
298
#define SKL_MAX_SRC_H 4096
299
#define SKL_MIN_DST_W 8
300
#define SKL_MAX_DST_W 4096
301
#define SKL_MIN_DST_H 8
302
#define SKL_MAX_DST_H 4096
303
 
304
struct intel_scaler {
305
	int in_use;
306
	uint32_t mode;
307
};
308
 
309
struct intel_crtc_scaler_state {
310
#define SKL_NUM_SCALERS 2
311
	struct intel_scaler scalers[SKL_NUM_SCALERS];
312
 
313
	/*
314
	 * scaler_users: keeps track of users requesting scalers on this crtc.
315
	 *
316
	 *     If a bit is set, a user is using a scaler.
317
	 *     Here user can be a plane or crtc as defined below:
318
	 *       bits 0-30 - plane (bit position is index from drm_plane_index)
319
	 *       bit 31    - crtc
320
	 *
321
	 * Instead of creating a new index to cover planes and crtc, using
322
	 * existing drm_plane_index for planes which is well less than 31
323
	 * planes and bit 31 for crtc. This should be fine to cover all
324
	 * our platforms.
325
	 *
326
	 * intel_atomic_setup_scalers will setup available scalers to users
327
	 * requesting scalers. It will gracefully fail if request exceeds
328
	 * avilability.
329
	 */
330
#define SKL_CRTC_INDEX 31
331
	unsigned scaler_users;
332
 
333
	/* scaler used by crtc for panel fitting purpose */
334
	int scaler_id;
335
};
336
 
337
/* drm_mode->private_flags */
338
#define I915_MODE_FLAG_INHERITED 1
339
 
6937 serge 340
struct intel_pipe_wm {
341
	struct intel_wm_level wm[5];
342
	uint32_t linetime;
343
	bool fbc_wm_enabled;
344
	bool pipe_enabled;
345
	bool sprites_enabled;
346
	bool sprites_scaled;
347
};
348
 
349
struct skl_pipe_wm {
350
	struct skl_wm_level wm[8];
351
	struct skl_wm_level trans_wm;
352
	uint32_t linetime;
353
};
354
 
6084 serge 355
struct intel_crtc_state {
356
	struct drm_crtc_state base;
357
 
4104 Serge 358
	/**
359
	 * quirks - bitfield with hw state readout quirks
360
	 *
361
	 * For various reasons the hw state readout code might not be able to
362
	 * completely faithfully read out the current state. These cases are
363
	 * tracked with quirk flags so that fastboot and state checker can act
364
	 * accordingly.
365
	 */
6084 serge 366
#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS	(1<<0) /* unreliable sync mode.flags */
4104 Serge 367
	unsigned long quirks;
368
 
6937 serge 369
	bool update_pipe; /* can a fast modeset be performed? */
370
	bool disable_cxsr;
371
	bool update_wm_pre, update_wm_post; /* watermarks are updated */
4560 Serge 372
 
373
	/* Pipe source size (ie. panel fitter input size)
374
	 * All planes will be positioned inside this space,
375
	 * and get clipped at the edges. */
376
	int pipe_src_w, pipe_src_h;
377
 
3746 Serge 378
	/* Whether to set up the PCH/FDI. Note that we never allow sharing
379
	 * between pch encoders and cpu encoders. */
380
	bool has_pch_encoder;
381
 
5354 serge 382
	/* Are we sending infoframes on the attached port */
383
	bool has_infoframe;
384
 
3746 Serge 385
	/* CPU Transcoder for the pipe. Currently this can only differ from the
386
	 * pipe on Haswell (where we have a special eDP transcoder). */
387
	enum transcoder cpu_transcoder;
388
 
389
	/*
390
	 * Use reduced/limited/broadcast rbg range, compressing from the full
391
	 * range fed into the crtcs.
392
	 */
393
	bool limited_color_range;
394
 
395
	/* DP has a bunch of special case unfortunately, so mark the pipe
396
	 * accordingly. */
397
	bool has_dp_encoder;
4104 Serge 398
 
6937 serge 399
	/* DSI has special cases */
400
	bool has_dsi_encoder;
401
 
5060 serge 402
	/* Whether we should send NULL infoframes. Required for audio. */
403
	bool has_hdmi_sink;
404
 
405
	/* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
406
	 * has_dp_encoder is set. */
407
	bool has_audio;
408
 
4104 Serge 409
	/*
410
	 * Enable dithering, used when the selected pipe bpp doesn't match the
411
	 * plane bpp.
412
	 */
3746 Serge 413
	bool dither;
414
 
415
	/* Controls for the clock computation, to override various stages. */
416
	bool clock_set;
417
 
4104 Serge 418
	/* SDVO TV has a bunch of special case. To make multifunction encoders
419
	 * work correctly, we need to track this at runtime.*/
420
	bool sdvo_tv_clock;
421
 
422
	/*
423
	 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
424
	 * required. This is set in the 2nd loop of calling encoder's
425
	 * ->compute_config if the first pick doesn't work out.
426
	 */
427
	bool bw_constrained;
428
 
3746 Serge 429
	/* Settings for the intel dpll used on pretty much everything but
430
	 * haswell. */
4104 Serge 431
	struct dpll dpll;
3746 Serge 432
 
4104 Serge 433
	/* Selected dpll when shared or DPLL_ID_PRIVATE. */
434
	enum intel_dpll_id shared_dpll;
435
 
5354 serge 436
	/*
437
	 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
438
	 * - enum skl_dpll on SKL
439
	 */
5060 serge 440
	uint32_t ddi_pll_sel;
441
 
4104 Serge 442
	/* Actual register state of the dpll, for shared dpll cross-checking. */
443
	struct intel_dpll_hw_state dpll_hw_state;
444
 
3746 Serge 445
	int pipe_bpp;
446
	struct intel_link_m_n dp_m_n;
4104 Serge 447
 
5060 serge 448
	/* m2_n2 for eDP downclock */
449
	struct intel_link_m_n dp_m2_n2;
5354 serge 450
	bool has_drrs;
5060 serge 451
 
4104 Serge 452
	/*
453
	 * Frequence the dpll for the port should run at. Differs from the
4560 Serge 454
	 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
455
	 * already multiplied by pixel_multiplier.
3746 Serge 456
	 */
4104 Serge 457
	int port_clock;
458
 
3746 Serge 459
	/* Used by SDVO (and if we ever fix it, HDMI). */
460
	unsigned pixel_multiplier;
4104 Serge 461
 
6084 serge 462
	uint8_t lane_count;
463
 
4104 Serge 464
	/* Panel fitter controls for gen2-gen4 + VLV */
465
	struct {
466
		u32 control;
467
		u32 pgm_ratios;
468
		u32 lvds_border_bits;
469
	} gmch_pfit;
470
 
471
	/* Panel fitter placement and size for Ironlake+ */
472
	struct {
473
		u32 pos;
474
		u32 size;
475
		bool enabled;
5060 serge 476
		bool force_thru;
4104 Serge 477
	} pch_pfit;
478
 
479
	/* FDI configuration, only valid if has_pch_encoder is set. */
480
	int fdi_lanes;
481
	struct intel_link_m_n fdi_m_n;
482
 
483
	bool ips_enabled;
4560 Serge 484
 
485
	bool double_wide;
5060 serge 486
 
487
	bool dp_encoder_is_mst;
488
	int pbn;
6084 serge 489
 
490
	struct intel_crtc_scaler_state scaler_state;
491
 
492
	/* w/a for waiting 2 vblanks during crtc enable */
493
	enum pipe hsw_workaround_pipe;
6937 serge 494
 
495
	/* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
496
	bool disable_lp_wm;
497
 
498
	struct {
499
		/*
500
		 * optimal watermarks, programmed post-vblank when this state
501
		 * is committed
502
		 */
503
		union {
504
			struct intel_pipe_wm ilk;
505
			struct skl_pipe_wm skl;
506
		} optimal;
507
	} wm;
3746 Serge 508
};
509
 
6084 serge 510
struct vlv_wm_state {
511
	struct vlv_pipe_wm wm[3];
512
	struct vlv_sr_wm sr[3];
513
	uint8_t num_active_planes;
514
	uint8_t num_levels;
515
	uint8_t level;
516
	bool cxsr;
517
};
518
 
5060 serge 519
struct intel_mmio_flip {
5354 serge 520
	struct work_struct work;
6084 serge 521
	struct drm_i915_private *i915;
522
	struct drm_i915_gem_request *req;
523
	struct intel_crtc *crtc;
6937 serge 524
	unsigned int rotation;
5060 serge 525
};
526
 
6084 serge 527
/*
528
 * Tracking of operations that need to be performed at the beginning/end of an
529
 * atomic commit, outside the atomic section where interrupts are disabled.
530
 * These are generally operations that grab mutexes or might otherwise sleep
531
 * and thus can't be run with interrupts disabled.
532
 */
533
struct intel_crtc_atomic_commit {
534
	/* Sleepable operations to perform before commit */
535
	bool disable_fbc;
536
	bool disable_ips;
537
	bool pre_disable_primary;
538
 
539
	/* Sleepable operations to perform after commit */
540
	unsigned fb_bits;
541
	bool wait_vblank;
542
	bool update_fbc;
543
	bool post_enable_primary;
544
	unsigned update_sprite_watermarks;
545
};
546
 
2326 Serge 547
struct intel_crtc {
548
	struct drm_crtc base;
549
	enum pipe pipe;
550
	enum plane plane;
551
	u8 lut_r[256], lut_g[256], lut_b[256];
3031 serge 552
	/*
553
	 * Whether the crtc and the connected output pipeline is active. Implies
554
	 * that crtc->enabled is set, i.e. the current mode configuration has
555
	 * some outputs connected to this crtc.
556
	 */
557
	bool active;
4560 Serge 558
	unsigned long enabled_power_domains;
2326 Serge 559
	bool lowfreq_avail;
560
	struct intel_overlay *overlay;
561
	struct intel_unpin_work *unpin_work;
562
 
3243 Serge 563
	atomic_t unpin_work_count;
564
 
3031 serge 565
	/* Display surface base address adjustement for pageflips. Note that on
566
	 * gen4+ this only adjusts up to a tile, offsets within a tile are
567
	 * handled in the hw itself (with the TILEOFF register). */
568
	unsigned long dspaddr_offset;
6084 serge 569
	int adjusted_x;
570
	int adjusted_y;
3031 serge 571
 
2326 Serge 572
	uint32_t cursor_addr;
5060 serge 573
	uint32_t cursor_cntl;
5354 serge 574
	uint32_t cursor_size;
5060 serge 575
	uint32_t cursor_base;
2342 Serge 576
 
6084 serge 577
	struct intel_crtc_state *config;
3746 Serge 578
 
3480 Serge 579
	/* reset counter value when the last flip was submitted */
580
	unsigned int reset_counter;
4104 Serge 581
 
582
	/* Access to these should be protected by dev_priv->irq_lock. */
583
	bool cpu_fifo_underrun_disabled;
584
	bool pch_fifo_underrun_disabled;
4560 Serge 585
 
586
	/* per-pipe watermark state */
587
	struct {
588
		/* watermarks currently being used  */
6937 serge 589
		union {
590
			struct intel_pipe_wm ilk;
591
			struct skl_pipe_wm skl;
592
		} active;
6084 serge 593
		/* allow CxSR on this pipe */
594
		bool cxsr_allowed;
4560 Serge 595
	} wm;
5060 serge 596
 
597
	int scanline_offset;
6084 serge 598
 
599
	struct {
600
		unsigned start_vbl_count;
601
		ktime_t start_vbl_time;
602
		int min_vbl, max_vbl;
603
		int scanline_start;
604
	} debug;
605
 
606
	struct intel_crtc_atomic_commit atomic;
607
 
608
	/* scalers available on this crtc */
609
	int num_scalers;
610
 
611
	struct vlv_wm_state wm_state;
2326 Serge 612
};
613
 
4104 Serge 614
struct intel_plane_wm_parameters {
615
	uint32_t horiz_pixels;
5060 serge 616
	uint32_t vert_pixels;
6084 serge 617
	/*
618
	 *   For packed pixel formats:
619
	 *     bytes_per_pixel - holds bytes per pixel
620
	 *   For planar pixel formats:
621
	 *     bytes_per_pixel - holds bytes per pixel for uv-plane
622
	 *     y_bytes_per_pixel - holds bytes per pixel for y-plane
623
	 */
4104 Serge 624
	uint8_t bytes_per_pixel;
6084 serge 625
	uint8_t y_bytes_per_pixel;
4104 Serge 626
	bool enabled;
627
	bool scaled;
6084 serge 628
	u64 tiling;
629
	unsigned int rotation;
630
	uint16_t fifo_size;
4104 Serge 631
};
632
 
2342 Serge 633
struct intel_plane {
634
	struct drm_plane base;
3746 Serge 635
	int plane;
2342 Serge 636
	enum pipe pipe;
3243 Serge 637
	bool can_scale;
2342 Serge 638
	int max_downscale;
6084 serge 639
	uint32_t frontbuffer_bit;
4104 Serge 640
 
641
	/* Since we need to change the watermarks before/after
642
	 * enabling/disabling the planes, we need to store the parameters here
643
	 * as the other pieces of the struct may not reflect the values we want
644
	 * for the watermark calculations. Currently only Haswell uses this.
645
	 */
646
	struct intel_plane_wm_parameters wm;
647
 
6084 serge 648
	/*
649
	 * NOTE: Do not place new plane state fields here (e.g., when adding
650
	 * new plane properties).  New runtime state should now be placed in
651
	 * the intel_plane_state structure and accessed via drm_plane->state.
652
	 */
653
 
2342 Serge 654
	void (*update_plane)(struct drm_plane *plane,
4104 Serge 655
			     struct drm_crtc *crtc,
2342 Serge 656
			     struct drm_framebuffer *fb,
657
			     int crtc_x, int crtc_y,
658
			     unsigned int crtc_w, unsigned int crtc_h,
659
			     uint32_t x, uint32_t y,
660
			     uint32_t src_w, uint32_t src_h);
4104 Serge 661
	void (*disable_plane)(struct drm_plane *plane,
662
			      struct drm_crtc *crtc);
6084 serge 663
	int (*check_plane)(struct drm_plane *plane,
664
			   struct intel_crtc_state *crtc_state,
665
			   struct intel_plane_state *state);
666
	void (*commit_plane)(struct drm_plane *plane,
667
			     struct intel_plane_state *state);
2342 Serge 668
};
669
 
3031 serge 670
struct intel_watermark_params {
671
	unsigned long fifo_size;
672
	unsigned long max_wm;
673
	unsigned long default_wm;
674
	unsigned long guard_size;
675
	unsigned long cacheline_size;
676
};
677
 
678
struct cxsr_latency {
679
	int is_desktop;
680
	int is_ddr3;
681
	unsigned long fsb_freq;
682
	unsigned long mem_freq;
683
	unsigned long display_sr;
684
	unsigned long display_hpll_disable;
685
	unsigned long cursor_sr;
686
	unsigned long cursor_hpll_disable;
687
};
688
 
6084 serge 689
#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
2326 Serge 690
#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
6084 serge 691
#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
2326 Serge 692
#define to_intel_connector(x) container_of(x, struct intel_connector, base)
693
#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
694
#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
2342 Serge 695
#define to_intel_plane(x) container_of(x, struct intel_plane, base)
6084 serge 696
#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
5060 serge 697
#define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
2326 Serge 698
 
3031 serge 699
struct intel_hdmi {
6937 serge 700
	i915_reg_t hdmi_reg;
3031 serge 701
	int ddc_bus;
6084 serge 702
	bool limited_color_range;
3480 Serge 703
	bool color_range_auto;
3031 serge 704
	bool has_hdmi_sink;
705
	bool has_audio;
706
	enum hdmi_force_audio force_audio;
3480 Serge 707
	bool rgb_quant_range_selectable;
5060 serge 708
	enum hdmi_picture_aspect aspect_ratio;
6084 serge 709
	struct intel_connector *attached_connector;
3031 serge 710
	void (*write_infoframe)(struct drm_encoder *encoder,
4104 Serge 711
				enum hdmi_infoframe_type type,
4560 Serge 712
				const void *frame, ssize_t len);
3031 serge 713
	void (*set_infoframes)(struct drm_encoder *encoder,
5060 serge 714
			       bool enable,
6084 serge 715
			       const struct drm_display_mode *adjusted_mode);
6937 serge 716
	bool (*infoframe_enabled)(struct drm_encoder *encoder,
717
				  const struct intel_crtc_state *pipe_config);
3031 serge 718
};
719
 
5060 serge 720
struct intel_dp_mst_encoder;
3031 serge 721
#define DP_MAX_DOWNSTREAM_PORTS		0x10
722
 
6084 serge 723
/*
724
 * enum link_m_n_set:
725
 *	When platform provides two set of M_N registers for dp, we can
726
 *	program them and switch between them incase of DRRS.
727
 *	But When only one such register is provided, we have to program the
728
 *	required divider value on that registers itself based on the DRRS state.
729
 *
730
 * M1_N1	: Program dp_m_n on M1_N1 registers
731
 *			  dp_m2_n2 on M2_N2 registers (If supported)
732
 *
733
 * M2_N2	: Program dp_m2_n2 on M1_N1 registers
734
 *			  M2_N2 registers are not supported
5060 serge 735
 */
6084 serge 736
 
737
enum link_m_n_set {
738
	/* Sets the m1_n1 and m2_n2 */
739
	M1_N1 = 0,
740
	M2_N2
5060 serge 741
};
742
 
3031 serge 743
struct intel_dp {
6937 serge 744
	i915_reg_t output_reg;
745
	i915_reg_t aux_ch_ctl_reg;
746
	i915_reg_t aux_ch_data_reg[5];
3031 serge 747
	uint32_t DP;
6084 serge 748
	int link_rate;
749
	uint8_t lane_count;
3031 serge 750
	bool has_audio;
751
	enum hdmi_force_audio force_audio;
6084 serge 752
	bool limited_color_range;
3480 Serge 753
	bool color_range_auto;
3031 serge 754
	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
4104 Serge 755
	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
3031 serge 756
	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
6084 serge 757
	/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
758
	uint8_t num_sink_rates;
759
	int sink_rates[DP_MAX_SUPPORTED_RATES];
5060 serge 760
	struct drm_dp_aux aux;
3031 serge 761
	uint8_t train_set[4];
762
	int panel_power_up_delay;
763
	int panel_power_down_delay;
764
	int panel_power_cycle_delay;
765
	int backlight_on_delay;
766
	int backlight_off_delay;
767
	struct delayed_work panel_vdd_work;
768
	bool want_panel_vdd;
5060 serge 769
	unsigned long last_power_cycle;
770
	unsigned long last_power_on;
771
	unsigned long last_backlight_off;
772
 
6937 serge 773
	struct notifier_block edp_notifier;
774
 
5354 serge 775
	/*
776
	 * Pipe whose power sequencer is currently locked into
777
	 * this port. Only relevant on VLV/CHV.
778
	 */
779
	enum pipe pps_pipe;
780
	struct edp_power_seq pps_delays;
781
 
5060 serge 782
	bool can_mst; /* this port supports mst */
783
	bool is_mst;
784
	int active_mst_links;
785
	/* connector directly attached - won't be use for modeset in mst world */
3243 Serge 786
	struct intel_connector *attached_connector;
5060 serge 787
 
788
	/* mst connector list */
789
	struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
790
	struct drm_dp_mst_topology_mgr mst_mgr;
791
 
792
	uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
793
	/*
794
	 * This function returns the value we have to program the AUX_CTL
795
	 * register with to kick off an AUX transaction.
796
	 */
797
	uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
798
				     bool has_aux_irq,
799
				     int send_bytes,
800
				     uint32_t aux_clock_divider);
801
 
6937 serge 802
	/* This is called before a link training is starterd */
803
	void (*prepare_link_retrain)(struct intel_dp *intel_dp);
804
 
805
	bool train_set_valid;
806
 
6084 serge 807
	/* Displayport compliance testing */
808
	unsigned long compliance_test_type;
809
	unsigned long compliance_test_data;
810
	bool compliance_test_active;
3031 serge 811
};
812
 
3243 Serge 813
struct intel_digital_port {
814
	struct intel_encoder base;
815
	enum port port;
4104 Serge 816
	u32 saved_port_bits;
3243 Serge 817
	struct intel_dp dp;
818
	struct intel_hdmi hdmi;
6084 serge 819
	enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
820
	bool release_cl2_override;
6937 serge 821
	/* for communication with audio component; protected by av_mutex */
822
	const struct drm_connector *audio_connector;
3243 Serge 823
};
824
 
5060 serge 825
struct intel_dp_mst_encoder {
826
	struct intel_encoder base;
827
	enum pipe pipe;
828
	struct intel_digital_port *primary;
829
	void *port; /* store this opaque as its illegal to dereference it */
830
};
831
 
6084 serge 832
static inline enum dpio_channel
4104 Serge 833
vlv_dport_to_channel(struct intel_digital_port *dport)
834
{
835
	switch (dport->port) {
836
	case PORT_B:
5060 serge 837
	case PORT_D:
4560 Serge 838
		return DPIO_CH0;
4104 Serge 839
	case PORT_C:
4560 Serge 840
		return DPIO_CH1;
4104 Serge 841
	default:
842
		BUG();
843
	}
844
}
845
 
6084 serge 846
static inline enum dpio_phy
847
vlv_dport_to_phy(struct intel_digital_port *dport)
848
{
849
	switch (dport->port) {
850
	case PORT_B:
851
	case PORT_C:
852
		return DPIO_PHY0;
853
	case PORT_D:
854
		return DPIO_PHY1;
855
	default:
856
		BUG();
857
	}
858
}
859
 
860
static inline enum dpio_channel
5060 serge 861
vlv_pipe_to_channel(enum pipe pipe)
862
{
863
	switch (pipe) {
864
	case PIPE_A:
865
	case PIPE_C:
866
		return DPIO_CH0;
867
	case PIPE_B:
868
		return DPIO_CH1;
869
	default:
870
		BUG();
871
	}
872
}
873
 
2326 Serge 874
static inline struct drm_crtc *
875
intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
876
{
877
	struct drm_i915_private *dev_priv = dev->dev_private;
878
	return dev_priv->pipe_to_crtc_mapping[pipe];
879
}
880
 
881
static inline struct drm_crtc *
882
intel_get_crtc_for_plane(struct drm_device *dev, int plane)
883
{
884
	struct drm_i915_private *dev_priv = dev->dev_private;
885
	return dev_priv->plane_to_crtc_mapping[plane];
886
}
887
 
888
struct intel_unpin_work {
2360 Serge 889
	struct work_struct work;
3243 Serge 890
	struct drm_crtc *crtc;
6084 serge 891
	struct drm_framebuffer *old_fb;
2326 Serge 892
	struct drm_i915_gem_object *pending_flip_obj;
893
	struct drm_pending_vblank_event *event;
3243 Serge 894
	atomic_t pending;
895
#define INTEL_FLIP_INACTIVE	0
896
#define INTEL_FLIP_PENDING	1
897
#define INTEL_FLIP_COMPLETE	2
5060 serge 898
	u32 flip_count;
899
	u32 gtt_offset;
6084 serge 900
	struct drm_i915_gem_request *flip_queued_req;
901
	u32 flip_queued_vblank;
902
	u32 flip_ready_vblank;
2326 Serge 903
	bool enable_stall_check;
904
};
905
 
4560 Serge 906
struct intel_load_detect_pipe {
907
	struct drm_framebuffer *release_fb;
908
	bool load_detect_temp;
909
	int dpms_mode;
910
};
2326 Serge 911
 
4560 Serge 912
static inline struct intel_encoder *
913
intel_attached_encoder(struct drm_connector *connector)
2326 Serge 914
{
915
	return to_intel_connector(connector)->encoder;
916
}
917
 
3243 Serge 918
static inline struct intel_digital_port *
919
enc_to_dig_port(struct drm_encoder *encoder)
920
{
921
	return container_of(encoder, struct intel_digital_port, base.base);
922
}
923
 
5060 serge 924
static inline struct intel_dp_mst_encoder *
925
enc_to_mst(struct drm_encoder *encoder)
926
{
927
	return container_of(encoder, struct intel_dp_mst_encoder, base.base);
928
}
929
 
4104 Serge 930
static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
931
{
932
	return &enc_to_dig_port(encoder)->dp;
933
}
934
 
3243 Serge 935
static inline struct intel_digital_port *
936
dp_to_dig_port(struct intel_dp *intel_dp)
937
{
938
	return container_of(intel_dp, struct intel_digital_port, dp);
939
}
940
 
941
static inline struct intel_digital_port *
942
hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
943
{
944
	return container_of(intel_hdmi, struct intel_digital_port, hdmi);
945
}
946
 
5354 serge 947
/*
948
 * Returns the number of planes for this pipe, ie the number of sprites + 1
949
 * (primary plane). This doesn't count the cursor plane then.
950
 */
951
static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
952
{
953
	return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
954
}
4560 Serge 955
 
5354 serge 956
/* intel_fifo_underrun.c */
957
bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
4560 Serge 958
					   enum pipe pipe, bool enable);
5354 serge 959
bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
4560 Serge 960
					   enum transcoder pch_transcoder,
961
					   bool enable);
5354 serge 962
void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
963
					 enum pipe pipe);
964
void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
965
					 enum transcoder pch_transcoder);
6937 serge 966
void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
967
void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
5354 serge 968
 
969
/* i915_irq.c */
5060 serge 970
void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
971
void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
972
void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
973
void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
5354 serge 974
void gen6_reset_rps_interrupts(struct drm_device *dev);
975
void gen6_enable_rps_interrupts(struct drm_device *dev);
976
void gen6_disable_rps_interrupts(struct drm_device *dev);
6084 serge 977
u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
5354 serge 978
void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
979
void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
5060 serge 980
static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
981
{
982
	/*
983
	 * We only use drm_irq_uninstall() at unload and VT switch, so
984
	 * this is the only thing we need to check.
985
	 */
5354 serge 986
	return dev_priv->pm.irqs_enabled;
5060 serge 987
}
4560 Serge 988
 
5060 serge 989
int intel_get_crtc_scanline(struct intel_crtc *crtc);
6084 serge 990
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
991
				     unsigned int pipe_mask);
4560 Serge 992
 
993
/* intel_crt.c */
994
void intel_crt_init(struct drm_device *dev);
995
 
996
 
997
/* intel_ddi.c */
6937 serge 998
void intel_ddi_clk_select(struct intel_encoder *encoder,
999
			  const struct intel_crtc_state *pipe_config);
4560 Serge 1000
void intel_prepare_ddi(struct drm_device *dev);
1001
void hsw_fdi_link_train(struct drm_crtc *crtc);
1002
void intel_ddi_init(struct drm_device *dev, enum port port);
1003
enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1004
bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1005
void intel_ddi_pll_init(struct drm_device *dev);
1006
void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1007
void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1008
				       enum transcoder cpu_transcoder);
1009
void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1010
void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
6084 serge 1011
bool intel_ddi_pll_select(struct intel_crtc *crtc,
1012
			  struct intel_crtc_state *crtc_state);
4560 Serge 1013
void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
6937 serge 1014
void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
4560 Serge 1015
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1016
void intel_ddi_fdi_disable(struct drm_crtc *crtc);
1017
void intel_ddi_get_config(struct intel_encoder *encoder,
6084 serge 1018
			  struct intel_crtc_state *pipe_config);
1019
struct intel_encoder *
1020
intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
4560 Serge 1021
 
5060 serge 1022
void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1023
void intel_ddi_clock_get(struct intel_encoder *encoder,
6084 serge 1024
			 struct intel_crtc_state *pipe_config);
5060 serge 1025
void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
6084 serge 1026
uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
4560 Serge 1027
 
5354 serge 1028
/* intel_frontbuffer.c */
5060 serge 1029
void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
6084 serge 1030
			     enum fb_op_origin origin);
5060 serge 1031
void intel_frontbuffer_flip_prepare(struct drm_device *dev,
1032
				    unsigned frontbuffer_bits);
1033
void intel_frontbuffer_flip_complete(struct drm_device *dev,
1034
				     unsigned frontbuffer_bits);
1035
void intel_frontbuffer_flip(struct drm_device *dev,
6084 serge 1036
			    unsigned frontbuffer_bits);
1037
unsigned int intel_fb_align_height(struct drm_device *dev,
1038
				   unsigned int height,
1039
				   uint32_t pixel_format,
1040
				   uint64_t fb_format_modifier);
1041
void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1042
			enum fb_op_origin origin);
1043
u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
1044
			      uint32_t pixel_format);
5060 serge 1045
 
5354 serge 1046
/* intel_audio.c */
1047
void intel_init_audio(struct drm_device *dev);
1048
void intel_audio_codec_enable(struct intel_encoder *encoder);
1049
void intel_audio_codec_disable(struct intel_encoder *encoder);
6084 serge 1050
void i915_audio_component_init(struct drm_i915_private *dev_priv);
1051
void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
5354 serge 1052
 
1053
/* intel_display.c */
6084 serge 1054
extern const struct drm_plane_funcs intel_plane_funcs;
5354 serge 1055
bool intel_has_pending_fb_unpin(struct drm_device *dev);
1056
int intel_pch_rawclk(struct drm_device *dev);
6084 serge 1057
int intel_hrawclk(struct drm_device *dev);
5354 serge 1058
void intel_mark_busy(struct drm_device *dev);
4560 Serge 1059
void intel_mark_idle(struct drm_device *dev);
1060
void intel_crtc_restore_mode(struct drm_crtc *crtc);
6084 serge 1061
int intel_display_suspend(struct drm_device *dev);
4560 Serge 1062
void intel_encoder_destroy(struct drm_encoder *encoder);
6084 serge 1063
int intel_connector_init(struct intel_connector *);
1064
struct intel_connector *intel_connector_alloc(void);
4560 Serge 1065
bool intel_connector_get_hw_state(struct intel_connector *connector);
1066
void intel_connector_attach_encoder(struct intel_connector *connector,
6084 serge 1067
				    struct intel_encoder *encoder);
4560 Serge 1068
struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1069
struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6084 serge 1070
					     struct drm_crtc *crtc);
4560 Serge 1071
enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
2326 Serge 1072
int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1073
				struct drm_file *file_priv);
4560 Serge 1074
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
6084 serge 1075
					     enum pipe pipe);
5354 serge 1076
bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1077
static inline void
1078
intel_wait_for_vblank(struct drm_device *dev, int pipe)
1079
{
1080
	drm_wait_one_vblank(dev, pipe);
1081
}
6937 serge 1082
static inline void
1083
intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1084
{
1085
	const struct intel_crtc *crtc =
1086
		to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1087
 
1088
	if (crtc->active)
1089
		intel_wait_for_vblank(dev, pipe);
1090
}
4560 Serge 1091
int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1092
void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
6084 serge 1093
			 struct intel_digital_port *dport,
1094
			 unsigned int expected_mask);
4560 Serge 1095
bool intel_get_load_detect_pipe(struct drm_connector *connector,
6084 serge 1096
				struct drm_display_mode *mode,
5060 serge 1097
				struct intel_load_detect_pipe *old,
1098
				struct drm_modeset_acquire_ctx *ctx);
4560 Serge 1099
void intel_release_load_detect_pipe(struct drm_connector *connector,
6084 serge 1100
				    struct intel_load_detect_pipe *old,
1101
				    struct drm_modeset_acquire_ctx *ctx);
5354 serge 1102
int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1103
			       struct drm_framebuffer *fb,
6937 serge 1104
			       const struct drm_plane_state *plane_state);
5060 serge 1105
struct drm_framebuffer *
1106
__intel_framebuffer_create(struct drm_device *dev,
6084 serge 1107
			   struct drm_mode_fb_cmd2 *mode_cmd,
1108
			   struct drm_i915_gem_object *obj);
4560 Serge 1109
void intel_prepare_page_flip(struct drm_device *dev, int plane);
1110
void intel_finish_page_flip(struct drm_device *dev, int pipe);
1111
void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
5354 serge 1112
void intel_check_page_flip(struct drm_device *dev, int pipe);
6084 serge 1113
int intel_prepare_plane_fb(struct drm_plane *plane,
1114
			   const struct drm_plane_state *new_state);
1115
void intel_cleanup_plane_fb(struct drm_plane *plane,
1116
			    const struct drm_plane_state *old_state);
1117
int intel_plane_atomic_get_property(struct drm_plane *plane,
1118
				    const struct drm_plane_state *state,
1119
				    struct drm_property *property,
1120
				    uint64_t *val);
1121
int intel_plane_atomic_set_property(struct drm_plane *plane,
1122
				    struct drm_plane_state *state,
1123
				    struct drm_property *property,
1124
				    uint64_t val);
1125
int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1126
				    struct drm_plane_state *plane_state);
5060 serge 1127
 
6084 serge 1128
unsigned int
1129
intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
1130
		  uint64_t fb_format_modifier, unsigned int plane);
1131
 
1132
static inline bool
1133
intel_rotation_90_or_270(unsigned int rotation)
1134
{
1135
	return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1136
}
1137
 
1138
void intel_create_rotation_property(struct drm_device *dev,
1139
					struct intel_plane *plane);
1140
 
5060 serge 1141
/* shared dpll functions */
4560 Serge 1142
struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
4104 Serge 1143
void assert_shared_dpll(struct drm_i915_private *dev_priv,
1144
			struct intel_shared_dpll *pll,
1145
			bool state);
1146
#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1147
#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
6084 serge 1148
struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1149
						struct intel_crtc_state *state);
5060 serge 1150
 
5354 serge 1151
void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1152
		      const struct dpll *dpll);
1153
void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1154
 
5060 serge 1155
/* modesetting asserts */
5354 serge 1156
void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157
			   enum pipe pipe);
4104 Serge 1158
void assert_pll(struct drm_i915_private *dev_priv,
1159
		enum pipe pipe, bool state);
1160
#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1161
#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1162
void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1163
		       enum pipe pipe, bool state);
1164
#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1165
#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
4560 Serge 1166
void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
2342 Serge 1167
#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1168
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
6084 serge 1169
unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
1170
					     int *x, int *y,
1171
					     unsigned int tiling_mode,
1172
					     unsigned int bpp,
1173
					     unsigned int pitch);
5354 serge 1174
void intel_prepare_reset(struct drm_device *dev);
1175
void intel_finish_reset(struct drm_device *dev);
5060 serge 1176
void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1177
void hsw_disable_pc8(struct drm_i915_private *dev_priv);
6084 serge 1178
void broxton_init_cdclk(struct drm_device *dev);
1179
void broxton_uninit_cdclk(struct drm_device *dev);
1180
void broxton_ddi_phy_init(struct drm_device *dev);
1181
void broxton_ddi_phy_uninit(struct drm_device *dev);
1182
void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1183
void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1184
void skl_init_cdclk(struct drm_i915_private *dev_priv);
6937 serge 1185
int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6084 serge 1186
void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
6937 serge 1187
void skl_enable_dc6(struct drm_i915_private *dev_priv);
1188
void skl_disable_dc6(struct drm_i915_private *dev_priv);
4560 Serge 1189
void intel_dp_get_m_n(struct intel_crtc *crtc,
6084 serge 1190
		      struct intel_crtc_state *pipe_config);
1191
void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
4560 Serge 1192
int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1193
void
6084 serge 1194
ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
4560 Serge 1195
				int dotclock);
6084 serge 1196
bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1197
			intel_clock_t *best_clock);
1198
int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
1199
 
4560 Serge 1200
bool intel_crtc_active(struct drm_crtc *crtc);
1201
void hsw_enable_ips(struct intel_crtc *crtc);
1202
void hsw_disable_ips(struct intel_crtc *crtc);
5060 serge 1203
enum intel_display_power_domain
1204
intel_display_port_power_domain(struct intel_encoder *intel_encoder);
6084 serge 1205
enum intel_display_power_domain
1206
intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
5060 serge 1207
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6084 serge 1208
				 struct intel_crtc_state *pipe_config);
5354 serge 1209
void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
3243 Serge 1210
 
6084 serge 1211
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1212
int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1213
 
6660 serge 1214
u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
6084 serge 1215
				     struct drm_i915_gem_object *obj,
1216
				     unsigned int plane);
1217
 
1218
u32 skl_plane_ctl_format(uint32_t pixel_format);
1219
u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1220
u32 skl_plane_ctl_rotation(unsigned int rotation);
1221
 
1222
/* intel_csr.c */
6937 serge 1223
void intel_csr_ucode_init(struct drm_i915_private *);
1224
void intel_csr_load_program(struct drm_i915_private *);
1225
void intel_csr_ucode_fini(struct drm_i915_private *);
6084 serge 1226
 
4560 Serge 1227
/* intel_dp.c */
6937 serge 1228
void intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
4560 Serge 1229
bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1230
			     struct intel_connector *intel_connector);
6084 serge 1231
void intel_dp_set_link_params(struct intel_dp *intel_dp,
1232
			      const struct intel_crtc_state *pipe_config);
4560 Serge 1233
void intel_dp_start_link_train(struct intel_dp *intel_dp);
1234
void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1235
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
6660 serge 1236
void intel_dp_encoder_reset(struct drm_encoder *encoder);
1237
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
4560 Serge 1238
void intel_dp_encoder_destroy(struct drm_encoder *encoder);
5060 serge 1239
int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
4560 Serge 1240
bool intel_dp_compute_config(struct intel_encoder *encoder,
6084 serge 1241
			     struct intel_crtc_state *pipe_config);
4560 Serge 1242
bool intel_dp_is_edp(struct drm_device *dev, enum port port);
6084 serge 1243
enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1244
				  bool long_hpd);
5060 serge 1245
void intel_edp_backlight_on(struct intel_dp *intel_dp);
1246
void intel_edp_backlight_off(struct intel_dp *intel_dp);
1247
void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1248
void intel_edp_panel_on(struct intel_dp *intel_dp);
1249
void intel_edp_panel_off(struct intel_dp *intel_dp);
1250
void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1251
void intel_dp_mst_suspend(struct drm_device *dev);
1252
void intel_dp_mst_resume(struct drm_device *dev);
6084 serge 1253
int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1254
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
5060 serge 1255
void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
5354 serge 1256
void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1257
uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
6084 serge 1258
void intel_plane_destroy(struct drm_plane *plane);
1259
void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1260
void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1261
void intel_edp_drrs_invalidate(struct drm_device *dev,
1262
		unsigned frontbuffer_bits);
1263
void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
6937 serge 1264
bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1265
					 struct intel_digital_port *port);
6084 serge 1266
void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
5354 serge 1267
 
6937 serge 1268
void
1269
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1270
				       uint8_t dp_train_pat);
1271
void
1272
intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1273
void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1274
uint8_t
1275
intel_dp_voltage_max(struct intel_dp *intel_dp);
1276
uint8_t
1277
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1278
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1279
			   uint8_t *link_bw, uint8_t *rate_select);
1280
bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1281
bool
1282
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1283
 
5060 serge 1284
/* intel_dp_mst.c */
1285
int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1286
void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
4560 Serge 1287
/* intel_dsi.c */
5060 serge 1288
void intel_dsi_init(struct drm_device *dev);
4560 Serge 1289
 
1290
 
1291
/* intel_dvo.c */
1292
void intel_dvo_init(struct drm_device *dev);
1293
 
1294
 
1295
/* legacy fbdev emulation in intel_fbdev.c */
6084 serge 1296
#ifdef CONFIG_DRM_FBDEV_EMULATION
4560 Serge 1297
extern int intel_fbdev_init(struct drm_device *dev);
6937 serge 1298
extern void intel_fbdev_initial_config_async(struct drm_device *dev);
4560 Serge 1299
extern void intel_fbdev_fini(struct drm_device *dev);
5354 serge 1300
extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
4560 Serge 1301
extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1302
extern void intel_fbdev_restore_mode(struct drm_device *dev);
1303
#else
1304
static inline int intel_fbdev_init(struct drm_device *dev)
1305
{
1306
	return 0;
1307
}
1308
 
6937 serge 1309
static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
4560 Serge 1310
{
1311
}
1312
 
1313
static inline void intel_fbdev_fini(struct drm_device *dev)
1314
{
1315
}
1316
 
5354 serge 1317
static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
4560 Serge 1318
{
1319
}
1320
 
1321
static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1322
{
1323
}
1324
#endif
1325
 
6084 serge 1326
/* intel_fbc.c */
6937 serge 1327
bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1328
void intel_fbc_deactivate(struct intel_crtc *crtc);
1329
void intel_fbc_update(struct intel_crtc *crtc);
6084 serge 1330
void intel_fbc_init(struct drm_i915_private *dev_priv);
6937 serge 1331
void intel_fbc_enable(struct intel_crtc *crtc);
6084 serge 1332
void intel_fbc_disable(struct drm_i915_private *dev_priv);
1333
void intel_fbc_disable_crtc(struct intel_crtc *crtc);
1334
void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1335
			  unsigned int frontbuffer_bits,
1336
			  enum fb_op_origin origin);
1337
void intel_fbc_flush(struct drm_i915_private *dev_priv,
1338
		     unsigned int frontbuffer_bits, enum fb_op_origin origin);
1339
void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1340
 
4560 Serge 1341
/* intel_hdmi.c */
6937 serge 1342
void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
4560 Serge 1343
void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1344
			       struct intel_connector *intel_connector);
1345
struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1346
bool intel_hdmi_compute_config(struct intel_encoder *encoder,
6084 serge 1347
			       struct intel_crtc_state *pipe_config);
4560 Serge 1348
 
1349
 
1350
/* intel_lvds.c */
1351
void intel_lvds_init(struct drm_device *dev);
1352
bool intel_is_dual_link_lvds(struct drm_device *dev);
1353
 
1354
 
1355
/* intel_modes.c */
1356
int intel_connector_update_modes(struct drm_connector *connector,
1357
				 struct edid *edid);
1358
int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1359
void intel_attach_force_audio_property(struct drm_connector *connector);
1360
void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
6084 serge 1361
void intel_attach_aspect_ratio_property(struct drm_connector *connector);
4560 Serge 1362
 
1363
 
1364
/* intel_overlay.c */
1365
void intel_setup_overlay(struct drm_device *dev);
1366
void intel_cleanup_overlay(struct drm_device *dev);
1367
int intel_overlay_switch_off(struct intel_overlay *overlay);
1368
int intel_overlay_put_image(struct drm_device *dev, void *data,
6084 serge 1369
			    struct drm_file *file_priv);
4560 Serge 1370
int intel_overlay_attrs(struct drm_device *dev, void *data,
6084 serge 1371
			struct drm_file *file_priv);
1372
void intel_overlay_reset(struct drm_i915_private *dev_priv);
2342 Serge 1373
 
3031 serge 1374
 
4560 Serge 1375
/* intel_panel.c */
1376
int intel_panel_init(struct intel_panel *panel,
5060 serge 1377
		     struct drm_display_mode *fixed_mode,
1378
		     struct drm_display_mode *downclock_mode);
4560 Serge 1379
void intel_panel_fini(struct intel_panel *panel);
1380
void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1381
			    struct drm_display_mode *adjusted_mode);
1382
void intel_pch_panel_fitting(struct intel_crtc *crtc,
6084 serge 1383
			     struct intel_crtc_state *pipe_config,
4560 Serge 1384
			     int fitting_mode);
1385
void intel_gmch_panel_fitting(struct intel_crtc *crtc,
6084 serge 1386
			      struct intel_crtc_state *pipe_config,
4560 Serge 1387
			      int fitting_mode);
5060 serge 1388
void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1389
				    u32 level, u32 max);
5354 serge 1390
int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
4560 Serge 1391
void intel_panel_enable_backlight(struct intel_connector *connector);
1392
void intel_panel_disable_backlight(struct intel_connector *connector);
1393
void intel_panel_destroy_backlight(struct drm_connector *connector);
1394
enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1395
extern struct drm_display_mode *intel_find_panel_downclock(
1396
				struct drm_device *dev,
1397
				struct drm_display_mode *fixed_mode,
1398
				struct drm_connector *connector);
5354 serge 1399
void intel_backlight_register(struct drm_device *dev);
1400
void intel_backlight_unregister(struct drm_device *dev);
4104 Serge 1401
 
5354 serge 1402
 
1403
/* intel_psr.c */
1404
void intel_psr_enable(struct intel_dp *intel_dp);
1405
void intel_psr_disable(struct intel_dp *intel_dp);
1406
void intel_psr_invalidate(struct drm_device *dev,
6084 serge 1407
			  unsigned frontbuffer_bits);
5354 serge 1408
void intel_psr_flush(struct drm_device *dev,
6084 serge 1409
		     unsigned frontbuffer_bits,
1410
		     enum fb_op_origin origin);
5354 serge 1411
void intel_psr_init(struct drm_device *dev);
6084 serge 1412
void intel_psr_single_frame_update(struct drm_device *dev,
1413
				   unsigned frontbuffer_bits);
5354 serge 1414
 
1415
/* intel_runtime_pm.c */
1416
int intel_power_domains_init(struct drm_i915_private *);
1417
void intel_power_domains_fini(struct drm_i915_private *);
6937 serge 1418
void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1419
void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1420
void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv);
1421
void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv);
5354 serge 1422
void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
6937 serge 1423
const char *
1424
intel_display_power_domain_str(enum intel_display_power_domain domain);
5354 serge 1425
 
1426
bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1427
				    enum intel_display_power_domain domain);
1428
bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1429
				      enum intel_display_power_domain domain);
1430
void intel_display_power_get(struct drm_i915_private *dev_priv,
1431
			     enum intel_display_power_domain domain);
6937 serge 1432
bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1433
					enum intel_display_power_domain domain);
5354 serge 1434
void intel_display_power_put(struct drm_i915_private *dev_priv,
1435
			     enum intel_display_power_domain domain);
6937 serge 1436
 
1437
static inline void
1438
assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1439
{
1440
	WARN_ONCE(dev_priv->pm.suspended,
1441
		  "Device suspended during HW access\n");
1442
}
1443
 
1444
static inline void
1445
assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1446
{
1447
	assert_rpm_device_not_suspended(dev_priv);
1448
	/* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1449
	 * too much noise. */
1450
	if (!atomic_read(&dev_priv->pm.wakeref_count))
1451
		DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1452
}
1453
 
1454
static inline int
1455
assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1456
{
1457
	int seq = atomic_read(&dev_priv->pm.atomic_seq);
1458
 
1459
	assert_rpm_wakelock_held(dev_priv);
1460
 
1461
	return seq;
1462
}
1463
 
1464
static inline void
1465
assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1466
{
1467
	WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1468
		  "HW access outside of RPM atomic section\n");
1469
}
1470
 
1471
/**
1472
 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1473
 * @dev_priv: i915 device instance
1474
 *
1475
 * This function disable asserts that check if we hold an RPM wakelock
1476
 * reference, while keeping the device-not-suspended checks still enabled.
1477
 * It's meant to be used only in special circumstances where our rule about
1478
 * the wakelock refcount wrt. the device power state doesn't hold. According
1479
 * to this rule at any point where we access the HW or want to keep the HW in
1480
 * an active state we must hold an RPM wakelock reference acquired via one of
1481
 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1482
 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1483
 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1484
 * users should avoid using this function.
1485
 *
1486
 * Any calls to this function must have a symmetric call to
1487
 * enable_rpm_wakeref_asserts().
1488
 */
1489
static inline void
1490
disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1491
{
1492
	atomic_inc(&dev_priv->pm.wakeref_count);
1493
}
1494
 
1495
/**
1496
 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1497
 * @dev_priv: i915 device instance
1498
 *
1499
 * This function re-enables the RPM assert checks after disabling them with
1500
 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1501
 * circumstances otherwise its use should be avoided.
1502
 *
1503
 * Any calls to this function must have a symmetric call to
1504
 * disable_rpm_wakeref_asserts().
1505
 */
1506
static inline void
1507
enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1508
{
1509
	atomic_dec(&dev_priv->pm.wakeref_count);
1510
}
1511
 
1512
/* TODO: convert users of these to rely instead on proper RPM refcounting */
1513
#define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv)	\
1514
	disable_rpm_wakeref_asserts(dev_priv)
1515
 
1516
#define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv)	\
1517
	enable_rpm_wakeref_asserts(dev_priv)
1518
 
5354 serge 1519
void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
6937 serge 1520
bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
5354 serge 1521
void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1522
void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1523
 
1524
void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1525
 
6084 serge 1526
void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1527
			     bool override, unsigned int mask);
1528
bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1529
			  enum dpio_channel ch, bool override);
1530
 
1531
 
4560 Serge 1532
/* intel_pm.c */
1533
void intel_init_clock_gating(struct drm_device *dev);
1534
void intel_suspend_hw(struct drm_device *dev);
5060 serge 1535
int ilk_wm_max_level(const struct drm_device *dev);
4560 Serge 1536
void intel_update_watermarks(struct drm_crtc *crtc);
1537
void intel_init_pm(struct drm_device *dev);
1538
void intel_pm_setup(struct drm_device *dev);
1539
void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1540
void intel_gpu_ips_teardown(void);
5060 serge 1541
void intel_init_gt_powersave(struct drm_device *dev);
1542
void intel_cleanup_gt_powersave(struct drm_device *dev);
4560 Serge 1543
void intel_enable_gt_powersave(struct drm_device *dev);
1544
void intel_disable_gt_powersave(struct drm_device *dev);
5060 serge 1545
void intel_suspend_gt_powersave(struct drm_device *dev);
1546
void intel_reset_gt_powersave(struct drm_device *dev);
4104 Serge 1547
void gen6_update_ring_freq(struct drm_device *dev);
6084 serge 1548
void gen6_rps_busy(struct drm_i915_private *dev_priv);
1549
void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
4560 Serge 1550
void gen6_rps_idle(struct drm_i915_private *dev_priv);
6084 serge 1551
void gen6_rps_boost(struct drm_i915_private *dev_priv,
1552
		    struct intel_rps_client *rps,
1553
		    unsigned long submitted);
1554
void intel_queue_rps_boost_for_request(struct drm_device *dev,
1555
				       struct drm_i915_gem_request *req);
1556
void vlv_wm_get_hw_state(struct drm_device *dev);
4560 Serge 1557
void ilk_wm_get_hw_state(struct drm_device *dev);
5354 serge 1558
void skl_wm_get_hw_state(struct drm_device *dev);
1559
void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1560
			  struct skl_ddb_allocation *ddb /* out */);
6084 serge 1561
uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
3031 serge 1562
 
4560 Serge 1563
/* intel_sdvo.c */
6937 serge 1564
bool intel_sdvo_init(struct drm_device *dev,
1565
		     i915_reg_t reg, enum port port);
3746 Serge 1566
 
4104 Serge 1567
 
4560 Serge 1568
/* intel_sprite.c */
1569
int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1570
int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1571
			      struct drm_file *file_priv);
6084 serge 1572
void intel_pipe_update_start(struct intel_crtc *crtc);
1573
void intel_pipe_update_end(struct intel_crtc *crtc);
4560 Serge 1574
 
1575
/* intel_tv.c */
1576
void intel_tv_init(struct drm_device *dev);
1577
 
6084 serge 1578
/* intel_atomic.c */
1579
int intel_connector_atomic_get_property(struct drm_connector *connector,
1580
					const struct drm_connector_state *state,
1581
					struct drm_property *property,
1582
					uint64_t *val);
1583
struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1584
void intel_crtc_destroy_state(struct drm_crtc *crtc,
1585
			       struct drm_crtc_state *state);
1586
struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1587
void intel_atomic_state_clear(struct drm_atomic_state *);
1588
struct intel_shared_dpll_config *
1589
intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1590
 
1591
static inline struct intel_crtc_state *
1592
intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1593
			    struct intel_crtc *crtc)
1594
{
1595
	struct drm_crtc_state *crtc_state;
1596
	crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1597
	if (IS_ERR(crtc_state))
1598
		return ERR_CAST(crtc_state);
1599
 
1600
	return to_intel_crtc_state(crtc_state);
1601
}
1602
int intel_atomic_setup_scalers(struct drm_device *dev,
1603
	struct intel_crtc *intel_crtc,
1604
	struct intel_crtc_state *crtc_state);
1605
 
1606
/* intel_atomic_plane.c */
1607
struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1608
struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1609
void intel_plane_destroy_state(struct drm_plane *plane,
1610
			       struct drm_plane_state *state);
1611
extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1612
 
6937 serge 1613
int drm_core_init(void);
1614
void set_fake_framebuffer();
1615
int kolibri_framebuffer_init(void *param);
1616
void shmem_file_delete(struct file *filep);
1617
void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1618
int drm_get_pci_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
1619
            struct drm_driver *driver);
1620
 
2326 Serge 1621
#endif /* __INTEL_DRV_H__ */