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Rev | Author | Line No. | Line |
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2326 | Serge | 1 | /* |
2 | * Copyright (c) 2006 Dave Airlie |
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3 | * Copyright (c) 2007-2008 Intel Corporation |
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4 | * Jesse Barnes |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice (including the next |
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14 | * paragraph) shall be included in all copies or substantial portions of the |
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15 | * Software. |
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16 | * |
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17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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23 | * IN THE SOFTWARE. |
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24 | */ |
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25 | #ifndef __INTEL_DRV_H__ |
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26 | #define __INTEL_DRV_H__ |
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27 | |||
28 | #include |
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3031 | serge | 29 | #include |
2326 | Serge | 30 | #include "i915_drv.h" |
3031 | serge | 31 | #include |
32 | #include |
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33 | #include |
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34 | #include |
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2326 | Serge | 35 | |
3482 | Serge | 36 | #define KBUILD_MODNAME "i915.dll" |
37 | |||
3746 | Serge | 38 | |
3031 | serge | 39 | #define cpu_relax() asm volatile("rep; nop") |
40 | |||
3746 | Serge | 41 | /** |
42 | * _wait_for - magic (register) wait macro |
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43 | * |
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44 | * Does the right thing for modeset paths when run under kdgb or similar atomic |
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45 | * contexts. Note that it's important that we check the condition again after |
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46 | * having timed out, since the timeout could be due to preemption or similar and |
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47 | * we've never had a chance to check the condition before the timeout. |
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48 | */ |
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2326 | Serge | 49 | #define _wait_for(COND, MS, W) ({ \ |
3031 | serge | 50 | unsigned long timeout__ = GetTimerTicks() + msecs_to_jiffies(MS); \ |
2326 | Serge | 51 | int ret__ = 0; \ |
2342 | Serge | 52 | while (!(COND)) { \ |
3031 | serge | 53 | if (time_after(GetTimerTicks(), timeout__)) { \ |
3746 | Serge | 54 | if (!(COND)) \ |
2326 | Serge | 55 | ret__ = -ETIMEDOUT; \ |
56 | break; \ |
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57 | } \ |
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3031 | serge | 58 | if (W ) { \ |
59 | msleep(W); \ |
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60 | } else { \ |
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61 | cpu_relax(); \ |
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62 | } \ |
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2326 | Serge | 63 | } \ |
64 | ret__; \ |
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65 | }) |
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66 | |||
3031 | serge | 67 | #define wait_for_atomic_us(COND, US) ({ \ |
68 | unsigned long timeout__ = GetTimerTicks() + usecs_to_jiffies(US); \ |
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69 | int ret__ = 0; \ |
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70 | while (!(COND)) { \ |
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71 | if (time_after(GetTimerTicks(), timeout__)) { \ |
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72 | ret__ = -ETIMEDOUT; \ |
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73 | break; \ |
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74 | } \ |
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75 | cpu_relax(); \ |
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76 | } \ |
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77 | ret__; \ |
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78 | }) |
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79 | |||
2326 | Serge | 80 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
81 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) |
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82 | |||
83 | #define MSLEEP(x) do { \ |
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84 | if (in_dbg_master()) \ |
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85 | mdelay(x); \ |
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86 | else \ |
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87 | msleep(x); \ |
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88 | } while(0) |
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89 | |||
90 | #define KHz(x) (1000*x) |
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91 | #define MHz(x) KHz(1000*x) |
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92 | |||
93 | /* |
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94 | * Display related stuff |
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95 | */ |
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96 | |||
97 | /* store information about an Ixxx DVO */ |
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98 | /* The i830->i865 use multiple DVOs with multiple i2cs */ |
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99 | /* the i915, i945 have a single sDVO i2c bus - which is different */ |
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100 | #define MAX_OUTPUTS 6 |
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101 | /* maximum connectors per crtcs in the mode set */ |
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102 | #define INTELFB_CONN_LIMIT 4 |
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103 | |||
104 | #define INTEL_I2C_BUS_DVO 1 |
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105 | #define INTEL_I2C_BUS_SDVO 2 |
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106 | |||
107 | /* these are outputs from the chip - integrated only |
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108 | external chips are via DVO or SDVO output */ |
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109 | #define INTEL_OUTPUT_UNUSED 0 |
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110 | #define INTEL_OUTPUT_ANALOG 1 |
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111 | #define INTEL_OUTPUT_DVO 2 |
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112 | #define INTEL_OUTPUT_SDVO 3 |
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113 | #define INTEL_OUTPUT_LVDS 4 |
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114 | #define INTEL_OUTPUT_TVOUT 5 |
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115 | #define INTEL_OUTPUT_HDMI 6 |
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116 | #define INTEL_OUTPUT_DISPLAYPORT 7 |
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117 | #define INTEL_OUTPUT_EDP 8 |
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3243 | Serge | 118 | #define INTEL_OUTPUT_UNKNOWN 9 |
2326 | Serge | 119 | |
120 | #define INTEL_DVO_CHIP_NONE 0 |
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121 | #define INTEL_DVO_CHIP_LVDS 1 |
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122 | #define INTEL_DVO_CHIP_TMDS 2 |
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123 | #define INTEL_DVO_CHIP_TVOUT 4 |
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124 | |||
125 | struct intel_framebuffer { |
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126 | struct drm_framebuffer base; |
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127 | struct drm_i915_gem_object *obj; |
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128 | }; |
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129 | |||
130 | struct intel_fbdev { |
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131 | struct drm_fb_helper helper; |
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132 | struct intel_framebuffer ifb; |
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133 | struct list_head fbdev_list; |
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134 | struct drm_display_mode *our_mode; |
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135 | }; |
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136 | |||
137 | struct intel_encoder { |
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138 | struct drm_encoder base; |
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3031 | serge | 139 | /* |
140 | * The new crtc this encoder will be driven from. Only differs from |
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141 | * base->crtc while a modeset is in progress. |
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142 | */ |
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143 | struct intel_crtc *new_crtc; |
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144 | |||
2326 | Serge | 145 | int type; |
146 | bool needs_tv_clock; |
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3031 | serge | 147 | /* |
148 | * Intel hw has only one MUX where encoders could be clone, hence a |
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149 | * simple flag is enough to compute the possible_clones mask. |
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150 | */ |
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151 | bool cloneable; |
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152 | bool connectors_active; |
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2326 | Serge | 153 | void (*hot_plug)(struct intel_encoder *); |
3746 | Serge | 154 | bool (*compute_config)(struct intel_encoder *, |
155 | struct intel_crtc_config *); |
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3480 | Serge | 156 | void (*pre_pll_enable)(struct intel_encoder *); |
3031 | serge | 157 | void (*pre_enable)(struct intel_encoder *); |
158 | void (*enable)(struct intel_encoder *); |
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3746 | Serge | 159 | void (*mode_set)(struct intel_encoder *intel_encoder); |
3031 | serge | 160 | void (*disable)(struct intel_encoder *); |
161 | void (*post_disable)(struct intel_encoder *); |
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162 | /* Read out the current hw state of this connector, returning true if |
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163 | * the encoder is active. If the encoder is enabled it also set the pipe |
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164 | * it is connected to in the pipe parameter. */ |
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165 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); |
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2326 | Serge | 166 | int crtc_mask; |
3746 | Serge | 167 | enum hpd_pin hpd_pin; |
2326 | Serge | 168 | }; |
169 | |||
3243 | Serge | 170 | struct intel_panel { |
171 | struct drm_display_mode *fixed_mode; |
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172 | int fitting_mode; |
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173 | }; |
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174 | |||
2326 | Serge | 175 | struct intel_connector { |
176 | struct drm_connector base; |
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3031 | serge | 177 | /* |
178 | * The fixed encoder this connector is connected to. |
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179 | */ |
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2326 | Serge | 180 | struct intel_encoder *encoder; |
3031 | serge | 181 | |
182 | /* |
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183 | * The new encoder this connector will be driven. Only differs from |
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184 | * encoder while a modeset is in progress. |
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185 | */ |
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186 | struct intel_encoder *new_encoder; |
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187 | |||
188 | /* Reads out the current hw, returning true if the connector is enabled |
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189 | * and active (i.e. dpms ON state). */ |
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190 | bool (*get_hw_state)(struct intel_connector *); |
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3243 | Serge | 191 | |
192 | /* Panel info for eDP and LVDS */ |
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193 | struct intel_panel panel; |
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194 | |||
195 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ |
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196 | struct edid *edid; |
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3746 | Serge | 197 | |
198 | /* since POLL and HPD connectors may use the same HPD line keep the native |
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199 | state of connector->polled in case hotplug storm detection changes it */ |
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200 | u8 polled; |
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2326 | Serge | 201 | }; |
202 | |||
3746 | Serge | 203 | struct intel_crtc_config { |
204 | struct drm_display_mode requested_mode; |
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205 | struct drm_display_mode adjusted_mode; |
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206 | /* This flag must be set by the encoder's compute_config callback if it |
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207 | * changes the crtc timings in the mode to prevent the crtc fixup from |
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208 | * overwriting them. Currently only lvds needs that. */ |
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209 | bool timings_set; |
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210 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
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211 | * between pch encoders and cpu encoders. */ |
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212 | bool has_pch_encoder; |
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213 | |||
214 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
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215 | * pipe on Haswell (where we have a special eDP transcoder). */ |
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216 | enum transcoder cpu_transcoder; |
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217 | |||
218 | /* |
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219 | * Use reduced/limited/broadcast rbg range, compressing from the full |
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220 | * range fed into the crtcs. |
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221 | */ |
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222 | bool limited_color_range; |
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223 | |||
224 | /* DP has a bunch of special case unfortunately, so mark the pipe |
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225 | * accordingly. */ |
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226 | bool has_dp_encoder; |
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227 | bool dither; |
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228 | |||
229 | /* Controls for the clock computation, to override various stages. */ |
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230 | bool clock_set; |
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231 | |||
232 | /* Settings for the intel dpll used on pretty much everything but |
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233 | * haswell. */ |
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234 | struct dpll { |
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235 | unsigned n; |
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236 | unsigned m1, m2; |
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237 | unsigned p1, p2; |
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238 | } dpll; |
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239 | |||
240 | int pipe_bpp; |
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241 | struct intel_link_m_n dp_m_n; |
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242 | /** |
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243 | * This is currently used by DP and HDMI encoders since those can have a |
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244 | * target pixel clock != the port link clock (which is currently stored |
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245 | * in adjusted_mode->clock). |
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246 | */ |
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247 | int pixel_target_clock; |
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248 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
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249 | unsigned pixel_multiplier; |
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250 | }; |
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251 | |||
2326 | Serge | 252 | struct intel_crtc { |
253 | struct drm_crtc base; |
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254 | enum pipe pipe; |
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255 | enum plane plane; |
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256 | u8 lut_r[256], lut_g[256], lut_b[256]; |
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3031 | serge | 257 | /* |
258 | * Whether the crtc and the connected output pipeline is active. Implies |
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259 | * that crtc->enabled is set, i.e. the current mode configuration has |
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260 | * some outputs connected to this crtc. |
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261 | */ |
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262 | bool active; |
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3480 | Serge | 263 | bool eld_vld; |
3031 | serge | 264 | bool primary_disabled; /* is the crtc obscured by a plane? */ |
2326 | Serge | 265 | bool lowfreq_avail; |
266 | struct intel_overlay *overlay; |
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267 | struct intel_unpin_work *unpin_work; |
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268 | int fdi_lanes; |
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269 | |||
3243 | Serge | 270 | atomic_t unpin_work_count; |
271 | |||
3031 | serge | 272 | /* Display surface base address adjustement for pageflips. Note that on |
273 | * gen4+ this only adjusts up to a tile, offsets within a tile are |
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274 | * handled in the hw itself (with the TILEOFF register). */ |
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275 | unsigned long dspaddr_offset; |
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276 | |||
2326 | Serge | 277 | struct drm_i915_gem_object *cursor_bo; |
278 | uint32_t cursor_addr; |
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279 | int16_t cursor_x, cursor_y; |
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280 | int16_t cursor_width, cursor_height; |
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281 | bool cursor_visible; |
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2342 | Serge | 282 | |
3746 | Serge | 283 | struct intel_crtc_config config; |
284 | |||
3031 | serge | 285 | /* We can share PLLs across outputs if the timings match */ |
286 | struct intel_pch_pll *pch_pll; |
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3243 | Serge | 287 | uint32_t ddi_pll_sel; |
3480 | Serge | 288 | |
289 | /* reset counter value when the last flip was submitted */ |
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290 | unsigned int reset_counter; |
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2326 | Serge | 291 | }; |
292 | |||
2342 | Serge | 293 | struct intel_plane { |
294 | struct drm_plane base; |
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3746 | Serge | 295 | int plane; |
2342 | Serge | 296 | enum pipe pipe; |
297 | struct drm_i915_gem_object *obj; |
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3243 | Serge | 298 | bool can_scale; |
2342 | Serge | 299 | int max_downscale; |
300 | u32 lut_r[1024], lut_g[1024], lut_b[1024]; |
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3746 | Serge | 301 | int crtc_x, crtc_y; |
302 | unsigned int crtc_w, crtc_h; |
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303 | uint32_t src_x, src_y; |
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304 | uint32_t src_w, src_h; |
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2342 | Serge | 305 | void (*update_plane)(struct drm_plane *plane, |
306 | struct drm_framebuffer *fb, |
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307 | struct drm_i915_gem_object *obj, |
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308 | int crtc_x, int crtc_y, |
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309 | unsigned int crtc_w, unsigned int crtc_h, |
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310 | uint32_t x, uint32_t y, |
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311 | uint32_t src_w, uint32_t src_h); |
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312 | void (*disable_plane)(struct drm_plane *plane); |
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313 | int (*update_colorkey)(struct drm_plane *plane, |
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314 | struct drm_intel_sprite_colorkey *key); |
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315 | void (*get_colorkey)(struct drm_plane *plane, |
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316 | struct drm_intel_sprite_colorkey *key); |
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317 | }; |
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318 | |||
3031 | serge | 319 | struct intel_watermark_params { |
320 | unsigned long fifo_size; |
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321 | unsigned long max_wm; |
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322 | unsigned long default_wm; |
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323 | unsigned long guard_size; |
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324 | unsigned long cacheline_size; |
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325 | }; |
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326 | |||
327 | struct cxsr_latency { |
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328 | int is_desktop; |
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329 | int is_ddr3; |
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330 | unsigned long fsb_freq; |
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331 | unsigned long mem_freq; |
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332 | unsigned long display_sr; |
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333 | unsigned long display_hpll_disable; |
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334 | unsigned long cursor_sr; |
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335 | unsigned long cursor_hpll_disable; |
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336 | }; |
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337 | |||
2326 | Serge | 338 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
339 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
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340 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
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341 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
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2342 | Serge | 342 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
2326 | Serge | 343 | |
344 | #define DIP_HEADER_SIZE 5 |
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345 | |||
346 | #define DIP_TYPE_AVI 0x82 |
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347 | #define DIP_VERSION_AVI 0x2 |
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348 | #define DIP_LEN_AVI 13 |
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3031 | serge | 349 | #define DIP_AVI_PR_1 0 |
350 | #define DIP_AVI_PR_2 1 |
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3480 | Serge | 351 | #define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2) |
352 | #define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2) |
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353 | #define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2) |
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2326 | Serge | 354 | |
2342 | Serge | 355 | #define DIP_TYPE_SPD 0x83 |
2326 | Serge | 356 | #define DIP_VERSION_SPD 0x1 |
357 | #define DIP_LEN_SPD 25 |
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358 | #define DIP_SPD_UNKNOWN 0 |
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359 | #define DIP_SPD_DSTB 0x1 |
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360 | #define DIP_SPD_DVDP 0x2 |
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361 | #define DIP_SPD_DVHS 0x3 |
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362 | #define DIP_SPD_HDDVR 0x4 |
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363 | #define DIP_SPD_DVC 0x5 |
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364 | #define DIP_SPD_DSC 0x6 |
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365 | #define DIP_SPD_VCD 0x7 |
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366 | #define DIP_SPD_GAME 0x8 |
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367 | #define DIP_SPD_PC 0x9 |
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368 | #define DIP_SPD_BD 0xa |
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369 | #define DIP_SPD_SCD 0xb |
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370 | |||
371 | struct dip_infoframe { |
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372 | uint8_t type; /* HB0 */ |
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373 | uint8_t ver; /* HB1 */ |
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374 | uint8_t len; /* HB2 - body len, not including checksum */ |
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375 | uint8_t ecc; /* Header ECC */ |
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376 | uint8_t checksum; /* PB0 */ |
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377 | union { |
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378 | struct { |
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379 | /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */ |
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380 | uint8_t Y_A_B_S; |
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381 | /* PB2 - C 7:6, M 5:4, R 3:0 */ |
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382 | uint8_t C_M_R; |
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383 | /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */ |
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384 | uint8_t ITC_EC_Q_SC; |
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385 | /* PB4 - VIC 6:0 */ |
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386 | uint8_t VIC; |
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3031 | serge | 387 | /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */ |
388 | uint8_t YQ_CN_PR; |
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2326 | Serge | 389 | /* PB6 to PB13 */ |
390 | uint16_t top_bar_end; |
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391 | uint16_t bottom_bar_start; |
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392 | uint16_t left_bar_end; |
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393 | uint16_t right_bar_start; |
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3031 | serge | 394 | } __attribute__ ((packed)) avi; |
2326 | Serge | 395 | struct { |
396 | uint8_t vn[8]; |
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397 | uint8_t pd[16]; |
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398 | uint8_t sdi; |
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3031 | serge | 399 | } __attribute__ ((packed)) spd; |
2326 | Serge | 400 | uint8_t payload[27]; |
401 | } __attribute__ ((packed)) body; |
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402 | } __attribute__((packed)); |
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403 | |||
3031 | serge | 404 | struct intel_hdmi { |
3746 | Serge | 405 | u32 hdmi_reg; |
3031 | serge | 406 | int ddc_bus; |
407 | uint32_t color_range; |
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3480 | Serge | 408 | bool color_range_auto; |
3031 | serge | 409 | bool has_hdmi_sink; |
410 | bool has_audio; |
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411 | enum hdmi_force_audio force_audio; |
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3480 | Serge | 412 | bool rgb_quant_range_selectable; |
3031 | serge | 413 | void (*write_infoframe)(struct drm_encoder *encoder, |
414 | struct dip_infoframe *frame); |
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415 | void (*set_infoframes)(struct drm_encoder *encoder, |
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416 | struct drm_display_mode *adjusted_mode); |
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417 | }; |
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418 | |||
419 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
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420 | #define DP_LINK_CONFIGURATION_SIZE 9 |
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421 | |||
422 | struct intel_dp { |
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423 | uint32_t output_reg; |
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3746 | Serge | 424 | uint32_t aux_ch_ctl_reg; |
3031 | serge | 425 | uint32_t DP; |
426 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; |
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427 | bool has_audio; |
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428 | enum hdmi_force_audio force_audio; |
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429 | uint32_t color_range; |
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3480 | Serge | 430 | bool color_range_auto; |
3031 | serge | 431 | uint8_t link_bw; |
432 | uint8_t lane_count; |
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433 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
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434 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
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435 | struct i2c_adapter adapter; |
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436 | struct i2c_algo_dp_aux_data algo; |
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437 | bool is_pch_edp; |
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438 | uint8_t train_set[4]; |
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439 | int panel_power_up_delay; |
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440 | int panel_power_down_delay; |
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441 | int panel_power_cycle_delay; |
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442 | int backlight_on_delay; |
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443 | int backlight_off_delay; |
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444 | struct delayed_work panel_vdd_work; |
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445 | bool want_panel_vdd; |
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3243 | Serge | 446 | struct intel_connector *attached_connector; |
3031 | serge | 447 | }; |
448 | |||
3243 | Serge | 449 | struct intel_digital_port { |
450 | struct intel_encoder base; |
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451 | enum port port; |
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3480 | Serge | 452 | u32 port_reversal; |
3243 | Serge | 453 | struct intel_dp dp; |
454 | struct intel_hdmi hdmi; |
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455 | }; |
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456 | |||
2326 | Serge | 457 | static inline struct drm_crtc * |
458 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) |
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459 | { |
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460 | struct drm_i915_private *dev_priv = dev->dev_private; |
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461 | return dev_priv->pipe_to_crtc_mapping[pipe]; |
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462 | } |
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463 | |||
464 | static inline struct drm_crtc * |
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465 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) |
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466 | { |
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467 | struct drm_i915_private *dev_priv = dev->dev_private; |
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468 | return dev_priv->plane_to_crtc_mapping[plane]; |
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469 | } |
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470 | |||
471 | struct intel_unpin_work { |
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2360 | Serge | 472 | struct work_struct work; |
3243 | Serge | 473 | struct drm_crtc *crtc; |
2326 | Serge | 474 | struct drm_i915_gem_object *old_fb_obj; |
475 | struct drm_i915_gem_object *pending_flip_obj; |
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476 | struct drm_pending_vblank_event *event; |
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3243 | Serge | 477 | atomic_t pending; |
478 | #define INTEL_FLIP_INACTIVE 0 |
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479 | #define INTEL_FLIP_PENDING 1 |
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480 | #define INTEL_FLIP_COMPLETE 2 |
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2326 | Serge | 481 | bool enable_stall_check; |
482 | }; |
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483 | |||
484 | struct intel_fbc_work { |
||
2360 | Serge | 485 | struct delayed_work work; |
2326 | Serge | 486 | struct drm_crtc *crtc; |
487 | struct drm_framebuffer *fb; |
||
488 | int interval; |
||
489 | }; |
||
490 | |||
3243 | Serge | 491 | int intel_pch_rawclk(struct drm_device *dev); |
492 | |||
3031 | serge | 493 | int intel_connector_update_modes(struct drm_connector *connector, |
494 | struct edid *edid); |
||
2326 | Serge | 495 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
496 | |||
497 | extern void intel_attach_force_audio_property(struct drm_connector *connector); |
||
498 | extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector); |
||
499 | |||
500 | extern void intel_crt_init(struct drm_device *dev); |
||
3031 | serge | 501 | extern void intel_hdmi_init(struct drm_device *dev, |
3746 | Serge | 502 | int hdmi_reg, enum port port); |
3243 | Serge | 503 | extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
504 | struct intel_connector *intel_connector); |
||
3031 | serge | 505 | extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); |
3746 | Serge | 506 | extern bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
507 | struct intel_crtc_config *pipe_config); |
||
3031 | serge | 508 | extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if); |
509 | extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, |
||
510 | bool is_sdvob); |
||
2326 | Serge | 511 | extern void intel_dvo_init(struct drm_device *dev); |
512 | extern void intel_tv_init(struct drm_device *dev); |
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3031 | serge | 513 | extern void intel_mark_busy(struct drm_device *dev); |
3480 | Serge | 514 | extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj); |
3031 | serge | 515 | extern void intel_mark_idle(struct drm_device *dev); |
2326 | Serge | 516 | extern bool intel_lvds_init(struct drm_device *dev); |
3480 | Serge | 517 | extern bool intel_is_dual_link_lvds(struct drm_device *dev); |
3031 | serge | 518 | extern void intel_dp_init(struct drm_device *dev, int output_reg, |
519 | enum port port); |
||
3243 | Serge | 520 | extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
521 | struct intel_connector *intel_connector); |
||
522 | extern void intel_dp_init_link_config(struct intel_dp *intel_dp); |
||
523 | extern void intel_dp_start_link_train(struct intel_dp *intel_dp); |
||
524 | extern void intel_dp_complete_link_train(struct intel_dp *intel_dp); |
||
3746 | Serge | 525 | extern void intel_dp_stop_link_train(struct intel_dp *intel_dp); |
3243 | Serge | 526 | extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); |
527 | extern void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
||
528 | extern void intel_dp_check_link_status(struct intel_dp *intel_dp); |
||
3746 | Serge | 529 | extern bool intel_dp_compute_config(struct intel_encoder *encoder, |
530 | struct intel_crtc_config *pipe_config); |
||
2326 | Serge | 531 | extern bool intel_dpd_is_edp(struct drm_device *dev); |
3243 | Serge | 532 | extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp); |
533 | extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp); |
||
534 | extern void ironlake_edp_panel_on(struct intel_dp *intel_dp); |
||
535 | extern void ironlake_edp_panel_off(struct intel_dp *intel_dp); |
||
536 | extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); |
||
537 | extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
||
2326 | Serge | 538 | extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder); |
3746 | Serge | 539 | extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
3031 | serge | 540 | extern void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
541 | enum plane plane); |
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2326 | Serge | 542 | |
543 | /* intel_panel.c */ |
||
3243 | Serge | 544 | extern int intel_panel_init(struct intel_panel *panel, |
545 | struct drm_display_mode *fixed_mode); |
||
546 | extern void intel_panel_fini(struct intel_panel *panel); |
||
547 | |||
2326 | Serge | 548 | extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, |
549 | struct drm_display_mode *adjusted_mode); |
||
550 | extern void intel_pch_panel_fitting(struct drm_device *dev, |
||
551 | int fitting_mode, |
||
3031 | serge | 552 | const struct drm_display_mode *mode, |
2326 | Serge | 553 | struct drm_display_mode *adjusted_mode); |
554 | extern u32 intel_panel_get_max_backlight(struct drm_device *dev); |
||
555 | extern void intel_panel_set_backlight(struct drm_device *dev, u32 level); |
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3243 | Serge | 556 | extern int intel_panel_setup_backlight(struct drm_connector *connector); |
3031 | serge | 557 | extern void intel_panel_enable_backlight(struct drm_device *dev, |
558 | enum pipe pipe); |
||
2326 | Serge | 559 | extern void intel_panel_disable_backlight(struct drm_device *dev); |
560 | extern void intel_panel_destroy_backlight(struct drm_device *dev); |
||
561 | extern enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
||
562 | |||
3031 | serge | 563 | struct intel_set_config { |
564 | struct drm_encoder **save_connector_encoders; |
||
565 | struct drm_crtc **save_encoder_crtcs; |
||
566 | |||
567 | bool fb_changed; |
||
568 | bool mode_changed; |
||
569 | }; |
||
570 | |||
3480 | Serge | 571 | extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
3031 | serge | 572 | int x, int y, struct drm_framebuffer *old_fb); |
573 | extern void intel_modeset_disable(struct drm_device *dev); |
||
3480 | Serge | 574 | extern void intel_crtc_restore_mode(struct drm_crtc *crtc); |
2326 | Serge | 575 | extern void intel_crtc_load_lut(struct drm_crtc *crtc); |
3031 | serge | 576 | extern void intel_crtc_update_dpms(struct drm_crtc *crtc); |
2326 | Serge | 577 | extern void intel_encoder_destroy(struct drm_encoder *encoder); |
3031 | serge | 578 | extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode); |
579 | extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder); |
||
580 | extern void intel_connector_dpms(struct drm_connector *, int mode); |
||
581 | extern bool intel_connector_get_hw_state(struct intel_connector *connector); |
||
582 | extern void intel_modeset_check_state(struct drm_device *dev); |
||
3746 | Serge | 583 | extern void intel_plane_restore(struct drm_plane *plane); |
2326 | Serge | 584 | |
3031 | serge | 585 | |
2326 | Serge | 586 | static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector) |
587 | { |
||
588 | return to_intel_connector(connector)->encoder; |
||
589 | } |
||
590 | |||
3243 | Serge | 591 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
592 | { |
||
593 | struct intel_digital_port *intel_dig_port = |
||
594 | container_of(encoder, struct intel_digital_port, base.base); |
||
595 | return &intel_dig_port->dp; |
||
596 | } |
||
597 | |||
598 | static inline struct intel_digital_port * |
||
599 | enc_to_dig_port(struct drm_encoder *encoder) |
||
600 | { |
||
601 | return container_of(encoder, struct intel_digital_port, base.base); |
||
602 | } |
||
603 | |||
604 | static inline struct intel_digital_port * |
||
605 | dp_to_dig_port(struct intel_dp *intel_dp) |
||
606 | { |
||
607 | return container_of(intel_dp, struct intel_digital_port, dp); |
||
608 | } |
||
609 | |||
610 | static inline struct intel_digital_port * |
||
611 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) |
||
612 | { |
||
613 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); |
||
614 | } |
||
615 | |||
3480 | Serge | 616 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
617 | struct intel_digital_port *port); |
||
618 | |||
2326 | Serge | 619 | extern void intel_connector_attach_encoder(struct intel_connector *connector, |
620 | struct intel_encoder *encoder); |
||
621 | extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector); |
||
622 | |||
623 | extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
||
624 | struct drm_crtc *crtc); |
||
625 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
||
626 | struct drm_file *file_priv); |
||
3243 | Serge | 627 | extern enum transcoder |
628 | intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
||
629 | enum pipe pipe); |
||
2326 | Serge | 630 | extern void intel_wait_for_vblank(struct drm_device *dev, int pipe); |
631 | extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); |
||
3243 | Serge | 632 | extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
2326 | Serge | 633 | |
634 | struct intel_load_detect_pipe { |
||
635 | struct drm_framebuffer *release_fb; |
||
636 | bool load_detect_temp; |
||
637 | int dpms_mode; |
||
638 | }; |
||
3031 | serge | 639 | extern bool intel_get_load_detect_pipe(struct drm_connector *connector, |
2326 | Serge | 640 | struct drm_display_mode *mode, |
641 | struct intel_load_detect_pipe *old); |
||
3031 | serge | 642 | extern void intel_release_load_detect_pipe(struct drm_connector *connector, |
2326 | Serge | 643 | struct intel_load_detect_pipe *old); |
644 | |||
645 | extern void intelfb_restore(void); |
||
646 | extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
||
647 | u16 blue, int regno); |
||
648 | extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
||
649 | u16 *blue, int regno); |
||
650 | extern void intel_enable_clock_gating(struct drm_device *dev); |
||
651 | |||
652 | extern int intel_pin_and_fence_fb_obj(struct drm_device *dev, |
||
653 | struct drm_i915_gem_object *obj, |
||
654 | struct intel_ring_buffer *pipelined); |
||
3031 | serge | 655 | extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); |
2326 | Serge | 656 | |
657 | extern int intel_framebuffer_init(struct drm_device *dev, |
||
658 | struct intel_framebuffer *ifb, |
||
2342 | Serge | 659 | struct drm_mode_fb_cmd2 *mode_cmd, |
2326 | Serge | 660 | struct drm_i915_gem_object *obj); |
661 | extern int intel_fbdev_init(struct drm_device *dev); |
||
3480 | Serge | 662 | extern void intel_fbdev_initial_config(struct drm_device *dev); |
2326 | Serge | 663 | extern void intel_fbdev_fini(struct drm_device *dev); |
3031 | serge | 664 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state); |
2326 | Serge | 665 | extern void intel_prepare_page_flip(struct drm_device *dev, int plane); |
666 | extern void intel_finish_page_flip(struct drm_device *dev, int pipe); |
||
667 | extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane); |
||
668 | |||
669 | extern void intel_setup_overlay(struct drm_device *dev); |
||
670 | extern void intel_cleanup_overlay(struct drm_device *dev); |
||
671 | extern int intel_overlay_switch_off(struct intel_overlay *overlay); |
||
672 | extern int intel_overlay_put_image(struct drm_device *dev, void *data, |
||
673 | struct drm_file *file_priv); |
||
674 | extern int intel_overlay_attrs(struct drm_device *dev, void *data, |
||
675 | struct drm_file *file_priv); |
||
676 | |||
677 | extern void intel_fb_output_poll_changed(struct drm_device *dev); |
||
678 | extern void intel_fb_restore_mode(struct drm_device *dev); |
||
679 | |||
2342 | Serge | 680 | extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
681 | bool state); |
||
682 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
||
683 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) |
||
684 | |||
2326 | Serge | 685 | extern void intel_init_clock_gating(struct drm_device *dev); |
2342 | Serge | 686 | extern void intel_write_eld(struct drm_encoder *encoder, |
687 | struct drm_display_mode *mode); |
||
688 | extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); |
||
3746 | Serge | 689 | extern void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
690 | struct intel_link_m_n *m_n); |
||
691 | extern void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
||
692 | struct intel_link_m_n *m_n); |
||
3031 | serge | 693 | extern void intel_prepare_ddi(struct drm_device *dev); |
694 | extern void hsw_fdi_link_train(struct drm_crtc *crtc); |
||
695 | extern void intel_ddi_init(struct drm_device *dev, enum port port); |
||
2342 | Serge | 696 | |
697 | /* For use by IVB LP watermark workaround in intel_sprite.c */ |
||
3031 | serge | 698 | extern void intel_update_watermarks(struct drm_device *dev); |
2342 | Serge | 699 | extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, |
700 | uint32_t sprite_width, |
||
701 | int pixel_size); |
||
3031 | serge | 702 | extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe, |
703 | struct drm_display_mode *mode); |
||
2342 | Serge | 704 | |
3480 | Serge | 705 | extern unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
706 | unsigned int tiling_mode, |
||
3243 | Serge | 707 | unsigned int bpp, |
708 | unsigned int pitch); |
||
709 | |||
2342 | Serge | 710 | extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
711 | struct drm_file *file_priv); |
||
712 | extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data, |
||
713 | struct drm_file *file_priv); |
||
714 | |||
3031 | serge | 715 | extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg); |
716 | |||
717 | /* Power-related functions, located in intel_pm.c */ |
||
718 | extern void intel_init_pm(struct drm_device *dev); |
||
719 | /* FBC */ |
||
720 | extern bool intel_fbc_enabled(struct drm_device *dev); |
||
721 | extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); |
||
722 | extern void intel_update_fbc(struct drm_device *dev); |
||
723 | /* IPS */ |
||
724 | extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv); |
||
725 | extern void intel_gpu_ips_teardown(void); |
||
726 | |||
3746 | Serge | 727 | extern bool intel_using_power_well(struct drm_device *dev); |
3480 | Serge | 728 | extern void intel_init_power_well(struct drm_device *dev); |
729 | extern void intel_set_power_well(struct drm_device *dev, bool enable); |
||
3031 | serge | 730 | extern void intel_enable_gt_powersave(struct drm_device *dev); |
731 | extern void intel_disable_gt_powersave(struct drm_device *dev); |
||
732 | extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv); |
||
733 | extern void ironlake_teardown_rc6(struct drm_device *dev); |
||
734 | |||
735 | extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
||
736 | enum pipe *pipe); |
||
3243 | Serge | 737 | extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); |
738 | extern void intel_ddi_pll_init(struct drm_device *dev); |
||
3746 | Serge | 739 | extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); |
3243 | Serge | 740 | extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
741 | enum transcoder cpu_transcoder); |
||
742 | extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); |
||
743 | extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); |
||
744 | extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev); |
||
745 | extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock); |
||
746 | extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc); |
||
747 | extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
||
748 | extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); |
||
749 | extern bool |
||
750 | intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); |
||
751 | extern void intel_ddi_fdi_disable(struct drm_crtc *crtc); |
||
3031 | serge | 752 | |
3746 | Serge | 753 | extern void intel_display_handle_reset(struct drm_device *dev); |
754 | |||
2326 | Serge | 755 | #endif /* __INTEL_DRV_H__ */><>><>><> |